Silicon epitaxial substrate manufacturing method and silicon epitaxial substrate

Abstract

To restrain failure of a device by reducing phosphorus diffusion to an epitaxial layer from a substrate side at the time of heat treatment of a device manufacturing step, while restraining stacking fault of epitaxial layers.SOLUTION: The method includes: a step of adding phosphorus as a dopant, so that a transit time between 700°C or less and 600°C or more is 50 or more and 280 or less minutes and electric resistivity is between 0.7 mΩ cm or more and 1.0 mΩ cm or less, and a step of growing a silicon single crystal so that an oxygen concentration is 9.0E+17(atoms / cm3) or less at a straight body; a step of cutting a silicon semiconductor substrate from the silicon single crystal; and a step of forming an epitaxial film on the silicon semiconductor substrate, and forming Si distortion defect due to Si-P defect that is a deposit of silicon (Si) and phosphorus (P) formed at the time of growing the silicon single crystal to 1E+12( / cm3) or more and 1E+13( / cm3) or less, in a depth range of 10 μm immediately below the epitaxial layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a silicon epitaxial substrate and a silicon epitaxial substrate. [Background technology]

[0002] Epitaxial silicon substrates for power metal oxide semiconductor field effect transistors (MOSFETs) are required to have low resistivity, and currently, substrates with resistivity of less than 1 mΩ·cm are known.

[0003] However, when a high concentration of phosphorus is added during the growth of a single crystal ingot to reduce the resistivity to, for example, 1.1 mΩ cm or less, it is known that when an epitaxial layer is grown on a silicon semiconductor substrate cut from such a single crystal ingot, a large number of stacking faults (hereinafter also referred to as "SFs") occur in the epitaxial layer. These stacking faults appear as steps on the surface of the epitaxial silicon substrate and are detected as an increase in the number of light point defects (LPDs) on the substrate surface.

[0004] The origin of stacking faults is believed to be silicon-phosphorus precipitates (Si-P defects).

[0005] According to Patent Document 1, in particular, in single crystals that are highly doped with phosphorus to reduce resistivity, the concentration is about 1E+20 atoms / cc, and it is described that silicon and phosphorus precipitates (Si-P defects) are formed particularly when the temperature of the single crystal is in the range of 600°C to 700°C.

[0006] In order to suppress the formation of Si-P defects, Patent Document 1 proposes a technology in which the time it takes to pass through the temperature range from 700°C or less to 600°C or more during the cooling process during silicon single crystal growth is set to less than 300 minutes, thereby producing silicon single crystals with an electrical resistivity of 0.6 mΩ cm or more and 1.0 mΩ cm or less while reducing stacking faults. Furthermore, Patent Document 2 describes a technology for producing silicon single crystals with low resistivity by limiting the time spent at 570°C±70°C during silicon single crystal growth to between 20 minutes and 200 minutes, thereby suppressing the growth of stacking faults in epitaxial layers during epitaxial film formation. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent Publication No. 2021-109807 [Patent Document 2] WO2014 / 175120 publication Summary of the Invention [Problem to be solved by the invention]

[0008] In the silicon epitaxial substrates manufactured by the methods described in Patent Documents 1 and 2, the occurrence of stacking faults during the formation of the epitaxial layer is suppressed. However, in the subsequent device manufacturing process, when the silicon epitaxial substrate is heat-treated, the diffusion of phosphorus from the substrate to the epitaxial layer cannot be sufficiently suppressed, resulting in a decrease in resistivity of the epitaxial layer, which may result in failure to obtain the designed electrical characteristics and cause device failure.

[0009] The present invention has been made to solve the above-mentioned problems, and has an object to provide a method for manufacturing a silicon epitaxial substrate, and a silicon epitaxial substrate, which are capable of suppressing stacking faults in the epitaxial layer while reducing phosphorus diffusion from the substrate side to the epitaxial layer during heat treatment in the device manufacturing process, thereby suppressing device defects. [Means for solving the problem]

[0010] The method for producing a silicon epitaxial substrate according to the present invention, which has been made to solve the above problems, comprises the steps of: passing a straight body portion from 700°C to 600°C for a period of 50 to 280 minutes; adding phosphorus as a dopant so that the electrical resistivity is 0.7 mΩ cm to 1.0 mΩ cm; and adding an oxygen concentration of 9.0E+17 (atoms / cm 3 ) or less; cutting out a silicon semiconductor substrate from the silicon single crystal; forming an epitaxial film on the silicon semiconductor substrate; and determining whether or not the Si strain defects due to Si-P defects, which are precipitates of silicon (Si) and phosphorus (P) formed during crystal growth of the silicon single crystal, are 1E+12 ( / cm 3 ) or more 1E+13( / cm 3 ) the following steps of forming the substrate.

[0011] It is also preferable to have, before the step of forming the epitaxial film, the steps of placing the silicon semiconductor substrate in an epitaxial growth furnace and maintaining the silicon semiconductor substrate in the epitaxial growth furnace at 750° C. or more and 1000° C. or less for 120 to 300 seconds.

[0012] According to this method, the average maximum side size of Si-P defects after crystal growth can be set to 50 nm or less, and the occurrence of stacking faults can be suppressed. That is, if the average maximum side size of Si-P defects after crystal growth is larger than 50 nm, stacking faults are likely to occur in the epitaxial layer when the epitaxial layer is grown, but this can be suppressed. In addition, the silicon epitaxial substrate produced had a Si strain defect of 1E+12( / cm2) caused by Si-P defects formed during crystal growth in the range of 10 μm depth from just below the epitaxial layer. 3 ) or more 1E+13( / cm 3) or less. These silicon distortion defects capture interstitial oxygen (0) during the subsequent heat treatment, forming gettering sites with sufficient density, which prevents phosphorus from penetrating from the substrate side into the epitaxial layer. As a result, device failures caused by phosphorus diffusion from the substrate side into the epitaxial layer can be suppressed.

[0013] The silicon epitaxial substrate according to the present invention, which has been made to solve the above-mentioned problems, is a silicon epitaxial substrate in which an epitaxial layer is formed on a silicon semiconductor substrate cut out from a silicon single crystal, and the silicon semiconductor substrate has an electrical resistivity of 0.7 mΩ cm or more and 1.0 mΩ cm or less and an oxygen concentration of 9.0E+17 (atoms / cm 3 ) or less, and in a depth range of 10 μm from directly below the epitaxial layer, the Si strain defects caused by Si-P defects, which are precipitates of silicon (Si) and phosphorus (P) formed during crystal growth of the silicon single crystal, are 1E+12 ( / cm 3 ) or more 1E+13( / cm 3 ) It is characterized by the presence of the following:

[0014] The electrical resistivity of the silicon semiconductor substrate is 0.75 mΩ cm or more and 0.9 mΩ cm or less, and the oxygen concentration is 4.0E+17 (atoms / cm 3) More than 9.0E+17(atoms / cm 3) It is desirable that the following: In the silicon semiconductor substrate, it is preferable that the surface on which the epitaxial layer is formed is a surface located relatively closer to the tail of the silicon single crystal, and the back surface is a surface located relatively closer to the head.

[0015] In the silicon epitaxial substrate having such a structure, the Si distortion defects remaining after the formation of the epitaxial layer are captured by interstitial oxygen (0) during the subsequent heat treatment, and gettering sites are formed with sufficient density, thereby preventing phosphorus from penetrating from the substrate side into the epitaxial layer during heat treatment in device manufacturing. As a result, device defects caused by phosphorus diffusion from the substrate side to the epitaxial layer can be suppressed. In addition, since the Si-P defects after the crystal growth remain as Si distortion defects even during the epitaxial growth, it is important to control the size and density of the Si-P defects after the crystal growth. Effect of the Invention

[0016] According to the present invention, in a silicon epitaxial substrate, stacking faults in the epitaxial layer can be suppressed while phosphorus diffusion from the substrate side to the epitaxial layer during heat treatment in the device manufacturing process can be reduced, thereby suppressing device defects. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a schematic diagram of a pulling device for the Czochralski method. [Diagram 2] FIG. 2 is a schematic diagram of an epitaxial growth furnace. [Diagram 3] FIG. 3 is a flowchart showing a method for manufacturing a silicon epitaxial substrate according to the present invention. [Figure 4] FIG. 4 is a graph showing the relationship between the time it takes for a silicon single crystal to pass through a temperature range of 700-600° C. when it is cooled and the density of Si distortion defects in a depth range of 10 μm from just below the epitaxial layer after the formation of the epitaxial film. [Diagram 5] FIG. 5 is a graph showing the relationship between the time it takes for a silicon single crystal to pass through a temperature range of 700-600° C. when it is cooled and the average side size of Si-P defects after crystal growth. [Figure 6]FIG. 6 is a graph showing the relationship between the time it takes for a silicon single crystal to pass through a temperature range of 700-600° C. when it is cooled and the number of LPDs of 65 nm or more in an epitaxial substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, the present invention is not limited to the embodiment described below. In addition, in each drawing, the same or corresponding elements are appropriately assigned the same reference numerals. Furthermore, it should be noted that the drawings are schematic, and the dimensional relationship of each element, the ratio of each element, etc. may differ from the actual ones. There may also be parts in which the dimensional relationship and ratio differ between the drawings.

[0019] First, a pulling apparatus and an epitaxial growth furnace used in a method for producing a silicon epitaxial substrate according to an embodiment of the present invention will be described.

[0020] Fig. 1 is a schematic diagram of a pulling device using the Czochralski method. In the pulling device shown in Fig. 1, a quartz crucible 3 filled with silicon melt 2 is rotatably installed in the center of a furnace 1. A side heater 4 for heating the quartz crucible 3 from the periphery and a bottom heater 5 for heating the quartz crucible 3 from the bottom are installed around the quartz crucible 3. In addition, a radiation shield 6 is installed above the quartz crucible 3 to control the temperature of the silicon melt 2 in the quartz crucible 3 and the single crystal 9 to be pulled.

[0021] In a single crystal pulling apparatus using the Czochralski method, a seed crystal 8 held at the lower end of a wire 7 is immersed in the surface of silicon melt 2 in a quartz crucible 3, and the wire 7 is pulled up while rotating the quartz crucible 3 and the seed crystal 8, thereby growing a single crystal 9. Here, the silicon single crystal 9 to be produced has an electrical resistivity of 0.7 mΩ·cm or more and 1.0 mΩ·cm or less, preferably 0.75 to 0.9 mΩ·cm, and an oxygen concentration of 9.0+E17 atoms / cm 3Less than 4.0E+17 atoms / cm 3 More than 8.0+E17atoms / cm 3 Adjust it so that it becomes as follows.

[0022] Fig. 2 is a schematic diagram of an epitaxial growth furnace. As shown in Fig. 2, in an epitaxial growth furnace 10, a silicon semiconductor substrate W is placed on a susceptor 14 installed in a chamber 11. Then, the susceptor 14 and the silicon semiconductor substrate W are rotated in a predetermined direction around a rotation axis O. Then, a reaction gas G is supplied horizontally from a reaction gas supply pipe 12 to an exhaust pipe 13 while the silicon semiconductor substrate W is heated to a predetermined temperature by a heater outside the chamber 11. As a result, an epitaxial layer is grown on the surface of the silicon semiconductor substrate W.

[0023] [Manufacturing method] Fig. 3 is a flow chart showing a method for producing a silicon epitaxial substrate according to the present invention. As shown in Fig. 3, the method for producing a silicon epitaxial substrate includes a single crystal growing step (S1), a slicing and oxide film forming step (S2), a furnace step (S3), a low temperature holding step (S4), an etching step (S5), and an epitaxial growth step (S6). In the single crystal growth step (S1), a silicon single crystal is grown using a pulling device using the Czochralski method. Here, phosphorus is added as a dopant to the silicon melt 2 so that the phosphorus concentration of the silicon epitaxial substrate to be manufactured is the desired value, and the target electrical resistivity of the silicon epitaxial substrate is 0.8 to 0.9 mΩ·cm and oxygen concentration is 4.0E+17 atoms / cm. 3 More than 8.0E+17atoms / cm 3 Adjust it so that it becomes as follows. More specifically, the following parameters were adjusted to obtain the desired resistivity and oxygen concentration: furnace pressure 350-80 Torr, furnace argon gas flow rate 120-60 L / min, single crystal pulling speed 1.0-0.4 mm / min, horizontal magnetic field strength 2000-4000 Gauss.

[0024] The length of the tail of the ingot produced at the final stage of the growth process is preferably 0 mm or more and 50 mm or less. By making the length of the tail portion 0 mm or more and 50 mm or less, the pulling time of the silicon single crystal at the growth temperature of Si-P defects, which is 700°C or less and 600°C or more, can be shortened.

[0025] Here, by setting the passing time to 50 min or more and 280 min or less, Si-P defects with an average maximum side length of 50 nm or more, which cause stacking faults, are not formed. In other words, if the average maximum side size of Si-P defects after crystal growth is greater than 50 nm, stacking faults are more likely to occur in the epitaxial layer when it is grown. However, by not forming Si-P defects of 50 nm or larger, the occurrence of stacking faults can be suppressed.

[0026] Furthermore, by setting the time for passing the silicon single crystal between 700°C and 600°C to 50 min or more and 280 min or less, after the subsequent epitaxial growth step (S7), the density is increased to 1E+12 ( / cm3) in the range of 10 μm depth from directly under the epitaxial film. 3 ) or more 1E+13( / cm 3 ) or less, and these can be used as impurity trapping sites. The reason for the depth range of 10 μm from just below the epitaxial film is that these are sites that trap oxygen and phosphorus that diffuse from the substrate to the epitaxial layer. In addition, the density of Si distortion defects is 1E+12 ( / cm 3 ), the function as a gettering site for oxygen and phosphorus decreases, and the 3 ), it is not preferable because it increases surface stacking faults after epitaxial growth. The Si distortion defect is an octahedral defect caused by a Si-P defect. This Si distortion defect is formed with sufficient density as a gettering site when the Si-P defect captures interstitial oxygen (O) during the subsequent oxidation heat treatment. This makes it possible to suppress phosphorus diffusion from the substrate side to the epitaxial layer during heat treatment in device manufacturing.

[0027] In the slicing and oxide film formation step (S2), the silicon single crystal is sliced, an oxide film is formed on the back side of the resulting silicon semiconductor substrate, and then mirror processing is performed. An oxide film with a thickness of 1 nm or less is formed on the mirror-finished surface of the substrate by cleaning. Specifically, it is preferable to treat the substrate with ozone water and form a chemical oxide film with a thickness of about 0.7 nm on the surface. As mentioned above, it is important that the oxide film on the substrate surface is stable in the subsequent low-temperature holding step (S4), and for this purpose an ozone oxide film is suitable.

[0028] In the furnace loading step (S3), the silicon semiconductor substrate is loaded into an epitaxial growth furnace.

[0029] The low-temperature holding step (S4) introduces a step of holding the temperature at 750° C. or more and 1000° C. or less for 120 to 300 seconds after raising the temperature in the epitaxial growth furnace. This treatment enables the process of phosphorus dissolving from Si-P defects into the surrounding area and the dissolved phosphorus escaping from the substrate to occur continuously and in a steady state in the subsequent epitaxial film growth process, thereby reducing the increase in distortion in the substrate surface and further suppressing the occurrence of stacking faults.

[0030] In the etching step (S5), hydrogen chloride etching is performed at 1150° C. or more and less than 1200° C., and in the subsequent epitaxial growth step (S6), a Si epitaxial layer is formed at 1100° C. or more and 1150° C. or less. In the silicon semiconductor substrate, the front surface on which the epitaxial layer is formed is the surface located relatively closer to the tail of the silicon single crystal, and the back surface is the surface located relatively closer to the head. This heat treatment redissolves and diffuses the Si-P defects formed during the crystal growth process. Then, the density of Si-P defects is reduced to 1E+12( / cm3) in the area of ​​10 μm depth from just below the epitaxial film. 3 ) or more 1E+13( / cm 3 ) The following Si distortion defects are formed:

[0031] The silicon epitaxial substrate thus formed is cut from a silicon single crystal in which the average maximum side size of Si-P defects after crystal growth is 50 nm or less, and the Si distortion defects due to Si-P defects are 1E+12( / cm 3 ) or more 1E+13( / cm 3 ) or less. The density of silicon distortion defects is 1E+12( / cm 3 ), the subsequent heat treatment will result in insufficient oxygen capture, resulting in a 3 ) is undesirable as it may cause epistacking faults. Since the average maximum side size of Si-P defects after crystal growth is 50 nm or less, the occurrence of stacking faults during the formation of the epitaxial layer can be suppressed. In addition, as mentioned above, in the range of 10 μm deep from just below the epitaxial layer, the Si strain defects caused by the Si-P defects formed during crystal growth are 1E+12( / cm 3 ) or more 1E+13( / cm 3 ) or less. Subsequent heat treatment captures interstitial oxygen (0) in these silicon distortion defects, forming gettering sites with sufficient density to prevent phosphorus from penetrating from the substrate into the epitaxial layer. As a result, device failures caused by phosphorus diffusion from the substrate into the epitaxial layer can be suppressed. EXAMPLES

[0032] The method for producing a silicon epitaxial substrate and the silicon epitaxial substrate according to the present invention will be further described with reference to examples. In the examples, the following experiments were carried out based on the above-described embodiment.

[0033] (Experiment 1) In experiment 1, the relationship between the time that the silicon single crystal passed through temperatures between 700°C and 600°C and the density of Si strain defects in the depth range of 10 μm from just below the epitaxial layer after the epitaxial film was formed was examined.

[0034] First, phosphorus-doped silicon single crystals were grown by the Czochralski method, with the resistivity adjusted to 0.75 mΩ·cm to 0.90 mΩ·cm in the straight body. The crystal orientation was (001), and the diameter was 200 mm. The oxygen concentration was 0.8E+18 atoms / cm. 3 It was decided. Specifically, the following parameters were adjusted to obtain the desired resistivity and oxygen concentration: furnace pressure 350-80 Torr, furnace argon gas flow rate 120-60 L / min, single crystal pulling speed 1.0-0.4 mm / min, horizontal magnetic field strength 2000-4000 Gauss.

[0035] In addition, the crystal length and cooling time of the tail portion of the single crystal ingot were controlled, and the passing time of the silicon single crystal from 700°C to 600°C was controlled under multiple conditions between 30 minutes and 600 minutes.

[0036] After that, various silicon single crystals were sliced, an oxide film was formed on the back surface, and a mirror finish was applied.Furthermore, the obtained silicon semiconductor substrate was treated with 1 ppm ozone water to form a chemical oxide film with a thickness of 0.7 nm on the surface.

[0037] Thereafter, the substrate was placed in an epitaxial growth furnace, and the temperature condition in the low-temperature holding step prior to epitaxial growth was set to 850° C. and maintained for 180 seconds.

[0038] Further, hydrogen chloride etching was performed at 1150° C. or more and less than 1200° C., and then a Si epitaxial layer was formed again at 1100° C. or more and 1150° C. or less in the epitaxial growth furnace.

[0039] Next, the density of Si-P defects was measured using a transmission electron microscope in a depth range of 10 μm from the surface of each type of single crystal. FIG. 4 shows the relationship between the time it takes for a silicon single crystal to pass through a temperature range of 600°C or higher and 700°C or lower when the silicon single crystal is cooled, and the density of Si distortion defects in the depth range of 10 μm from just below the epitaxial layer after the epitaxial film is formed. In the graph of FIG. 4, the vertical axis represents the density of Si strain defects ( / cm) in the depth range of 10 μm from just below the epitaxial layer. 3 ) and the horizontal axis represents the time (min) for the silicon single crystal to pass from 600°C to 700°C when cooled.

[0040] As shown in FIG. 4, when the cooling time of silicon single crystal exceeds 50 min, the density of Si strain defects becomes 1.2E+12( / cm 3 ) or more.

[0041] (Experiment 2) In experiment 2, we investigated the relationship between the time that silicon single crystals passed between 700°C and 600°C and the average maximum side size of Si-P defects after crystal growth.

[0042] In experiment 2, several types of silicon single crystals were grown under the same conditions as in experiment 1, and the various silicon single crystals were sliced ​​to produce silicon semiconductor substrates. That is, in growing silicon single crystals, the following parameters were adjusted to obtain the desired resistivity and oxygen concentration: furnace pressure 350-80 Torr, furnace argon gas flow rate 120-60 L / min, single crystal pulling speed 1.0-0.4 mm / min, horizontal magnetic field strength 2000-4000 Gauss. Then, for each of the silicon semiconductor substrates produced, the average maximum side size (nm) of the Si-P defects was measured using a transmission electron microscope. FIG. 5 shows the relationship between the time it takes for a silicon single crystal to pass through a temperature range from 700° C. or less to 600° C. or more when it is cooled and the average maximum side size of Si-P defects after crystal growth. In the graph of FIG. 5, the vertical axis represents the average maximum side size of Si-P defects after crystal growth, and the horizontal axis represents the time (min) that the silicon single crystal passes from 600° C. to 700° C. when cooled.

[0043] As shown in FIG. 5, it was found that the average maximum side size of Si-P defects after crystal growth can be reduced to 50 nm or less by setting the cooling time of the silicon single crystal to 280 min or less.

[0044] From the results of Experiments 1 and 2, it was found that by setting the time for cooling the silicon single crystal from 700°C to 600°C to 50 min to 280 min, the density of Si distortion defects after the formation of the epitaxial film was reduced to 1.2E+12( / cm 3 ) and that the average maximum side size of Si-P defects after crystal growth can be reduced to 50 nm or less.

[0045] (Experiment 3) In experiment 3, the relationship between the time taken for the silicon single crystal to pass through a temperature range of 600°C or higher and 700°C or lower when cooled and the number of LPDs of 65 nm or larger in the epitaxial substrate was examined.

[0046] In experiment 3, silicon single crystals were grown under the same conditions as in experiment 1. That is, in order to obtain the desired resistivity and oxygen concentration in growing the silicon single crystals, the following parameters were adjusted: furnace pressure 350-80 Torr, furnace argon gas flow rate 120-60 L / min, single crystal pulling speed 1.0-0.4 mm / min, horizontal magnetic field strength 2000-4000 Gauss. In addition, several types of single crystals were produced that had different cooling times between 600°C and 700°C, and epitaxial substrates were created from each type of single crystal. The occurrence of stacking faults (ie, the number of light point defects (LPDs)) in each epitaxial substrate was measured using a laser scattering particle counter (SP-1). FIG. 6 shows the relationship between the time it takes for a silicon single crystal to pass through temperatures of 600° C. or higher and 700° C. or lower when it is cooled and the number of LPDs of 65 nm or larger on an epitaxial substrate. In the graph of FIG. 6, the vertical axis represents the number of LPDs of 65 nm or more in the epitaxial substrate, and the horizontal axis represents the time (min) from 600° C. to 700° C. when the silicon single crystal is cooled. As shown in FIG. 6, by limiting the time it takes for the silicon single crystal to cool from 600°C to 700°C for 280 minutes or less, the number of LPDs could be reduced to 50 or less.

[0047] (Experiment 4) In experiment 4, the relationship between the substrate oxygen concentration and substrate resistivity (electrical resistivity) and the time it takes for the silicon single crystal to pass through a temperature range of 600°C or higher and 700°C or lower during cooling was examined.

[0048] Specifically, the oxygen concentration and resistivity of the silicon semiconductor substrate were set as targets during silicon single crystal growth, and the silicon single crystal was pulled up and controlled. That is, in order to obtain the desired resistivity and oxygen concentration during silicon single crystal growth, the following parameters were adjusted: furnace pressure 350-80 Torr, furnace argon gas flow rate 120-60 L / min, single crystal pulling speed 1.0-0.4 mm / min, horizontal magnetic field strength 2000-4000 Gauss. In addition, by changing the HZ (hot zone: furnace structure) of the single crystal pulling device, the cooling time of the silicon single crystal was set to four types: 20 min, 50 min, 280 min, and 300 min. The other conditions were the same as in Experiment 1 to manufacture the epitaxial substrates. Furthermore, each epitaxial substrate was annealed by holding it at 1000°C for 60 minutes. This annealing process was intended to diffuse phosphorus on the substrate side into the epitaxial film. For each epitaxial substrate, the thickness of the epitaxial film after formation and the thickness of the film after the subsequent annealing treatment were measured by FT-IR (Fourier transform infrared spectroscopy).

[0049] Example 1 In Example 1, the substrate oxygen concentration was set to 8.0E+17 (atoms / cm 3) The substrate resistivity was set to 0.81 (mΩ·cm). Table 1 shows the results of Example 1.

[0050] [Table 1]

[0051] When phosphorus from the substrate side diffuses into the epitaxial layer, the reflection position of the infrared light of the FT-IR moves closer to the surface. In other words, the film thickness measurement result decreases (the film thickness difference becomes larger). However, as shown in Table 1, when the silicon single crystal is cooled for a time period of 50 to 280 minutes from 700°C or less to 600°C or more, the film thickness difference becomes small at 0.3 μm. This is expected to be because oxygen is captured by the Si distortion defects, suppressing the diffusion of phosphorus.

[0052] Example 2 In Example 2, the substrate oxygen concentration was set to 4.5E+17 (atoms / cm 3) The substrate resistivity was set to 0.81 (mΩ·cm). Table 2 shows the results of Example 2.

[0053] [Table 2]

[0054] As shown in Table 2, when the silicon single crystal was cooled from 700°C to 600°C for 50 to 280 minutes, the difference in film thickness was small, between 0.3 and 0.4 μm. This is expected to be because oxygen was captured by the Si distortion defects, suppressing the diffusion of phosphorus.

[0055] Example 3 In Example 3, the substrate oxygen concentration was set to 8.0E+17 (atoms / cm 3) The substrate resistivity was set to 0.70 (mΩ·cm). Table 3 shows the results of Example 3.

[0056] [Table 3]

[0057] As shown in Table 3, when the silicon single crystal was cooled from 700°C to 600°C for 50 to 300 minutes, the difference in film thickness was small, between 0.3 and 0.4 μm. This is expected to be because oxygen was captured by the Si distortion defects, suppressing the diffusion of phosphorus.

[0058] Example 4 In Example 4, the substrate oxygen concentration was set to 8.0E+17 (atoms / cm 3) The substrate resistivity was set to 1.00 (mΩ·cm). Table 4 shows the results of Example 4.

[0059] [Table 4]

[0060] As shown in Table 4, when the silicon single crystal was cooled from 700°C to 600°C for 50 to 300 minutes, the difference in film thickness was small, between 0.2 and 0.3 μm. This is expected to be because oxygen was captured by the Si distortion defects, suppressing the diffusion of phosphorus.

[0061] Comparative Example 1 In Comparative Example 1, the substrate oxygen concentration was set to 1.1E+18 (atoms / cm 3) The substrate resistivity was set to 0.81 (mΩ·cm). Table 5 shows the results of Comparative Example 1.

[0062] [Table 5]

[0063] As shown in Table 5, when the silicon single crystal was cooled from 700°C or less to 600°C or more for 50 to 280 minutes, the difference in film thickness was large at 0.8 μm. This is expected to be because phosphorus on the substrate side diffused into the epitaxial layer, and the reflection position of the FT-IR infrared light moved closer to the surface side.

[0064] Comparative Example 2 In Comparative Example 2, the substrate oxygen concentration was set to 3.8E+17 (atoms / cm 3) The substrate resistivity was set to 0.81 (mΩ·cm). Table 6 shows the results of Comparative Example 2.

[0065] [Table 6]

[0066] As shown in Table 6, when the silicon single crystal was cooled through the 700-600°C temperature range for 50 minutes or more and 280 minutes or less, the difference in film thickness was large, ranging from 0.8 μm to 1.0 μm. The oxygen concentration is 3.8E+17 (atoms / cm 3) This is expected to be because, due to the low Si concentration, the trapping ability of Si strain defects and oxygen decreases, phosphorus on the substrate side diffuses into the epitaxial layer, and the reflection position of the infrared light of the FT-IR moves closer to the surface side.

[0067] Comparative Example 3 In Comparative Example 3, the substrate oxygen concentration was set to 8.0E+17 (atoms / cm 3) The substrate resistivity was set to 1.15 (mΩ·cm). Table 7 shows the results of Comparative Example 3.

[0068] [Table 7]

[0069] As shown in Table 7, when the silicon single crystal was cooled from 700°C to 600°C for 50 to 280 minutes, the difference in film thickness was small, at 0.1 to 0.2 μm. This is expected to be because the phosphorus concentration in the substrate was reduced, suppressing the diffusion of phosphorus itself.

[0070] Comparative Example 4 In Comparative Example 4, the substrate oxygen concentration was set to 8.0E+17 (atoms / cm 3) The substrate resistivity was set to 0.65 (mΩ·cm). Table 8 shows the results of Comparative Example 4.

[0071] [Table 8]

[0072] As shown in Table 8, when the silicon single crystal was cooled from 700°C or less to 600°C or more for a time of 50 to 280 minutes, the difference in film thickness was large at 0.9 μm. This is expected to be because the increased substrate phosphorus concentration promoted the diffusion of substrate-side phosphorus into the epitaxial layer, regardless of the passing time and density of Si distortion defects, and the reflection position of the FT-IR infrared light moved further toward the surface. It was found that even a low substrate resistivity of 0.65 mΩ·cm was not desirable.

[0073] As a result of experiment 3, the substrate oxygen concentration was 4.5E+17 (atoms / cm 3) More than 8.0E+17(atoms / cm 3) It was found that the substrate resistivity should preferably be 0.7 (mΩ·cm) or more and 1.0 (mΩ·cm) or less. [Explanation of symbols]

[0074] 1 furnace 2. Silicon melt 3 Quartz crucible 4 Side heater 5 Bottom Heater 6 Radiation Shield 7 Wire 8 seed crystals 9 crystal 10 Epitaxial growth equipment 11. Chamber 12 Reactant gas supply pipe 13 Exhaust W Silicon semiconductor substrate

Claims

1. In the straight body portion, the time required for passing through 700°C or less and 600°C or more is 50 minutes or more and 280 minutes or less, phosphorus is added as a dopant so that the electrical resistivity is 0.7 mΩ cm or more and 1.0 mΩ cm or less, and the oxygen concentration is 9.0E+17 (atoms / cm ３） growing a silicon single crystal such that cutting a silicon semiconductor substrate from the silicon single crystal; An epitaxial film is formed on the silicon semiconductor substrate, and within a depth range of 10 μm from directly below the epitaxial layer, Si strain defects caused by Si-P defects, which are precipitates of silicon (Si) and phosphorus (P) formed during crystal growth of the silicon single crystal, are 1E+12 ( / cm ３ ) or more 1E+13( / cm ３ ) forming the following; 2. A method for producing a silicon epitaxial substrate comprising the steps of:

2. Prior to the step of forming the epitaxial film, placing the silicon semiconductor substrate into an epitaxial growth furnace; maintaining the temperature in the epitaxial growth furnace at 750° C. or more and 1000° C. or less for 120 to 300 seconds; 2. The method for producing a silicon epitaxial substrate according to claim 1, further comprising the steps of:

3. A silicon epitaxial substrate in which an epitaxial layer is formed on a silicon semiconductor substrate cut out from a silicon single crystal, The silicon semiconductor substrate has an electrical resistivity of 0.7 mΩ·cm or more and 1.0 mΩ·cm or less, and an oxygen concentration of 9.0E+17 (atoms / cm ３） is as follows: In a depth range of 10 μm from directly below the epitaxial layer, the Si strain defects caused by Si-P defects, which are precipitates of silicon (Si) and phosphorus (P) formed during the crystal growth of the silicon single crystal, are 1E+12 ( / cm ３ ) or more 1E+13( / cm ３ ) A silicon epitaxial substrate comprising:

4. The electrical resistivity of the silicon semiconductor substrate is 0.75 mΩ cm or more and 0.9 mΩ cm or less, and the oxygen concentration is 4.0E+17 (atoms / cm ３） Above 8.0E+17 (atoms / cm ３） 4. The silicon epitaxial substrate according to claim 3, wherein:

5. 4. The silicon epitaxial substrate according to claim 3, wherein the surface on which the epitaxial layer is formed is a surface located relatively toward the tail side of the silicon single crystal, and the back surface is a surface located relatively toward the head side of the silicon semiconductor substrate.

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