Semiconductor manufacturing method

Abstract

To restrain failure of a device by reducing phosphorus diffusion to an epitaxial layer from a substrate side at the time of heat treatment of a device manufacturing step, while restraining stacking fault of epitaxial layers.SOLUTION: A silicon substrate manufacturing method includes: a step of adding phosphorus as a dopant, and growing a silicon single crystal with electric resistivity of 0.9 mΩ cm or less; and a step of cutting a silicon semiconductor substrate from the silicon single crystal. A transit time Y(min) between 700°C or less and 600°C or more in an area of the silicon single crystal, in which the silicon substrate with electric resistivity R is positioned, is controlled to satisfy formulae (1) and (2).SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor substrate, which is a silicon substrate or a silicon epitaxial substrate. [Background technology]

[0002] Silicon epitaxial substrates for power MOSFETs (metal oxide semiconductor field effect transistors) are required to have low resistivity, and currently, substrates with resistivity of less than 1 mΩ·cm are known.

[0003] However, when a high concentration of phosphorus is added during the growth of a silicon single crystal ingot to reduce the resistivity to, for example, 1.1 mΩ·cm or less, it is known that when an epitaxial layer is grown on a silicon substrate cut from such a silicon single crystal ingot, a large number of stacking faults (hereinafter also referred to as "SFs") occur in the epitaxial layer. These stacking faults appear as steps on the surface of the silicon epitaxial substrate and are detected as an increase in the number of light point defects (LPDs) on the substrate surface.

[0004] The origin of stacking faults is believed to be silicon-phosphorus precipitates (Si-P defects).

[0005] According to Patent Document 1, in particular, in single crystals that are heavily doped with phosphorus to reduce resistivity, the concentration is about 1×10 20 It is about atoms / cc, and it is described that silicon and phosphorus precipitates (Si-P defects) are formed when the temperature of the single crystal is in the range of 600°C to 700°C in particular.

[0006] In order to suppress the formation of Si-P defects, Patent Document 1 proposes a technology in which the time it takes to pass through the temperature range from 700°C or less to 600°C or more during the cooling process during silicon single crystal growth is set to less than 300 minutes, thereby producing silicon single crystals with an electrical resistivity of 0.6 mΩ cm or more and 1.0 mΩ cm or less while reducing stacking faults. Furthermore, Patent Document 2 describes a technology for producing silicon single crystals with low resistivity by limiting the time spent at 570°C±70°C during silicon single crystal growth to between 20 minutes and 200 minutes, thereby suppressing the growth of stacking faults in epitaxial layers during epitaxial film formation. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent Publication No. 2021-109807 [Patent Document 2] WO2014 / 175120 publication Summary of the Invention [Problem to be solved by the invention]

[0008] In the silicon epitaxial substrates manufactured by the methods described in Patent Documents 1 and 2, the occurrence of stacking faults during the formation of the epitaxial layer is suppressed. However, in the subsequent device manufacturing process, when the silicon epitaxial substrate is heat-treated, the diffusion of phosphorus from the substrate side to the epitaxial layer cannot be sufficiently suppressed, resulting in the diffusion of phosphorus from the substrate side to the epitaxial layer, reducing the resistivity of the epitaxial layer, and preventing the achievement of designed electrical characteristics, which may cause device failure.

[0009] The present invention has been made to solve the above-mentioned problems, and has an object to provide a method for manufacturing a semiconductor substrate that can suppress stacking faults in the epitaxial layer when the epitaxial layer is formed, while reducing phosphorus diffusion from the substrate side to the epitaxial layer during heat treatment in the device manufacturing process, thereby suppressing device defects. [Means for solving the problem]

[0010] A method for manufacturing a silicon substrate according to the present invention, which has been made to solve the above-mentioned problems, comprises the steps of growing a silicon single crystal having an electrical resistivity of 0.9 mΩ cm or less by adding phosphorus as a dopant, and cutting out a silicon substrate from the silicon single crystal, and is characterized in that the passing time Y (min) from 700°C or less to 600°C or more in a region of the silicon single crystal in which the silicon substrate having electrical resistivity R is located is controlled to be within a range that satisfies equations (1) and (2). Y≦5000×R 2 -6730×R+2310···(1) Y≧5429×R 2 -9906×R+4569···(2)

[0011] According to this method, by adjusting the time during which the silicon single crystal is grown at a temperature ranging from 700°C or lower to 600°C or higher in accordance with the resistivity of the silicon substrate so as to satisfy formulas (1) and (2), it is possible to keep the LPD density low and suppress the diffusion of phosphorus from the substrate to the epitaxial layer when forming an epitaxial layer on the silicon substrate. Effect of the Invention

[0012] According to the present invention, stacking faults can be suppressed during the formation of an epitaxial layer, while phosphorus diffusion from the substrate side to the epitaxial layer during heat treatment in the device manufacturing process can be reduced, thereby suppressing device defects. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a schematic diagram of a pulling device for the Czochralski method. [Diagram 2] FIG. 2 is a schematic diagram of an epitaxial growth furnace. [Diagram 3] FIG. 3 is a flowchart showing a method for manufacturing a silicon epitaxial substrate according to the present invention. [Figure 4] Figure 4 is a graph showing the relationship between the electrical resistivity (mΩ·cm) that satisfies the density of LPDs of 65 nm or more and 50 or less and the passing time Y (min) of silicon single crystals from 700°C to 600°C. [Diagram 5] Figure 5 is a graph showing the relationship between the electrical resistivity R (mΩ·cm) at which the diffusion of phosphorus from the substrate to the epitaxial layer is sufficiently suppressed and the time Y (min) for the silicon single crystal to pass from 700°C or less to 600°C or more. [Figure 6] FIG. 6 is a graph in which the graphs of FIG. 4 and FIG. 5 are superimposed. [Figure 7] FIG. 7 is a graph showing the relationship between the time it takes for a silicon single crystal to pass through a temperature range of 600° C. or higher and 700° C. or lower and the electrical resistivity and the LPD density, in which the measured LPD density is plotted for each sample. [Figure 8] FIG. 8 is a graph showing the relationship between the time it takes for a silicon single crystal to pass through a temperature range of 600° C. or higher and 700° C. or lower and the electrical resistivity and phosphorus diffusion when the silicon single crystal is cooled, and the measured phosphorus diffusion results are plotted for each sample. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, the present invention is not limited to the embodiment described below. In addition, in each drawing, the same or corresponding elements are appropriately assigned the same reference numerals. Furthermore, it should be noted that the drawings are schematic, and the dimensional relationship of each element, the ratio of each element, etc. may differ from the actual ones. There may also be parts in which the dimensional relationship and ratio differ between the drawings.

[0015] First, a pulling apparatus and an epitaxial growth furnace used in a method for manufacturing a semiconductor substrate according to an embodiment of the present invention will be described.

[0016] Fig. 1 is a schematic diagram of a pulling device using the Czochralski method. In the pulling device shown in Fig. 1, a quartz crucible 3 filled with silicon melt 2 is rotatably installed in the center of a furnace 1. A side heater 4 for heating the quartz crucible 3 from the periphery and a bottom heater 5 for heating the quartz crucible 3 from the bottom are installed around the quartz crucible 3. In addition, a radiation shield 6 is installed above the quartz crucible 3 to control the temperature of the silicon melt 2 in the quartz crucible 3 and the single crystal 9 to be pulled.

[0017] In a single crystal pulling apparatus using the Czochralski method, a seed crystal 8 held at the lower end of a wire 7 is immersed in the surface of silicon melt 2 in a quartz crucible 3, and the wire 7 is pulled up while rotating the quartz crucible 3 and the seed crystal 8, thereby growing a single crystal 9. Here, the concentration of phosphorus added is adjusted so that the electrical resistivity of the silicon single crystal to be produced is 0.9 mΩ·cm or less, preferably 0.7 to 0.9 mΩ·cm.

[0018] Fig. 2 is a schematic diagram of an epitaxial growth furnace. As shown in Fig. 2, in an epitaxial growth furnace 10, a semiconductor substrate W is placed on a susceptor 14 installed in a chamber 11. Then, the susceptor 14 and the semiconductor substrate W are rotated in a predetermined direction around a rotation axis O. Then, a reactive gas G is supplied horizontally from a reactive gas supply pipe 12 to an exhaust pipe 13 while the semiconductor substrate W is heated to a predetermined temperature by a heater outside the chamber 11. As a result, an epitaxial layer is grown on the surface of the semiconductor substrate W.

[0019] [Manufacturing method] 3 is a flowchart showing a method for manufacturing a semiconductor substrate according to the present invention. In this embodiment, a silicon substrate or a silicon epitaxial substrate is manufactured as a semiconductor substrate in which the density of light point defects (LPDs) of 65 nm or more in the epitaxial layer is 50 or less and the diffusion of phosphorus from the substrate to the epitaxial layer is sufficiently suppressed.

[0020] As shown in FIG. 3, the method for manufacturing a semiconductor substrate includes a single crystal growing step (S1), a slicing and oxide film forming step (S2), a furnace loading step (S3), a low temperature holding step (S4), an etching step (S5), and an epitaxial growth step (S6). In the single crystal growth step (S1), a silicon single crystal is grown using a pulling apparatus using the Czochralski method. Here, phosphorus is added as a dopant to the silicon melt 2, and each parameter of the pulling apparatus is adjusted so that the target electrical resistivity of the silicon epitaxial substrate is 0.9 mΩ·cm or less, preferably 0.7 to 0.9 mΩ·cm.

[0021] Furthermore, in this embodiment, when the electrical resistivity of the silicon substrate is R, the parameters of the pulling device are controlled to grow the silicon single crystal so that the passage time Y (min) between 700°C and 600°C in the region of the silicon single crystal where the silicon substrate (semiconductor substrate) with electrical resistivity R is located satisfies the following equations (1) and (2). Y≦5000×R 2 -6730×R+2310···(1) Y≧5429×R 2 -9906×R+4569···(2)

[0022] More specifically, the following parameters were adjusted to obtain the desired resistivity and oxygen concentration: furnace pressure 350-80 Torr, furnace argon gas flow rate 120-60 L / min, single crystal pulling speed 1.0-0.4 mm / min, horizontal magnetic field strength 2000-4000 Gauss.

[0023] The length of the tail of the silicon ingot produced at the final stage of the growing process is preferably 0 mm or more and 50 mm or less. By making the length of the tail portion 0 mm or more and 50 mm or less, the pulling time of the silicon single crystal at the growth temperature of Si-P defects, which is 700°C or less and 600°C or more, can be shortened in the straight body portion close to the tail portion side.

[0024] According to the research of the present inventors, when the electrical resistivity of the silicon substrate to be manufactured is R (mΩ cm), the passing time Y (min) of a silicon single crystal corresponding to the silicon substrate from 700°C or lower to 600°C or higher in order to achieve a density of LPDs of 65 nm or larger of 50 or less when an epitaxial layer is formed on the silicon substrate can be defined by the following formula (1). Y≦5000×R 2 -6730×R+2310···(1) If this region is shown graphically, as shown in FIG. 4, the region of silicon substrates and silicon single crystals that satisfies an LPD density of 50 or less during epitaxial layer formation can be identified.

[0025] Meanwhile, according to the research of the present inventors, the relationship between the resistivity R (mΩ cm) at which diffusion of phosphorus from the substrate to the epitaxial layer is sufficiently suppressed when a silicon substrate is heat-treated in the device manufacturing process after the formation of an epitaxial layer, and the transit time Y (min) between 700°C or less and 600°C or more of the silicon single crystal corresponding to the silicon substrate can be defined by the following equation (2). Y≧5429×R 2 -9906×R+4569···(2) If this region is shown on a graph, the region of the silicon substrate and silicon single crystal where the diffusion of phosphorus from the substrate to the epitaxial layer is sufficiently suppressed can be identified, as shown in Figure 5. The judgment of whether the suppression of phosphorus diffusion passes or fails is made by measuring the epitaxial layer film thickness using FT-IR and determining the difference in film thickness before and after heat treatment. When phosphorus present in the substrate diffuses toward the epilayer, the phosphorus concentration in the epilayer increases, and this makes use of the phenomenon that the depth from the wafer surface at which the infrared rays of the FT-IR are reflected decreases. More specifically, if the difference in film thickness exceeds 0.5 μm, it is judged as failing, and if the difference in film thickness is 0.5 μm or less, it is judged as passing.

[0026] Moreover, the region that simultaneously satisfies the region of formula 1 and the region of formula 2 is shown in Figure 6. By setting the resistivity R (Ω) and the passage time Y (min) from 700°C to 600°C (electrical resistivity 0.7 mΩ·cm to 0.9 mΩ·cm) shown in the hatched region in Figure 6, it is possible to manufacture a silicon substrate that satisfies an LPD density of 50 or less during epitaxial layer formation and to suppress the diffusion of phosphorus from the substrate to the epitaxial layer during heat treatment in device manufacturing.

[0027] In the slicing and oxide film formation process (S2), the silicon single crystal is sliced, an oxide film is formed on the back side, and then mirror processing is performed. An oxide film with a thickness of 1 nm or less is formed on the mirror-finished substrate surface by cleaning. Specifically, it is preferable to treat the substrate with ozone water and form a chemical oxide film with a thickness of about 0.7 nm on the surface. As mentioned above, it is important that the oxide film on the substrate surface is stable in the subsequent low-temperature holding process (S4), and for this purpose an ozone oxide film is suitable.

[0028] In the furnace loading step (S3), the silicon substrate is loaded into an epitaxial growth furnace.

[0029] The low-temperature holding step (S4) introduces a step of holding the temperature at 750° C. or more and 1000° C. or less for 120 to 300 seconds after raising the temperature in the epitaxial growth furnace. This treatment enables the process of phosphorus dissolving from Si-P defects into the surrounding area and the dissolved phosphorus escaping from the substrate to occur continuously and in a steady state in the subsequent epitaxial film growth process, thereby reducing the increase in distortion in the substrate surface and further suppressing the occurrence of stacking faults.

[0030] In the etching step (S5), hydrogen chloride etching is performed at 1150° C. or more and less than 1200° C., and in the subsequent epitaxial growth step (S6), a Si epitaxial layer is formed at 1100° C. or more and 1150° C. or less.

[0031] As described above, in this embodiment, by adjusting the time for passing through the temperature range from 700°C or less to 600°C or more during silicon single crystal growth in accordance with the resistivity of each region of the silicon single crystal so as to satisfy formulas (1) and (2), it is possible to reduce the density of LPDs of 65 nm or more to 50 or less when forming an epitaxial layer on a silicon substrate, and also to suppress the diffusion of phosphorus from the substrate side to the epitaxial layer during heat treatment in device fabrication.

[0032] In the above embodiment, it has been described that a silicon epitaxial substrate is manufactured by the etching process of step S6 in the flow of Fig. 3. That is, steps S1 to S6 are one embodiment of the semiconductor substrate manufacturing method of the present invention for manufacturing a silicon epitaxial substrate. Moreover, the process from step S1 to step S2 is one embodiment of the semiconductor substrate of the present invention for manufacturing a silicon substrate, and the silicon substrate manufactured in this manner can obtain the above-mentioned effects when an epitaxial layer is subsequently formed on the surface. EXAMPLES

[0033] The method for manufacturing a semiconductor substrate according to the present invention will be further described with reference to an example. In this example, the following experiment was carried out based on the above-described embodiment.

[0034] (Experiment 1) In experiment 1, we investigated the relationship between the time the silicon single crystal passed between 600°C and 700°C, the electrical resistance (mΩ·cm) of the silicon substrate produced from the silicon single crystal, and the LPD density of 65 nm or more when an epitaxial layer was formed on the silicon substrate.

[0035] First, a phosphorus-doped silicon single crystal was grown by the Czochralski method. This silicon single crystal had a diameter of 200 mm, a crystal orientation of (001), and an oxygen concentration of 0.9E+18 atoms / cm. 3 It was decided. In addition, 36 conditions were set in which the resistivity R of the silicon substrate was within the range of 0.7 mΩ·cm or more and 0.9 mΩ·cm or less, and the passing time from 700°C to 600°C or more when the silicon single crystal was cooled was within the range of 40 min or more and 300 min or less, with different resistivities of the silicon epitaxial substrate and different passing times from 700°C to 600°C or more when the silicon single crystal was cooled. Specifically, the following parameters were adjusted to obtain the desired resistivity and oxygen concentration: furnace pressure 350-80 Torr, furnace argon gas flow rate 120-60 L / min, single crystal pulling speed 1.0-0.4 mm / min, horizontal magnetic field strength 2000-4000 Gauss.

[0036] After that, various silicon single crystals were sliced, an oxide film was formed on the back surface, and a mirror finish was applied.Furthermore, the semiconductor substrate was treated with 1 ppm ozone water to form a chemical oxide film with a thickness of 0.7 nm on the surface.

[0037] Thereafter, the substrate was placed in an epitaxial growth furnace, and the temperature condition in the low-temperature holding step prior to epitaxial growth was set to 850° C. and maintained for 180 seconds.

[0038] Further, hydrogen chloride etching was performed at 1150° C. or more and less than 1200° C., and then a Si epitaxial layer was formed again at 1100° C. or more and 1150° C. or less in the epitaxial growth furnace.

[0039] Next, the occurrence of stacking faults (i.e., the number of light point defects (LPDs)) was measured for silicon epitaxial substrates obtained from various single crystals. The graph in Figure 7 shows the relationship between the time it takes for the silicon single crystal to pass from 700°C to 600°C when it is cooled, the electrical resistivity of the silicon substrate, and the LPD density of the epitaxial layer. The vertical axis of Figure 7 is the time (min) for the silicon single crystal to pass from 700°C to 600°C, and the horizontal axis is the electrical resistivity (mΩ·cm) of the silicon substrate. Also, in Figure 7, cases where 50 or fewer LPDs with a density of 65 nm or greater were measured are marked with an ◯, and cases where more than 50 LPDs were measured are marked with an ×.

[0040] From the graph in Fig. 7, we obtained equation (1) that correlates the time (min): Y for the silicon single crystal to pass between 700°C and 600°C and the electrical resistivity (mΩ cm): R of the silicon substrate in order to define the range in which the density of LPDs 65 nm or larger is 50 or less. Y≦5000×R 2 -6730×R+2310···(1)

[0041] (Experiment 2) In experiment 2, we investigated the relationship between the time required for silicon single crystal to pass through temperatures below 700°C and above 600°C, the electrical resistivity (mΩ·cm) of the silicon epitaxial substrate, and phosphorus diffusion from the substrate to the epitaxial layer during heat treatment in device fabrication.

[0042] In experiment 2, 36 types of silicon single crystals were grown under the same conditions as in experiment 1, with different passing times between 700°C and 600°C for the silicon single crystals and different electrical resistivity (mΩ·cm) for the silicon epitaxial substrate. The epitaxial substrates obtained from the various single crystals were then used to measure the diffusion of phosphorus from the substrate to the epitaxial layer during heat treatment in device fabrication.

[0043] The graph in Figure 8 shows the relationship between the time that the silicon single crystal passed between 700°C and 600°C, the electrical resistivity of the silicon substrate, and the diffusion of phosphorus from the substrate to the epitaxial layer. The vertical axis of Figure 8 is the time that the silicon single crystal passed between 700°C and 600°C (min), and the horizontal axis is the electrical resistivity of the silicon epitaxial substrate (mΩ·cm). In Figure 8, the judgment of whether the suppression of phosphorus diffusion passed or failed was made by measuring the epitaxial layer thickness using FT-IR and determining the difference in thickness before and after heat treatment. When phosphorus present in the substrate diffuses to the epilayer side, the phosphorus concentration in the epilayer increases, and the depth from the wafer surface where the infrared rays of FT-IR are reflected decreases. More specifically, if the difference in thickness exceeds 0.5 μm, it is judged as failing (×), and if the difference in thickness is 0.5 μm or less, it is judged as passing (◯).

[0044] From the graph in Figure 8, we obtained equation (2) that correlates the time (min): Y from 700°C to 600°C when the silicon single crystal is cooled, and the electrical resistivity (mΩ cm): R of the silicon epitaxial substrate, in order to define the range in which phosphorus diffusion can be suppressed during heat treatment in device manufacturing. Y≧5429×R 2 -9906×R+4569 ···(2)

[0045] (Experiment 3) In experiment 3, the conditions set within the range of formula (1) obtained in experiment 1 and the range of formula (2) obtained in experiment 2 (electrical resistivity 0.8 mΩ cm or more and 0.9 mΩ cm or less) were used as an example, and conditions outside this range were used as comparison examples to verify whether it was possible to simultaneously achieve 50 or fewer LPDs of 65 nm or more in the epitaxial layer and suppress the diffusion of phosphorus during heat treatment in device manufacturing.

[0046] In experiment 3, 12 types of silicon single crystals were grown under the same conditions as in experiment 1, but with different cooling times from 600°C to below 700°C and different electrical resistivity (mΩ·cm) of the silicon epitaxial substrate. For the epitaxial substrates obtained from the various single crystals, the LPD density of 65 nm or more in the epitaxial layer was measured, as well as the diffusion of phosphorus into the epitaxial layer during heat treatment during device fabrication.

[0047] Tables 1 and 2 show the conditions and results of experiment 3. In Table 1, the LPD evaluation was rated as ◯ when the LPD density of 65 nm or more was 50 or less, and × when it exceeded 50. The phosphorus diffusion evaluation was determined by measuring the thickness of the epitaxial layer using FT-IR and judging from the difference in thickness before and after the heat treatment. If the difference in thickness exceeded 0.5 μm, it was judged as failing (×), and if the difference in thickness was 0.5 μm or less, it was judged as passing (◯).

[0048] [Table 1]

[0049] [Table 2]

[0050] As shown in Tables 1 and 2, Example 1-3 satisfied both the ranges of the above formulae (1) and (2), and both the LPD density evaluation and the phosphorus diffusion evaluation were ◯. On the other hand, Comparative Example 1-8 did not satisfy both the above formulae (1) and (2), and at least either the LPD density evaluation or the phosphorus diffusion evaluation was ×. Therefore, it was confirmed that by setting the conditions for the passing time (min) from 700°C to 600°C when the silicon single crystal is cooled and the electrical resistivity (mΩ cm) of the silicon epitaxial substrate within ranges that satisfy both of the above formulas (1) and (2) (passing time of 50 min to 280 min, electrical resistivity of 0.8 mΩ cm to 0.9 mΩ cm), it is possible to keep the number of LPDs of 65 nm or larger in the epitaxial layer to 50 or less and to suppress the diffusion of phosphorus from the substrate to the epitaxial layer during heat treatment in device fabrication. [Explanation of symbols]

[0051] 1 furnace 2. Silicon melt 3 Quartz crucible 4 Side heater 5 Bottom Heater 6 Radiation Shield 7 Wire 8 seed crystals 9 crystal 10 Epitaxial growth equipment 11. Chamber 12 Reactant gas supply pipe 13 Exhaust W Semiconductor substrates (silicon substrates, silicon epitaxial substrates)

Claims

1. A step of growing a silicon single crystal having an electrical resistivity of 0.9 mΩ cm or less by adding phosphorus as a dopant; and cutting a silicon substrate from the silicon single crystal. A method for manufacturing a semiconductor substrate, comprising controlling a passing time Y (min) of 700°C or less and 600°C or more in a silicon single crystal region in which the silicon substrate is located, the passing time Y (min) being within a range that satisfies formula (1) and formula (2). Y≦5000×R ２ -6730×R+2310・・・(1) Y≧5429×R ２ -9906×R+4569・・・(2)

2. A step of growing a silicon single crystal having an electrical resistivity of 0.9 mΩ cm or less by adding phosphorus as a dopant; cutting a silicon substrate from the silicon single crystal; forming an epitaxial film on the surface of the silicon substrate, the epitaxial film having a density of 50 or less light point defects of 65 nm or more; A method for manufacturing a semiconductor substrate, comprising controlling a passing time Y (min) of 700°C or less and 600°C or more in a silicon single crystal region in which the silicon substrate is located, the passing time Y (min) being within a range that satisfies formula (1) and formula (2). Y≦5000×R ２ -6730×R+2310・・・(1) Y≧5429×R ２ -9906×R+4569・・・(2)

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