Voltage regulator and semiconductor device

Abstract

To provide a voltage regulator capable of suppressing the generation of an excessive voltage at an output terminal when a bonding wire of a voltage regulating terminal breaks.SOLUTION: The voltage regulator is provided with an output transistor M1 having a source connected to an input terminal VI and a drain connected to an output terminal VO, voltage-division resistors R1 and R2 connected between a voltage regulation terminal VA and a ground terminal and dividing an adjustment voltage VADJ input to the voltage regulation terminal VA to output a feedback voltage Vfb, a reference voltage circuit 20 for outputting a reference voltage Vref, an error amplifier circuit 10 for controlling a gate voltage of the output transistor M1 based on the reference voltage Vref and the feedback voltage Vfb, and a disconnection protection circuit for detecting a disconnection of a bonding wire W3 of the voltage regulation terminal VA, which comprises a first MOS transistor M2 having a source connected to the output terminal VO and a gate connected to the voltage regulation terminal VA.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a voltage regulator and a semiconductor device.

Background Art

[0002] Generally, a voltage regulator generates a constant voltage from a power supply voltage input to an input terminal and outputs the constant voltage to an output terminal. Then, even when the power supply voltage or the load current fluctuates, the output voltage is maintained at a constant value. In order to guarantee the accuracy of the output voltage when the output current is large, a voltage regulator provided with a feedback voltage terminal separate from the output terminal is known.

[0003] FIG. 5 shows a conventional voltage regulator and semiconductor device provided with a feedback voltage terminal.

[0004] The conventional voltage regulator 51 includes an operational amplifier OP1, an output transistor M1, voltage dividing resistors R1 and R2, a protection resistor Rp1, an input terminal Pi1, an output terminal Po1, and a feedback voltage terminal Pf1.

[0005] The semiconductor device 52 includes an input terminal Pi2 and an output terminal Po2. The output terminal Po2 is connected to the output terminal Po1 and the feedback voltage terminal Pf1 of the voltage regulator, and supplies a voltage to the load LD.

[0006] Since the feedback voltage terminal Pf1 is connected to the output terminal Po2, it is not affected by the output current and the voltage drop due to the bonding wire like the output terminal Po1, and the voltage of the output terminal Po2 is input.

[0007] The protection resistor Rp1 is connected between the output terminal Po1 and the feedback voltage terminal Pf1, and acts to limit the output voltage to a predetermined voltage when the bonding wire of the feedback voltage terminal Pf1 is disconnected (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0008] Patent Document 1 Japanese Patent Application Laid-Open No. 2004-128329 Summary of the Invention Problems to be Solved by the Invention

[0009] However, in a conventional voltage regulator, when the bonding wire of the feedback voltage terminal Rf1 is disconnected, since the protection resistor Rp1 is connected in series with the voltage dividing resistor, there is a problem that the output voltage becomes higher than the desired voltage value.

[0010] In view of the above circumstances, an object of the present invention is to provide a voltage regulator capable of suppressing the generation of an excessive voltage at the output terminal when the bonding wire of the feedback voltage terminal is disconnected. Means for Solving the Problems

[0011] A voltage regulator according to an embodiment of the present invention is a voltage regulator that inputs an input voltage from an input terminal and outputs an output voltage to an output terminal, and includes an output transistor having a source connected to the input terminal and a drain connected to the output terminal, a voltage dividing resistor connected between a voltage adjustment terminal and a ground terminal for dividing an adjustment voltage input to the voltage adjustment terminal and outputting a feedback voltage, a reference voltage circuit for outputting a reference voltage, an error amplification circuit for controlling a gate voltage of the output transistor based on the reference voltage and the feedback voltage, and a first MOS transistor having a source connected to the output terminal and a gate connected to the voltage adjustment terminal, and a disconnection protection circuit for detecting that the bonding wire of the voltage adjustment terminal is disconnected. Effects of the Invention

[0012] According to the present invention, since it has a first MOS transistor with a source connected to an output terminal and a gate connected to a voltage adjustment terminal, and includes a disconnection protection circuit for detecting that the bonding wire of the voltage adjustment terminal is disconnected, it is possible to provide a voltage regulator that can suppress the generation of an excessive voltage at the output terminal when the voltage adjustment terminal is disconnected.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0014] Hereinafter, the voltage regulator 1 and the semiconductor device 100 according to the embodiment of the present invention will be described with reference to the drawings.

[0015] FIG. 1 is a circuit diagram of the voltage regulator 1 and the semiconductor device 100 according to this embodiment.

[0016] The voltage regulator 1 includes an input terminal VI, an output terminal VO, a voltage adjustment terminal VA, an error amplification circuit 10, a reference voltage circuit 20, resistors R1 and R2 which are voltage dividing resistors, an output transistor M1, and a MOS transistor M2 which is a disconnection protection circuit.

[0017] The output transistor M1 has its source connected to the input terminal VI, its drain connected to the output terminal VO, and its gate connected to the output terminal of the error amplification circuit 10. The error amplification circuit 10 has its inverting input terminal - connected to the output terminal of the reference voltage circuit 20, and its non-inverting input terminal + connected to the connection point of resistor R1 and resistor R2 (the output terminal of the voltage dividing resistors). Resistors R1 and R2 are connected in series between the voltage adjustment terminal VA and the ground terminal. The MOS transistor M2 has its source connected to the output terminal VO, its drain connected to the output terminal of the voltage dividing resistors, and its gate connected to the voltage adjustment terminal VA.

[0018] The semiconductor device 100 includes an input terminal VIp and an output terminal VOp. The input terminal VIp is connected to the input terminal VI of the voltage regulator 1 by a bonding wire W1. The output terminal VOp is connected to the output terminal VO of the voltage regulator 1 by a bonding wire W2, and is further connected to the voltage adjustment terminal VA by a bonding wire W3, and supplies the output voltage VOUT to the load LD.

[0019] Since the voltage adjustment terminal VA is connected to the output terminal VOp, it is not affected by the voltage drop due to the output current and the wiring resistance of the bonding wire W2 like the output terminal VO, and the voltage of the output terminal VOp is input.

[0020] The operation of the voltage regulator 1 will be described.

[0021] The voltage regulator 1 generates a constant voltage from the input voltage VIN input to the input terminal VI and outputs it as the output voltage VOUT from the output terminal VO. Resistors R1 and R2 generate a feedback voltage Vfb from the adjustment voltage VADJ input from the voltage adjustment terminal VA. The error amplification circuit 10 controls the gate voltage of the output transistor M1 based on the reference voltage Vref output by the reference voltage circuit 20 and the feedback voltage Vfb. That is, the output voltage VOUT of the voltage regulator 1 is controlled to a voltage at which the feedback voltage Vfb becomes equal to the reference voltage Vref.

[0022] Next, the operation when the bonding wire W3 connected to the voltage adjustment terminal VA is disconnected will be described.

[0023] When the bonding wire W3 connected to the voltage adjustment terminal VA is disconnected, the adjustment voltage VADJ and the feedback voltage Vfb drop to the voltage of the ground terminal. The error amplification circuit 10 controls the gate voltage of the output transistor M1 to decrease so that the output voltage VOUT increases.

[0024] At this time, when the gate-source voltage of the MOS transistor M2 becomes equal to or higher than the threshold voltage due to the increase in the output voltage VOUT as the source voltage and the decrease in the adjustment voltage VADJ as the gate voltage, the MOS transistor M2 turns on. When the MOS transistor M2 turns on, the feedback voltage Vfb increases to the output voltage VOUT.

[0025] The error amplification circuit 10 controls the gate voltage of the output transistor M1 so that the feedback voltage Vfb input to the non-inverting input terminal + becomes equal to the reference voltage Vref of the reference voltage circuit 20 input to the inverting input terminal -. Therefore, the output voltage VOUT becomes equal to the reference voltage Vref and stabilizes.

[0026] Therefore, the voltage regulator 1 according to the present embodiment can suppress the generation of an excessive voltage at the output terminal VO when the bonding wire W3 connected to the voltage adjustment terminal VA is disconnected.

[0027] Also, the disconnection protection circuit does not interfere with the operation of the voltage regulator 1 during normal operation.

[0028] First, before the voltage regulator 1 is started, since both the output voltage VOUT and the adjustment voltage VADJ are at a low voltage, the MOS transistor M2 does not turn on.

[0029] Next, when the voltage regulator 1 is activated, as the output voltage VOUT increases, the adjustment voltage VADJ also increases, so the MOS transistor M2 does not turn on. At this time, the threshold voltage of the MOS transistor M2 may be set to be equal to or lower than the voltage drop from the output voltage VOUT at startup.

[0030] Figure 2 is a circuit diagram showing another example of the disconnection protection circuit of the voltage regulator 1 of the present embodiment.

[0031] The disconnection protection circuit of Figure 2 includes MOS transistors M2, M3, M4, M5, and M6. The depletion-type MOS transistor M3, which is a current source, is provided between the drain of the MOS transistor 2 and the ground terminal and functions as a pull-down element. The source of the MOS transistor M4 is connected to the ground terminal, and the gate is connected to the drain of the MOS transistor 2. The MOS transistors M5 and M6 form a current mirror circuit and control the voltage of the gate of the output transistor M1 connected to the output terminal according to the current flowing through the MOS transistor M4 connected to the input terminal.

[0032] The operation when the bonding wire W3 connected to the voltage adjustment terminal VA is disconnected will be described.

[0033] When the bonding wire W3 connected to the voltage adjustment terminal VA is disconnected, the adjustment voltage VADJ and the feedback voltage Vfb drop to the voltage of the ground terminal. The error amplification circuit 10 controls the gate voltage of the output transistor M1 to decrease so that the output voltage VOUT increases.

[0034] At this time, when the gate-source voltage of the MOS transistor M2 becomes equal to or higher than the threshold voltage due to the increase in the output voltage VOUT which is the source voltage and the decrease in the adjustment voltage VADJ which is the gate voltage, the MOS transistor M2 turns on. When the MOS transistor M2 turns on, the MOS transistor M4, which has been pulled down by the current of the MOS transistor M3, turns on because its gate voltage increases. Therefore, the MOS transistor M4 increases the gate voltage of the output transistor M1 via the current mirror circuits of the MOS transistors M5 and M6, and controls the output voltage VOUT to decrease.

[0035] Since the gate voltage of the MOS transistor M2 is the ground voltage, the MOS transistor M2 turns off when the output voltage VOUT which is the source voltage becomes higher than the threshold voltage. Therefore, the output voltage VOUT stabilizes at a voltage higher than the ground voltage by the threshold voltage of the MOS transistor M2.

[0036] Therefore, the voltage regulator 1 according to the present embodiment can suppress the occurrence of an excessive voltage at the output terminal VO when the bonding wire W3 connected to the voltage adjustment terminal VA is disconnected.

[0037] Also, the disconnection protection circuit does not interfere with the operation of the voltage regulator 1 during normal operation.

[0038] First, before the voltage regulator 1 is started, since both the output voltage VOUT and the adjustment voltage VADJ are low voltages, the MOS transistor M2 is off, and the MOS transistor M4 is not turned on by the current of the MOS transistor M3 either.

[0039] Next, when the voltage regulator 1 is started, as the output voltage VOUT increases, the adjustment voltage VADJ also increases, so the MOS transistor M2 does not turn on. At this time, the threshold voltage of the MOS transistor M2 may be set to be equal to or lower than the voltage drop from the output voltage VOUT at startup.

[0040] FIG. 3 is a circuit diagram showing another example of the disconnection protection circuit of the voltage regulator 1 according to the present embodiment.

[0041] The voltage regulator 1 in FIG. 3 is configured by dividing the resistor R1 into a series connection of a resistor R1a and a resistor R1b in the voltage regulator 1 in FIG. 2. And the MOS transistor M2 has its gate connected to the connection point of the resistors R1a and R1b. When the disconnection protection circuit is configured in this way, when the bonding wire W3 is disconnected, the MOS transistor M2 turns on quickly, so that an overshoot of the output voltage VOUT can be suppressed.

[0042] FIG. 4 is a circuit diagram showing another example of the disconnection protection circuit of the voltage regulator 1 according to the present embodiment.

[0043] The disconnection protection circuit in FIG. 4 is configured such that the MOS transistors M5 and M6 constituting the current mirror circuit in the disconnection protection circuits in FIGS. 2 and 3 are shared as the active load of the error amplifier circuit 10. With this configuration, the number of elements can be reduced, so that the voltage regulator 1 can have a smaller area.

[0044] As described above, according to the voltage regulator 1 of the present embodiment, since the disconnection protection circuit is provided at the voltage adjustment terminal VA, even if the bonding wire W3 connected to the voltage adjustment terminal VA is disconnected, an excessive voltage is generated at the output terminal VO of the voltage regulator 1. can be suppressed.

[0045] Note that the present invention is not limited to the above-described embodiments as they are, and can be implemented in various forms. And various omissions, additions, replacements, or changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

[0046] For example, a plurality of resistors R1 in FIG. 3 may be connected in series, and the gate of the first MOS transistor may be connected to an arbitrary connection point of the resistor R1.

Description of symbols

[0047] 1 Voltage regulator 10 Error amplification circuit 20 Reference voltage circuit R1, R2 Resistors (voltage dividing resistors) M1 Output transistor M2 Disconnection protection circuit M3 Constant current source M4, M5, M6, M7, M8 MOS transistors VI Input terminal VIp Input terminal pin VO Output terminal VOp Output terminal pin VA Voltage adjustment terminal W1, W2, W3 Bonding wires 100 Semiconductor device

Claims

1. A voltage regulator that receives an input voltage from an input terminal and outputs an output voltage to an output terminal, comprising: An output transistor having a source connected to the input terminal and a drain connected to the output terminal; A voltage dividing resistor connected between a voltage adjustment terminal and a ground terminal, for dividing the adjustment voltage input to the voltage adjustment terminal and outputting a feedback voltage; A reference voltage circuit for outputting a reference voltage; An error amplification circuit for controlling the gate voltage of the output transistor based on the reference voltage and the feedback voltage; A disconnection protection circuit comprising a first MOS transistor having a source connected to the output terminal and a gate connected to the voltage adjustment terminal, for detecting that the bonding wire of the voltage adjustment terminal is disconnected; A voltage regulator characterized by comprising the above.

2. The disconnection protection circuit: Has the drain of the first MOS transistor connected to the output terminal of the voltage dividing resistor; When detecting that the bonding wire is disconnected, it drops the output voltage to the reference voltage. The voltage regulator according to claim 1, characterized by the above.

3. The disconnection protection circuit: A current source connected between the drain of the first MOS transistor and the ground terminal; A second MOS transistor having a gate connected to the drain of the first MOS transistor and a source connected to the ground terminal; A current mirror circuit having an input terminal connected to the drain of the second MOS transistor and an output terminal connected to the gate of the output transistor. When detecting that the bonding wire is disconnected, it drops the output voltage from the ground voltage to a voltage that is higher than the threshold voltage of the first MOS transistor by the threshold voltage. The voltage regulator according to claim 1, characterized by the above.

4. The voltage dividing resistor is configured by connecting a plurality of first resistors in series between the voltage adjustment terminal and the output terminal of the voltage dividing resistor, and the gate of the first MOS transistor is connected to an arbitrary connection point of the first resistors. The voltage regulator according to claim 3, characterized by the above.

5. The current mirror circuit is configured to share an active load of the error amplification circuit. The voltage regulator according to claim 3, characterized by the above.

6. The input terminal of the voltage regulator according to any one of claims 1 to 5 is connected to an input pin, and the output terminal and the voltage adjustment terminal are connected to an output pin. A semiconductor device characterized by...

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