Semiconductor device manufacturing method and inspection system

Abstract

To provide a semiconductor device manufacturing method and an inspection system capable of identifying the location of crystal defects that may cause the expansion of stacking faults.SOLUTION: A method for manufacturing a semiconductor device includes the steps of preparing a substrate having a semiconductor substrate and a semiconductor layer formed on the semiconductor substrate, expanding stacking faults originating from crystal defects contained in the semiconductor substrate into the semiconductor layer, detecting the stacking faults that have expanded into the semiconductor layer and identifying the positions of the crystal defects that are the origins of the stacking faults, and, reducing the stacking faults that have expanded into the semiconductor layer after the step of identifying the positions of the crystal defects.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and an inspection system.

Background Art

[0002] As a substrate of a semiconductor device, an epitaxial substrate in which a semiconductor layer is epitaxially grown on a semiconductor substrate may be used.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a semiconductor device including an epitaxial substrate, stacking defects starting from crystal defects in the semiconductor substrate may expand into the semiconductor layer, resulting in failure to obtain predetermined characteristics.

[0005] An object of the present disclosure is to provide a method for manufacturing a semiconductor device and an inspection system capable of specifying the position of a crystal defect from which stacking defect expansion can occur.

Means for Solving the Problems

[0006] The method for manufacturing a semiconductor device according to the present disclosure includes a step of preparing a substrate having a semiconductor substrate and a semiconductor layer formed on the semiconductor substrate, a step of expanding stacking defects starting from crystal defects included in the semiconductor substrate into the semiconductor layer, a step of detecting the stacking defects expanded in the semiconductor layer and specifying the position of the crystal defects that are the starting points of the stacking defects, and a step of reducing the stacking defects expanded in the semiconductor layer after the step of specifying the position of the crystal defects.

Effects of the Invention

[0007] According to the present disclosure, it is possible to identify the positions of crystal defects where the expansion of stacking defects can occur.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Embodiments for carrying out will be described below.

[0010] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [], collective orientations by <>, individual planes by (), and collective planes by {}. Also, a negative crystallographic index is usually expressed by attaching "-" (bar) above the number, but in the present disclosure, a negative sign is attached before the number.

[0011] 〔1〕 A method for manufacturing a semiconductor device according to an aspect of the present disclosure includes a step of preparing a substrate having a semiconductor substrate and a semiconductor layer formed on the semiconductor substrate, a step of expanding a stacking defect starting from a crystal defect contained in the semiconductor substrate into the semiconductor layer, a step of detecting the stacking defect expanded in the semiconductor layer and specifying the position of the crystal defect that is the origin of the stacking defect, and a step of reducing the stacking defect expanded in the semiconductor layer after the step of specifying the position of the crystal defect.

[0012] Since the stacking defect is expanded starting from the crystal defect, the position of the crystal defect where the expansion of the stacking defect can occur in the substrate after the semiconductor device is manufactured can be specified. Also, after specifying the position of the crystal defect, in order to reduce the stacking defect, a change in the characteristics of the semiconductor device based on the remaining stacking defect can be suppressed.

[0013] 〔2〕 In 〔1〕, the semiconductor substrate may be a silicon carbide single crystal substrate. Since a silicon carbide single crystal substrate is likely to contain crystal defects such as basal plane dislocations, specifying the position of the crystal defect is particularly effective.

[0014] 〔3〕 In 〔1〕 or 〔2〕, the step of expanding the stacking defect may include a step of setting the temperature of the substrate to a first temperature and irradiating the substrate with light at a first intensity, and the step of reducing the stacking defect may include a step of setting the temperature of the substrate to a second temperature higher than the first temperature and irradiating the substrate with light at a second intensity lower than the first intensity. In this case, it is easy to control the expansion and reduction of the stacking defect.

[0015] [4] In any one of [1] to [3], the substrate may have a plurality of chip regions, and a step of determining a chip region in which the ratio of the area of the stacking defect starting from the crystal defect in the chip region to the area of the chip region exceeds 5% in total as a defective chip region. In this case, it is easy to select a chip region in which characteristics are likely to change due to energization or the like.

[0016] [5] In any one of [1] to [4], a step of specifying the crystal orientation of the substrate based on the stacking defect extended in the semiconductor layer may be included. In this case, it is easy to manufacture a semiconductor device with higher accuracy.

[0017] [6] An inspection system according to another aspect of the present disclosure includes an expansion unit that expands a stacking defect starting from a crystal defect included in a semiconductor substrate of a substrate having a semiconductor substrate and a semiconductor layer formed on the semiconductor substrate into the semiconductor layer, a specifying unit that detects the stacking defect expanded in the semiconductor layer and specifies the position of the crystal defect that was the starting point of the stacking defect, and a reducing unit that reduces the stacking defect expanded in the semiconductor layer.

[0018] The expansion unit expands a stacking defect starting from a crystal defect, and the specifying unit can specify the position of the crystal defect where the stacking defect may expand in the substrate after the semiconductor device is manufactured. Further, after specifying the position of the crystal defect, by reducing the stacking defect by the reducing unit, it is possible to suppress a change in the characteristics of the semiconductor device based on the remaining stacking defect.

[0019] [Embodiment of the Present Disclosure] An embodiment of the present disclosure relates to an inspection system used in the manufacturing process of a semiconductor device. FIG. 1 is a diagram showing an inspection system according to the embodiment.

[0020] As shown in FIG. 1, an inspection system 1 according to the embodiment includes an expansion unit 10, a specifying unit 20, and a reducing unit 30.

[0021] The extension part 10 has, for example, a light irradiation device 11. The light irradiation device 11 has a heater 12 for heating the substrate 50 and a light source 13 for irradiating the substrate 50 with light. The heater 12 may be built in a chuck for fixing the substrate 50.

[0022] The specifying part 20 has, for example, a photoluminescence measurement device 21 and an image processing device 22. The photoluminescence measurement device 21 acquires a photoluminescence image of the substrate 50, and the image processing device 22 analyzes the photoluminescence image. Instead of the photoluminescence measurement device 21, a confocal optical microscope may be used, and the image processing device 22 may analyze an optical microscope image.

[0023] The reduction part 30 has, for example, a light irradiation device 31. The light irradiation device 31 has a heater 32 for heating the substrate 50 and a light source 33 for irradiating the substrate 50 with light. The heater 32 may be built in a chuck for fixing the substrate 50.

[0024] Next, a method for manufacturing a semiconductor device using the inspection system 1 will be described. FIG. 2 is a flowchart showing the method for manufacturing a semiconductor device. FIGS. 3 to 5 are top views showing the method for manufacturing a semiconductor device. FIGS. 6 to 8 are cross-sectional views showing the method for manufacturing a semiconductor device.

[0025] First, prepare a substrate 50 (step S1). In preparing the substrate 50, as shown in FIGS. 3 and 6, a semiconductor layer 52 is formed on a semiconductor substrate 51. For example, the semiconductor substrate 51 is a silicon carbide single crystal substrate, and the semiconductor layer 52 is a silicon carbide single crystal layer. The semiconductor substrate 51 has a main surface 51A. The main surface 51A is, for example, a surface in which the (000-1) plane is inclined by an off-angle of 8° or less in the off direction. The off direction may be, for example, the [11-20] direction or the [1-100] direction. The off-angle may be, for example, 1° or more, or 2° or more. The off-angle may be 6° or less, or 4° or less. The semiconductor layer 52 can be formed by epitaxial growth on the main surface 51A and inherits the crystal orientation of the semiconductor substrate 51. Also, an orientation flat 59 is formed on the substrate 50. For example, the orientation flat 59 is formed to include a (1-100) plane perpendicular to the [1-100] direction. Depending on the off direction, it is parallel to the [11-20] direction on the main surface 51A or parallel to a direction inclined by an off-angle from the [11-20] direction. The substrate 50 is provided with a plurality of chip regions 55. The chip regions 55 are arranged vertically and horizontally in a plan view perpendicular to the main surface 51A. A plurality of semiconductor devices can be obtained by singulating the substrate 50 along the dicing region between adjacent chip regions 55. FIGS. 3 to 5 typically illustrate only four chip regions 55.

[0026] As shown in FIG. 6, the semiconductor substrate 51 includes crystal defects 53 that reach the main surface 51A. The crystal defects 53 are basal plane dislocations such as edge dislocations. The crystal defects 53 are within the (000-1) plane, but in FIGS. 6 to 8, the off-angle is exaggerated.

[0027] After preparing the substrate 50, the substrate 50 is transported to the expansion unit 10. Then, as shown in FIGS. 4 and 7, a stacking defect 54 starting from a crystal defect 53 is expanded in the semiconductor layer 52 in the light irradiation device 11 of the expansion unit 10 (step S2). For example, the temperature of the substrate 50 is set to a first temperature by the heater 12, and the substrate 50 is irradiated with light at a first intensity. As the light, light having an energy higher than the band gap of the material constituting the semiconductor layer 52 is used. When the semiconductor layer 52 is made of polytype 4H hexagonal silicon carbide, for example, ultraviolet light, X-rays, or electron beams are used as the light. For example, when ultraviolet light is used as the light, the first temperature is 80° C. or higher and 150° C. or lower, and the first intensity is 5 W / cm 2 or more and 50 W / cm 2 or less.

[0028] The stacking defect 54 expands according to the crystal orientation of the semiconductor layer 52. For example, some of the stacking defects 54 expand to form a quadrilateral such as a parallelogram having a side with a long side parallel to the [1-100] direction in plan view, and other stacking defects 54 expand to form a triangle in plan view. Note that when the stacking defect 54 expands to a certain size, the expansion of the stacking defect 54 saturates.

[0029] Next, the substrate 50 is transported to the specific unit 20. Then, the stacking defect 54 expanded in the semiconductor layer 52 is detected, and the position of the crystal defect 53 that is the starting point of the stacking defect 54 is specified (step S3). For example, a photoluminescence image of the substrate 50 is acquired by the photoluminescence measurement device 21, and the photoluminescence image is analyzed by the image processing device 22. In this analysis, the stacking defect 54 expanded in the semiconductor layer 52 is detected, and the position of the crystal defect 53 that is the starting point of the stacking defect 54 is specified. The crystal defect 53 is located at the apex of the triangle or quadrilateral of the stacking defect 54. When it is not possible to specify which apex among the plurality of apexes has the crystal defect 53, it may be regarded that the crystal defect 53 exists at all the apexes. FIG. 9 is a diagram showing an example of a chip region 55 including the stacking defect 54.

[0030] Next, the substrate 50 is conveyed to the reduction unit 30. Then, as shown in FIGS. 5 and 8, the stacking defect 54 is reduced in the light irradiation device 31 of the reduction unit 30 (step S4). The stacking defect 54 in the semiconductor layer 52 may be eliminated. For example, the temperature of the substrate 50 is set to a second temperature by the heater 32, and the substrate 50 is irradiated with light at a second intensity. As the light, light having an energy higher than the band gap of the material constituting the semiconductor layer 52 is used. When the semiconductor layer 52 is made of polytype 4H hexagonal silicon carbide, for example, ultraviolet light, X-rays, or electron beams are used as the light. The second temperature is higher than the first temperature, and the second intensity is lower than the first intensity. For example, when ultraviolet light is used as the light, the second temperature is 150°C or higher and 250°C or lower, and the second intensity is 0.01 W / cm 2 or more and 1 W / cm 2 or less.

[0031] Next, ion implantation into the semiconductor layer 52, formation of electrodes, formation of insulating films, etc. are performed (step S5). Next, singulation along the dicing region is performed (step S6).

[0032] In this way, a plurality of semiconductor devices can be manufactured.

[0033] According to the present embodiment, the position of the crystal defect 53 where the expansion of the stacking defect 54 occurs in the substrate 50 can be specified. Further, after specifying the position of the crystal defect 53, since the stacking defect 54 is reduced, a change in characteristics based on the stacking defect 54 can be suppressed. It is also possible to specify a semiconductor device including such a crystal defect 53 from among a plurality of semiconductor devices.

[0034] Since a silicon carbide single crystal substrate is likely to contain crystal defects such as basal plane dislocations, when the semiconductor substrate 51 is a silicon carbide single crystal substrate, specifying the position of the crystal defect 53 is particularly effective.

[0035] In a semiconductor device including a crystal defect 53 that is the origin of a stacking defect 54, although the stacking defect 54 is reduced, the stacking defect 54 expands starting from the crystal defect 53 while energization is repeated during a test or actual operation, and depending on the degree of the stacking defect 54, there is a possibility that predetermined characteristics cannot be obtained. Therefore, in step S3, not only the position of the crystal defect 53 that is the origin of the stacking defect 54 is specified, but also for each chip region 55, the total area S11 of the stacking defects 54 starting from the crystal defects 53 within the chip region 55 may be obtained. Then, the ratio (S11 / S10×100(%)) of the area S11 to the area S10 of the chip region 55 is calculated, and when this ratio exceeds a predetermined threshold value, the chip region 55 may be determined as a defective chip region. By making such a determination, it is possible to identify a semiconductor device in which there is a high possibility that predetermined characteristics cannot be obtained without performing a test after manufacturing. For example, the threshold value is 5%. When the threshold value is 5%, it is easy to select the chip region 55 in which the characteristics are likely to change due to energization or the like. The threshold value may be 4% or may be 3%.

[0036] FIG. 10 is a diagram showing an example of the relationship between the ratio R of the total area of stacking defects in a transistor and the shift amount ΔVDS of the source-drain voltage. As shown in FIG. 10, the shift amount ΔVDS increases as the ratio R increases, and when the ratio R is 5% or less, the shift amount ΔVDS is 0.1V or less.

[0037] Note that the area of the stacking defect 54 can be measured as follows. In the photoluminescence measurement device 21, the stacking defect 54 in the photoluminescence image can be displayed with a white contrast by filtering only the emission wavelength caused by the stacking defect 54. Next, the boundary line of the black-and-white contrast is obtained by image processing, and the area of the stacking defect 54 can be obtained by calculating the white area. Also, by calculating the shape of the white region for each type such as a triangle or a trapezoid, the area can be obtained for each stacking defect 54 with a different expansion method.

[0038] The same light irradiation device may be used between the expansion part 10 and the reduction part 30. Also, the expansion and reduction of the stacking defect vary depending on the temperature and the intensity of the irradiated light. FIG. 11 is a diagram showing an example of the conditions under which the stacking defect expands and the conditions under which it contracts when irradiated with ultraviolet rays. As shown in FIG. 11, when comparing the first condition 61 under which the stacking defect expands and the second condition 62 under which it contracts, if the intensity of the ultraviolet rays is the same, the temperature is higher under the second condition 62 than under the first condition 61, and if the temperature is the same, the intensity of the ultraviolet rays is lower under the second condition 62 than under the first condition 61. Therefore, when the second temperature is higher than the first temperature and the second intensity is lower than the first intensity, it is easy to control the expansion and contraction of the stacking defect 54.

[0039] In step S3, not only the position of the crystal defect 53 that is the starting point of the stacking defect 54 is specified, but the crystal orientation of the substrate 50 may also be specified based on the stacking defect 54. The approximate crystal orientation of the substrate 50 can be specified by the orientation flat 59. However, since the orientation flat 59 is formed by machining, some deviation may occur. In contrast, the stacking defect 54 expands so as to reflect the crystal orientation of the substrate 50. Therefore, even if there is some deviation in the orientation flat 59, the substrate orientation can be accurately specified based on the stacking defect 54. Then, if ion implantation or the like is performed later based on the crystal orientation specified based on the stacking defect 54, a semiconductor device with higher precision can be manufactured.

[0040] In step S3, although the crystal defect 53 is located at the vertex of the triangle or quadrilateral of the stacking defect 54, if it cannot be specified which vertex it is, it may be regarded that the crystal defect 53 exists at all vertices. Also, as described above, when the stacking defect 54 expands to a certain size, the expansion of the stacking defect 54 saturates. Therefore, the stacking defect 54 may be expanded under the condition that the expansion of the stacking defect 54 reaches saturation and the condition that it does not reach saturation, and the vertex that coincides under both conditions may be set as the position of the crystal defect 53.

[0041] Although the embodiments have been described in detail above, the present disclosure is not limited to specific embodiments, and various modifications and changes are possible within the scope described in the claims.

Explanation of Signs

[0042] 1 Inspection system 10 Extension part 11 Light irradiation device 12 Heater 13 Light source 20 Specific part 21 Photoluminescence measurement device 22 Image processing device 30 Reduction part 31 Light irradiation device 32 Heater 33 Light source 50 Substrate 51 Semiconductor substrate 51A Main surface 52 Semiconductor layer 53 Crystal defect 54 Lamination defect 55 Chip area 59 Orientation flat

Claims

1. A step of preparing a substrate having a semiconductor substrate and a semiconductor layer formed on the semiconductor substrate; A step of expanding a stacking defect starting from a crystal defect contained in the semiconductor substrate into the semiconductor layer; A step of detecting the stacking defect expanded in the semiconductor layer and specifying the position of the crystal defect that is the origin of the stacking defect; After the step of specifying the position of the crystal defect, a step of reducing the stacking defect expanded in the semiconductor layer; A method for manufacturing a semiconductor device, comprising:

2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon carbide single crystal substrate.

3. The step of expanding the stacking defect includes a step of setting the temperature of the substrate to a first temperature and irradiating the substrate with light at a first intensity; The step of reducing the stacking defect includes a step of setting the temperature of the substrate to a second temperature higher than the first temperature and irradiating the substrate with light at a second intensity lower than the first intensity. The method for manufacturing a semiconductor device according to claim 1 or claim 2.

4. The substrate has a plurality of chip regions, A step of determining a defective chip region in which the ratio of the area of the stacking defect starting from the crystal defect in the chip region to the area of the chip region exceeds 5% in total. The method for manufacturing a semiconductor device according to claim 1 or claim 2.

5. The method for manufacturing a semiconductor device according to claim 1 or claim 2, further comprising a step of specifying the crystal orientation of the substrate based on the stacking defect expanded in the semiconductor layer.

6. An expansion unit that expands a stacking defect starting from a crystal defect contained in the semiconductor substrate of a substrate having a semiconductor substrate and a semiconductor layer formed on the semiconductor substrate into the semiconductor layer; A specifying unit that detects the stacking defect expanded in the semiconductor layer and specifies the position of the crystal defect that is the origin of the stacking defect; A reducing unit that reduces the stacking defect expanded in the semiconductor layer; An inspection system, comprising:

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