Semiconductor device and manufacturing method of them

Abstract

To provide a semiconductor device having a super junction structure, capable of providing a technique for suppressing an imbalance of a charge of a super junction structure.SOLUTION: A semiconductor device 1 comprises: a first super junction layer 13 that contains a super junction structure in which a first conductive column 13a and a second conductive column 13b are repeatedly and alternately arranged along at least one direction; and an epitaxial layer 100 to be laminated onto the first super junction layer. The epitaxial layer is arranged at a position to be exposed to the lower surface of the epitaxial layer, and includes a second super junction layer 102 containing the super junction structure in which a first conductive region 14a and a second conductive region 17 are alternately and repeatedly arranged along at least one direction. Both of the first conductive region and the second conductive region of the second super junction layer are a diffusion region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] As a structure that achieves both low on-resistance and high breakdown voltage, a super junction structure in which n-type columns and p-type columns are alternately and repeatedly arranged along at least one direction has been proposed. Patent Document 1 discloses an example of a semiconductor device having such a super junction structure.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When manufacturing a semiconductor device having a super junction structure, an epitaxial layer may be grown on the super junction structure, and various diffusion regions may be formed in the epitaxial layer. If the thickness of the epitaxial layer is formed thinner than the design value due to manufacturing variations, a part of the diffusion region formed in the epitaxial layer may be formed so as to overlap the super junction structure. In this case, the charge balance of the super junction structure is disrupted, and there is a concern about a decrease in the breakdown voltage of the semiconductor device. This specification provides a technology capable of suppressing the disruption of the charge balance of the super junction structure in a semiconductor device having a super junction structure.

Means for Solving the Problems

[0005] The semiconductor device disclosed in this specification may include a first superjunction layer (13) including a superjunction structure in which first conductivity type columns (13a) and second conductivity type columns (13b) are alternately repeated along at least one direction, and an epitaxial layer (100) stacked on the first superjunction layer. The epitaxial layer may be disposed at a position exposed on the lower surface of the epitaxial layer and may have a second superjunction layer (102) including a superjunction structure in which first conductivity type regions (14a) and second conductivity type regions (17) are alternately repeated along at least one direction. The first conductivity type region and the second conductivity type region of the second superjunction layer may be diffusion regions. When the thickness of the epitaxial layer is formed thinner than the design value due to manufacturing variations when manufacturing this semiconductor device, the second superjunction layer is formed so as to overlap the first superjunction layer. Since the second superjunction layer is charge-balanced, even if the second superjunction layer is formed so as to overlap the first superjunction layer, the breakdown of charge balance can be suppressed. The semiconductor device has a structure capable of suppressing the breakdown of charge balance in the superjunction structure.

[0006] The manufacturing method of the semiconductor device disclosed in this specification may include a step of forming an epitaxial layer (100) on a first super-junction layer (13) including a super-junction structure in which first-conductivity-type columns (13a) and second-conductivity-type columns (13b) are alternately and repeatedly arranged along at least one direction, and a step of ion-implanting first-conductivity-type impurities and second-conductivity-type impurities into the epitaxial layer to form a second super-junction layer (102) including a super-junction structure in which first-conductivity-type regions (14a) and second-conductivity-type regions (17) are alternately and repeatedly arranged along at least one direction. The second super-junction layer may be disposed at a position exposed on the lower surface of the epitaxial layer. In this manufacturing method of the semiconductor device, when the thickness of the epitaxial layer is formed thinner than the design value due to manufacturing variations, the second super-junction layer is formed so as to overlap the first super-junction layer. Since the second super-junction layer is charge-balanced, even if the second super-junction layer is formed so as to overlap the first super-junction layer, the breakdown of charge balance can be suppressed. The above manufacturing method of the semiconductor device can manufacture a semiconductor device while suppressing the breakdown of charge balance of the super-junction structure.

Brief Description of the Drawings

[0007]

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Embodiments for Carrying Out the Invention

[0008] Hereinafter, the semiconductor device disclosed in this specification will be described with reference to the drawings. For the purpose of clarity of illustration, only one of the repeatedly arranged components may be labeled with a reference numeral.

[0009] (First Embodiment) As shown in FIG. 1, the semiconductor device 1 is a type of power semiconductor device called a MOSFET, and includes a semiconductor substrate 10, a drain electrode 22 covering the lower surface of the semiconductor substrate 10, a source electrode 24 covering the upper surface of the semiconductor substrate 10, and a plurality of trench gates 30 provided in the upper layer portion of the semiconductor substrate 10.

[0010] The material of the semiconductor substrate 10 is not particularly limited, and may be, for example, silicon carbide. The material of the semiconductor substrate 10 may be silicon, a nitride semiconductor, or gallium oxide instead of silicon carbide. The semiconductor substrate 10 has an n + -type drain region 11, an n - -type lower drift region 12, a first superjunction layer 13, and an epitaxial layer 100.

[0011] The drain region 11 is provided at a position exposed on the lower surface of the semiconductor substrate 10. The drain region 11 contains a high concentration of n-type impurities and has an ohmic contact with the drain electrode 22.

[0012] The lower drift region 12 is provided between the drain region 11 and the first superjunction layer 13, and is in contact with each of the drain region 11 and the first superjunction layer 13. The concentration of the n-type impurity in the lower drift region 12 is lower than the concentration of the n-type impurity in the drain region 11.

[0013] The first superjunction layer 13 is provided between the lower drift region 12 and the epitaxial layer 100, and is in contact with both the lower drift region 12 and the epitaxial layer 100. The first superjunction layer 13 has a plurality of n-type columns 13a and a plurality of p-type columns 13b. The n-type columns 13a and the p-type columns 13b are arranged to alternately repeat along at least one direction (in this example, the y-direction) within the cross-section of the semiconductor substrate 10 (in this example, within the xy-plane). The plurality of n-type columns 13a and the plurality of p-type columns 13b are not particularly limited when viewed in plan of the semiconductor substrate 10, and may be arranged, for example, in a stripe shape. Instead of this example, the plurality of n-type columns 13a and the plurality of p-type columns 13b may be arranged, for example, in a lattice shape when viewed in plan of the semiconductor substrate 10. The concentration of the n-type impurity in the n-type column 13a is higher than the concentration of the n-type impurity in the lower drift region 12.

[0014] In the first superjunction layer 13, in the repeating direction (in this example, the y-direction), it is configured such that the positive charge amount when the plurality of n-type columns 13a are depleted balances the negative charge amount when the plurality of p-type columns 13b are depleted, constituting a superjunction structure. Specifically, it is configured such that the product of the width (Wn) and the n-type impurity concentration (Nn) of the n-type column 13a measured along the repeating direction is substantially equal to the product of the width (Wp) and the p-type impurity concentration (Np) of the p-type column 13b. Here, when 100×(Wn×Nn - Wp×Np) / (Wn×Nn) is within ±10%, it can be said that (Wn×Nn) and (Wp×Np) are substantially equal.

[0015] The epitaxial layer 100 is provided by being stacked on the first super junction layer 13, and includes an n-type upper drift region 14, a p-type body region 15, an n + -type source region 16, a plurality of p-type regions 17, a plurality of p-type electric field relaxation regions 18, and a plurality of p-type trench electric field relaxation regions 19.

[0016] The upper drift region 14 is provided at a position exposed on the lower surface of the epitaxial layer 100. The upper drift region 14 is provided between the first super junction layer 13 and the body region 15, and is in contact with both the first super junction layer 13 and the body region 15. Further, the upper drift region 14 is in contact with the lower side surfaces of each of the plurality of trench gates 30. The concentration of the n-type impurity in the upper drift region 14 is lower than the concentration of the n-type impurity in the n-type column 13a constituting the first super junction layer 13.

[0017] The body region 15 is provided on the upper drift region 14 and is arranged in the upper layer portion of the epitaxial layer 100. The body region 15 is provided between the upper drift region 14 and the source region 16, is in contact with both the upper drift region 14 and the source region 16, and separates the upper drift region 14 and the source region 16. The body region 15 is electrically connected to the source electrode 24 via a p-type contact region (not shown). The concentration of the p-type impurity in the body region 15 is adjusted according to a desired gate threshold voltage.

[0018] The source region 16 is provided on the body region 15 and is provided at a position exposed on the upper surface of the epitaxial layer 100. The source region 16 is in contact with the upper side surface of the trench gate 30. The source region 16 contains a high concentration of n-type impurities and has an ohmic contact with the source electrode 24.

[0019] Each of the plurality of p-type regions 17 is provided at a position exposed on the lower surface of the epitaxial layer 100. Each of the plurality of p-type regions 17 extends along at least one direction (in this example, the y direction) within the cross-section of the semiconductor substrate 10, and is arranged at intervals along the direction orthogonal to its longitudinal direction (in this example, the x direction). Therefore, when a portion of the upper drift region 14 sandwiched between a pair of p-type regions 17 is an n-type region 14a, the n-type region 14a and the p-type region 17 are arranged to alternately repeat along at least one direction (in this example, the x direction) within the cross-section of the semiconductor substrate 10. Similar to the first superjunction layer 13, the plurality of n-type regions 14a and the plurality of p-type regions 17 are configured such that the positive charge amount when the plurality of n-type regions 14a are depleted and the negative charge amount when the plurality of p-type regions 17 are depleted balance each other in their repeating direction (in this example, the x direction), thus forming a superjunction structure. Therefore, the plurality of n-type regions 14a and the plurality of p-type regions 17 constitute the second superjunction layer 102.

[0020] The repeating direction of the second superjunction layer 102 (in this example, the x direction) and the repeating direction of the first superjunction layer 13 (in this example, the y direction) are in an intersecting relationship (in this example, a perpendicular relationship). Instead of this example, the repeating direction of the second superjunction layer 102 and the repeating direction of the first superjunction layer 13 may be in a parallel relationship.

[0021] Each of the plurality of electric field relaxation regions 18 protrudes downward from the lower surface of the body region 15 and extends to a position deeper than the bottom surface of the trench gate 30. In this example, each of the plurality of electric field relaxation regions 18 is in contact with the upper surface of the corresponding p-type region 17 among the plurality of p-type regions 17. Instead of this example, each of the plurality of electric field relaxation regions 18 may be arranged away from the p-type region 17. The concentration of p-type impurities in the electric field relaxation region 18 is higher than the concentration of p-type impurities in the p-type region 17. That is, the concentration of p-type impurities in the electric field relaxation region 18 is appropriately adjusted according to the purpose of electric field relaxation and is not adjusted to balance charges with the adjacent upper drift region 14. Note that when the repetitive pitch width of the second super junction layer 102 is narrow, the concentration of p-type impurities in the p-type region 17 becomes high. Therefore, the concentration of p-type impurities in the electric field relaxation region 18 may be lower than the concentration of p-type impurities in the p-type region 17.

[0022] Each of the plurality of electric field relaxation regions 18 extends along at least one direction (in this example, the y direction) within the cross-section of the semiconductor substrate 10, and is arranged at intervals along the direction orthogonal to its longitudinal direction (in this example, the x direction). That is, when the epitaxial layer 100 is viewed in plan, the longitudinal direction of each of the plurality of electric field relaxation regions 18 is parallel to the longitudinal direction of the corresponding p-type region 17 among the plurality of p-type regions 17. In this example, the p-type regions 17 of the second superjunction layer 102 are arranged so as to overlap the formation range of the electric field relaxation regions 18 when the epitaxial layer 100 is viewed in plan. In particular, in this example, the widths of the p-type regions 17 and the electric field relaxation regions 18 measured along the x direction are configured to be equal, and the p-type regions 17 of the second superjunction layer 102 are arranged to coincide with the formation range of the electric field relaxation regions 18 when the epitaxial layer 100 is viewed in plan. Instead of this example, the width of the p-type region 17 measured along the x direction may be configured to be larger than the width of the electric field relaxation region 18. In this case, the p-type regions 17 of the second superjunction layer 102 may be formed to include the formation range of the electric field relaxation regions 18 and wider than the electric field relaxation regions 18 when the epitaxial layer 100 is viewed in plan (that is, the p-type regions 17 may protrude laterally beyond the side surfaces of the electric field relaxation regions 18). When the p-type regions 17 of the second superjunction layer 102 are formed wider, the design freedom for obtaining the charge balance of the second superjunction layer 102 is improved.

[0023] Each of the plurality of trench electric field relaxation regions 19 is provided so as to protrude downward from the bottom surface of the corresponding trench gate 30 among the plurality of trench gates 30. In this example, the depth of the bottom surface of the trench electric field relaxation region 19 is the same as the depth of the bottom surface of the electric field relaxation region 18. Instead of this example, the depth of the bottom surface of the trench electric field relaxation region 19 may be shallower than the depth of the bottom surface of the electric field relaxation region 18. The concentration of the p-type impurity in the trench electric field relaxation region 19 is appropriately adjusted for the purpose of electric field relaxation. Note that the trench electric field relaxation region 19 may not be formed depending on the characteristics desired for the semiconductor device 1.

[0024] Each of the plurality of trench gates 30 is filled in a trench formed in the upper portion of the epitaxial layer 100, penetrates the source region 16 and the body region 15, and reaches the upper drift region 14. In this example, each of the plurality of trench gates 30 extends along at least one direction (in this example, the y direction) in the cross section of the semiconductor substrate 10, and is arranged at intervals along the direction (in this example, the x direction) orthogonal to its longitudinal direction. That is, when the epitaxial layer 100 is viewed in plan, the longitudinal direction of each of the plurality of trench gates 30 is parallel to the longitudinal direction of the p-type region 17 and the electric field relaxation region 18. Instead of this example, the longitudinal direction of each of the plurality of trench gates 30 may intersect the longitudinal direction of the p-type region 17 and the electric field relaxation region 18 when the epitaxial layer 100 is viewed in plan. Each of the plurality of trench gates 30 has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is formed of polysilicon containing impurities and faces the semiconductor substrate 10 through the gate insulating film 34. The gate insulating film 34 is formed of silicon oxide and covers the inner wall of the trench.

[0025] Next, with reference to FIG. 1, the operation of the semiconductor device 1 will be described. When the potential of the gate electrode 32 of the trench gate 30 is higher than that of the source electrode 24 and is controlled to be higher than the threshold value in a state where the potential of the drain electrode 22 is higher than that of the source electrode 24, the semiconductor device 1 turns on. At this time, an inversion layer is formed in the body region 15 of the portion separating the source region 16 and the upper drift region 14. Electrons supplied from the source region 16 reach the upper drift region 14 via the channel of the inversion layer. The electrons that have reached the upper drift region 14 flow into the drain region 11 via the n-type column 13a of the first superjunction layer 13 and the lower drift region 12. Since the n-type column 13a of the first superjunction layer 13 has a high concentration of n-type impurities, the semiconductor device 1 can have the characteristic of low on-resistance.

[0026] When the potential of the gate electrode 32 of the trench gate 30 is controlled to be the same as the potential of the source electrode 24, the channel of the inversion layer disappears and the semiconductor device 1 turns off. The plurality of n-type columns 13a and the plurality of p-type columns 13b constituting the superjunction structure are substantially completely depleted, and a wide range of the first superjunction layer 13 is depleted. In the depleted first superjunction layer 13, the electric field distribution is made uniform in the thickness direction of the semiconductor substrate 10. Therefore, since the first superjunction layer 13 can bear a large potential difference, the semiconductor device 1 can have the characteristic of high breakdown voltage.

[0027] (First manufacturing method of semiconductor device) Next, with reference to FIGS. 2 to 8, some steps of the manufacturing method of the semiconductor device 1 will be described. For other steps for manufacturing the semiconductor device 1, known manufacturing techniques can be used.

[0028] First, as shown in FIG. 2, a drain region 11 which is an n + -type silicon carbide substrate is prepared. Next, although not particularly limited, for example, an epitaxial growth technique such as CVD (Chemical Vapor Deposition) method is used to grow an n - -type epitaxial layer of silicon carbide from the surface of the drain region 11. Next, a plurality of n-type columns 13a and a plurality of p-type columns 13b are formed in the upper layer portion of the epitaxial layer by using photolithography technology and ion implantation technology, and a first superjunction layer 13 is formed in the upper layer portion of the epitaxial layer. The portion other than the first superjunction layer 13 in the epitaxial layer becomes the lower drift region 12.

[0029] Next, as shown in FIG. 3, although not particularly limited, for example, an epitaxial layer 100 of silicon carbide is grown from the surface of the first super-junction layer 13 by using an epitaxial growth technique such as CVD (Chemical Vapor Deposition). The epitaxial layer 100 may be epitaxially grown to contain an n-type impurity, or may be epitaxially grown undoped. Next, an n-type impurity is ion-implanted into the epitaxial layer 100 by using an ion implantation technique to form the upper drift region 14. The concentration of the n-type impurity ion-implanted at a position exposed on the lower surface of the epitaxial layer 100 in the upper drift region 14 is adjusted to be the n-type region 14a (see FIG. 1) of the second super-junction layer 102. Note that the n-type impurity may be ion-implanted into the entire epitaxial layer 100, or may be ion-implanted only into a necessary portion by using a photolithography technique.

[0030] Next, as shown in FIG. 4, a p-type impurity is ion-implanted at a position exposed on the lower surface of the epitaxial layer 100 by using a photolithography technique and an ion implantation technique to form a plurality of p-type regions 17. A portion of the upper drift region 14 sandwiched between a pair of p-type regions 17 becomes the n-type region 14a, and the second super-junction layer 102 is formed by the plurality of n-type regions 14a and the plurality of p-type regions 17.

[0031] Next, as shown in FIG. 5, using photolithography technology and ion implantation technology, p-type impurities are ion-implanted into the epitaxial layer 100 to form a plurality of electric field relaxation regions 18. Note that ion implantation may be performed using a mask common to the mask for forming the plurality of p-type regions 17 to form the plurality of electric field relaxation regions 18. The p-type region 17 has a concentration of p-type impurities adjusted to form the second superjunction layer 102, and the electric field relaxation region 18 has a concentration of p-type impurities suitable for the purpose of electric field relaxation, and the concentrations of p-type impurities in both are different. For this reason, the concentration distribution of p-type impurities in the thickness direction (in this example, the z direction) of the epitaxial layer 100 has a step including a bending point between the p-type region 17 and the electric field relaxation region 18. Note that the plurality of electric field relaxation regions 18 may be formed using a mask different from the mask for forming the plurality of p-type regions 17. In this case, by using a mask that opens corresponding to the plurality of trench electric field relaxation regions 19 (see FIG. 1) in addition to the plurality of electric field relaxation regions 18, the plurality of electric field relaxation regions 18 and the plurality of trench electric field relaxation regions 19 may be formed simultaneously.

[0032] Next, as shown in FIG. 6, using ion implantation technology, p-type impurities are ion-implanted into the upper layer portion of the epitaxial layer 100 to form the body region 15, and further, n-type impurities are ion-implanted at a position exposed on the upper surface of the epitaxial layer 100 to form the source region 16.

[0033] Next, as shown in FIG. 7, using dry etching technology, a trench 42 that penetrates the source region 16 and the body region 15 from the upper surface of the epitaxial layer 100 and reaches the upper drift region 14 is formed.

[0034] Next, as shown in FIG. 8, using ion implantation technology, p-type impurities are ion-implanted into the bottom surface of the trench 42 to form the trench electric field relaxation region 19. After that, using a known manufacturing technology, the trench gate 30, the drain electrode 22, and the source electrode 24 are formed, and the semiconductor device 1 is completed.

[0035] Here, a comparative example in which the second super junction layer 102 is not formed will be described. The thickness of the epitaxial layer 100 may be formed thinner than the design value due to manufacturing variations. In the comparative example in which the second super junction layer 102 is not formed, a part of the electric field relaxation region 18 is formed so as to overlap the first super junction layer 13. When a part of the electric field relaxation region 18 is formed so as to overlap the first super junction layer 13, the charge balance of the first super junction layer 13 is disrupted, and there is a concern about a decrease in the breakdown voltage of the semiconductor device.

[0036] On the other hand, in the semiconductor device 1 of the present embodiment, when the thickness of the epitaxial layer 100 is formed thinner than the design value due to manufacturing variations, the second super junction layer 102 is formed so as to overlap the first super junction layer 13. The plurality of n-type regions 14a and the plurality of p-type regions 17 constituting the second super junction layer 102 are diffusion regions formed by ion implantation. When the thickness of the epitaxial layer 100 is formed thinner than the design value due to manufacturing variations, both are formed so as to overlap the first super junction layer 13. Note that the thickness of the second super junction layer 102 is formed to be large enough to allow for manufacturing variations in the epitaxial layer 100. Since the plurality of n-type regions 14a and the plurality of p-type regions 17 are charge-balanced, even if the second super junction layer 102 is formed so as to overlap the first super junction layer 13, the disruption of the charge balance can be suppressed. Thus, the semiconductor device 1 of the present embodiment has a structure capable of suppressing the disruption of the charge balance of the first super junction layer 13.

[0037] (Second Embodiment) FIG. 9 shows a perspective view of a main part of the semiconductor device 2 according to the second embodiment. Note that components that are substantially the same as those of the semiconductor device 1 shown in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

[0038] The semiconductor device 2 includes a p-type region 170 disposed below the body region 15 in contact with the lower surface of the body region 15. The p-type region 170 is provided at a position exposed on the lower surface of the epitaxial layer 100. The semiconductor device 2 further includes an n-type JFET region 140 provided between adjacent body regions 15. The JFET region 140 extends from the upper surface to the lower surface of the epitaxial layer 100 between adjacent body regions 15. The semiconductor device 2 further includes a planar gate 130 provided on the upper surface of the epitaxial layer 100. The planar gate 130 has a gate electrode 132 and a gate insulating film 134. The gate electrode 132 faces the body region 15 at a portion separating the source region 16 and the JFET region 140 with the gate insulating film 134 interposed therebetween.

[0039] If a portion of the JFET region 140 sandwiched between a pair of p-type regions 170 is defined as an n-type region 140a, the n-type region 140a and the p-type region 170 are arranged to alternately repeat along at least one direction (in this example, the x direction) within the cross-section of the semiconductor substrate 10, constituting a superjunction structure. Accordingly, the n-type region 140a and the p-type region 170 constitute a second superjunction layer 102.

[0040] Also in the semiconductor device 2, the thickness of the epitaxial layer 100 may be formed thinner than the design value due to manufacturing variations. In this case, the second superjunction layer 102 is formed so as to overlap the first superjunction layer 13. Note that the thickness of the second superjunction layer 102 is formed to be large enough to allow for manufacturing variations of the epitaxial layer 100. Since the n-type region 140a and the p-type region 170 constituting the second superjunction layer 102 are charge-balanced, even if the second superjunction layer 102 is formed to overlap the first superjunction layer 13, the breakdown of charge balance can be suppressed. Thus, the semiconductor device 2 has a structure capable of suppressing the breakdown of charge balance in the first superjunction layer 13.

[0041] As described above, specific examples of the present invention have been described in detail. However, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples exemplified above. In addition, the technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Also, the technology exemplified in this specification or the drawings can achieve a plurality of objectives simultaneously, and achieving one of these objectives itself has technical utility.

Description of Reference Numerals

[0042] 1, 2: Semiconductor device, 10: Semiconductor substrate, 11: Drain region, 12: Lower drift region, 13: First superjunction layer, 13a: n-type column, 13b: p-type column, 14: Upper drift region, 14a: n-type region, 15: Body region, 16: Source region, 17: p-type region, 18: Electric field relaxation region, 19: Trench electric field relaxation region, 22: Drain electrode, 24: Source electrode, 30: Trench gate, 100: Epitaxial layer, 102: Second superjunction layer

Claims

1. A first superjunction layer (13) including a superjunction structure in which first conductivity type columns (13a) and second conductivity type columns (13b) are alternately repeated along at least one direction, and an epitaxial layer (100) laminated on the first superjunction layer, wherein the epitaxial layer has a second superjunction layer (102) disposed at a position exposed on the lower surface of the epitaxial layer and including a superjunction structure in which first conductivity type regions (14a) and second conductivity type regions (17) are alternately repeated along at least one direction, wherein the first conductivity type region and the second conductivity type region of the second superjunction layer are diffusion regions, a semiconductor device.

2. further comprising a trench gate (30) extending from the upper surface to the lower surface of the epitaxial layer, wherein the epitaxial layer has a second conductivity type body region (15) provided in an upper layer portion of the epitaxial layer and penetrated by the trench gate, and further has a second conductivity type electric field relaxation region (18) protruding downward from the lower surface of the body region and extending to a position deeper than the bottom surface of the trench gate, wherein the concentration of the second conductivity type impurity in the electric field relaxation region is different from the concentration of the second conductivity type impurity in the second conductivity type region of the second superjunction layer, the semiconductor device according to claim 1.

3. The concentration of the second conductivity type impurity in the second conductivity type region of the second superjunction layer is lower than the concentration of the second conductivity type impurity in the electric field relaxation region, the semiconductor device according to claim 2.

4. When the epitaxial layer is viewed in plan, the second conductivity type region of the second superjunction layer is arranged to overlap with the formation range of the electric field relaxation region, the semiconductor device according to claim 2.

5. When the epitaxial layer is viewed in plan, the second conductivity type region of the second superjunction layer includes the formation range of the electric field relaxation region and is formed wider than the electric field relaxation region, the semiconductor device according to claim 4.

6. The semiconductor device according to claim 2, wherein when the epitaxial layer is viewed in plan view, the electric field relaxation region and the second conductivity type region of the second superjunction layer extend parallel to the longitudinal direction of the trench gate.

7. The semiconductor device according to claim 1, wherein a repeating direction in which the first conductivity type columns and the second conductivity type columns of the first superjunction layer are repeatedly arranged intersects with a repeating direction in which the first conductivity type region and the second conductivity type region of the second superjunction layer are repeatedly arranged.

8. The epitaxial layer The semiconductor device according to claim 2, further comprising a second conductivity type trench electric field relaxation region (19) protruding downward from the bottom surface of the trench gate.

9. A step of forming an epitaxial layer (100) on a first superjunction layer (13) including a superjunction structure in which first conductivity type columns (13a) and second conductivity type columns (13b) are alternately repeatedly arranged along at least one direction; A step of ion-implanting a first conductivity type impurity and a second conductivity type impurity into the epitaxial layer to form a second superjunction layer (102) including a superjunction structure in which a first conductivity type region (14a) and a second conductivity type region (17) are alternately repeatedly arranged along at least one direction, and A method of manufacturing a semiconductor device, wherein the second superjunction layer is disposed at a position exposed on the lower surface of the epitaxial layer.

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