Power supply management circuit and electronic device

Abstract

To provide a power supply management circuit and an electronic device capable of executing appropriate processing in accordance with an abnormality.SOLUTION: A power supply management circuit 100 includes a first output stage 118_1 including a first high-side transistor MH1 and a first low-side transistor ML1, a second output stage 118_2 including a second high-side transistor MH2 and a second low-side transistor ML2, a first peak current detection circuit 160_1 for detecting whether a first current flowing through the first high-side transistor has reached a first peak threshold value, and a second peak current detection circuit 160_2 for detecting whether a second current flowing through the second high-side transistor has reached a second peak threshold value. In a second mode, the operation of the first output stage and the second output stage stops in accordance with the detection by the first peak current detection circuit that the first current has not reached the first peak threshold value within the detection period in which the first current reaches the first peak threshold value.SELECTED DRAWING: Figure 17

Description

Technical Field

[0001] The present disclosure relates to a power management circuit and an electronic device.

Background Art

[0002] Conventionally, a power management circuit has been proposed that includes two-channel DC / DC converters, operates these DC / DC converters separately in a first mode, and operates the outputs of these DC / DC converters together in a single system in a second mode (see Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] However, the inventors of the present invention have come to recognize the following problems. That is, in the technology described in Patent Document 1, if an abnormality such as disconnection of a wire at a terminal occurs in one channel, since the two channels are combined into a single system in the second mode, the abnormality may not be detected appropriately.

[0005] The present disclosure has been made in view of such circumstances, and one of its exemplary purposes is to provide a power management circuit and an electronic device that can execute appropriate processing in response to an abnormality.

[0006] One aspect of the present disclosure is a power management circuit. The power management circuit includes a first output stage including a first high-side transistor and a first low-side transistor, a second output stage including a second high-side transistor and a second low-side transistor, a first peak current detection circuit configured to detect whether a first current flowing through the first high-side transistor reaches a first peak threshold, and a second peak current detection circuit configured to detect whether a second current flowing through the second high-side transistor reaches a second peak threshold. In a first mode, the first output stage and the second output stage operate independently to generate respective individual output signals, and the first peak current detection circuit and the second peak current detection circuit are enabled. In a second mode, the first output stage and the second output stage operate in cooperation to generate a common output signal, and the first peak current detection circuit is enabled. The operations of the first output stage and the second output stage stop in the second mode in response to the first peak current detection circuit detecting that the first current does not reach the first peak threshold within a detection period during which the first current is to reach the first peak threshold.

[0007] Another aspect of the present disclosure is an electronic device. The electronic device includes the above-described power management circuit.

[0008] Note that any combination of the above components, as well as those obtained by converting the expressions of the present disclosure among methods, apparatuses, systems, etc., are also effective as aspects of the present disclosure.

Brief Description of the Drawings

[0009]

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[0010] [Detailed Description] (Overview) The overview of some exemplary embodiments of the present disclosure will be described. This overview is provided as a prelude to the detailed description that follows and is intended to provide a basic understanding of the embodiments by simplifying and explaining some concepts of one or more embodiments. It is not intended to limit the scope of the invention or the disclosure. This overview is not an exhaustive overview of all possible embodiments, nor is it intended to identify the important elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variation) or a plurality of embodiments (examples or variations) disclosed herein.

[0011] A power management circuit according to one embodiment includes a first output stage including a first high-side transistor and a first low-side transistor, a second output stage including a second high-side transistor and a second low-side transistor, a first peak current detection circuit that detects whether or not a first current flowing through the first high-side transistor has reached a first peak threshold value, and a second peak current detection circuit that detects whether or not a second current flowing through the second high-side transistor has reached a second peak threshold value. In the first mode, the first output stage and the second output stage operate independently to generate individual output signals, and the first peak current detection circuit and the second peak current detection circuit are enabled. In the second mode, the first output stage and the second output stage operate in cooperation to generate a common output signal, and the first peak current detection circuit is enabled. The operations of the first output stage and the second output stage stop in the second mode in response to the first peak current detection circuit detecting that the first current does not reach the first peak threshold value within a detection period during which the first current should reach the first peak threshold value.

[0012] According to this configuration, by stopping the operations of the first output stage and the second output stage in response to the first current not reaching the first peak threshold value within the detection period, appropriate processing in response to abnormalities such as terminal disconnection can be executed.

[0013] In one embodiment, the detection period may be a period from when the first high-side transistor and the second high-side transistor are each turned on in the second mode until the detection time elapses.

[0014] In one embodiment, the second peak current detection circuit may be invalid in the second mode.

[0015] In one embodiment, in the second mode, when it is detected by the first peak current detection circuit that the first current has reached the first peak threshold value within the detection period, the operations of the first output stage and the second output stage may continue.

[0016] In one embodiment, the power management circuit may further include a controller that controls the operations of the first output stage and the second output stage in the second mode. The controller may stop the operations of the first output stage and the second output stage when the first current does not reach the first peak threshold value within the detection period.

[0017] In one embodiment, the operations of the first output stage and the second output stage may be stopped by control from a controller provided outside the power management circuit when the first current does not reach the first peak threshold value within the detection period in the second mode.

[0018] In one embodiment, in the second mode, when a certain time has elapsed after the controller stops the operations of the first output stage and the second output stage, the first high-side transistor and the second high-side transistor may be each turned on. The first peak current detection circuit may detect the first current in the detection period after the certain time has elapsed.

[0019] The electronic device according to another embodiment includes the above power management circuit.

[0020] According to this configuration, by stopping the operations of the first output stage and the second output stage in response to the first current not reaching the first peak threshold value within the detection period, appropriate processing in response to abnormalities such as terminal disconnection can be executed.

[0021] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Also, the embodiments are illustrative and not intended to limit the disclosure and the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and the invention.

[0022] In this specification, the state where "member A is connected to member B" means that in addition to the case where member A and member B are physically directly connected, member A and member B are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their combination.

[0023] Similarly, the state where "member C is connected (provided) between member A and member B" means that in addition to the case where member A and member C, or member B and member C are directly connected, they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their combination.

[0024] (Power Management Circuit According to the First Embodiment) FIG. 1 is a block diagram of a power management circuit 100 according to the first embodiment. The power management circuit 100 includes a first circuit block BLK1, a second circuit block BLK2, a mode selector 120, a sequencer 130, a first input pin VIN1, a first output pin LX1, a first ground pin PGND1, a first feedback pin FB1, a second input pin VIN2, a second output pin LX2, a second ground pin PGND2, a second feedback pin FB2, and a ground pin GND, and is housed in one package.

[0025] The power management circuit 100 can select one mode from a first mode and a second mode. In this embodiment, the mode is selected by the mode selector 120 according to an external setting or the like. In the first mode, the first circuit block BLK1 and the second circuit block BLK2 operate independently, and the power management circuit 100 functions as a two-channel (two-output) DC / DC converter. In the second mode, the first circuit block BLK1 and the second circuit block BLK2 operate in cooperation, and the power management circuit 100 functions as a one-channel (one-output) DC / DC converter.

[0026] The first circuit block BLK1 includes a first feedback controller 110_1, a first pre-driver 112_1, a first output stage 118_1, a first current detection circuit 140_1, and an abnormality detection circuit 190. The second circuit block BLK2 includes a second feedback controller 110_2, a second pre-driver 112_2, a second output stage 118_2, and a second current detection circuit 140_2.

[0027] In the first mode, the first output stage 118_1 and the second output stage 118_2 operate independently to generate individual output signals. In the second mode, the first output stage 118_1 and the second output stage 118_2 operate in cooperation to generate a common output signal.

[0028] The first output stage 118_1 includes a first high-side transistor MH1 and a first low-side transistor ML1. The first high-side transistor MH1 is composed of a P-channel MOS (Metal Oxide Semiconductor) transistor, and the first low-side transistor ML1 is composed of an N-channel MOS transistor. Note that the first high-side transistor MH1 may be composed of an N-channel MOS transistor, and the first low-side transistor ML1 may be composed of an N-channel MOS transistor. The first high-side transistor MH1 is provided between a first input pin VIN1 and a first output pin LX1. The first low-side transistor ML1 is provided between the first output pin LX1 and a first ground pin PGND1.

[0029] The first pre-driver 112_1 has a first high-side pre-driver 114_1 and a first low-side pre-driver 116_1. The first high-side pre-driver 114_1 drives the first high-side transistor MH1. The first low-side pre-driver 116_1 drives the first low-side transistor ML1.

[0030] The first current detection circuit 140_1 detects the current of the first output stage 118_1 (specifically, the first high-side transistor MH1 or the first low-side transistor ML1). The first current detection circuit 140_1 detects, for example, overcurrent, peak current, zero current, and negative current in the first output stage 118_1.

[0031] The abnormality detection circuit 190 detects an abnormality in the current path based on the detection result of the first current detection circuit 140_1 and the like.

[0032] The second output stage 118_2 includes a second high-side transistor MH2 and a second low-side transistor ML2. The second high-side transistor MH2 is composed of a P-channel MOS transistor, and the second low-side transistor ML2 is composed of an N-channel MOS transistor. Note that the second high-side transistor MH2 may be composed of an N-channel MOS transistor, and the second low-side transistor ML2 may be composed of an N-channel MOS transistor. The second high-side transistor MH2 is provided between the second input pin VIN2 and the second output pin LX2. The second low-side transistor ML2 is provided between the second output pin LX2 and the second ground pin PGND2.

[0033] The second pre-driver 112_2 has a second high-side pre-driver 114_2 and a second low-side pre-driver 116_2. The second high-side pre-driver 114_2 drives the second high-side transistor MH2. The second low-side pre-driver 116_2 drives the second low-side transistor ML2.

[0034] The second current detection circuit 140_2 detects the current of the second output stage 118_2 (specifically, the second high-side transistor MH2 or the second low-side transistor ML2). The second current detection circuit 140_2 detects, for example, overcurrent, peak current, zero current, and negative current in the first output stage 118_2.

[0035] The first circuit block BLK1 and the second circuit block BLK2 can have the same core. The first feedback controller 110_1 and the second feedback controller 110_2 may have the same function and configuration. Also, the first pre-driver 112_1 and the second pre-driver 112_2 may have the same function and configuration. Furthermore, the sizes of the first high-side transistor MH1 and the second high-side transistor MH2 may be equal, and the sizes of the first low-side transistor ML1 and the second low-side transistor ML2 may also be equal.

[0036] The sequencer 130 controls the start and stop timing of each of the first circuit block BLK1 and the second circuit block BLK2. For example, the sequencer 130 starts the first circuit block BLK1 and the second circuit block BLK2 by using, as a trigger, an instruction to start the system or power-on. Also, when the sequencer 130 receives an instruction to stop the system, it stops the first circuit block BLK1 and the second circuit block BLK2.

[0037] FIG. 2 is a block diagram of the first current detection circuit 140_1 and the second current detection circuit 140_2 according to the present embodiment. In the present embodiment, in the first mode, both the first current detection circuit 140_1 and the second current detection circuit 140_2 are effective, and in the second mode, the first current detection circuit 140_1 is effective and the second current detection circuit 140_2 is ineffective.

[0038] The first current detection circuit 140_1 includes a first overcurrent detection circuit 150_1, a first peak current detection circuit 160_1, and a first low-side current detection circuit 170_1. The first overcurrent detection circuit 150_1 detects an overcurrent in the first high-side transistor MH1. The first peak current detection circuit 160_1 detects that the high-side transistor has reached a predetermined peak threshold value in order to perform PFM (Pulse Frequency Modulation) control (also referred to as intermittent mode control). Specifically, the first peak current detection circuit 160_1 detects whether or not the current flowing through the first high-side transistor MH1 (hereinafter, also referred to as "the first current") has reached the first peak threshold value. The first peak current detection circuit 160_1 transmits a signal Sp (such as an output signal of a comparator and a timer described later) indicating the detection result to the abnormality detection circuit 190. The first low-side current detection circuit 170_1 detects a zero current or a negative current in the first low-side transistor ML1.

[0039] The second current detection circuit 140_2 includes a second overcurrent detection circuit 150_2, a second peak current detection circuit 160_2, and a second low-side current detection circuit 170_2. The second overcurrent detection circuit 150_2 detects an overcurrent in the second high-side transistor MH2. The second peak current detection circuit 160_2 detects that the high-side transistor has reached a predetermined peak threshold for performing PFM control. Specifically, the second peak current detection circuit 160_2 detects whether the current flowing through the second high-side transistor MH2 (hereinafter also referred to as "the second current") has reached the second peak threshold. The second low-side current detection circuit 170_2 detects a zero current or a negative current in the second low-side transistor ML2.

[0040] FIG. 3 is a block diagram of the first system 10 in the first mode. In the first mode, the power management circuit 100 forms a two-channel (two-output) DC / DC converter together with external components.

[0041] In the first mode, an input voltage V IN is supplied to the first input pin VIN1 and the second input pin VIN2, respectively. The first ground pin PGND1, the second ground pin PGND2, and the ground pin GND are each grounded. The first ground pin PGND1 and the second ground pin PGND2 may be separated. One end of the inductor L1 is connected to the first output pin LX1, and one end of the inductor L2 is connected to the second output pin LX2. The other end of the output capacitor Co1, one end of which is grounded, is connected to the other end of the inductor L1, and the other end of the output capacitor Co2, one end of which is grounded, is connected to the other end of the inductor L2. An output signal V OUT1 of the DC / DC converter of the first channel is output from the other end of the inductor L1, and an output signal V OUT2 of the DC / DC converter of the second channel is output from the other end of the inductor L2.

[0042] In the first mode, a feedback signal V corresponding to the output signal V OUT1 of the DC / DC converter of the first channel is applied to the first feedback pin FB1.FB1 is fed back. To the second feedback pin FB2, a feedback signal V OUT2 corresponding to the output signal V FB2 of the second channel DC / DC converter is fed back. The first feedback controller 110_1 generates a control signal S FB1 based on the feedback signal V H1 , S L1 . The second feedback controller 110_2 generates a control signal S FB2 based on the feedback signal V H2 , S L2 .

[0043] The first high-side pre-driver 114_1 drives the first high-side transistor MH1 according to the control signal S H1 , and the first low-side pre-driver 116_1 drives the first low-side transistor ML1 according to the control signal S L1 . The second high-side pre-driver 114_2 drives the second high-side transistor MH2 according to the control signal S H2 , and the second low-side pre-driver 116_2 drives the second low-side transistor ML2 according to the control signal S L2 .

[0044] FIG. 4 is a block diagram of the second system 12 in the second mode. In the second mode, the power management circuit 100 forms a 1-channel (1 output) DC / DC converter together with external components. Specifically, a common inductor L1 is connected to the first output pin LX1 and the second output pin LX2. Also, a pair of the first high-side transistor MH1 and the second high-side transistor MH2 are electrically connected in parallel, and a pair of the first low-side transistor ML1 and the second low-side transistor ML2 are electrically connected in parallel.

[0045] In the second mode, to the first feedback pin FB1, a feedback signal V OUT1 corresponding to the output signal V FB1is fed back. The second feedback pin FB2 pin may be unconnected.

[0046] In the second mode, the first feedback controller 110_1 controls the operations of the first output stage 118_1 and the second output stage 118_2. The first feedback controller 110_1 generates a control signal S FB1 based on the feedback signal V H1 , S L1 . At this time, the operation of the second feedback controller 110_2 is stopped. Although the operations of the first output stage 118_1 and the second output stage 118_2 are controlled by the first feedback controller 110_1, the second feedback controller 110_2 may also be operating. The first feedback controller 110_1 and the second circuit block BLK2 (specifically, the second pre-driver 112_2) are connected via the signal path 102. The control signal S H3 , S L3 is supplied from the first feedback controller 110_1 to the second pre-driver 112_2 via the signal path 102. For example, the control signal S H3 includes a replica of a pulse signal instructing the on and off of the first high-side transistor MH1, and the control signal S L3 may include a replica of a pulse signal instructing the on and off of the first low-side transistor ML1.

[0047] The first pre-driver 112_1 operates in response to the control signal S H1 , S L1 . Also, the second pre-driver 112_2 operates in response to the control signal S H2 , S L2 and instead operates in response to the control signal S H3 , S L3 from the first feedback controller 110_1. Thereby, the first high-side transistor MH1 and the second high-side transistor MH2 turn on and off substantially simultaneously, and the first low-side transistor ML1 and the second low-side transistor ML2 turn on and off substantially simultaneously.

[0048] In the second mode, the operations of the first output stage 118_1 and the second output stage 118_2 are stopped in response to the first peak current detection circuit 160 detecting that the first current does not reach the first peak threshold within the detection period during which the first current should reach the first peak threshold. Specifically, the first high-side transistor ML1, the first low-side transistor ML1, the second high-side transistor MH2, and the second low-side transistor ML2 all enter the off state. The detection period may be a period from when the first high-side transistor MH1 and the second high-side transistor MH2 are each turned on until a predetermined detection time (for example, about several hundred nanoseconds to several microseconds) elapses in the second mode. The detection time is determined by, for example, the input voltage V IN , the output signal V OUT1 and the inductance value of the inductor L1, etc.

[0049] In this embodiment, the first feedback controller 110_1 stops the operations of the first output stage 118_1 and the second output stage 118_2 in response to the first peak current detection circuit 160_1 detecting that the first current does not reach the first peak threshold within the detection period. Thereby, for example, when the first input pin VIN1 or the first output pin LX1 is open, it is suppressed that a current larger than necessary flows through the inductor L1. Note that instead of the control by the first feedback controller 110_1, the operations of the first output stage 118_1 and the second output stage 118_2 may be stopped by the first circuit block BLK1 and the second circuit block BLK2 entering the disabled state.

[0050] In the second mode, when a certain period of time has elapsed after the operations of the first output stage 118_1 and the second output stage 118_2 are stopped, the first high-side transistor MH1 and the second high-side transistor MH2 are each turned on. The first peak current detection circuit 160_1 detects the first current during a detection period after a certain period of time has elapsed (after the first high-side transistor MH1 and the second high-side transistor MH2 are turned on). Thereby, it is determined again whether the first current reaches the first peak threshold value, and the state of the first input pin VIN1 or the first output pin LX1 can be detected.

[0051] In the second mode, when the first peak current detection circuit 160_1 detects that the first current has reached the first peak threshold value within the detection period, the operations of the first output stage 118_1 and the second output stage 118_2 continue. Thereby, when there is no abnormality in the first input pin VIN1 or the first output pin LX1, the first output stage 118_1 and the second output stage 118_2 can operate normally.

[0052] Also, the common output signal V OUT1 increases with the passage of time during the detection period. If the first current does not reach the first peak threshold value even though the output signal V OUT1 increases during the detection period, there may be an abnormality such as the first input pin VIN or the first output pin LX1 being open, as will be described later. Therefore, in response to the first peak current detection circuit 160_1 detecting that the first current does not reach the first peak threshold value, by stopping the operations of the first output stage 118_1 and the second output stage 118_2, it becomes possible to execute more appropriate processing in response to the abnormality.

[0053] In the second mode, the abnormality detection circuit 190 detects an abnormality in the current path based on the fact that the first peak current detection circuit 160_1 has detected that the first current does not reach the first peak threshold value within the detection period. As a result, for example, by outputting the detection result to an external device (for example, an image display device or an audio output device), the user can recognize an open circuit of, for example, the first input pin VIN1 or the first output pin LX1.

[0054] Also, in the second mode, in response to the first peak current detection circuit 160_1 detecting that the first current does not reach the first peak threshold value within the detection period, the abnormality detection circuit 190 transmits a signal So to the first feedback controller 110_1 so as to stop the operations of the first output stage 118_1 and the second output stage 118_2.

[0055] With reference to FIGS. 5 and 6, the configurations and functions of the first overcurrent detection circuit 150_1 and the second overcurrent detection circuit 150_2 according to the present embodiment will be described. FIG. 5 shows the state in the first mode, and FIG. 6 shows the state in the second mode.

[0056] The first overcurrent detection circuit 150_1 is configured to detect an overcurrent flowing through the first high-side transistor MH1. Specifically, the first overcurrent detection circuit 150_1 compares the current I flowing through the first high-side transistor MH1 with a first overcurrent threshold value I MH1 The second overcurrent detection circuit 150_2 is configured to detect an overcurrent flowing through the second high-side transistor MH2. Specifically, the second overcurrent detection circuit 150_2 compares the current I flowing through the second high-side transistor MH2 with a second overcurrent threshold value I OCP1 with the second overcurrent threshold value I MH2 and compares it with the second overcurrent threshold value I OCP2

[0057] In the first mode, both the first overcurrent detection circuit 150_1 and the second overcurrent detection circuit 150_2 are enabled, and each circuit block BLK# (# = 1, 2) performs overcurrent protection in response to the output of the corresponding overcurrent detection circuit 150_#.

[0058] In the second mode, only the first overcurrent detection circuit 150_1 is enabled, and the second overcurrent detection circuit 150_2 is disabled. In the second mode, the first circuit block BLK1 and the second circuit block BLK2 perform overcurrent protection in response to the output of the first overcurrent detection circuit 150_1.

[0059] The first overcurrent detection circuit 150_1 compares the voltage V DS1 (drain-source voltage) across the first high-side transistor MH1 with a first threshold voltage ΔV OCP1 corresponding to a first overcurrent threshold I OCP1 . The second overcurrent detection circuit 150_2 is configured similarly.

[0060] The first overcurrent detection circuit 150_1 includes a replica transistor 152, a current source 154, and a comparator 156. The replica transistor 152 is a replica of the first high-side transistor MH1, and its source is connected to the first input pin VIN1. The gate of the replica transistor 152 is biased to be in the same state as the first high-side transistor MH1. The current source 154 is connected to the drain of the replica transistor 152 and supplies current to the replica transistor 152. The voltage ΔV OCP1 across the replica transistor 152 is defined according to the current generated by the current source 154.

[0061] The comparator 156 compares the voltage V DS1 across the first high-side transistor MH1 with the voltage ΔV OCP across the replica transistor 152. The current source 154 includes a constant current source 154a and a current DAC 154b, and the sum of their output currents may be supplied to the replica transistor 152.

[0062] The configurations and functions of the first peak current detection circuit 160_1 and the second peak current detection circuit 160_2 according to this embodiment will be described with reference to Fig. 7 and Fig. 8. Fig. 7 shows a state in the first mode, and Fig. 8 shows a state in the second mode.

[0063] The first peak current detection circuit 160_1 detects the current I MH1 The first peak threshold I PEAK1 The second peak current detection circuit 160_2 detects the current I MH2 The second peak threshold I PEAK2 Compare with.

[0064] In the first mode, the first peak current detection circuit 160_1 and the second peak current detection circuit 160_2 are enabled, and each circuit block BLK_# (#=1, 2) operates according to the output of the corresponding peak current detection circuit 160_#.

[0065] In the second mode, only the first peak current detection circuit 160_1 is enabled, and the second peak current detection circuit 160_2 is disabled. The first circuit block BLK1 and the second circuit block BLK2 operate according to the output of the first peak current detection circuit 160_1.

[0066] The first peak current detection circuit 160_1 detects the voltage V DS1 The first peak threshold I PEAK1 Threshold voltage ΔV according to IPEAK1 The second peak current detection circuit 160_2 is configured similarly.

[0067] The first peak current detection circuit 160_1 and the first peak current detection circuit 160_2 can be configured similarly to the first overcurrent detection circuit 150_1 and the second overcurrent detection circuit 150_2, except for a timer 168 described later. The first peak current detection circuit 160_1 includes a replica transistor 162, a current source 164, a comparator 166, and a timer 168.

[0068] The replica transistor 162 includes a plurality of transistor elements 162a and 162b connected in series. In this embodiment, it includes two P-channel MOS transistors connected in series. The source of the transistor element 162a is connected to the first input pin VIN1, and its drain is connected to the source of the transistor element 162b.

[0069] In the second mode, some of the plurality of transistor elements 162a and 162b can be bypassed by the switch SW. When the switch SW is turned on, the voltage drop of the replica transistor 162 becomes 1 / 2, and the threshold voltage ΔV IPEAK1 can be appropriately scaled.

[0070] The current source 164 is connected to the drain of the replica transistor 162 and supplies current to the replica transistor 162. The voltage ΔV IPEAK across both ends of the replica transistor 162 is defined according to the current generated by the current source 164.

[0071] The comparator 166 compares the voltage V DS1 across both ends of the first high-side transistor MH1 with the voltage ΔV IPEAK across both ends of the replica transistor 162. The comparator 166 may output an output signal IPEAKOUT indicating the comparison result to the abnormality detection circuit 190. In this embodiment, the output signal IPEAKOUT goes high when the first current reaches the first peak threshold, and goes low when the first current does not reach the first peak threshold. The current source 164 includes a constant current source 164a and a current DAC 164b, and the sum of their output currents may be supplied to the replica transistor 162.

[0072] The timer 168 outputs an output signal TIMEOUT according to the passage of time to the abnormality detection circuit 190 in the second mode. In this embodiment, the output signal TIMEOUT goes low during the detection period of the second mode and goes high at the timing when the detection period has elapsed.

[0073] Referring to FIGS. 9 and 10, the configuration of the first low-side current detection circuit 170_1 according to this embodiment will be described. FIG. 9 shows the state in the first mode, and FIG. 10 shows the state in the second mode. The second low-side current detection circuit 170_2 may be configured in the same manner as the first low-side current detection circuit 170_1.

[0074] The first low-side current detection circuit 170_1 compares the current I flowing through the first low-side transistor ML1 with a negative threshold value near or equal to zero. The first low-side current detection circuit 170_1 is a voltage comparator with an offset, and compares the drain voltage and the source voltage of the first low-side transistor ML1. ML1 The first low-side current detection circuit 170_1 includes a differential amplifier 172 with an offset and a voltage comparator 174. The differential amplifier 172 includes a tail current source 172a, an input differential pair 172b, and a resistive load 172c. The resistive load 172c is configured such that its resistance value can be switched according to the mode.

[0075] In the first mode, the first low-side current detection circuit 170_1 and the second low-side current detection circuit 170_2 operate independently. Specifically, the first low-side current detection circuit 170_1 detects a zero current or a negative current in the first low-side transistor ML1, and the second low-side current detection circuit 170_2 detects a zero current or a negative current in the second low-side transistor ML2.

[0076] (Power Management Circuit According to the Related Art and Its Problems)

[0077] Before explaining the details of the operation of the power management circuit 100 according to this embodiment, the operation of the power management circuit according to the related art and its problems will be described. The power management circuit according to the related art is mainly different from the power management circuit 100 according to this embodiment in that it does not include an abnormality detection circuit 190.

[0078] ​FIG. 11 is a diagram for explaining an example of the operation of the first overcurrent detection circuit 150_1 when the first output pin LX1 is open in the second mode. As shown in FIG. 11, when the first output pin LX1 is open, even if the first high-side transistor MH1 is in the on state, the voltage V DS1 across the first high-side transistor MH1 becomes 0V, and no current flows through the first high-side transistor MH1.

[0079] On the other hand, a current I_L1 flows from the on-state second high-side transistor MH2 to the inductor L1. At this time, the first overcurrent detection circuit 150_1 cannot detect the current of the first high-side transistor MH1. Therefore, even if the current I_L1 flowing through the inductor L1 becomes an overcurrent, the first overcurrent detection circuit 150_1 cannot detect the overcurrent, and there is a possibility that a current I_L1 larger than necessary flows through the inductor L1. Similarly, when the first input pin VIN1 is open instead of the first output pin LX1, the first overcurrent detection circuit 150_1 cannot detect the current I_L1 flowing through the inductor L1.

[0080] Thus, in the second mode, even if the first input pin VIN1 or the first output pin LX1 is open, the first overcurrent detection circuit 150_1 cannot appropriately detect an abnormality.

[0081] FIG. 12 is a diagram for explaining an example of the operation of the first peak current detection circuit 160_1 when the first output pin LX1 is open in the second mode. When the first output pin LX1 is open, as described with reference to FIG. 11, the voltage V DS1 across the first high-side transistor MH1 becomes 0V, and no current flows through the first high-side transistor MH1. On the other hand, a current I_L1 flows from the second high-side transistor MH2 to the inductor L1.

[0082] In the power management circuit according to the related art, when the comparison signal IPEAKOUT of the comparator 166 does not go high within a predetermined period, the first high-side transistor MH1 and the second high-side transistor MH2 are turned off, and the first low-side transistor ML1 and the second low-side transistor ML2 are turned on. At this time, if the output signal V OUT1 has a ripple greater than or equal to the extent at which OVP (Over Voltage Protection) operates, the shutdown function of the system operates.

[0083] With reference to FIG. 13, an example of the operation of the power management circuit according to the related art will be described. FIG. 13 is a timing chart showing an example of the operation of the power management circuit according to the related art when the first output pin LX1 is open.

[0084] At timing t11, the first high-side transistor MH1 and the second high-side transistor MH2 are turned on, and the current I_L2 flowing through the inductor L1 begins to increase. However, since the first output pin LX1 is open, no current flows through the first high-side transistor MH1, and the output signal IPEAKOUT of the comparator 166 remains low.

[0085] When a predetermined time elapses from timing t11, at timing t12, the output signal TIMEOUT of the timer 168 goes high. In response to this output signal TIMEOUT, the first high-side transistor MH1 and the second high-side transistor MH2 are each turned off, and the first low-side transistor ML1 and the second low-side transistor ML2 are each turned on. Accordingly, the voltage V of the first output pin LX1 LX1 drops.

[0086] Thereafter, the output signal V is charged by the output capacitor Co1 by the current I_L1 OUT1When it exceeds the threshold, the overvoltage protection function operates and the system shuts down (at timing t13). In this way, the system can be shut down by the overvoltage protection function of the system, and an abnormality in the power management circuit (open circuit of the first input pin VIN1 or the first output pin LX1) may be detected. However, as will be described later with reference to FIG. 14, there are cases where the overvoltage protection function does not operate and an abnormality in the power management circuit cannot be detected.

[0087] FIG. 14 is a timing chart showing another example of the operation of the power management circuit according to the related art when the first output pin LX1 is open.

[0088] At timings t21 to t22, the power management circuit operates in the same manner as at timings t11 to t12. After the first high-side transistor MH1 and the second high-side transistor MH2 are turned off and the first low-side transistor ML1 and the second low-side transistor ML2 are turned on at timing t22, the output signal V OUT1 If it does not reach the threshold, the overvoltage protection function does not operate, and there is a possibility that the power management circuit is determined to be normal. Also, depending on the system, there may be cases where there is no overvoltage protection function, or even if there is an overvoltage protection function, the system is not stopped in case of an abnormality.

[0089] In this way, according to the power management circuit according to the related art, even when the first input pin VIN1 and the first output pin LX1 are open, the abnormality may not be detected.

[0090] FIG. 15 is a diagram for explaining an example of the behavior of the first low-side current detection circuit 170_1 when the first ground pin PGND1 is open in the second mode. FIG. 16 is a timing chart for explaining an example of the operation of the first low-side current detection circuit 170_1 when the first ground pin PGND1 is open in the second mode.

[0091] As shown in FIG. 15, when the first ground pin PGND1 is open, the voltage dVds1 across both ends of the first low-side transistor ML1 becomes 0V, and no current flows through the first low-side transistor ML1. On the other hand, a current I_L2 flows from the second low-side transistor ML2 through the inductor L1.

[0092] Referring to FIG. 16, the operation of the power management circuit according to the related art will be described. At timing t31, the first low-side transistor ML1 and the second low-side transistor ML2 turn on. At this time, the voltage dVds1 across both ends of the first low-side transistor ML1 is 0V, and no current flows through the first low-side transistor ML1. Therefore, the output signal ZERODET_OH of the first low-side current detection circuit 170_1 becomes high, and it can be detected that an abnormality (open of the first ground pin PGND1) has occurred in the first output stage 118_1.

[0093] As described above, in the power management circuit according to the related art, when the first ground pin PGND1 is open, the abnormality can be detected.

[0094] Note that even when the first ground pin PGND1 and the second ground pin PGND2 are common to the ground pin PGND, when the first low-side transistor ML1 and the second low-side transistor ML2 turn on, no current flows through the first low-side transistor ML1. Therefore, even when the first ground pin PGND1 and the second ground pin PGND2 are common to the ground pin PGND, the abnormality can be detected by the first low-side current detection circuit 170_1.

[0095] As described above, in the power management circuit according to the related art, when the first ground pin PGND1 is open, the abnormality can be detected, but when the first input pin VIN1 or the first output pin LX1 is open, the abnormality may not be detected.

[0096] Generally, when the first input pin VIN1 or the first output pin LX1 is open, when mounting components such as chips on a PCB (Printed Circuit Board), these terminals are most likely to be open. The disconnection of the solder of the terminals during use occurs at the terminals at the corners of the package. The input pins and output pins are generally not arranged at the corners of the package and have a terminal shape with a large area. Therefore, the possibility of these terminals being open during use is low. Thus, it is preferable to be able to detect the abnormality when the first input pin VIN1 and the first output pin LX1 are open at the stage of mounting the chip on a PCB or the like.

[0097] (Operation in the second mode of the power management circuit according to the first embodiment) FIG. 17 is a flowchart for explaining an example of the operation in the second mode of the power management circuit 100 according to the first embodiment.

[0098] The first feedback controller 110_1 turns on the first high-side transistor MH1 and the second high-side transistor MH2 respectively (S101). Specifically, the first feedback controller 110_1 controls the control signals S H1 ,S L1 ,S H3 ,S L3 so that the first high-side transistor MH1 and the second high-side transistor MH2 are in the on state and the first low-side transistor ML1 and the second low-side transistor ML2 are in the off state. The timer 168 starts counting in response to the first high-side transistor MH1 and the second high-side transistor MH2 being turned on respectively (S103).

[0099] Next, the abnormality detection circuit 190 determines whether or not the current (first current) flowing through the first high-side transistor ML1 has reached the first peak threshold based on the output signal IPEAKOUT from the comparator 166 (S105). Specifically, when the output signal IPEAKOUT goes high during the detection period, the abnormality detection circuit 190 determines that the first current has reached the first peak threshold. When the output signal IPEAKOUT does not go high during the detection period, the abnormality detection circuit 190 determines that the first current has not reached the first peak threshold.

[0100] If it is determined in S105 that the first current has reached the first peak threshold, the first feedback controller 110_1 continues the operations of the first output stage 118_1 and the second output stage 118_2 (S109), and the process shown in FIG. 17 ends.

[0101] If it is determined in S105 that the first current has not reached the first peak threshold, the abnormality detection circuit 190 determines whether or not the detection period has elapsed based on the output signal TIMEOUT from the timer 168 (S107). Specifically, when the detection time has elapsed since the first high-side transistor MH1 and the second high-side transistor MH2 were each turned on, the abnormality detection circuit 190 determines that the detection period has elapsed. Also, when the detection time has not elapsed since the first high-side transistor MH1 and the second high-side transistor MH2 were each turned on, the abnormality detection circuit 190 determines that the detection period has not elapsed. If it is determined in S107 that the detection period has not elapsed, the process returns to S105.

[0102] When it is determined in S107 that the detection period has elapsed, the abnormality detection circuit 190 notifies the first feedback controller 110_1 that the first current has not reached the first peak threshold within the detection period (S111).

[0103] Next, the first feedback controller 110_1 stops the operations of the first output stage 118_1 and the second output stage 118_2 (S113). Specifically, the first feedback controller 110_1 turns off all of the first high-side transistor MH1, the first low-side transistor ML1, the second high-side transistor MH2, and the second low-side transistor ML2.

[0104] Next, the first feedback controller 110_1 determines whether to re-inspect the first current (S115). For example, when the number of times the processes of S101 to S107 (the process of determining whether the first peak has reached the first peak threshold value within the detection period) have been executed exceeds a predetermined number of times, the first feedback controller 110_1 may determine not to re-inspect the first current. Also, when the number of times the processes of S101 to S107 have been executed does not exceed a predetermined number of times, the sequencer 130 may determine to re-inspect the first current.

[0105] When it is determined in S115 not to re-inspect the first current, the process shown in FIG. 17 ends with the operations of the first output stage 118_1 and the second output stage 118_2 stopped.

[0106] When it is determined in S115 to re-inspect the first current, the first feedback controller 110_1 determines whether a certain period of time has elapsed since the first output stage 118_1 and the second output stage 118_2 stopped operating (S117). When it is determined in S117 that the certain period of time has not elapsed, the process of S117 is repeatedly executed. When it is determined in S117 that the certain period of time has elapsed, the process returns to S101, and the first feedback controller 110_1 starts (resumes) the operations of the first output stage 118_1 and the second output stage 118_2. Thereby, whether the first current reaches the peak threshold value is inspected again.

[0107] FIG. 18 is a timing chart showing an example of the operation of the power management circuit 100 according to the present embodiment. At timing t41, the first high-side transistor MH1 and the second high-side transistor MH2 are turned on respectively, and a current I_L1 starts to flow through the inductor L1. If the first current flowing through the first high-side transistor MH1 does not reach the first peak threshold value within the detection period T1 from timing t41 to timing t42, the output signal IPEAKOUT of the comparator 166 remains low.

[0108] At timing t42 when the detection period T1 elapses, the first feedback controller 110_1 stops the operations of the first output stage 118_1 and the second output stage 118_2. In response to this, the voltage V LX1 and the voltage V LX2 of the first output pin LX1 decrease. Thereby, the power management circuit 100 can suppress the current I_L1 from flowing through the inductor L1 and execute appropriate processing in response to an open of the first input pin VIN or the first output pin LX1. Also, due to the stop of this operation, the user can recognize an abnormality such as an open at the first input pin VIN or the first output pin LX1.

[0109] As described above, the configuration and operation of the power management circuit 100 according to the present embodiment have been described. According to the power management circuit 100 according to the present embodiment, in the second mode, in response to the first peak current detection circuit 160_1 detecting that the first current does not reach the first peak threshold value within the detection period during which the first current should reach the first peak threshold value, the operations of the first output stage 118_1 and the second output stage 118_2 stop. Thereby, appropriate processing in response to an abnormality such as an open of the first input pin VIN1 or the first output pin LX1 can be executed. Before an overcurrent flows through the inductor L1, the user can recognize an abnormality such as an open of the first input pin VIN1 or the first output pin LX1.

[0110] In the present embodiment, mainly, an example in which the first feedback controller 110_1 stops the operations of the first output stage 118_1 and the second output stage 118_2 has been described. However, the present invention is not limited to this. When the first current does not reach the peak threshold value within the detection period, the enable of the first circuit block BLK1 and the second circuit block BLK2 may be disabled. As a result, the control of the first output stage 118_1 and the second output stage 118_2 by the first feedback controller 110_1 ends, and the operations of the first output stage 118_1 and the second output stage 118_2 stop.

[0111] (Second Embodiment) FIG. 19 is a block diagram of the electronic device 14 according to the second embodiment. The electronic device 14 according to the second embodiment includes an external controller 300 in addition to the power management circuit 100. The external controller 300 stops the operations of the first output stage 118_1 and the second output stage 118_2 when the first current does not reach the peak threshold value within the detection period. The external controller 300 may include a sequential circuit configured by combining a plurality of discrete components.

[0112] In the second embodiment, the operations of the first output stage 118_1 and the second output stage 118_2 are stopped by the control from the external controller 300 in response to the first current not reaching the first peak threshold value within the detection period in the second mode.

[0113] FIG. 20 is a timing chart showing an example of the operation of the electronic device 14 in the second mode. At timing t51, the first output stage 118_1 and the second output stage 118_2 start operating, and the current I_L1 flowing through the inductor L1 starts to increase. If the first current does not reach the first peak threshold value within the detection period T1, the interrupt request IRQ goes high, and the abnormality detection circuit 190 communicates with the external controller 300. The external controller 300 transmits a control signal to the power management circuit 100 to stop the operations of the first output stage 118_1 and the second output stage 118_2. Thereby, the operations of the first output stage 118_1 and the second output stage 118_2 are stopped. Note that the external controller 300 may transmit a control signal to the power management circuit 100 to disable the first circuit block BLK1 and the second circuit block BLK2.

[0114] (Supplementary Note) Although the embodiments according to the present disclosure have been described using specific terms, this description is merely an exemplification for facilitating understanding and does not limit the present disclosure or the scope of the claims. The scope of the present invention is defined by the scope of the claims. Further, not only the embodiments but also the embodiments, examples, and modifications not described herein are included in the scope of the present invention. One or more elements of one embodiment can be combined with one or more elements of another embodiment.

[0115] (Appendix) The technology disclosed in this specification can be grasped as follows in one aspect.

[0116] (Item 1) a first output stage including a first high-side transistor and a first low-side transistor; a second output stage including a second high-side transistor and a second low-side transistor; a first peak current detection circuit that detects whether or not a first current flowing through the first high-side transistor reaches a first peak threshold value; A second peak current detection circuit that detects whether or not a second current flowing through the second high-side transistor has reached a second peak threshold value. In the first mode, the first output stage and the second output stage operate independently to generate respective individual output signals, and the first peak current detection circuit and the second peak current detection circuit are enabled. In the second mode, the first output stage and the second output stage operate in cooperation to generate a common output signal, and the first peak current detection circuit is enabled. The operations of the first output stage and the second output stage are stopped in the second mode in response to the first peak current detection circuit detecting that the first current does not reach the first peak threshold value within a detection period during which the first current is to reach the first peak threshold value. A power management circuit.

[0117] (Item 2) The detection period is a period from when the first high-side transistor and the second high-side transistor are each turned on in the second mode until a detection time has elapsed. The power management circuit according to Item 1.

[0118] (Item 3) The second peak current detection circuit is disabled in the second mode. The power management circuit according to Item 1 or 2.

[0119] (Item 4) In the second mode, if the first peak current detection circuit detects that the first current has reached the first peak threshold value within the detection period, the operations of the first output stage and the second output stage continue. The power management circuit according to any one of Items 1 to 3.

[0120] (Item 5) Further comprising a controller that controls the operations of the first output stage and the second output stage in the second mode. When the first current does not reach the first peak threshold value within the detection period, the controller stops the operations of the first output stage and the second output stage. The power management circuit according to any one of items 1 to 4.

[0121] (Item 6) In the second mode, when the first current does not reach the first peak threshold value within the detection period, the operations of the first output stage and the second output stage are stopped by control from a controller provided outside the power management circuit. The power management circuit according to any one of items 1 to 4.

[0122] (Item 7) In the second mode, when a certain period of time has elapsed after the controller stops the operations of the first output stage and the second output stage, the first high-side transistor and the second high-side transistor are each turned on. The first peak current detection circuit detects the first current in the detection period after the elapse of the certain period of time. The power management circuit according to item 5 or 6.

[0123] (Item 8) An electronic device including the power management circuit according to any one of items 1 to 7. Electronic device.

Explanation of Signs

[0124] 10 First System, 12 Second System, 14 Electronic Device, 100 Power Management Circuit, 110_1 First Feedback Controller, 110_2 Second Feedback Controller, 112_1 First Predriver, 112_2 Second Predriver, 114_1 First High-Side Predriver, 114_2 Second High-Side Predriver, 116_1 First Low-Side Predriver, 116_2 Second Low-Side Predriver, 118_1 First Output Stage, 118_2 Second Output Stage, 120 Mode Selector, 130 Sequencer, 140_1 First Current Detection Circuit, 140_2 Second Current Detection Circuit, 150_1 First Overcurrent Detection Circuit, 150_2 Second Overcurrent Detection Circuit, 160_1 First Peak Current Detection Circuit, 160_2 Second Peak Current Detection Circuit, 166 Comparator, 168 Timer, 170_1 First Low-Side Current Detection Circuit, 170_2 Second Low-Side Current Detection Circuit, 190 Abnormality Detection Circuit, 300 External Controller, BLK1 First Circuit Block, BLK2 Second Circuit Block, MH1 First High-Side Transistor, MH1 Second High-Side Transistor, MH2 Second High-Side Transistor, ML1 First High-Side Transistor, ML1 First Low-Side Transistor, ML2 Second Low-Side Transistor, VIN1 First Input Pin, VIN2 Second Input Pin, LX1 First Output Pin, LX2 Second Output Pin, PGND1 First Ground Pin, PGND2 Second Ground Pin.

Claims

1. a first output stage including a first high-side transistor and a first low-side transistor; a second output stage including a second high-side transistor and a second low-side transistor; a first peak current detection circuit configured to detect whether a first current flowing through the first high-side transistor has reached a first peak threshold; a second peak current detection circuit configured to detect whether a second current flowing through the second high-side transistor has reached a second peak threshold; and in a first mode, the first output stage and the second output stage operate independently to generate respective individual output signals, and the first peak current detection circuit and the second peak current detection circuit are enabled; in a second mode, the first output stage and the second output stage operate in cooperation to generate a common output signal, and the first peak current detection circuit is enabled; in the second mode, operations of the first output stage and the second output stage are stopped in response to the first peak current detection circuit detecting that the first current does not reach the first peak threshold within a detection period during which the first current is to reach the first peak threshold; a power management circuit.

2. The detection period is a period from when the first high-side transistor and the second high-side transistor are each turned on in the second mode until a detection time has elapsed. The power management circuit according to claim 1. The power management circuit according to claim 1.

3. The second peak current detection circuit is disabled in the second mode. The power management circuit according to claim 1. The power management circuit according to claim 1.

4. In the second mode, when the first peak current detection circuit detects that the first current has reached the first peak threshold within the detection period, operations of the first output stage and the second output stage continue. The power management circuit according to claim 1. The power management circuit according to claim 1.

5. further comprising a controller configured to control operations of the first output stage and the second output stage in the second mode; the controller stops operations of the first output stage and the second output stage when the first current does not reach the first peak threshold within the detection period. The power management circuit according to claim 1. The power management circuit according to claim 1.

6. In the second mode, the operations of the first output stage and the second output stage are stopped by control from a controller provided outside the power management circuit when the first current does not reach the first peak threshold value within the detection period. The power management circuit according to claim 1. **Claim 7** In the second mode, when a certain period of time has elapsed after the controller stops the operations of the first output stage and the second output stage, the controller turns on the first high-side transistor and the second high-side transistor respectively. The first peak current detection circuit detects the first current in the detection period after the elapse of the certain period of time. The power management circuit according to claim 5. **Claim 8** An electronic device comprising the power management circuit according to any one of claims 1 to 7. Electronic device.

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