Nonvolatile memory device

Abstract

To provide a nonvolatile memory device capable of improving stability of operations during reading.SOLUTION: A nonvolatile memory device (1) includes: a memory element (82) capable of executing a program operation; reference current generation units (2, 5, 6, and 7) configured to generate a constant current (I5); an N-channel MOSFET (92) having a first drain connected to the reference current generation unit, a first source connected to the drain of the memory element, and a first gate; an output stage (OUT) connected to the first drain to output read data; and a capacity (CC) connected between an applied end of a reverse signal of the first drain on the output stage and the first gate, in which the read data is output from the output stage based on the magnitude relationship between the constant current and a current (I2) flowing to the memory element.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present disclosure relates to a non-volatile memory device.

Background Art

[0002] Conventionally, there has been a non-volatile memory device that utilizes hot carrier injection into a transistor. This type of non-volatile memory device includes first and second transistors with aligned characteristics in an initial state as memory elements, and hot carriers are injected only into one of the transistors to change the characteristics of the transistor. In a subsequent read operation, based on the magnitude relationship of the drain currents when a common gate voltage is supplied to the first and second transistors, it is determined whether "0" data or "1" data is stored. For example, a state where the drain current of the first transistor is smaller (a state where the characteristics of the first transistor have changed) corresponds to a state where "0" data is stored, and a state where the drain current of the second transistor is smaller (a state where the characteristics of the second transistor have changed) corresponds to a state where "1" data is stored.

[0003] Note that the technology related to the above is disclosed in, for example, Patent Document 1.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] In the non-volatile memory device as described above, the stability of the operation during read (reading) is important.

[0006] In view of the above situation, an object of the present disclosure is to provide a non-volatile memory device capable of improving the stability of the operation during read.

[0007] A non-volatile memory device according to an aspect of the present disclosure includes a memory element capable of executing a program operation, a reference current generation unit configured to generate a constant current, an N-channel MOSFET having a first drain connected to the reference current generation unit, a first source connected to the drain of the memory element, and a first gate, an output stage connected to the first drain and configured to output read data, a capacitor connected between an application end of an inversion signal of the first drain in the output stage and the first gate, and is configured such that read data is output from the output stage based on a magnitude relationship between the constant current and the current flowing through the memory element. Also, a non-volatile memory device according to an aspect of the present disclosure includes a memory element capable of executing a program operation,

[0008] a constant current source configured to generate a constant current, a first mirror element configured to mirror the constant current generated by the constant current source, a second mirror element configured to mirror the constant current generated by the constant current source and including a gate connected to the gate of the first mirror element, a first gate voltage generation unit connected to the first mirror element and configured to generate a gate voltage of the memory element, a current generation unit configured to generate a reference current by copying the current flowing through the second mirror element, an N-channel MOSFET having a first drain connected to the current generation unit, a first source connected to the drain of the memory element, and a first gate, an output stage connected to the first drain and configured to output read data, and is configured such that read data is output from the output stage based on a magnitude relationship between the reference current and the current flowing through the memory element. and is configured such that read data is output from the output stage based on a magnitude relationship between the reference current and the current flowing through the memory element. and is configured such that read data is output from the output stage based on a magnitude relationship between the reference current and the current flowing through the memory element.

[0009] Also, a non-volatile memory device according to an aspect of the present disclosure includes a memory element capable of executing a program operation, a first constant current generation unit configured to generate a first constant current, a first gate voltage generation unit configured to generate a gate voltage of the memory element based on the first constant current, a second constant current generation unit independent of the first constant current generation unit and configured to generate a second constant current, an N-channel MOSFET having a first drain connected to the second constant current generation unit, a first source connected to the drain of the memory element, and a first gate, an output stage connected to the first drain and configured to output read data, and is configured such that read data is output from the output stage based on a magnitude relationship between the second constant current and a current flowing through the memory element.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

[0011] [Detailed Description] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0012] <Regarding Memory Elements> A memory element is an element capable of executing a program operation and is composed of a transistor. The memory element is also called an OTP element.

[0013] FIG. 1 is a diagram showing voltage application to a memory element MT during a program operation. The memory element MT is composed of an NMOS transistor (N-channel type MOSFET (metal-oxide-semiconductor field-effect transistor)). FIG. 2 is a longitudinal cross-sectional view of the memory element MT corresponding to FIG. 1.

[0014] As shown in FIGS. 1 and 2, during the program operation, a high voltage Vpp is applied to the gate G of the memory element MT, a high voltage Vpp is applied to the source S, and a ground potential Vss (= 0V) is applied to the drain D. The high voltage Vpp is, for example, +6.5V.

[0015] Due to such voltage application, as shown by the arrow in FIG. 2, hot carriers (electrons) flowing from the drain D to the source S side are generated directly below the gate G. The hot carriers are attracted by the high voltage Vpp (positive voltage) applied to the gate G and trapped by the sidewall SSw on the source S side provided along the side of the gate G (the trapped hot carriers E are illustrated in FIG. 2).

[0016] FIG. 3 is a diagram showing voltage application to memory elements MT1 and MT2 (NMOS transistors) during a read operation. FIG. 4 is a longitudinal cross-sectional view of the memory elements MT1 and MT2 corresponding to FIG. 3.

[0017] As shown in FIGS. 3 and 4, during the read operation, gate voltages Vg1 and Vg2 are applied to the respective gates G of the memory elements MT1 and MT2, drain voltages Vd1 and Vd2 are applied to the respective drains D, and a ground potential Vs (= 0 V) is applied to each source. The gate voltages Vg1 and Vg2 are, for example, 2 V. The drain voltages Vd1 and Vd2 are, for example, +0.5 V.

[0018] In FIGS. 3 and 4, as an example, a case is shown where the memory element MT1 is in a state before execution of a program operation (unprogrammed state) and the memory element MT2 is in a state after execution of a program operation (programmed state).

[0019] As shown in FIG. 4, in the memory element MT2 after the program operation has been executed, since hot carriers E are trapped in the sidewall SSw, an electric field due to the gate voltage Vg2 does not reach directly below the sidewall SSw, and the channel CN2 is interrupted on the source S side. Therefore, the gate threshold voltage becomes high and it is difficult for a drain current to flow. On the other hand, as shown in FIG. 4, the memory element MT1 in which the program operation has not been executed is in an on state because the gate threshold voltage is low, and a drain current flows.

[0020] Data can be read by utilizing the magnitude of the drain current depending on the unprogrammed state or the programmed state of such a memory element. Here, in FIG. 5, the solid line waveform INI represents the gate-source voltage dependency of the drain current of the memory element in the unprogrammed state, and the dotted line waveform PRG represents the gate-source voltage dependency of the drain current of the memory element in the programmed state. Thus, the gate threshold voltage Vth increases due to the program operation.

[0021] <First Embodiment> FIG. 6 is a diagram showing the configuration of the nonvolatile memory device 1 according to the first embodiment of the present disclosure.

[0022] The nonvolatile memory device 1 includes a constant current source 2, mirror elements 3 to 5, current mirrors 6 to 9, and inverters 10 and 11. The nonvolatile memory device 1 also includes switches SS1, SS2, SD, and SH. In FIG. 6, the power supply voltage VDD is, for example, VDD = +6.5V.

[0023] The constant current source 2 includes input transistors 21 and 22, PMOS transistors (P-channel MOSFETs) 23 and 24, a resistor 25, a drive transistor 26, and a resistor 27. The input transistors 21 and 22 are both composed of NMOS transistors. A reference voltage Vref is applied to the gate of the input transistor 21. The source of the input transistor 21 is connected to one end of the resistor 25. The drain of the input transistor 21 is connected to the drain of the PMOS transistor 23. The source of the PMOS transistor 23 is connected to the applied end of the power supply voltage VDD. The gate of the PMOS transistor 23 is connected to the gate of the PMOS transistor 24. The source of the PMOS transistor 24 is connected to the applied end of the power supply voltage VDD. The drain of the PMOS transistor 24 is connected to the drain of the input transistor 22. The drain and gate of the PMOS transistor 24 are short-circuited. The source of the input transistor 22 is connected to one end of the resistor 25. The other end of the resistor 25 is connected to the ground terminal (the applied end of the ground potential).

[0024] The drive transistor 26 is composed of a PMOS transistor. The source of the drive transistor 26 is connected to the applied end of the power supply voltage VDD. The gate of the drive transistor 26 is connected to the drain of the PMOS transistor 23. The drain of the drive transistor 26 is connected to one end of the resistor 27. The other end of the resistor 27 is connected to the ground terminal. The node Nd1 to which the drive transistor 26 and the resistor 27 are connected is connected to the gate of the input transistor 22.

[0025] A current I21 corresponding to a reference voltage Vref flows through the input transistor 21. A current I22 corresponding to a sense voltage Vsns flows through the input transistor 22. The sense voltage Vsns is generated at a node Nd1 (gate of the input transistor 22). The current I22 is mirrored by a current mirror formed by PMOS transistors 23 and 24, and becomes a current I23 flowing through the PMOS transistor 23. According to the balance between the currents I23 and I21, the gate of the drive transistor 26 is driven, and the on-resistance of the drive transistor 26 is adjusted. Thereby, the sense voltage Vsns is controlled to match the reference voltage Vref. The sense voltage Vsns and the resistor 27 generate a current I20 as a constant current.

[0026] The current mirror 8 includes a reference element 81, a data element 82, a resistor R2, and a switch SW8. Both the reference element 81 and the data element 82 are memory elements composed of NMOS transistors. As described above, the memory element is an element capable of executing a program operation. The data element 82 is the target of the program operation. That is, the data element 82 can take an unprogrammed state or a programmed state. The reference element 81 maintains the unprogrammed state.

[0027] The mirror element 4 is composed of a PMOS transistor. The source of the mirror element 4 is connected to the applied end of the power supply voltage VDD. The gate of the mirror element 4 is connected to the gate of the drive transistor 26. The drain of the mirror element 4 is connected to one end of the resistor R2.

[0028] The gate of the reference element 81 is connected to the other end of the resistor R2. A switch SW8 is connected between the other end of the resistor R2 and the drain of the reference element 81. The source of the reference element 81 is connected to the ground terminal. The gate of the data element 82 is connected to one end of the resistor R2. A switch SS1 is connected between the source of the data element 82 and the ground terminal.

[0029] The drain of the data element 82 is connected to the output-side transistor 72 of the current mirror 7 at the node Nd2 via the output-side transistor 92 included in the current mirror 9 described later.

[0030] The current I20 is mirror-ringed by the mirror element 4 and becomes the current I1. When the switch SW8 is in the on state, the current I1 flows through the reference element 81 and the resistor R2. The Vgs (gate-source voltage) of the data element 82 becomes a voltage obtained by adding the voltage generated across both ends of the resistor R2 to the Vgs of the reference element 81. That is, the gate voltage generation unit VGT1 composed of the resistor R2 and the reference element 81 generates the gate voltage of the data element 82. Note that the resistor R2 may be connected to the source of the reference element 81.

[0031] The reference element 81 and the data element 82 have the same structure and have the same electrical characteristics as each other before the execution of the program operation. Therefore, in the state before the program operation is executed on the data element 82 (the state where both the reference element 81 and the data element 82 are unprogrammed), the current (drain current) I2 flowing through the data element 82 satisfies I2 > I1.

[0032] Note that, for a transistor, the structure is a concept including the size of the transistor. Therefore, for any plurality of transistors, the fact that the structures are the same as each other means that the sizes of the plurality of transistors are also the same as each other. When the structures of a certain plurality of transistors are the same as each other, if hot carrier injection by a program operation is not performed on the plurality of transistors, the electrical characteristics (including the gate threshold voltage, etc.) of the plurality of transistors are also the same as each other. However, the fact that the structures and electrical characteristics of any plurality of transistors are the same means that they are the same in design, and actually may include errors (that is, the same is to be understood as a concept including errors).

[0033] Here, the mirror element 5 is composed of a PMOS transistor. The source of the mirror element 5 is connected to the applied end of the power supply voltage VDD. The gate of the mirror element 5 is connected to the gate of the drive transistor 26. The drain of the mirror element 5 is connected to the input side of a current mirror 6 composed of an NMOS transistor. The output side of the current mirror 6 is connected to the input side of a current mirror 7 composed of a PMOS transistor. Specifically, the current mirror 7 has an input side transistor 71 and an output side transistor 72. The drain of the input side transistor 71 is connected to the output side of the current mirror 6. The drain of the output side transistor 72 is connected to the drain of the output side transistor 92 at the node Nd2.

[0034] The current I20 is mirrored by the mirror element 5 to become the current I3. The current I3 is mirrored by the current mirror 6 to become the current I4. The current I4 is mirrored by the current mirror 7 to become the current I5. The current I5 flowing through the output side transistor 72 becomes a reference current (constant current). That is, the reference current generation unit is composed of the constant current source 2, the mirror element 5, and the current mirrors 6 and 7. For example, if I1 = I3 = I4 = I5 = 1 μA, in the state before the data element 82 executes the program operation (unprogrammed state), for example, I2 = 3 μA.

[0035] The node Nd2 is connected to the input end of the inverter 10. The input end of the inverter 11 is connected to the output end of the inverter 10. The output signal Sout is output from the output end of the inverter 11. The output stage OUT is composed of the inverters 10 and 11.

[0036] Switch SH is connected between the applied terminal of power supply voltage VDD and node Nd2. In the reset state with switch SH turned on, the voltage at the input terminal of inverter 10 is fixed at a high level, and output signal Sout is fixed at a high level. When switch SH is switched from the reset state to the off state, in the state before the data element 82 executes the programming operation (unprogrammed state), I2 > I5, current is drawn from node Nd2, and the voltage at the input terminal of inverter 10 drops to a low level. For example, in the case of the above current value example, since I2 = 3 μA and I5 = 1 μA, 2 μA of current is drawn from node Nd2. As a result, the output signal Sout output from inverter 11 becomes a low level. That is, output signal Sout is output as a signal indicating the state where "0" is stored.

[0037] On the other hand, in the state after the data element 82 executes the programming operation (programmed state), the gate threshold voltage of the data element 82 increases and I2 = 0. When switch SH is switched from the reset state to the off state, in the state after the data element 82 executes the programming operation, I5 > I2, and the voltage at the input terminal of inverter 10 is maintained at a high level. Therefore, the output signal Sout output from inverter 11 becomes a high level. That is, output signal Sout is output as a signal indicating the state where "1" is stored.

[0038] In this way, in the present embodiment, in the state before the data element 82 executes the programming operation, current mirror 8 generates current I2 that is larger than reference current I5, and in the state after the data element 82 executes the programming operation, I2 < I5. Then, by detecting the magnitude relationship between currents I2 and I5 by inverters 10 and 11 (output stage OUT), 1-bit data is read out.

[0039] When executing a program operation on the data element 82, the switch SS1 is in the off state, and the switches SD and SS2 are in the on state, so that a ground potential is applied to the drain of the data element 82 and a power supply voltage VDD is applied to the source of the data element 82. At this time, the switch SW8 is in the off state, and the power supply voltage VDD is applied to the gate of the data element 82. During the read operation, the switch SS1 is in the on state, and the switches SD and SS2 are in the off state. At this time, the switch SW8 is in the on state.

[0040] Next, the current mirror 9 will be described. The current mirror 9 is provided to control the drain voltage of the data element 82 to a low voltage. Thereby, it is suppressed that the data element 82 is erroneously programmed during the read operation.

[0041] The current mirror 9 includes an input-side transistor 91, an output-side transistor 92, and a resistor R1. The mirror element 3 is composed of a PMOS transistor.

[0042] The source of the mirror element 3 is connected to the application terminal of the power supply voltage VDD. The gate of the mirror element 3 is connected to the gate of the drive transistor 26. Both the input-side transistor 91 and the output-side transistor 92 are composed of NMOS transistors. The gate and drain of the input-side transistor 91 are short-circuited. The drain of the input-side transistor 91 is connected to the drain of the mirror element 3. The source of the input-side transistor 91 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the ground terminal. The gate of the output-side transistor 92 is connected to the gate of the input-side transistor 91. The source of the output-side transistor 92 is connected to the drain of the data element 82. The drain of the output-side transistor 92 is connected to the node Nd2.

[0043] The current I20 is mirror-ringed by the mirror element 3 and becomes the current I6. The current I6 flows through the input-side transistor 91 and the resistor R1. The voltage that is decreased by only the Vgs of the output-side transistor 92 from the voltage obtained by adding the voltage generated across both ends of the resistor R1 to the Vgs of the input-side transistor 91 is applied as the drain voltage of the data element 82. Note that a gate voltage generation unit VGT2 that generates the gate voltage of the output-side transistor 92 is configured from the input-side transistor 91 and the resistor R1.

[0044] Further, the nonvolatile memory device 1 has a storage circuit 15. The storage circuit 15 includes a data element 82, an output-side transistor 92, an output-side transistor 72, switches SS1, SS2, SD, SH, and inverters 10, 11. As described above, in this embodiment, it is possible to miniaturize the storage circuit 15 corresponding to one-bit data. Note that the nonvolatile memory device 1 actually corresponds to a plurality of bits (for example, 32 bits), and the storage circuit 15 is provided for each of the plurality of bits. Also, the configurations other than the storage circuit 15 in the configuration shown in FIG. 6 are common circuits for the plurality of bits.

[0045] <Regarding the First Problem> Next, the first problem solved by the nonvolatile memory device 1 according to the first embodiment will be described. As shown in FIG. 6, in the nonvolatile memory device 1, a capacitor CC is connected and provided between the output terminal of the inverter 10 (the application terminal of the inverted signal of the drain in the output-side transistor (NMOS transistor) 92) and the gate of the output-side transistor 92. The capacitor CC is configured by, for example, a MOS capacitor or a MIM (Metal-Insulator-Metal) capacitor. In particular, if the capacitor CC is configured by a MOM (Metal-Oxide-Metal) capacitor that uses the wiring capacitance, the circuit area can be reduced. The capacitor CC is included in the storage circuit 15. That is, the capacitor CC is provided for each of the plurality of bits.

[0046] Here, in the configuration of FIG. 6, assume that the capacitor CC is not provided. The problems in this case will be described with reference to the waveform diagram shown in FIG. 7. FIG. 7 is a diagram showing an example of the waveforms of the ramp voltage Vrp and the gate voltage IGT during read. The ramp voltage is the voltage generated at node Nd2 (the drain of the output transistor 72). The gate voltage IGT is the voltage applied to the gate of the output transistor 92.

[0047] When the switch SH switches from the on-state reset state to the off-state, if the data element 82 is in the unprogrammed state, I2 > I5, and the ramp voltage Vrp tries to drop from the high level to the low level. Here, there may be variations in the fall of the ramp voltage Vrp among the multiple-bit memory circuits 15. As shown in FIG. 7, assume that the ramp voltage Vrp1 in the memory circuit 15 corresponding to a certain first bit falls to the low level first. The ramp voltage Vrp1 first decreases gently and then drops steeply. The ramp voltage Vrp2 in the memory circuit 15 corresponding to a certain second bit (a bit different from the first bit) tries to fall later than the ramp voltage Vrp1. Assume that Vrp2 is decreasing gently when Vrp1 drops steeply. When Vrp1 drops, the gate voltage IGT decreases due to the parasitic capacitance C92 between the drain and gate of the output transistor 92 (the dashed line in FIG. 7). Then, the drain voltage of the data element 82 in the memory circuit 15 corresponding to the second bit decreases, and the drain current I2 decreases. As a result, the ramp voltage Vrp2 cannot decrease and increases (the dashed line in FIG. 7). Thereafter, the ramp voltage Vrp2 fluctuates, and the data to be read becomes difficult to be determined. That is, the read at a certain bit may affect the reads at other bits.

[0048] In order to solve the first problem of reduced operational stability during such a read operation, a capacitor CC is provided. Even when the lamp voltage Vrp1 falls, the output of the inverter 10 rises to a high level, so the gate voltage IGT rises via the capacitor CC (solid line in FIG. 7). Therefore, a decrease in the gate voltage IGT is suppressed, and a decrease in the drain current I2 in the memory circuit 15 corresponding to the second bit is suppressed. In this way, the capacitor CC has a cancellation compensation function that acts to cancel out a decrease in the gate voltage IGT. Therefore, the lamp voltage Vrp2 can fall (solid line in FIG. 7), and the read data is determined. That is, it is possible to suppress the influence of a read at a certain bit on the reads of other bits. Since the capacitor CC is provided for each of a plurality of bits, it is possible to suppress the influence from a read at any bit.

[0049] <Regarding the second problem> Next, the second problem solved by the nonvolatile memory device 1 according to the first embodiment will be described. Here, FIG. 9 is a diagram showing the configuration of a nonvolatile memory device 100 according to a comparative example for comparison.

[0050] The difference from the first embodiment (FIG. 6) of the configuration of the nonvolatile memory device 100 shown in FIG. 9 is that the current mirrors 6 and 7 are not provided, and the drain of the mirror element 5 is connected to the drain of the output-side transistor 92. As a result, the current I3 flowing through the mirror element 5 becomes a reference current (constant current), and data is read based on the magnitude relationship between the current I3 and the drain current I2.

[0051] In the non-volatile memory device 100, when the lamp voltage Vrp (the drain voltage of the mirror element 5) falls during a read operation, the gate voltage MGT of the mirror element 5 decreases due to the parasitic capacitance C5 between the drain and gate of the mirror element 5. Then, the Vgs of the mirror element 4 increases, and the current I1 increases. As a result, the gate voltage DGT of the data element 82 generated by the reference element 81 and the resistor R2 increases. Then, if the data element 82 is in an unprogrammed state, the drain current I2 flowing through the data element 82 increases. Here, the mirror element 5, the output-side transistor 92, and the data element 82 are provided for each of a plurality of bits. For the bits of the data element 82 in the programmed state, it is desired to suppress the decrease in the lamp voltage Vrp. However, the increase in the current capacity of the data element 82 due to the increase in the current I1 is greater than the increase in the current I3 flowing through the mirror element 5 due to the decrease in the gate voltage MGT, and the current I1 should be in a state where it may not vary.

[0052] As described above, in the non-volatile memory device 100, there is a risk that the operating stability may decrease due to the influence of the decrease in the lamp voltage Vrp during a read operation. Therefore, in order to solve such a second problem, in the non-volatile memory 1 (FIG. 6) according to the first embodiment, current mirrors 6 and 7 are provided. The current mirrors 6 and 7 constitute a current generation unit that copies the current I3 flowing through the mirror element 5 to generate a reference current I5. In this embodiment, when the lamp voltage Vrp falls, the gate voltage of the output-side transistor 72 included in the current mirror 7 decreases due to the parasitic capacitance between the drain and gate of the output-side transistor 72, but the influence on the gate voltage of the mirror element 4 is suppressed. Therefore, the influence on the current I1 is suppressed, and the operating stability is improved.

[0053] <Modification example> FIG. 8 is a diagram showing the configuration of the nonvolatile memory device 1 according to a modified example of the first embodiment. The difference between the configuration according to this modified example and the first embodiment (FIG. 6) is the current mirror 70. The current mirror 70 includes an input-side transistor 71 and an output-side transistor 73. The input-side transistor 71 is common to the current mirror 7. The drain of the output-side transistor 73 composed of a PMOS transistor is connected to the drain of the input-side transistor 91 included in the gate voltage generation unit VGT2. As a result, the current I4 flowing through the input-side transistor 71 is mirrored to become the current I6 flowing through the output-side transistor 73, and the current I6 is supplied to the input-side transistor 91.

[0054] According to such a configuration, at startup, the gate voltage of the data element 82 rises, the current I5 starts to flow, and the input-side transistor 91 starts to operate and the output-side transistor 92 becomes in a state where it can conduct current in this order. As a result, when the data element 82 is in the program state and it is expected that the lamp voltage Vrp maintains a high level, the fall of the lamp voltage Vrp is suppressed.

[0055] <Second Embodiment> FIG. 10 is a diagram showing the configuration of the nonvolatile memory 1X according to the second embodiment of the present disclosure. The difference between the configuration of the nonvolatile memory device 1X and the above comparative example (FIG. 9) is that the constant current sources 2A and 2B are provided.

[0056] The constant current sources 2A and 2B are independent and are each configured in the same manner as the internal configuration of the constant current source 2 shown in FIG. 9. The gate of the mirror element 5 is connected to the gate of the drive transistor of the constant current source 2A (not shown in FIG. 10, corresponding to the drive transistor 26 in FIG. 9). The gates of the mirror elements 3 and 4 are commonly connected to the gate of the drive transistor of the constant current source 2B (not shown in FIG. 10). The constant current generation unit 200A is configured from the mirror element 5 and the constant current source 2A, and the constant current generation unit 200A generates a constant current I3. The constant current generation unit 200B is configured from the mirror elements 3 and 4 and the constant current source 2B, and the constant current generation unit 200B generates constant currents I6 and I1.

[0057] With such a configuration, when the lamp voltage Vrp drops during readout, the gate voltage MGTA of the mirror element 5 decreases due to the parasitic capacitance C5 between the drain and gate of the mirror element 5. However, since the constant current sources 2A and 2B are independent, the influence on the gate voltage MGTB of the mirror element 4 is suppressed. Therefore, the influence on the current I1 is suppressed, and the stability of the operation during readout is improved.

[0058] <Others> Various technical features disclosed in this specification can be variously modified in addition to the above embodiments without departing from the gist of the technical creation. That is, the above embodiments should be considered as illustrative in all respects and not restrictive, and the technical scope of the present invention is not limited to the above embodiments, but should be understood to include all modifications belonging to the meaning and scope equivalent to the claims.

[0059] <Appendix> As described above, the non-volatile memory device (1) according to one aspect of the present disclosure is a memory element (82) capable of executing a program operation, a reference current generation unit (2, 5, 6, 7) configured to generate a constant current (I5), an N-channel MOSFET (92) having a first drain connected to the reference current generation unit, a first source connected to the drain of the memory element, and a first gate, an output stage (OUT) connected to the first drain and configured to output read data, a capacitor (CC) connected between the application end of the inverted signal of the first drain in the output stage and the first gate, and is provided with configured such that read data is output from the output stage based on the magnitude relationship between the constant current and the current (I2) flowing through the memory element (first configuration).

[0060] Further, in the above-described first configuration, the memory element, the N-channel MOSFET, the output stage, and the storage circuit having the capacitor may be provided for each of a plurality of bits (second configuration).

[0061] Further, in the above-described first or second configuration, the capacitor (CC) may be configured by a MOM capacitor (third configuration).

[0062] Also, a non-volatile memory device (1) according to an aspect of the present disclosure includes a memory element (82) capable of executing a program operation, a constant current source (2) configured to generate a constant current (I20), a first mirror element (4) configured to mirror the constant current generated by the constant current source, a second mirror element (5) configured to mirror the constant current generated by the constant current source and including a gate connected to the gate of the first mirror element, a first gate voltage generation unit (VGT1) connected to the first mirror element and configured to generate a gate voltage of the memory element, a current generation unit (6, 7) configured to generate a reference current (I5) by copying a current (I3) flowing through the second mirror element, an N-channel MOSFET (92) having a first drain connected to the current generation unit, a first source connected to the drain of the memory element, and a first gate, an output stage (OUT) connected to the first drain and configured to output read data, and is configured such that read data is output from the output stage based on a magnitude relationship between the reference current and a current (I2) flowing through the memory element (fourth configuration).

[0063] ​Also, in the fourth configuration described above, the current generation unit may have a first current mirror (6) connected to the second mirror element and a second current mirror (7) connected to the first current mirror and configured to output the reference current (fifth configuration).

[0064] Also, in the fourth or fifth configuration described above, a third current mirror (70) that commonly has an input - side transistor (71) included in the second current mirror (7) and has an output - side transistor (73), and a second gate voltage generation unit (VGT2) configured to generate the voltage of the first gate based on the current (I6) flowing through the output - side transistor may be provided (sixth configuration).

[0065] Also, in any of the fourth to sixth configurations described above, the first gate voltage generation unit (VGT1) may have a MOS transistor (81) with a short - circuited gate - drain and a second resistor (R2) connected to the drain or source of the MOS transistor (seventh configuration).

[0066] Also, a non - volatile memory device (1X) according to an aspect of the present disclosure includes a memory element (82) capable of executing a program operation, a first constant - current generation unit (200B) configured to generate a first constant current (I1), a first gate voltage generation unit (VGT1) configured to generate the gate voltage of the memory element based on the first constant current, a second constant - current generation unit (200A) that is independent of the first constant - current generation unit and is configured to generate a second constant current (I3), an N - channel MOSFET (92) having a first drain connected to the second constant - current generation unit, a first source connected to the drain of the memory element, and a first gate, an output stage (OUT) connected to the first drain and configured to output read data, and is provided with Based on the magnitude relationship between the second constant current and the current (I2) flowing through the memory element, read data is output from the output stage (eighth configuration).

[0067] Further, in the eighth configuration described above, a third constant current generation unit (200B) that is independent of the second constant current generation unit (200A) and is configured to generate the third constant current (I6); and a second gate voltage generation unit (VGT2) configured to generate the voltage of the first gate based on the third constant current may be provided (ninth configuration).

Industrial Applicability

[0068] The present disclosure can be used, for example, in non-volatile memory devices mounted on various semiconductor devices.

Explanation of Signs

[0069] 1,1X Non-volatile memory device 2,2A,2B Constant current source 3 - 5 Mirror element 6 - 9 Current mirror 10,11 Inverter 15 Memory circuit 21,22 Input transistor 23,24 PMOS transistor 25 Resistor 26 Drive transistor 27 Resistor 70 Current mirror 71 Input-side transistor 72 Output-side transistor 73 Output-side transistor 81 Reference element 82 Data element 91 Input-side transistor 92 Output-side transistor 100 Non-volatile memory device 200A,200B Constant current generation unit C5,C92 Parasitic capacitance CC Capacitance E hot carrier MT, MT1, MT2 memory elements OUT output stage R1, R2 resistors SS1, SS2, SD, SH switches SSw sidewall SW8 switch VGT1, VGT2 gate voltage generation units

Claims

1. A memory element capable of executing a program operation, A reference current generation unit configured to generate a constant current, An N-channel MOSFET having a first drain connected to the reference current generation unit, a first source connected to the drain of the memory element, and a first gate, An output stage connected to the first drain and configured to output read data, A capacitor connected between an application end of an inversion signal of the first drain in the output stage and the first gate, Comprising, A non-volatile memory device in which read data is output from the output stage based on a magnitude relationship between the constant current and a current flowing through the memory element.

2. The non-volatile memory device according to claim 1, wherein a storage circuit having the memory element, the N-channel MOSFET, the output stage, and the capacitor is provided for each of a plurality of bits.

3. The non-volatile memory device according to claim 1, wherein the capacitor is constituted by a MOM capacitor.

4. A memory element capable of executing a program operation, A constant current source configured to generate a constant current, A first mirror element configured to mirror the constant current generated by the constant current source, A second mirror element configured to mirror the constant current generated by the constant current source and including a gate connected to the gate of the first mirror element, A first gate voltage generation unit connected to the first mirror element and configured to generate a gate voltage of the memory element, A current generation unit configured to generate a reference current by copying a current flowing through the second mirror element, An N-channel MOSFET having a first drain connected to the current generation unit, a first source connected to the drain of the memory element, and a first gate, An output stage connected to the first drain and configured to output read data, Comprising, A non-volatile memory device in which read data is output from the output stage based on a magnitude relationship between the reference current and a current flowing through the memory element.

5. The current generation unit is A first current mirror connected to the second mirror element, A second current mirror connected to the first current mirror and configured to output the reference current, The non-volatile memory device according to claim 4, having.

6. A third current mirror that commonly has the input-side transistors included in the second current mirror and has output-side transistors; A second gate voltage generation unit configured to generate the voltage of the first gate based on the current flowing through the output-side transistors; The non-volatile memory device according to claim 5, comprising the above.

7. The first gate voltage generation unit includes: A MOS transistor with a short-circuited gate-drain; A second resistor connected to the drain or source of the MOS transistor; The non-volatile memory device according to claim 4, having the above.

8. A memory element capable of executing a program operation; A first constant current generation unit configured to generate a first constant current; A first gate voltage generation unit configured to generate the gate voltage of the memory element based on the first constant current; A second constant current generation unit independent of the first constant current generation unit and configured to generate a second constant current; An N-channel MOSFET having a first drain connected to the second constant current generation unit, a first source connected to the drain of the memory element, and a first gate; An output stage connected to the first drain and configured to output read data; Comprising: A non-volatile memory device in which read data is output from the output stage based on the magnitude relationship between the second constant current and the current flowing through the memory element.

9. A third constant current generation unit independent of the second constant current generation unit and configured to generate a third constant current; A second gate voltage generation unit configured to generate the voltage of the first gate based on the third constant current; The non-volatile memory device according to claim 8, comprising the above.

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