Coordinate rotation processing device, phase-limited correlation calculation device, methods for the same, and program

Abstract

To provide a coordinate rotation processing device, a phase-limited correlation calculation device, a method for the same, and a program that achieve a small scale circuit that obtains an output vector having a difference between deflection angles of two input vectors as a new deflection angle and a magnitude (intensity) not depending on the input vectors.SOLUTION: A coordinate rotation processing device 100 can be used in a phase-limited correlation calculation device for associating two images. A CORDIC processing unit 101 performs: first phase processing of inputting a vector based on a first input vector and a normalization vector in which orthogonal coordinates are represented by (N, 0), to obtain a normalized first vector having a deflection angle of the first input vector; and second phase processing of inputting a second input vector and a vector based on the normalized first vector to the CORDIC processing unit, to obtain an output vector having a difference between deflection angles of the first input vector and the second input vector as the deflection angle.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a coordinate rotation processing device, a phase-limited correlation operation device, and methods and programs thereof.

Background Art

[0002] Conventionally, in the fields of communication and image / video signal processing, there are techniques for associating (matching, aligning) two signals or images. For example, by aligning the positions of objects in two images on the left and right sides in stereo vision as in Patent Document 1, distance measurement and three-dimensional measurement become possible. Also, as in Patent Document 2, by searching for a registered marker image from a captured image and aligning it, for example, positioning of a substrate of a lithography apparatus is performed. In recent years, in order to improve the above-described measurement accuracy and alignment accuracy, there has been an increasing demand for a robust alignment with sub-pixel accuracy higher than that of pixels of a captured image and independent of an imaging target and imaging conditions. In order to meet this demand, a technique using a phase-limited correlation function is known (Patent Document 1 and Non-Patent Document 1).

[0003] On the other hand, in the technique using a phase-limited correlation function, the amount of calculation required for two-dimensional discrete Fourier transform and the amount of calculation required for phase operation (vector operation) for two images increase. As a lightweight vector operation technique, a coordinate data rotation arithmetic unit called "CORDIC" that can realize coordinate rotation only by repeating bit shift and addition / subtraction is disclosed in Non-Patent Document 2. Also, Patent Documents 3 and 4 disclose vector-mode CORDIC and rotation-mode CORDIC. Vector-mode CORDIC converts rectangular coordinates to polar coordinates and outputs the distance (absolute value) from the origin of two-dimensional coordinates. Rotation-mode CORDIC inputs the declination information obtained in vector mode as a rotation angle and outputs orthogonal coordinates obtained by rotating other orthogonal coordinates by the rotation angle.

Prior Art Documents

Patent Documents

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-071922 [Patent Document 2] Japanese Patent Application Laid-Open No. 2017-015994 [Patent Document 3] Japanese Patent No. 3283504 [Patent Document 4] Japanese Patent Application Laid-Open No. 2017-123057 [Non-Patent Document]

[0005] [Non-Patent Document 1] Sei Nagashima, Takafumi Aoki, Tatsuo Higuchi, Koji Kobayashi, "Improvement of High Performance Subpixel Image Matching Based on Phase Limited Correlation Method", The 218th Research Meeting of the Tohoku Branch of the Instrumentation and Control Engineers Society (October 9, 2004), Document No. 218-15 [Non-Patent Document 2] J. E. Volder. "The CORDIC trigonometric computing technique", IRE Transactions on Electronic Computers, EC-8:330-334, 1959. [Summary of the Invention] [Problems to be Solved by the Invention]

[0006] In phase-limited correlation operation, it is necessary to generate a normalized output vector by using the difference in the phase angles of two input vectors as a new phase angle. Patent Document 3 does not suggest any configuration for generating such an output vector. Also, in Patent Document 4, an output vector having the difference in the phase angles of two input vectors can be obtained, but a circuit (a circuit for performing absolute value calculation and division) for performing normalization processing is required to obtain a normalized output vector, resulting in an increase in the circuit scale.

[0007] An object of the present invention is to realize a small-scale circuit that obtains an output vector having a magnitude (strength) independent of the input vectors by using the difference in the declination angles of two input vectors as a new declination angle.

Means for Solving the Problem

[0008] A coordinate rotation processing device according to an aspect of the present invention includes: a CORDIC processing unit that outputs a vector having an angle obtained by rotating one of the two vectors by an angle of the other vector and a magnitude obtained by multiplying the magnitude of the one vector by a scaling factor in response to the input of the two vectors; a first phase processing means for generating a normalized first vector having an angle of the first input vector and a magnitude obtained by multiplying the magnitude of the normalized vector by the scaling factor from the first input vector and the normalized vector represented by (N, 0) in orthogonal coordinates using the CORDIC processing unit; a second phase processing means for generating an output vector having an angle obtained by rotating the normalized first vector by an angle of the second input vector and a magnitude obtained by multiplying the magnitude of the normalized first vector by the scaling factor from the second input vector and the normalized first vector using the CORDIC processing unit.

Advantages of the Invention

[0009] According to the present invention, a circuit that obtains an output vector having a magnitude (strength) independent of the input vectors by using the difference in the declination angles of two input vectors as a new declination angle can be realized on a small scale.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential for the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0012] <First Embodiment> FIG. 1(A) and FIG. 1(B) are diagrams showing a configuration example of the coordinate rotation processing apparatus according to the present embodiment. FIG. 1(A) is a functional block diagram showing each functional unit corresponding to each process performed by the coordinate rotation processing apparatus 100 according to the present embodiment. FIG. 1(B) is a block diagram showing a hardware configuration example of the data processing apparatus 110 that realizes the coordinate rotation processing apparatus 100 shown in FIG. 1(A).

[0013] As shown in FIG. 1(B), the data processing apparatus 110 includes a CPU 111, a RAM 112, a ROM 113, a communication I / F (interface) 114, a recording I / F 115, and a display I / F 116, and can be realized by an information processing apparatus such as a so-called personal computer. The data processing apparatus 110 can be connected to a recording medium 120 such as a hard disk or a semiconductor memory via the recording I / F 115, and can be connected to a display device 121 such as a liquid crystal display via the display I / F 116. Further, the data processing apparatus 110 can be connected to, for example, an imaging device 130 and various NWs (networks) 131 via the communication I / F 114.

[0014] The ROM 113 holds various programs including the data processing program according to the present embodiment. The program in the ROM 113 is expanded in the RAM 112 and executed by the CPU 111. The RAM 112 is used as a work area of the CPU 111 in addition to the program being expanded, and temporarily stores input image data, image data during processing, and the like.

[0015] The communication I / F 114 communicates with, for example, the imaging device 130 and the network 131. When the communication I / F 114 receives image data or the like sent from, for example, the imaging device 130 or the network 131, those image data are temporarily stored in the RAM 112 under the control of the CPU 111. The CPU 111 performs various image processes and the like on those image data as necessary, and displays them on the screen of the display device 121 via the display I / F 116, or records them on the recording medium 120 via the recording I / F 115.

[0016] The CPU 111 performs various processes and controls in the data processing device 110, and can also execute a data processing program and the like according to the present embodiment to perform various image processes including data conversion processing as described later. In the present embodiment, an example is given in which the processing of each functional unit of the coordinate rotation processing device 100 in Fig. 1(A) is realized by software processing in which the CPU 111 executes a program. Of course, the processing of each of those functional units may be realized by a hardware configuration such as a circuit corresponding to each. Also, each functional unit may be realized by one device, or may be realized by a plurality of devices.

[0017] As shown in Fig. 1(A), the coordinate rotation processing device 100 includes a Vector-Rotation CORDIC processing unit (hereinafter referred to as the CORDIC processing unit 101), a data selection unit 102, a data holding unit 103, and a control unit 104.

[0018] First, the CORDIC processing unit 101 will be described. When the processing is completed in the vector mode processing and the rotation mode processing and the declination is not required externally, it is redundant to convert the rotation direction information into the declination in the vector mode processing and return it to the original rotation direction information in the rotation mode processing. If the rotation direction information is directly sent from the vector mode processing to the rotation mode processing, the coordinate rotation operation can be performed efficiently, and since the conversion / inverse conversion to the declination is not required, low-latency processing becomes possible.

[0019] Fig. 2 shows a configuration example of the CORDIC processing unit 101. As shown in Fig. 2, there are two pipelines: a pipeline CORDIC 201 composed of a coordinate rotation arithmetic unit that performs vector mode processing, and a pipeline CORDIC 202 composed of a coordinate rotation arithmetic unit that performs rotation mode processing. Between the corresponding coordinate rotation arithmetic units of each stage of these two pipelines, two-valued rotation direction information 203 indicating the rotation direction is sent from the vector mode (pipeline CORDIC 201) to the rotation mode (pipeline CORDIC 202). The pipeline CORDIC 201 (vector mode processing) repeats a plurality of rotation processes described later for the input vector (x 0 ', y 0 ') to rotate by the argument angle of the input vector and converge to a vector with a magnitude multiplied by the scaling factor. The pipeline CORDIC 202 (rotation mode processing) repeats a plurality of rotation processes according to the rotation direction information 203 to perform the same plurality of rotation processes as the vector mode processing on the input vector (x 0 , y 0 ). As a result, from the pipeline CORDIC 202, a vector obtained by rotating the input vector (x 0 , y 0 ) by the argument angle of the input vector (x 0 ', y 0 ) and scaling it by the scaling factor is obtained.

[0020] Fig. 3 shows the circuit configuration of the i-th stage (i = 0, 1, 2, 3 ···) of the pipeline. Fig. 3 shows a coordinate rotation arithmetic unit 301 that performs the i-th stage vector mode processing and a coordinate rotation arithmetic unit 302 that performs the i-th stage rotation mode processing. The coordinate rotation arithmetic unit 301 and the coordinate rotation arithmetic unit 302 have the same circuit configuration. However, the sign bit sign(y i ') of y i ' is input to the adder / subtractor 304 of the coordinate rotation arithmetic unit 301, and the value obtained by inverting the sign bit sign(y i ') by the inverter 306 is input to the adder / subtractor 304 of the coordinate rotation arithmetic unit 302. That is, y iThe sign bit of ' sign(y i ') is used as the rotation direction information 203 indicating the rotation direction at each stage of the rotation mode process. The input data x i ', y i ' is vector coordinate data, and the coordinate rotation operation unit 301 receives this data and performs vector mode operations using two shift circuits 303 and two adders / subtracters 304. Each operation result is recorded in the register 305 as output data x i+1 ' and y i+1 ' and provided to the next stage (stage i + 1). Also, the input data x i , y i is rotation coordinate data, and the coordinate rotation operation unit 302 performs rotation mode operations on the input rotation coordinate data using two shift circuits 303 and two adders / subtracters 304.

[0021] The direction of coordinate rotation by the adder / subtracter 304 of the coordinate rotation operation unit 301 and the coordinate rotation operation unit 302 is determined by the sign bit of the y i ' data, that is, sign(y i '). For example, assuming that the vector coordinate data (x i ', y i ) is in the first or fourth quadrant, if sign(y i ) = 0, a right rotation operation is performed, and if sign(y i ) = 1, a left rotation operation is performed. On the other hand, in the coordinate rotation operation unit 302, since sign(y i ) is inverted by the inverter 306, if sign(y i ) = 0, a left rotation operation is performed, and if sign(y i ) = 1, a right rotation operation is performed. The operation processes by the coordinate rotation operation unit 301 and the coordinate rotation operation unit 302 are common. Hereinafter, the operation of the coordinate rotation operation unit 302 will be described. For example, in the adder / subtracter 304, the rotation operation of rotating the rotation coordinate data x i , y i to the right to obtain x i+1 , y i+1 is as follows. x i+1 = x i + (2 -i)·y i y i+1 =y i -(2 -i )·x i ··· (1)

[0022] The data on the left side of Equation (1) becomes the input data of the operation unit in the next stage (stage (i + 1)). Also, the data obtained by multiplying (2 -i ) with the data on the right side of Equation (1) is the data x i , y i that is obtained by the shift circuit 303 which right-shifts i bits. On the other hand, when rotating left, the addition on the right side of Equation (1) is switched to subtraction and the subtraction is switched to addition for calculation. With the above circuit configuration, in the case of an n-stage pipeline, in vector mode processing, the angle of the input vector (x 0 ', y 0 ') converges to 0° (y n ' = 0) and n rotations are performed. And in rotation mode processing, the same rotations as the n rotations in vector mode processing are applied to the input vector (x 0 , y 0 ). In rotation mode processing, since the signal obtained by inverting sign(y i ') by the inverter 306 is used, as will be described later with reference to FIGS. 5(A) and 5(B), the input vector (x 0 , y 0 ) rotates by the angle of the input vector (x 0 ', y 0 ) in the direction of that angle.

[0023] Based on the angle information of the vector input to the vector mode processing (pipeline CORDIC201) as described above, a new vector obtained by rotating the vector input to the rotation mode processing (pipeline CORDIC202) is generated. Note that although the case where CORDIC has a pipeline configuration has been described above, the present disclosure is not limited to such a pipeline configuration and is also applicable to a recursive configuration of CORDIC, and the same effects can be obtained.

[0024] In FIG. 1, the vector input orthogonal coordinate data 10 corresponds to the above-described coordinate data for vectors, and the rotation input orthogonal coordinate data 13 corresponds to the above-described coordinate data for rotation. Therefore, the CORDIC processing unit 101 generates a vector (rotation output orthogonal coordinate data 14) obtained by rotating the vector to be rotated (rotation input orthogonal coordinate data 13) by the deflection angle of the input vector (vector input orthogonal coordinate data 10) of the coordinate rotation processing apparatus 100. In the first phase processing described later, the rotation output orthogonal coordinate data 14 is stored in the data holding unit 103 as a normalized first vector (described later). Also, in the second phase processing described later, the rotation output orthogonal coordinate data 14 is output as an output vector (described later) of the coordinate rotation processing apparatus 100. The data selection unit 102 selects either a normalized vector of (N, 0) with the normalization intensity being N or one of the output orthogonal coordinate data 12 read from the data holding unit 103, and supplies it to the CORDIC processing unit 101 as the rotation input orthogonal coordinate data 13. More specifically, the data selection unit 102 selects a normalized vector in the first phase processing described later, and selects the output orthogonal coordinate data 12 read from the data holding unit 103 in the second phase processing described later. The control unit 104 controls using the CORDIC processing unit 101, the data selection unit 102, and the data holding unit 103 to obtain an output vector having a deflection angle that is the difference in the deflection angles of the first input vector and the second input vector and having an intensity independent of the first input vector and the second input vector.

[0025] FIG. 4(A) is a flowchart showing the coordinate rotation processing by the coordinate rotation processing apparatus 100 of the first embodiment. FIG. 5 is an image diagram of vector rotation in the first phase processing and the second phase processing. Hereinafter, the processing of the coordinate rotation processing apparatus 100 will be described using these figures. In the present embodiment, an output vector having a phase difference between the first input vector and the second input vector as the deflection angle and having a normalized intensity independent of the first input vector and the second input vector is obtained by two processing steps of the first phase processing (S401) and the second phase processing (S402).

[0026] (First Phase Processing) In S401, the control unit 104 executes the first-phase processing. In the first-phase processing, the control unit 104 inputs the first input vector as the vector input orthogonal coordinate data 10 and the normalized vector (N, 0) with the intensity N as the rotation input orthogonal coordinate data 13 to the CORDIC processing unit 101. As a result, from the CORDIC processing unit 101, the rotation output orthogonal coordinate data 14 having the deflection angle of the first input vector and the intensity N1 obtained by scaling the intensity N by the scaling coefficient is obtained. Hereinafter, the rotation output orthogonal coordinate data 14 obtained by the first-phase processing is referred to as the normalized first vector. Here, the scaling coefficient is a coefficient corresponding to the number of processing stages of CORDIC. When the number of rotations is i, the intensity N1 of the normalized first vector is N1 = N(1 + 2 -2i ) 1 / 2 as shown. Therefore, the intensity N1 of the normalized first vector depends on the number of rotations i and does not depend on the input vector.

[0027] Fig. 5(A) shows the vector image of the first-phase processing. When the deflection angle of the first input vector 501 is θ 1 , the normalized vector 502 (θ = 0) is rotated by θ 1 by the rotation processing by the CORDIC processing unit 101, and the normalized first vector 503 having the deflection angle of θ 1 is generated as shown in the figure. The obtained normalized first vector 503 is stored in the data holding unit 103. Note that the data holding unit 103 may be an internal memory composed of an SRAM or a register, or may be an external memory such as a DRAM or an external recording device.

[0028] (Second-phase processing) In step S402, the control unit 104 executes the second-phase process. In the second-phase process, the control unit 104 inputs the second input vector to the CORDIC processing unit 101 as the vector input orthogonal coordinate data 10. Also, the data selection unit 102 selects the normalized first vector stored in the data holding unit 103 by the first-phase process (step S401). At this time, the data selection unit 102 generates conjugate data of the selected normalized first vector (data with the sign of the Y-axis data inverted in orthogonal coordinates) and provides it to the CORDIC processing unit 101 as the rotation input orthogonal coordinate data 13. As a result, a normalized second vector having the phase difference between the first input vector and the second input vector as the deflection angle is obtained as the output vector. Note that the intensity N2 of the output vector obtained by the second-phase process is a value obtained by multiplying N1 by the scaling factor. If the number of rotations is i, then N2 = N1(1 + 2 -2i ) 1 / 2 is shown. Thus, similar to the intensity N1 of the normalized first vector, the intensity N2 of the normalized second vector depends only on the number of rotations i and does not depend on the input vector.

[0029] FIG. 5(B) shows a vector image of the second-phase process. As described above, the second input vector 511 is used as the vector input orthogonal coordinate data 10, and the conjugated normalized first vector 503' obtained by conjugating the normalized first vector 503 is used as the rotation input orthogonal coordinate data 13 (θ = -θ 1 ) and is input to the CORDIC processing unit 101. When the deflection angle of the second input vector 511 is θ 2 , the conjugated normalized first vector 503' is rotated by θ 2 by the rotation process of the CORDIC processing unit 101, and as shown in the figure, a normalized second vector 512 having a deflection angle of θ 2 -θ 1 is generated. Thus, the normalized second vector 512 is obtained from the coordinate rotation processing device 100 as the output vector.

[0030] In S403, the control unit 104 determines whether to newly execute the first-phase processing and the second-phase processing. When the first input vector or the second input vector is newly input or updated (YES in S403), the control unit 104 determines to newly execute the first-phase processing and the second-phase processing. In this case, the process returns to S401, and the above-described first-phase processing and second-phase processing are executed to generate a new output vector. On the other hand, when an end instruction is received (YES in S404), this process ends.

[0031] As described above, in the first embodiment, the generation of a vector having the phase difference between two vector data (the first input vector and the second input vector) as the deflection angle and the normalized intensity (N2) is realized by a small circuit-scale Vector-Rotation CORDIC configuration. In the first-phase processing and the second-phase processing, although it has been described that the first input vector and the second input vector are processed one by one, it is not limited to this. For example, in the first-phase processing, a plurality of different first input vectors may be processed to obtain a plurality of normalized first vectors, and in the second-phase processing, a plurality of output vectors may be obtained by using each of one second input vector and the plurality of normalized first vectors. Alternatively, in the first-phase processing, one first input vector may be processed to obtain a normalized first vector, and in the second-phase processing, a plurality of output vectors may be obtained by using each of a plurality of different second input vectors and the normalized first vector. Alternatively, in the first-phase processing, a plurality of different first input vectors may be processed to obtain a plurality of normalized first vectors, and in the second-phase processing, a plurality of output vectors may be obtained by using a pair having a specific relevance among the plurality of second input vectors and the plurality of normalized first vectors.

[0032] Also, in the above, in order to obtain the vector of the phase difference, the conjugate data of the normalized first vector was used as the rotation input orthogonal coordinate data 13 in the second phase process (step S402), but it is not limited to this. For example, the conjugation process can also be performed by rotating the normalized vector in the reverse direction in the first phase process (step S401). More specifically, in the first phase process, the above-mentioned conjugated normalized first vector can be obtained by inputting the rotation direction information 203 to the adder / subtractor 304 without inverting it (without passing through the inverter 306) in the coordinate rotation operation unit 302 that performs the rotation mode process. And in the second phase process, by inverting the rotation direction information 203 by the inverter 306 and inputting it to the adder / subtractor 304, an output vector having the phase difference as the deflection angle can be obtained.

[0033] Also, by using the normalized first vector as it is without conjugating it as described above, it is also possible to generate a vector obtained by adding phases instead of the phase difference. For example, as shown in FIG. 5(C), when the second input vector 511a with the deflection angle θ being θ 2 and the normalized first vector 503 (θ = θ 1 ) are input to the CORDIC processing unit 101, the normalized first vector 503 rotates further by θ 2 in the same direction. As a result, the deflection angle of the normalized second vector 512a (output vector) becomes θ 1 + θ 2 . Note that even in this case, the intensity is N2 as in the case of the phase difference.

[0034] <Second Embodiment> In the second embodiment, a process suitable for the case where there is a change only in one of the two input vectors, the first input vector and the second input vector, will be described. Here, the vector data with no change is used as the first input vector. The configuration of the coordinate rotation processing apparatus 100 is the same as that of the first embodiment (FIGS. 1 to 3).

[0035] The flowchart of the coordinate rotation process by the coordinate rotation processor 100 according to the second embodiment is shown in FIG. 4(B). The first phase process and the second phase process in the first time are the same as those in the first embodiment, and the control unit 104 executes the first phase process (S401) and the second phase process (S402). In this embodiment, it is assumed that only the second input vector changes. In S410, only the fact that the second input vector has been updated is set as a condition for executing a new process. Further, since there is no change in the first input vector, only the second phase process needs to be performed in this new process. Therefore, when the control unit 104 determines that the second input vector has been updated (YES in step S410), the control unit 104 omits the first phase process and executes the second phase process (S402). When an end instruction is received (YES in S404), this process ends.

[0036] As described above, in the second embodiment, the first phase process is executed in response to the input of the first input vector, and thereafter, the second phase process is executed using the result of the first phase process and the input second input vector to generate an output vector. According to the second embodiment, when only one of the two input vectors (the first input vector and the second input vector) changes, it is possible to provide a coordinate rotation processor in which the number of processing steps is approximately halved compared to the first embodiment.

[0037] <Third Embodiment> In the third embodiment, a phase-limited correlation arithmetic unit that uses the coordinate rotation processing device 100 described in the first or second embodiment will be described. Hereinafter, mainly, the configurations and processes added to the first and second embodiments will be described. FIG. 6 is a block diagram showing a configuration example of the phase-limited correlation arithmetic unit 600 according to the third embodiment. The phase-limited correlation arithmetic unit 600 can be realized, for example, by the data processing device 110 shown in FIG. 1(B). The coordinate rotation processing unit 610 has the same functional configuration as the coordinate rotation processing device 100 described in the first or second embodiment. The FFT processing unit 601, the coordinate rotation processing unit 610, the inverse FFT processing unit 602, and the peak determination unit 603 operate under the control of the control unit 620 to perform phase-limited correlation arithmetic processing. FIG. 7(A) is a flowchart showing the phase-limited correlation arithmetic processing by the phase-limited correlation arithmetic unit 600 of the third embodiment.

[0038] In S701, the FFT processing unit 601 performs a Fourier transform (FFT processing in this embodiment) on the first input signal to generate vector information of frequency components, that is, a plurality of vectors each consisting of the intensity and phase information of each frequency. These plurality of vectors are used as a plurality of first input vectors of the coordinate rotation processing unit 610. Note that FFT represents Fast Fourier Transformation. The plurality of generated first input vectors are input from the FFT processing unit 601 to the coordinate rotation processing unit 610. In S702, the coordinate rotation processing unit 610 inputs each of the plurality of first input vectors to the CORDIC processing unit 101 as vector input orthogonal coordinate data 10 and performs first phase processing. The plurality of normalized first vectors obtained by performing the first phase processing on each of the plurality of first input vectors are held in the data holding unit 103. The first phase processing for the first input vector is as described in the first embodiment.

[0039] Subsequently, in S703, the FFT processing unit 601 performs FFT processing on the second input signal to generate a plurality of vectors each consisting of the intensity and phase information of each frequency. These plurality of vectors are provided to the coordinate rotation processing unit 610 as second input vectors. In S704, the coordinate rotation processing unit 610 performs second phase processing using each of the plurality of normalized first vectors held in the data holding unit 103 and each of the plurality of second input vectors input in S703 to obtain a plurality of output vectors. The second phase processing is as described in the first embodiment, where the second input vector is input to the CORDIC processing unit 101 as vector input orthogonal coordinate data 10 and the normalized first vector is input as rotation input orthogonal coordinate data 13. However, the pair of the normalized first vector and the second input vector used for the second phase processing is a pair of vectors corresponding to the same frequency among the plurality of normalized first vectors and the plurality of second input vectors.

[0040] Next, in S705, the inverse FFT processing unit 602 generates a phase-limited correlation value by performing an inverse Fourier transform (in this embodiment, an inverse fast Fourier transform is used) on the output vector group obtained from the coordinate rotation processing unit 610 in S704. Then, in S706, the peak determination unit 603 obtains a correlation coordinate value from the intensity information of the phase-limited correlation value. This correlation coordinate value corresponds to, for example, the relative positional shift between two images and can be used for various image processes such as image matching and alignment. In S707, the control unit 620 determines whether the first input signal or the second input signal has been updated as a condition for executing the next new process. In this embodiment, when it is determined that the first input signal or the second input signal has been updated (YES in S707), the control unit 620 controls to execute the processes of S701 to S706 described above and obtains a correlation coordinate value for the new input signal. When an end instruction for the process is received (YES in S708), the process ends. Note that when it is assumed that only the second signal is updated without the first signal being updated, the control unit 620 may perform a phase-limited correlation operation process as shown in FIG. 7(B). That is, after performing the processes of S701 to S706, in S710, the control unit 620 determines whether the second input signal has been updated. When the control unit 620 determines that the second input signal has been updated (YES in S710), it executes S703 to S706 to obtain a correlation coordinate value for the new second input signal.

[0041] Note that the input signal of the phase-limited correlation operation device 600 may be a one-dimensional signal or a two-dimensional signal. Examples of the one-dimensional input signal include audio data, time-series measurement results of the object to be measured, or line information of a captured image. In that case, the FFT processing unit 601 and the inverse FFT processing unit 602 perform one-dimensional FFT processing. Also, in the peak determination unit 603, the peak position is determined by one-dimensional function fitting processing or the like. Examples of the two-dimensional input signal include captured image data. In the case of a two-dimensional input signal, two-dimensional FFT processing is also performed, and in the peak determination unit 603, the peak position is determined by two-dimensional fitting, for example, parabola fitting.

[0042] As described above, according to the third embodiment, it is possible to provide a phase-limited correlation arithmetic unit with a small circuit scale by means of a Vector-Rotation CORDIC configuration.

[0043] <Fourth Embodiment> In the fourth embodiment, a phase-limited correlation arithmetic unit having a configuration different from that of the third embodiment will be described. Note that the parts different from the third embodiment will be mainly described.

[0044] FIG. 8(A) is a block diagram showing a configuration example of a phase-limited correlation arithmetic unit 800 according to the fourth embodiment. The phase-limited correlation arithmetic unit 800 can be realized, for example, by the data processing device 110 shown in FIG. 1(B). Further, FIG. 8(B) is a block diagram showing a configuration example of a coordinate rotation processing unit 810 according to the fourth embodiment. Also, FIG. 9 is a flowchart showing a phase-limited correlation arithmetic process for a two-dimensional image according to the fourth embodiment. The phase-limited correlation arithmetic process is executed by the operation of each functional unit in FIGS. 8(A) and 8(B) under the control of the control unit 820. Hereinafter, the configuration and process of the phase-limited correlation arithmetic unit 800 will be described by taking as an example the process when a two-dimensional image is input as an input signal.

[0045] In S901 and S902, the FFT processing unit 802 performs FFT processing (horizontal) and FFT processing (vertical) on the first two-dimensional image. The data required for each processing step is stored in the phase-limited correlation data holding unit 804, and the memory reading unit 801 reads the input data required for each processing step from the phase-limited correlation data holding unit 804. In S901, the memory reading unit 801 reads the first two-dimensional image from the phase-limited correlation data holding unit 804 and provides it to the FFT processing unit 802 (phase-limited correlation data holding unit 804 → data 86 → memory reading unit 801 → data 81 → FFT processing unit 802). Also, the processing results of the FFT processing unit 802 (the processing results of S901 and S902) are stored in the phase-limited correlation data holding unit 804 from the memory writing unit 803 (FFT processing unit 802 → data 82 → memory writing unit 803 → data 87 → phase-limited correlation data holding unit 804). Note that the phase-limited correlation data holding unit 804 requires a large-capacity memory corresponding to the case where the two-dimensional image size is large. In such a case, an external storage device such as a DRAM may be used.

[0046] Next, in S903, the coordinate rotation processing unit 810 performs first-phase processing. A configuration example of the coordinate rotation processing unit 810 is shown in FIG. 8(B). The coordinate rotation processing unit 810 has substantially the same configuration as the coordinate rotation processing apparatus 100 described in the first embodiment, but since it has a phase-limited correlation data holding unit 804, the data holding unit 103 is omitted. Therefore, the input vector is acquired from the phase-limited correlation data holding unit 804, and the normalized first vector, which is the result of the first-phase processing, is held in the phase-limited correlation data holding unit 804. Input data required for the processing is read from the phase-limited correlation data holding unit 804 by the memory reading unit 801 and input to the coordinate rotation processing unit 810. In the first-phase processing, as described above in the third embodiment (S702 in FIG. 7), a normalized first vector is obtained for each of a plurality of first input vectors. The plurality of first input vectors obtained from the results of the FFT processing in S901 to S902 are held in the phase-limited correlation data holding unit 804. The memory reading unit 801 reads each of the plurality of first input vectors from the phase-limited correlation data holding unit 804 and provides it to the coordinate rotation processing unit 810 as vector input orthogonal coordinate data 10 (input vector). That is, the data is transferred as follows: phase-limited correlation data holding unit 804 → data 86 (first input vector) → memory reading unit 801 → vector input orthogonal coordinate data 10 → coordinate rotation processing unit 810. The plurality of normalized first vectors, which are the processing results of the first-phase processing by the coordinate rotation processing unit 810, are stored in the phase-limited correlation data holding unit 804 by the memory writing unit 803. That is, the data is transferred as follows: coordinate rotation processing unit 810 → rotation output orthogonal coordinate data 14 (normalized first vector) → memory writing unit 803 → data 87 → phase-limited correlation data holding unit 804.

[0047] In S904 to S905, the FFT processing unit 802 performs FFT processing (horizontal) and FFT processing (vertical) on a second two-dimensional image different from the first two-dimensional image, and obtains a plurality of second input vectors for input to the coordinate rotation processing unit 810. The obtained plurality of second input vectors are stored in the phase-limited correlation data holding unit 804 by the memory writing unit 803. The FFT processing in S904 to S905 is the same as the FFT processing in S901 to S902. In S906, the coordinate rotation processing unit 810 performs a second phase processing using the plurality of second input vectors and the plurality of normalized first vectors. That is, the memory reading unit 801 reads the second input vector from the phase-limited correlation data holding unit 804 and provides it to the coordinate rotation processing unit 810 (phase-limited correlation data holding unit 804 → data 86 → memory reading unit 801 → data 83 → coordinate rotation processing unit 810). Also, the memory reading unit 801 reads the normalized first vector from the phase-limited correlation data holding unit 804 and provides it to the coordinate rotation processing unit 810 (phase-limited correlation data holding unit 804 → data 86 → memory reading unit 801 → data 84 → coordinate rotation processing unit 810). As described in the third embodiment, in the second phase processing, among the plurality of second input vectors and the plurality of normalized first vectors, pairs of vectors corresponding to the same frequency are read from the phase-limited correlation data holding unit 804 and provided to the coordinate rotation processing unit 810. The rotation output orthogonal coordinate data 14 (output vector), which is the processing result of the second phase processing by the coordinate rotation processing unit 810, is stored from the memory writing unit 803 into the phase-limited correlation data holding unit 804. That is, the data is transferred as coordinate rotation processing unit 810 → rotation output orthogonal coordinate data 14 (output vector) → memory writing unit 803 → data 87 → phase-limited correlation data holding unit 804.

[0048] In S907 and S908, the FFT processing unit 802 performs an inverse FFT process on the output vector group obtained by the second phase process. The memory readout unit 801 provides the FFT processing unit 802 with a plurality of output vectors obtained by the second phase process from the phase-limited correlation data holding unit 804. That is, the data (output vector) is transferred as follows: phase-limited correlation data holding unit 804 → data 86 (output vector) → memory readout unit 801 → data 81 → FFT processing unit 802. The memory writing unit 803 stores the phase-limited correlation data, which is the result of the inverse FFT process by the FFT processing unit 802, in the phase-limited correlation data holding unit 804. That is, the data is transferred as follows: FFT processing unit 802 → data 82 (phase-limited correlation data) → memory writing unit 803 → data 87 → phase-limited correlation data holding unit 804.

[0049] Next, in S909, peak determination processing is performed on the phase-limited correlation data obtained in S908. Note that the peak determination processing is assumed to be performed by the upper control unit 820 in the fourth embodiment. In S910, the control unit 820 determines whether or not the update of the second two-dimensional image has been updated. In the fourth embodiment, as described with reference to FIG. 7(B) in the third embodiment, it is assumed that an update occurs only in the second two-dimensional image. When an update occurs in the second two-dimensional image (YES in S910), the process returns to S904, and the above-described process is repeated for the new second two-dimensional image. Also, when an end instruction is received (YES in S911), this process ends.

[0050] In this embodiment, the FFT processing unit 802 performs FFT processing and inverse FFT processing. It is assumed that which of the FFT processing and the inverse FFT processing the FFT processing unit 802 performs is instructed by the control unit 820. For example, the control unit 820 designates an address for reading the first two-dimensional image (or the second two-dimensional image) to the memory reading unit 801 and instructs the FFT processing unit 802 to perform FFT processing. Further, the control unit 820 designates an address for reading the output vector group from the coordinate rotation processing unit 810 to the memory reading unit 801 and instructs the FFT processing unit 802 to perform inverse FFT processing. Note that the switching between the FFT processing and the inverse FFT processing in the FFT processing unit 802 is not limited to the instruction from the control unit 820, and any method may be used as long as the FFT processing and the inverse FFT processing can be appropriately switched. For example, bits may be provided to distinguish whether each of the two-dimensional image and the output vector is an object of FFT processing or inverse FFT processing, and the FFT processing unit 802 may determine these bits and switch between the FFT processing and the inverse FFT processing.

[0051] As described above, in the fourth embodiment, the FFT circuits included in one FFT processing unit 802 are shared by the FFT processing and the inverse FFT processing. Therefore, the FFT processing and the inverse FFT processing can share many circuit configurations. Thus, the phase-limited correlation arithmetic unit 800 can be provided with a smaller circuit configuration compared to the configuration of the third embodiment (FIG. 7) having the FFT processing unit 601 and the inverse FFT processing unit 602 separately.

[0052] <Fifth Embodiment> In the fourth embodiment, all the processing results by the FFT processing unit 802 and the coordinate rotation processing unit 810 are temporarily held in the phase-limited correlation data holding unit 804. However, when the phase-limited correlation data holding unit 804 is configured by an external storage device such as a DRAM, it may take time to save and read data, so it may be desirable to minimize data access to the phase-limited correlation data holding unit 804. In the fifth embodiment, a configuration example for reducing data access to the phase-limited correlation data holding unit 804 with respect to the fourth embodiment will be described. FIG. 10 is a block diagram showing a configuration example of the phase-limited correlation arithmetic unit 800a according to the fifth embodiment. The phase-limited correlation arithmetic unit 800a can be realized, for example, by the data processing device 110 shown in FIG. 1(B). FIG. 11 is a flowchart showing the phase-limited correlation arithmetic processing for a two-dimensional image according to the fifth embodiment.

[0053] In the phase-limited correlation arithmetic unit 800a of the fifth embodiment, a data transfer path 88 from the memory write unit 803 to the memory read unit 801 is added to the configuration of the phase-limited correlation arithmetic unit 800 of the fourth embodiment (FIG. 8(A)). As described above, when the phase-limited correlation data holding unit 804 is configured by a DRAM, the data transfer time may be a problem. According to the fifth embodiment, this data transfer path 88 enables the phase-limited correlation arithmetic processing to be performed without passing through the phase-limited correlation data holding unit 804 that takes time for data transfer.

[0054] The individual processing steps of the fifth embodiment shown in FIG. 11 are the same as those of the fourth embodiment (FIG. 9), but in S1100, the FFT processing (vertical) in S905 and the second phase processing in S906 are batch-processed without passing through the phase-limited correlation data holding unit 804. In the FFT processing (vertical) in S905, vector information (intensity, phase) for each frequency is appropriately output as a processing result. This is the second input vector required for the second phase processing (S905). In S906, the memory readout unit 801 acquires the second input vector via the data transfer path 88, and reads out the normalized first vector corresponding to the frequency corresponding to this second input vector from the phase-limited correlation data holding unit 804. Then, the second phase processing (step S406) is executed by inputting the read normalized first vector and the second input vector supplied via the data transfer path 88 to the coordinate rotation processing unit 810.

[0055] As described above, in the fifth embodiment, it is possible to reduce the processes of writing and reading the second input vector to the phase-limited correlation data holding unit 804. As a result, it is possible to reduce the processing time of the phase-limited correlation operation or reduce the data bandwidth related to the phase-limited correlation data holding unit 804.

[0056] As a modification of the fifth embodiment, examples in which the steps to be processed collectively are different are shown in FIGS. 12(A) and 12(B). In FIG. 12(A), there is S1200 that collectively processes the second-phase processing (step S906) by the coordinate rotation processing unit 810 and the inverse FFT processing (vertical) (step S907) by the FFT processing unit 802. In S1200, when an output vector is obtained by the second-phase processing (S906), the memory readout unit 801 acquires the output vector via the data transfer path 88 and provides it to the FFT processing unit 802, and the FFT processing unit 802 executes the inverse FFT processing (S907). The contents of the second-phase processing and the inverse FFT processing are as described above. Further, in FIG. 12(B), there is a step S1210 that collectively processes the FFT processing (vertical) (step S905), the second-phase processing (step S906), and the inverse FFT processing (vertical) (step S907). S1210 is a process that combines the collective processes of S1100 and S1200. However, in this case, the FFT processing (vertical) in S905 and the inverse FFT processing (vertical) in S907 are executed simultaneously. Therefore, it is necessary to have two FFT processing units 802 or to perform time-division processing of the FFT processing (vertical) (step S905) and the inverse FFT processing (vertical) (step S907) in the FFT processing unit 802. On the other hand, the amount of access to the phase-limited correlation data holding unit 804 can be reduced the most.

[0057] <Sixth Embodiment> In the sixth embodiment, a configuration for reducing the data held in the data holding unit 103 in the coordinate rotation processing apparatus will be described. FIG. 13 is a block diagram showing a configuration example of the coordinate rotation processing apparatus 100a according to the sixth embodiment. The coordinate rotation processing apparatus 100a can be realized, for example, by the data processing apparatus 110 shown in FIG. 1(B). Further, in the coordinate rotation processing apparatus 100a, a vector compression unit 1301 and a vector generation unit 1302 are added to the configuration of the coordinate rotation processing apparatus 100 of the first embodiment (FIG. 1(A)).

[0058] The vector compression unit 1301 reduces the data amount of the normalized first vector generated by the first phase processing (S401) (data on either the X-axis or Y-axis in the orthogonal coordinate system, or in the case of complex number representation, data on either the real part or the imaginary part). In this embodiment, the X-axis data is used. More specifically, among the normalized first vectors, only the quadrant data (2 bits), which is the sign of the X-axis data and the Y-axis data, and the X-axis data (unsigned) are supplied to the data holding unit 103 as the compressed data 15. Among the Y-axis data, data other than the sign data is discarded. Also, in the second phase processing (S402), the compressed data 15 stored in the data holding unit 103 is read out as the data 16, and the data selection unit 102 selects this and inputs it as the selected compressed data 17 to the vector generation unit 1302.

[0059] The vector generation unit 1302 generates the Y-axis data from the X-axis data of the selected compressed data 17, assigns the quadrant data (2 bits), restores the normalized first vector, and inputs it as the rotation input orthogonal coordinate data 13 to the CORDIC processing unit 101. The method for generating the Y-axis data (method for restoring the vector) in the vector generation unit 1302 is as follows. The normalized first vector is normalized with the intensity N1 as described above. That is, as shown in FIG. 14(A), the normalized first vector is a vector indicating somewhere on the circular orbit with the length N1 as the radius in the orthogonal coordinate system. Therefore, it is possible to generate the Y-axis data (= √(N1 2 - [X-axis data] 2 )). Specific methods for generating the Y-axis data include operations using the theoretical function or approximation function of the circular orbit, or data generation using a look-up table and interpolation processing.

[0060] As described above, in the sixth embodiment, by using only the X-axis data or the Y-axis data as the normalized first vector, the amount of data held in the data holding unit 103 and the amount of transferred data can be reduced. Further, the memory size used for the data holding unit 103 can be reduced. Also, it is obvious that the configuration of the sixth embodiment can be applied to the phase-limited correlation operation devices of the third to fifth embodiments. In that case, the amount of data held in the phase-limited correlation data holding unit 804 and the amount of transferred data can be reduced.

[0061] <Seventh Embodiment> The seventh embodiment is another embodiment similar to the sixth embodiment and relates to a method for improving the accuracy of the deflection angle during compression. The parts changed from the sixth embodiment will be mainly described.

[0062] In the sixth embodiment, only the data of either the X-axis or the Y-axis is used as the compressed data, whereas in the seventh embodiment, the smaller of the X-axis and the Y-axis is used as the compressed data. Specifically, the vector compression unit 1301 supplies the following three pieces of data as the compressed data 15 to the data holding unit 103 among the normalized first vectors. · Quadrant data (2 bits) representing the signs of the X-axis data and the Y-axis data. · Minimum data (unsigned) which is the smaller of the X-axis data and the Y-axis data. · Flag data (1 bit) which is a flag indicating whether it is X-axis data or Y-axis data.

[0063] In the second phase processing (S402), the data selection unit 102 reads out the compressed data 15 stored in the data holding unit 103 as data 16, selects it as the selected compressed data 17, and inputs it to the vector generation unit 1302. In the vector generation unit 1302, the maximum data, which is the data of the other axis, is generated from the intensity N1 of the normalized first vector and the minimum data, which is the data of one axis. Next, based on the flag data, the minimum data and the maximum data are assigned to the X-axis data and the Y-axis data, or the maximum data and the minimum data. Then, quadrant data (2 bits) is further added thereto and input to the CORDIC processing unit 101 as the rotation input orthogonal coordinate data 13.

[0064] The method for generating the Y-axis data by the vector generation unit 1302 is as follows. The normalized first vector is normalized with the intensity N1 as described above. That is, the normalized first vector is a vector indicating somewhere on a circular orbit with a radius of length N1 in the orthogonal coordinate system as shown in FIG. 14(A). Therefore, the Y-axis data can be generated from the X-axis. However, in the region where the vector has a small deflection angle, that is, in the region close to the X-axis, the change in the Y-axis data is large with respect to the change in the X-axis data. Therefore, when the Y-axis data is generated from the X-axis, the reproduction accuracy of the deflection angle of the generated vector deteriorates, or the bit width of the X-axis data must be increased to improve the accuracy.

[0065] Therefore, in the seventh embodiment, as shown in FIG. 14(B), when the X-axis data is small (x ≦ y), that is, when the deflection angle is 45° to 90°, the X-axis data is retained, and the Y-axis data is generated from this X-axis data. In the range of 45° to 90° of the deflection angle, the change in the Y-axis data is small with respect to the change in the X-axis data. In other words, the X-axis data is more dominant with respect to the generated vector. Therefore, since the vector generation unit 1302 generates the Y-axis data using the dominant X-axis data, the reproduction accuracy of the generated vector is improved. On the other hand, as shown in FIG. 14(C), when the Y-axis data is small (x > y), that is, when the deflection angle is 0° to 45°, the Y-axis data is retained, and the X-axis data is generated from the retained Y-axis data. In the range of 0° to 45°, the change in the X-axis data is small with respect to the change in the Y-axis data. In other words, the Y-axis data is more dominant with respect to the generated vector. Since the vector generation unit 1302 generates the X-axis data using the dominant Y-axis data, the reproduction accuracy of the generated vector is improved.

[0066] As described above, in the seventh embodiment, by setting the data held in the data holding unit 103 to only the smaller one of the X-axis data and the Y-axis data and the approximate flag data, the amount of data to be held, that is, the transfer data amount and the memory size can be reduced. Furthermore, the accuracy of the rotation input orthogonal coordinate data 13 to be generated can be improved.

[0067] <Eighth Embodiment> In the eighth embodiment, the input data to the CORDIC processing unit 101 in the coordinate rotation processing device is reduced. FIG. 15 is a block diagram showing a configuration example of the coordinate rotation processing device 100b according to the eighth embodiment. The coordinate rotation processing device 100b can be realized, for example, by the data processing device 110 shown in FIG. 1(B). An exponent part sharing unit 1501 is added to the configuration of the first embodiment (FIG. 1). Also, it is assumed that the vector data (first input vector, second input vector) input to the coordinate rotation processing device 100b is floating-point input orthogonal coordinate data 18 in floating-point format. For example, as described in the third embodiment, when FFT processing is performed before the coordinate rotation processing device 100b, the operation may be performed in floating-point type in order to perform FFT processing with high precision. However, when floating-point type data is input and processed as it is, the processing in the CORDIC processing unit 101 will also be performed in floating-point type, resulting in an increase in circuit scale. In the case of double-precision floating-point numbers, it is 64 bits, and in the case of single-precision floating-point numbers, it is 32 bits, and the data volume also increases. Therefore, the eighth embodiment has an exponent part sharing unit 1501 that converts floating-point input orthogonal coordinate data into exponent part shared floating-point input orthogonal coordinate data.

[0068] The outline of the processing of the exponent part sharing unit 1501 is shown in FIG. 16. FIG. 16(A) illustrates the case where the floating-point input orthogonal coordinate data (real part data, imaginary part data) is in single-precision floating-point format. That is, it is 1 bit for the sign, 23 bits for the mantissa part, and 8 bits for the exponent part. Also, in the example of the floating-point data shown in the figure, the exponent part of the real part is 10 (multiplied by 2 to the 10th power), and the exponent part of the imaginary part is 4 (multiplied by 2 to the 4th power), and the real part is larger.

[0069] In the exponent part sharing unit 1501, digit adjustment is performed by shifting the data of the mantissa part (bit shift) according to the larger exponent part. For example, in the case of FIG. 16(B), by shifting the data of the imaginary part 6 bits to the right, the exponent parts of the data of the real part and the imaginary part are made the same (2 10) can align the digits. Further, as shown in FIG. 16(C), the exponent common part 1501 outputs, as input orthogonal coordinate data (output data) represented by a floating decimal number with a common exponent, data of a predetermined number of digits obtained by performing rounding processing at a predetermined digit position. At this time, the exponent data is excluded and not used in the subsequent processing. The reason why such processing is effective is that the information necessary as the information of the vector pipeline of the CORDIC processing unit 101 is the information of the deflection angle, that is, the information of the ratio of the real part and the imaginary part, and the vector intensity information is unnecessary.

[0070] As described above, in the eighth embodiment, the input data of the CORDIC processing unit 101 can be reduced. Specifically, in the example shown in this embodiment, a total of 64-bit data of 32-bit floating decimal type data for each of the real part and the imaginary part can be converted and compressed into a total of 32-bit data of 16-bit integer type data for each of the real part and the imaginary part.

[0071] Note that the processing of the exponent common part 1501 may be arranged outside the coordinate rotation processing device 100b. In particular, when the input data of the coordinate rotation processing device 100b is once stored in a memory or the like, the data amount can be reduced by the processing of the exponent common part 1501 before being stored in the memory, and the memory capacity and the data transfer amount can be reduced.

[0072] <Other Embodiments> The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. Further, it can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

[0073] The foregoing embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be construed in a limited manner by these. That is, the present invention can be implemented in various forms without departing from its technical idea or its main features. Each embodiment may be implemented in combination with each other.

[0074] The disclosure of this specification includes the following coordinate rotation processing device, phase-limited correlation operation device, and their methods and programs. (Item 1) A CORDIC processing unit that outputs a vector having an angle obtained by rotating one of the two vectors by the declination angle of the other vector and a magnitude obtained by multiplying the magnitude of the one vector by a scaling factor in response to the input of two vectors; First phase processing means for generating a normalized first vector having an angle of the first input vector and a magnitude obtained by multiplying the magnitude of the normalized vector by the scaling factor from the first input vector and a normalized vector whose orthogonal coordinates are represented by (N, 0) using the CORDIC processing unit; Second phase processing means for generating an output vector having an angle obtained by rotating the normalized first vector by the declination angle of the second input vector and a magnitude obtained by multiplying the magnitude of the normalized first vector by the scaling factor from the second input vector and the normalized first vector using the CORDIC processing unit. A coordinate rotation processing device characterized by comprising: (Item 2) The scaling factor is a coefficient that depends on the number of rotations of the CORDIC processing unit, and when the number of rotations is i, it is represented by (1 + 2 - 2i)1 / 2. The coordinate rotation processing device according to Item 1, characterized in that: (Item 3) The first phase processing means inputs the first input vector and the normalization vector to the CORDIC processing unit to obtain the normalized first vector rotated in the direction of the argument angle of the first input vector. The second phase processing means inputs the second input vector and the conjugate vector of the normalized first vector to the CORDIC processing unit, thereby obtaining the output vector having the difference between the argument angles of the first input vector and the second input vector as the argument angle. The coordinate rotation processing apparatus according to item 1 or 2, characterized in that. (Item 4) The first phase processing means inputs the first input vector and the normalization vector to the CORDIC processing unit to obtain the normalized first vector rotated in the direction opposite to the argument angle of the first input vector. The second phase processing means inputs the second input vector and the normalized first vector to the CORDIC processing unit to obtain the output vector rotated in the same direction as the argument angle of the second input vector, thereby obtaining the output vector having the difference between the argument angles of the first input vector and the second input vector as the argument angle. The coordinate rotation processing apparatus according to item 1 or 2, characterized in that. (Item 5) The coordinate rotation processing apparatus according to any one of items 1 to 4, further comprising control means for controlling each of the first phase processing means and the second phase processing means to execute processing to generate the output vector in response to an update of the first input vector or the second input vector. (Item 6) The coordinate rotation processing apparatus according to any one of items 1 to 4, further comprising control means for controlling the first phase processing means to execute processing in response to an input of the first input vector, and after the first phase processing means executes the processing, the second phase processing means executes processing in response to an input or an update of the second input vector to generate the output vector. (Item 7) Compression means for generating and holding in a holding unit compression data representing the normalized first vector from the orthogonal coordinate data representing the normalized first vector, using the data of one axis out of the data of two axes and not using the data of the other axis; Vector generation means for restoring the normalized first vector by generating the data of the other axis of the orthogonal coordinate data based on the data of the one axis of the compression data held in the holding unit and providing the restored normalized first vector to the second phase processing means, the coordinate rotation processing apparatus according to any one of Items 1 to 6, further comprising the vector generation means. (Item 8) The coordinate rotation processing apparatus according to Item 7, wherein the axis of the data with the smaller value out of the data of the two axes of the orthogonal coordinate data is used as the data of the one axis. (Item 9) The coordinate rotation processing apparatus according to Item 7 or 8, wherein the vector generation means uses a function of a circular orbit having the intensity of the normalized first vector as a radius, or an approximation function of the circular orbit, or a look-up table, to generate the data of the other axis from the data of the one axis. (Item 10) The coordinate rotation processing apparatus according to any one of Items 1 to 9, further comprising normalization means for providing orthogonal coordinate data with a shared exponent part to the CORDIC processing unit by sharing the exponent parts of the first data and the second data, each represented by a floating decimal, of the orthogonal coordinate data representing a vector. (Item 11) The normalization means matches the value of the exponent part of the one data with the smaller value of the exponent parts of the first data and the second data to the value of the exponent part of the other data with the larger value of the exponent parts, and generates the data of the mantissa part of the one data by bit-shifting the data of the mantissa part of the one data by an amount corresponding to matching the value of the exponent part of the one data to the value of the exponent part of the other data, the coordinate rotation processing apparatus according to Item 10. (Item 12) The commonization means is the coordinate rotation processing device according to item 11, which is characterized by rounding the data of the fractional part of the first data and the data of the fractional part of the second data at a predetermined digit position. (Item 13) The commonization means is the coordinate rotation processing device according to item 11 or 12, which is characterized by excluding the value of the exponent part from the orthogonal coordinate data whose exponent part is commonized and providing it to the CORDIC processing unit. (Item 14) Conversion means for performing a Fourier transform on the input signal and obtaining a vector representing the intensity and phase for each frequency of the converted data; The coordinate rotation processing device according to any one of items 1 to 13, where the coordinate rotation processing device uses the vector obtained by the conversion means from the first signal as the first input vector and the vector obtained by the conversion means from the second signal as the second input vector to obtain the output vector. Inverse conversion means for performing an inverse Fourier transform on the output vector to generate phase-limited correlation data; A phase-limited correlation operation device, comprising generation means for generating correlation coordinate values of the first signal and the second signal based on the phase-limited correlation data. (Item 15) The first signal and the second signal are one-dimensional data, and the conversion means and the inverse conversion means respectively perform one-dimensional fast Fourier transform (FFT processing) and one-dimensional inverse fast Fourier transform (inverse FFT processing). This is the phase-limited correlation operation device according to item 14. (Item 16) The first signal and the second signal are two-dimensional data, and the conversion means and the inverse conversion means respectively perform two-dimensional FFT processing and inverse FFT processing. This is the phase-limited correlation operation device according to item 14. (Item 17) The conversion means executes FFT processing using an FFT circuit. The inverse conversion means executes inverse FFT processing using the FFT circuit. This is the phase-limited correlation operation device according to any one of items 14 to 16. (Item 18) The phase-limited correlation arithmetic unit according to any one of Items 14 to 17, further comprising holding means for temporarily holding the first input vector and the second input vector obtained from the conversion means to provide them to the coordinate rotation processing device, and for temporarily holding the output vector obtained from the coordinate rotation processing device to provide it to the inverse conversion means. (Item 19) Holding means for temporarily holding the first input vector obtained from the conversion means to provide it to the coordinate rotation processing device, and for temporarily holding the output vector obtained from the coordinate rotation processing device to provide it to the inverse conversion means; The phase-limited correlation arithmetic unit according to any one of Items 14 to 17, comprising a data transfer path for providing the second input vector obtained from the conversion means to the coordinate rotation processing device without holding it in the holding means. (Item 20) Holding means for temporarily holding the first input vector and the second input vector obtained from the conversion means to provide them to the coordinate rotation processing device; The phase-limited correlation arithmetic unit according to any one of Items 14 to 17, comprising a data transfer path for providing the output vector obtained from the coordinate rotation processing device to the inverse conversion means without holding it in the holding means. (Item 21) Holding means for temporarily holding the first input vector obtained from the conversion means to provide it to the coordinate rotation processing device; The phase-limited correlation arithmetic unit according to any one of Items 14 to 17, comprising a data transfer path for providing the second input vector obtained from the conversion means to the coordinate rotation processing device without holding it in the holding means, and for providing the output vector obtained from the coordinate rotation processing device to the inverse conversion means without holding it in the holding means. (Item 22) A CORDIC processing step that outputs a vector having an angle obtained by rotating one of the two vectors by the deflection angle of the other vector in response to the input of the two vectors, and a magnitude obtained by multiplying the magnitude of the one vector by a scaling factor; First phase processing means for generating a normalized first vector having an angle of the first input vector and a magnitude obtained by multiplying the magnitude of the normalized vector by the scaling factor from the first input vector and the normalized vector whose orthogonal coordinates are represented by (N, 0) by the CORDIC processing step; A coordinate rotation processing method comprising: a second phase processing step of generating an output vector having an angle obtained by rotating the normalized first vector by the deflection angle of the second input vector and a magnitude obtained by multiplying the magnitude of the normalized first vector by the scaling factor from the second input vector and the normalized first vector by the CORDIC processing step. (Item 23) A conversion step of performing a Fourier transform on an input signal and obtaining a vector representing the intensity and phase for each frequency of the converted data; An acquisition step of acquiring the output vector by using, as the first input vector, the vector obtained by the conversion step from the first signal and, as the second input vector, the vector obtained by the conversion step from the second signal by the coordinate rotation processing method described in Item 22; An inverse conversion step of performing an inverse Fourier transform on the output vector to generate phase-limited correlation data; A phase-limited correlation calculation method comprising: a generation step of generating a correlation coordinate value between the first signal and the second signal based on the phase-limited correlation data. (Item 24) A program for causing a computer to function as each means of the coordinate rotation processing apparatus according to any one of claims 1 to 13 or the phase-limited correlation calculation apparatus according to any one of claims 14 to 21.

[0075] The invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the claims are appended to disclose the scope of the invention.

Explanation of Signs

[0076] 100, 100a, 100b: Coordinate rotation processing device, 102: Data selection unit, 103: Data holding unit, 600, 800, 800a: Phase-limited correlation operation device, 601: FFT processing unit, 602: Inverse FFT processing unit, 610, 810: Coordinate rotation processing unit

Claims

1. A CORDIC processing unit that outputs a vector having an angle obtained by rotating one of the two vectors by an angle of deviation of the other vector and a magnitude obtained by multiplying the magnitude of the one vector by a scaling factor in response to an input of two vectors; First phase processing means for generating a normalized first vector having an angle of deviation of the first input vector and a magnitude obtained by multiplying the magnitude of the normalized vector by the scaling factor from the first input vector and a normalized vector whose orthogonal coordinates are represented by (N, 0) using the CORDIC processing unit; Second phase processing means for generating an output vector having an angle obtained by rotating the normalized first vector by an angle of deviation of the second input vector and a magnitude obtained by multiplying the magnitude of the normalized first vector by the scaling factor from the second input vector and the normalized first vector using the CORDIC processing unit, wherein the coordinate rotation processing apparatus is characterized by comprising the second phase processing means.

2. The scaling factor is a coefficient that depends on the number of rotations of the CORDIC processing unit. When the number of rotations is i, it is represented by (1 + 2 －２ｉ ). The coordinate rotation processing device according to claim 1, characterized in that.

3. The first phase processing means inputs the first input vector and the normalized vector to the CORDIC processing unit to obtain the normalized first vector rotated in the direction of the angle of deviation of the first input vector, and the second phase processing means inputs the second input vector and the conjugate vector of the normalized first vector to the CORDIC processing unit, thereby obtaining the output vector having the difference between the angles of deviation of the first input vector and the second input vector as the angle of deviation. The coordinate rotation processing apparatus according to claim 1, characterized in that.

4. The first phase processing means inputs the first input vector and the normalized vector to the CORDIC processing unit to obtain the normalized first vector rotated in the direction opposite to the angle of deviation of the first input vector, and the second phase processing means inputs the second input vector and the normalized first vector to the CORDIC processing unit to obtain the output vector rotated in the same direction as the angle of deviation of the second input vector, thereby obtaining the output vector having the difference between the angles of deviation of the first input vector and the second input vector as the angle of deviation. The coordinate rotation processing apparatus according to claim 1, characterized in that.

5. The coordinate rotation processing device according to claim 1, further comprising control means for controlling each of the first phase processing means and the second phase processing means to execute processing so as to generate the output vector in accordance with an update of the first input vector or the second input vector.

6. The coordinate rotation processing device according to claim 1, further comprising control means for controlling the first phase processing means to execute processing in response to an input of the first input vector, and after the first phase processing means has executed the processing, controlling the second phase processing means to execute processing in response to an input of the second input vector or an update of the second input vector so as to generate the output vector.

7. Compression means for generating compression data representing the normalized first vector from the orthogonal coordinate data representing the normalized first vector, using data of one of the two axes and not using data of the other axis, and holding the compression data in a holding unit; Vector generation means for restoring the normalized first vector by generating data of the other axis of the orthogonal coordinate data based on data of the one axis of the compression data held in the holding unit and providing the restored normalized first vector to the second phase processing means, the coordinate rotation processing device according to claim 1 being further characterized by comprising the vector generation means.

8. The coordinate rotation processing device according to claim 7, wherein the axis of the data having a smaller value among the data of the two axes of the orthogonal coordinate data is used as the data of the one axis.

9. The coordinate rotation processing device according to claim 7, wherein the vector generation means uses a function of a circular orbit having the intensity of the normalized first vector as the radius, an approximation function of the circular orbit, or a look-up table to generate the data of the other axis from the data of the one axis.

10. The coordinate rotation processing device according to claim 1, further comprising normalization means for normalizing the orthogonal coordinate data representing the vector by sharing the exponent parts of the first data and the second data, each represented by a floating point number, and providing the orthogonal coordinate data with the shared exponent part to the CORDIC processing unit.

11. The normalization means matches the value of the exponent part of the one data having a smaller exponent part value among the first data and the second data with the value of the exponent part of the other data having a larger exponent part value; The coordinate rotation processing apparatus according to claim 10, characterized in that data of the fractional part of the one data is generated by bit-shifting the data of the fractional part of the one data by an amount corresponding to the value of the exponent part of the one data adjusted to the value of the exponent part of the other data.

12. The coordinate rotation processing apparatus according to claim 11, characterized in that the commoning means rounds each of the data of the fractional part of the first data and the data of the fractional part of the second data at a predetermined digit position.

13. The coordinate rotation processing apparatus according to claim 11, characterized in that the commoning means excludes the value of the exponent part from the orthogonal coordinate data in which the exponent part is commoned and provides it to the CORDIC processing unit.

14. Conversion means for performing a Fourier transform on an input signal and obtaining a vector representing the intensity and phase for each frequency of the converted data; The coordinate rotation processing apparatus according to claim 1, wherein the coordinate rotation processing apparatus uses the vector obtained by the conversion means from the first signal as the first input vector and the vector obtained by the conversion means from the second signal as the second input vector to obtain the output vector. Inverse conversion means for performing an inverse Fourier transform on the output vector to generate phase-limited correlation data; A phase-limited correlation arithmetic device comprising generation means for generating correlation coordinate values of the first signal and the second signal based on the phase-limited correlation data.

15. The phase-limited correlation arithmetic device according to claim 14, characterized in that the first signal and the second signal are one-dimensional data, and the conversion means and the inverse conversion means respectively perform one-dimensional fast Fourier transform (FFT processing) and one-dimensional inverse fast Fourier transform (inverse FFT processing).

16. The phase-limited correlation arithmetic device according to claim 14, characterized in that the first signal and the second signal are two-dimensional data, and the conversion means and the inverse conversion means respectively perform two-dimensional FFT processing and inverse FFT processing.

17. The conversion means executes FFT processing using an FFT circuit, The inverse conversion means executes inverse FFT processing using the FFT circuit, The phase-limited correlation arithmetic device according to claim 14, characterized in that.

18. A holding means for temporarily holding the first input vector and the second input vector obtained from the conversion means to provide them to the coordinate rotation processing device, and for temporarily holding the output vector obtained from the coordinate rotation processing device to provide it to the inverse conversion means, the phase-limited correlation arithmetic device according to claim 14, characterized in that it further comprises this.

19. A holding means for temporarily holding the first input vector obtained from the conversion means to provide it to the coordinate rotation processing device, and for temporarily holding the output vector obtained from the coordinate rotation processing device to provide it to the inverse conversion means; A data transfer path for providing the second input vector obtained from the conversion means to the coordinate rotation processing device without holding it in the holding means, the phase-limited correlation arithmetic device according to claim 14, characterized in that it comprises this.

20. A holding means for temporarily holding the first input vector and the second input vector obtained from the conversion means to provide them to the coordinate rotation processing device; A data transfer path for providing the output vector obtained from the coordinate rotation processing device to the inverse conversion means without holding it in the holding means, the phase-limited correlation arithmetic device according to claim 14, characterized in that it comprises this.

21. A holding means for temporarily holding the first input vector obtained from the conversion means to provide it to the coordinate rotation processing device; A data transfer path for providing the second input vector obtained from the conversion means to the coordinate rotation processing device without holding it in the holding means, and for providing the output vector obtained from the coordinate rotation processing device to the inverse conversion means without holding it in the holding means, the phase-limited correlation arithmetic device according to claim 14, characterized in that it comprises this.

22. A CORDIC processing step for outputting a vector having an angle obtained by rotating one of the two vectors by the declination angle of the other vector and a magnitude obtained by multiplying the magnitude of the one vector by a scaling factor in response to the input of the two vectors; A first phase processing means for generating a normalized first vector having an angle of the first input vector and a magnitude obtained by multiplying the magnitude of the normalized vector by the scaling factor from the first input vector and the normalized vector whose orthogonal coordinates are represented by (N, 0) by the CORDIC processing step; A coordinate rotation processing method, comprising: a second phase processing step of generating, by the CORDIC processing step, an output vector having an angle obtained by rotating the normalized first vector by an angle of deviation of the second input vector from the second input vector and a magnitude obtained by multiplying the magnitude of the normalized first vector by the scaling coefficient.

23. A conversion step of performing a Fourier transform on an input signal and obtaining a vector representing the intensity and phase for each frequency of the converted data. An acquisition step of acquiring the output vector by using, as the first input vector, the vector obtained by the conversion step from the first signal and, as the second input vector, the vector obtained by the conversion step from the second signal, by the coordinate rotation processing method according to claim 22. An inverse conversion step of performing an inverse Fourier transform on the output vector to generate phase-limited correlation data. A generation step of generating correlation coordinate values of the first signal and the second signal based on the phase-limited correlation data. A phase-limited correlation calculation method characterized by comprising:

24. A program for causing a computer to function as each means of the coordinate rotation processing device according to any one of claims 1 to 13 or the phase-limited correlation calculation device according to any one of claims 14 to 21.

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