Display device

Abstract

To provide a display device with high reliability by achieving high mobility in an oxide semiconductor.SOLUTION: A first oxide member is formed on a base material member. First heat treatment is performed to grow crystal from a surface toward an inside to form a first oxide crystal member at least partially in contact with the base material member. A second oxide member is formed on the first oxide crystal member. Second heat treatment is performed to grow crystal using the first oxide crystal member as a seed. A high mobility transistor is formed using a laminated oxide material in which a second oxide crystal member is provided. A driver circuit is formed on the same substrate using the transistor.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a display device using an oxide semiconductor, a method for manufacturing the same, and an electronic device including the display device.

Background Art

[0002] Transistors formed on a glass substrate or the like, such as a liquid crystal display device, are composed of amorphous silicon, polycrystalline silicon, or the like. Although transistors using amorphous silicon have a low field-effect mobility, they can correspond to the enlargement of the glass substrate area. Also, transistors using polycrystalline silicon have a high field-effect mobility but have the drawback of not being suitable for the enlargement of the glass substrate area.

[0003] Regarding transistors using silicon, techniques for manufacturing transistors using an oxide semiconductor and applying them to electronic devices and optical devices have been attracting attention. For example, as an oxide semiconductor, zinc oxide, In-Ga-Zn-O-based oxide is used to manufacture transistors, and techniques for using them in switching elements of pixels of a display device are disclosed in Patent Document 1 and Patent Document 2.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] A transistor that forms a channel region in an oxide semiconductor has a higher field-effect mobility than a transistor using amorphous silicon. The field-effect mobility of an amorphous silicon transistor is usually about 0.5 cm / Vs, whereas the field-effect mobility of a transistor using an oxide semiconductor is 10 to 20 cm obtained. Also, an oxide semiconductor can form an active layer by a sputtering method or the like, and can be easily manufactured without using a laser device like a transistor using polycrystalline silicon. 2 / Vs. Also, an oxide semiconductor can form an active layer by a sputtering method or the like, and can be easily manufactured without using a laser device like a transistor using polycrystalline silicon. / Vs is obtained. Also, an oxide semiconductor can form an active layer by a sputtering method or the like, and can be easily manufactured without using a laser device like a transistor using polycrystalline silicon. 2 / Vs is obtained. Also, an oxide semiconductor can form an active layer by a sputtering method or the like, and can be easily manufactured without using a laser device like a transistor using polycrystalline silicon. An oxide semiconductor can form an active layer by a sputtering method or the like, and can be easily manufactured without using a laser device like a transistor using polycrystalline silicon. An oxide semiconductor can form an active layer by a sputtering method or the like, and can be easily manufactured without using a laser device like a transistor using polycrystalline silicon.

[0006] Forming a transistor on a glass substrate or a plastic substrate using such an oxide semiconductor is expected to be applied to a liquid crystal display device, an organic EL display device, an electronic paper, etc. Forming a transistor on a glass substrate or a plastic substrate using such an oxide semiconductor is expected to be applied to a liquid crystal display device, an organic EL display device, an electronic paper, etc. .

[0007] On the other hand, large display devices are becoming popular. Even in home TVs, TVs with a diagonal of 40 inches to 50 inches are beginning to spread, and it is thought that the spread will accelerate further in the future. A transistor using an oxide semiconductor can obtain a field-effect mobility more than 10 times that of a transistor of amorphous silicon as described above, so that sufficient performance can be obtained as a pixel switching element even in a large display device. On the other hand, large display devices are becoming popular. Even in home TVs, TVs with a diagonal of 40 inches to 50 inches are beginning to spread, and it is thought that the spread will accelerate further in the future. A transistor using an oxide semiconductor can obtain a field-effect mobility more than 10 times that of a transistor of amorphous silicon as described above, so that sufficient performance can be obtained as a pixel switching element even in a large display device. On the other hand, large display devices are becoming popular. Even in home TVs, TVs with a diagonal of 40 inches to 50 inches are beginning to spread, and it is thought that the spread will accelerate further in the future. A transistor using an oxide semiconductor can obtain a field-effect mobility more than 10 times that of a transistor of amorphous silicon as described above, so that sufficient performance can be obtained as a pixel switching element even in a large display device. On the other hand, large display devices are becoming popular. Even in home TVs, TVs with a diagonal of 40 inches to 50 inches are beginning to spread, and it is thought that the spread will accelerate further in the future. A transistor using an oxide semiconductor can obtain a field-effect mobility more than 10 times that of a transistor of amorphous silicon as described above, so that sufficient performance can be obtained as a pixel switching element even in a large display device. On the other hand, large display devices are becoming popular. Even in home TVs, TVs with a diagonal of 40 inches to 50 inches are beginning to spread, and it is thought that the spread will accelerate further in the future. A transistor using an oxide semiconductor can obtain a field-effect mobility more than 10 times that of a transistor of amorphous silicon as described above, so that sufficient performance can be obtained as a pixel switching element even in a large display device.

[0008] However, when trying to configure not only the pixel but also the driver circuit with transistors using an oxide semiconductor, the performance of conventional oxide semiconductor transistors was insufficient. Specifically, in order to increase the current capacity of the transistor, it is necessary to further increase the field-effect mobility of the conventional oxide semiconductor several times. The field-effect mobility is 10 cm However, when trying to configure not only the pixel but also the driver circuit with transistors using an oxide semiconductor, the performance of conventional oxide semiconductor transistors was insufficient. Specifically, in order to increase the current capacity of the transistor, it is necessary to further increase the field-effect mobility of the conventional oxide semiconductor several times. The field-effect mobility is 10 cm However, when trying to configure not only the pixel but also the driver circuit with transistors using an oxide semiconductor, the performance of conventional oxide semiconductor transistors was insufficient. Specifically, in order to increase the current capacity of the transistor, it is necessary to further increase the field-effect mobility of the conventional oxide semiconductor several times. The field-effect mobility is 10 cm However, when trying to configure not only the pixel but also the driver circuit with transistors using an oxide semiconductor, the performance of conventional oxide semiconductor transistors was insufficient. Specifically, in order to increase the current capacity of the transistor, it is necessary to further increase the field-effect mobility of the conventional oxide semiconductor several times. The field-effect mobility is 10 cm 2Acid of / Vs When a driver is configured using a transistor using a compound semiconductor, the size of the display device is less than 20 inches. To configure a display device larger than that, it was necessary to separately mount a driver.

Means for Solving the Problem

[0009] One aspect of the present invention disclosed in this specification is an active matrix type display device having a plurality of pixels, a plurality of signal lines, and a plurality of scanning lines on an insulating substrate, wherein a field effect mobility of at least 50 cm / Vs or more, preferably 100 cm / Vs or more, and having a transistor of an oxide semiconductor, and a gate driver having the transistor as one component, 2 / Vs or more, preferably 100 cm 2 / Vs or more, and having a transistor of an oxide semiconductor, and a gate driver having the transistor as one component, / Vs or more, and having a transistor of an oxide semiconductor, and a gate driver having the transistor as one component, a display device having a source line driving analog switch.

[0010] In the above display device, its size is at least 20 inches or more.

[0011] One aspect of the present invention disclosed in this specification is an active matrix type display device having a plurality of pixels, a plurality of signal lines, and a plurality of scanning lines on an insulating substrate, wherein a field effect mobility of at least 50 cm / Vs or more, preferably 100 cm / Vs or more, and having a transistor of an oxide semiconductor, and a gate driver having the transistor as one component, 2 / Vs or more, preferably 100 cm 2 / Vs or more, and having a transistor of an oxide semiconductor, and a gate driver having the transistor as one component, / Vs or more, and having a transistor of an oxide semiconductor, and a gate driver having the transistor as one component, a display device having a source driver.

[0012] In the above display device, its size is at least 20 inches or more.

[0013] One of the means for improving the field effect mobility described above is to form an oxide member on a base member​ Performing a heat treatment to cause crystal growth from the surface toward the interior and contacting at least a part of the underlying member to form a first oxide crystal member, and a method for producing a laminated oxide material in which a second oxide crystal member is laminated and provided on the first oxide crystal member. In particular, the first oxide crystal member and the second oxide crystal member share a common c-axis. Note that the first oxide crystal member has a c-axis orientation in a direction perpendicular to the surface of the first oxide crystal member. Note that a plurality of elements on adjacent planes in the a-b plane are the same. Also, the c-axis direction of the first oxide crystal member is uniform in the depth direction. In the above production method, the crystal-oriented lower surface of the first oxide crystal member is provided in contact with at least a part or all of the underlying member. By appropriately adjusting the film thickness of the oxide member, the conditions of the heat treatment, etc., the crystal-oriented lower surface of the first oxide crystal member is provided in contact with at least a part or all of the underlying member. Also, in the above production method, annealing is performed after forming the oxide member, a second oxide semiconductor layer is formed on the upper surface thereof, and then crystal growth is caused toward the surface of the second oxide semiconductor layer above the interface between the first oxide crystal part and the second oxide semiconductor layer. The first oxide crystal member corresponds to a seed crystal for the second oxide semiconductor layer. It is important that a polycrystalline layer is formed as the second oxide crystal member on the upper side thereof. The higher the crystallinity of the oxide semiconductor layer, the higher the field-effect mobility transistor can be realized.

[0014]

[0015]

[0016]

[0017] ​​​​​​​​​​​​Moreover, the higher the crystallinity of the oxide semiconductor layer, the more the change in the threshold voltage of the transistor before and after the BT test can be suppressed, and high reliability can be achieved. Also, the higher the crystallinity of the oxide semiconductor layer, the more the change in the temperature dependence of the electrical characteristics of the transistor,

[0018] for example, the change in the on-current and off-current from -30°C to 120°C can be suppressed.

[0019] In addition, in the above configuration, one of the features of the oxide crystal member having a c-axis orientation in contact with the base member is that it is a polycrystalline member.

[0020] The technical idea of the present invention is to purify the oxide semiconductor itself by intentionally removing the impurities of water and hydrogen that are inadvertently present, without adding anything further to the oxide semiconductor. That is, by removing water or hydrogen that constitutes the donor level, further reducing oxygen vacancies, and sufficiently supplying oxygen, which is the main component material of the oxide semiconductor, the oxide semiconductor is purified.

[0021] When the oxide semiconductor is formed into a film, hydrogen at a level of 10 20 cm -3 is measured by SIMS (secondary ion mass spectrometry). By intentionally removing the water or hydrogen that causes this donor level, and further adding oxygen (one of the components of the oxide semiconductor) that decreases simultaneously with the removal of water or hydrogen, the oxide semiconductor is purified and made into an electrically i-type (intrinsic) semiconductor.

[0022] In addition, in the technical idea of the present invention, the less the amount of water and hydrogen in the oxide semiconductor, the better. ​​​​​The smaller the better, and the fewer carriers, the better. That is, the carrier density is 1×1 0 12 cm -3 less than, more preferably less than the measurement limit of 1.45×10 10 cm -3 less than is required. Furthermore, in terms of the technical idea of the present invention, being close to zero or zero is ideal. In particular, the oxide semiconductor is placed in an atmosphere of oxygen, nitrogen, or ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), and heat-treated at 450°C or higher and 8 50°C or lower, preferably 550°C or higher and 750°C or lower, to remove water or hydrogen that becomes an n-type impurity and achieve high purity. Also, by removing impurities such as water or hydrogen, the oxide semiconductor can be highly purified, and the carrier density can be 1×10 less than, more preferably less than the measurement limit of 1.45×10 1×10 12 cm -3 less than, more preferably less than the measurement limit of 1.45×10 10 cm - 3 less than.

[0023] Furthermore, when the heat treatment is at 450°C or higher and 850°C or lower, preferably 600°C or higher and 700°C or lower at a high temperature it is possible to highly purify the oxide semiconductor and crystallize it. The oxide semiconductor grows crystals from the surface to the inside, and becomes an oxide semiconductor having a polycrystalline region with c-axis orientation. semiconductor having a polycrystalline region with c-axis orientation as a seed crystal, and a second oxide semiconductor is provided thereon, and heat-treated at 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower, so that the second oxide semiconductor becomes a seed crystal

[0024] The oxide semiconductor used in the present invention is an oxide semiconductor having a polycrystalline region with c-axis orientation as a seed crystal, a second oxide semiconductor is provided thereon, and heat-treated at 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower, so that the second oxide semiconductor becomes a seed crystal It can be a polycrystalline region having a c-axis orientation similar to that of a single crystal. That is, ideal axial growth or epitaxial growth can be achieved in which the c-axis of the seed crystal and the second oxide semiconductor are coaxial.

[0025] Also, the second oxide semiconductor that is coaxial with the seed crystal is not only solid-phase growth by heat treatment after film formation, but the second oxide semiconductor is formed while heating at 200°C or higher and 600°C or lower, typically by sputtering, and crystal growth can be achieved while depositing. Further, when the substrate is heated to 200°C or higher and 600°C or lower during film formation of the oxide semiconductor film by sputtering, direct epitaxial growth or axial growth can be achieved.

[0026] Furthermore, by reducing and preferably eliminating the carriers of the oxide semiconductor, the oxide semiconductor functions as a path for carriers to pass through in the transistor. As a result, the oxide semiconductor is a highly purified i-type (intrinsic) semiconductor, and by making the carriers absent or extremely small, the off-current can be made extremely low in the off state of the transistor. This is the technical idea of the oxide semiconductor used in the present invention.

[0027] Also, when the oxide semiconductor functions as a path and is made into a highly purified i-type (intrinsic) semiconductor having no or extremely few carriers in the oxide semiconductor itself, the carriers are supplied by the source and drain of the electrodes. By appropriately selecting the electron affinity χ and Fermi level of the oxide semiconductor, ideally the Fermi level that coincides with the intrinsic Fermi level, and the work functions of the source and drain electrodes, carriers can be injected from the source electrode and the drain electrode. ​​​​​​​​​be enabled, and n-type and p-type transistors can be fabricated as appropriate .

[0028] All of the above oxide crystal members and oxide members are metal oxides, specifically quaternary metal oxides such as In-Sn-Ga-Zn-O films, or ternary metal oxides such as In-Ga-Zn-O films, I n-Sn-Zn-O films, In-Al-Zn-O films, Sn-Ga-Zn-O films, Al-Ga -Zn-O films, Sn-Al-Zn-O systems, or binary metal oxides such as In-Zn-O films, Sn-Zn-O films, Al-Zn-O films, Zn-Mg-O films, Sn-Mg-O films, In-M g-O films, In-O films, Sn-O films, Zn-O films, etc. can be used. Here, for example, an In-Sn-Ga-Zn-O film means an oxide film containing indium (In) , tin (Sn), gallium (Ga), and zinc (Zn), and its stoichiometric ratio is not particularly limited .

[0029] In addition, for the above oxide crystal members and oxide members, thin films represented by InMO 3 (ZnO) m (where m > 0 and m is not a natural number) can be used. Here, M represents one or more metal elements selected from Ga, Al , Mn, and Co. For example, as M, there are Ga, Ga and Al, Ga and Mn, or Ga and Co, etc

[0030] Alternatively, an oxide semiconductor material represented by In-A-B-O can also be used. Here, A is one or more elements selected from Group 13 elements such as gallium (Ga) and aluminum (Al), and Group 14 elements represented by silicon (Si) and germani um (Ge), etc ​Yes. Also, B represents one or more types of elements selected from Group 12 elements typified by zinc (Zn). Note that the contents of In, A, and B are arbitrary, including the case where the content of A is zero. On the other hand, the contents of In and B are not zero. That is, the above notations include In-Ga- Zn-O, In-Zn-O, and the like. Also, the oxide semiconductor material denoted as In-Ga-Zn- O in this specification is InGaO 3 (ZnO) m (m > 0, and m is not a natural number), and the fact that m is not a natural number can be confirmed using ICP-MS analysis or RBS analysis.

[0031] Also, as one of the processes for purification, a first heat treatment is performed in an atmosphere containing almost no hydrogen and moisture (nitrogen atmosphere, oxygen atmosphere, dry air atmosphere (for example, for moisture, dew point -40 °C or lower, preferably dew point -50 °C or lower), etc.). This first heat treatment can also be called dehydration or dehydrogenation to desorb H, OH, etc. from the oxide semiconductor layer, and is a heat treatment that raises the temperature in an inert atmosphere and then switches to an atmosphere containing oxygen in the middle, or can be called an oxidation treatment when performing a heat treatment in an oxygen atmosphere.

[0032] The first heat treatment can use a heating method using an electric furnace, a GRTA (Gas Rapid Thermal Anneal) method using a heated gas, or an instant heating method such as an LRTA (Lamp Rapid Thermal Anneal) method using lamp light. Also, the first heat treatment may be simultaneously performed with heating by irradiating light of 450 nm or less. The oxide semiconductor layer that has undergone the first heat treatment for purification is the first heat treatment For the processed oxide semiconductor layer, heating is performed under conditions such that even when measurement is carried out up to 450 °C by TDS (Thermal Desorption Spectroscopy), at least one of the two peaks of water is not detected, specifically, the peak that appears around 300 °C is not detected. Therefore, for a transistor using an oxide semiconductor layer that has undergone heat treatment for purification, even when measurement is carried out up to 450 °C by TDS, the peak of water that appears around at least 300 °C is not detected. For the processed oxide semiconductor layer, heating is performed under conditions such that even when measurement is carried out up to 450 °C by TDS (Thermal Desorption Spectroscopy), at least one of the two peaks of water is not detected, specifically, the peak that appears around 300 °C is not detected. Therefore, for a transistor using an oxide semiconductor layer that has undergone heat treatment for purification, even when measurement is carried out up to 450 °C by TDS, the peak of water that appears around at least 300 °C is not detected. For the processed oxide semiconductor layer, heating is performed under conditions such that even when measurement is carried out up to 450 °C by TDS (Thermal Desorption Spectroscopy), at least one of the two peaks of water is not detected, specifically, the peak that appears around 300 °C is not detected. Therefore, for a transistor using an oxide semiconductor layer that has undergone heat treatment for purification, even when measurement is carried out up to 450 °C by TDS, the peak of water that appears around at least 300 °C is not detected.

[0033] The first heat treatment is preferably performed by heating at a high temperature for a short time so that crystal growth occurs only on the surface because there is no polycrystalline layer that serves as a seed for crystal growth. Also, since a good plate-like polycrystalline layer can be obtained when the surface of the oxide semiconductor layer is flat, it is desirable that the flatness of the underlying member, for example, the insulating layer or the substrate, is as high as possible. By increasing the flatness, it becomes easier to form a polycrystalline layer that contacts the entire surface of the underlying member, which is useful. For example, the flatness is preferably the same as that of a commercially available silicon wafer, for example, the height difference in AFM measurement in a region with a surface roughness of 1 μm square is 1 nm or less, preferably 0.2 nm. The first heat treatment is preferably performed by heating at a high temperature for a short time so that crystal growth occurs only on the surface because there is no polycrystalline layer that serves as a seed for crystal growth. Also, since a good plate-like polycrystalline layer can be obtained when the surface of the oxide semiconductor layer is flat, it is desirable that the flatness of the underlying member, for example, the insulating layer or the substrate, is as high as possible. By increasing the flatness, it becomes easier to form a polycrystalline layer that contacts the entire surface of the underlying member, which is useful. For example, the flatness is preferably the same as that of a commercially available silicon wafer, for example, the height difference in AFM measurement in a region with a surface roughness of 1 μm square is 1 nm or less, preferably 0.2 nm.

[0034] The polycrystalline layer increases the electrical conductivity σ by the overlapping and connection of the electron clouds of In in the oxide semiconductor. Therefore, a transistor having a polycrystalline layer can achieve a high field-effect mobility. The polycrystalline layer increases the electrical conductivity σ by the overlapping and connection of the electron clouds of In in the oxide semiconductor. Therefore, a transistor having a polycrystalline layer can achieve a high field-effect mobility.

[0035] One method of further performing crystal growth using the flat plate-like polycrystalline layer formed by the first heat treatment as a seed is shown below with reference to FIGS. 1(A), 1(B), and 1(C). One method of further performing crystal growth using the flat plate-like polycrystalline layer formed by the first heat treatment as a seed is shown below with reference to FIGS. 1(A), 1(B), and 1(C).

[0036] ​​​​To briefly explain the process sequence, after forming the first oxide semiconductor layer on the base member, a first heat treatment for purification is performed. By the same process as the first heat treatment for purification, a polycrystalline layer with aligned crystal orientations is formed on the surface of the first oxide semiconductor layer, and a second oxide semiconductor layer is laminated thereon. Further, by performing a second heat treatment for crystallization, the second oxide semiconductor layer is crystallized using the polycrystalline layer on the surface of the first oxide semiconductor layer as a seed, and the process is carried out in this order. By the same process as the first heat treatment for purification, a polycrystalline layer with aligned crystal orientations is formed on the surface of the first oxide semiconductor layer. By the same process as the first heat treatment for purification, a polycrystalline layer with aligned crystal orientations is formed on the surface of the first oxide semiconductor layer, and a second oxide semiconductor layer is laminated thereon. Further, by performing a second heat treatment for crystallization, the second oxide semiconductor layer is crystallized using the polycrystalline layer on the surface of the first oxide semiconductor layer as a seed. Further, by performing a second heat treatment for crystallization, the second oxide semiconductor layer is crystallized using the polycrystalline layer on the surface of the first oxide semiconductor layer as a seed, and the process is carried out in this order. Further, by performing a second heat treatment for crystallization, the second oxide semiconductor layer is crystallized using the polycrystalline layer on the surface of the first oxide semiconductor layer as a seed, and the process is carried out in this order.

[0037] In the first heat treatment, crystal growth occurs from the surface in a state where there is no crystal layer serving as a seed for crystal growth. In contrast, in the second heat treatment, since there is a flat polycrystalline layer serving as a seed, good crystallinity can be obtained by heating at the lowest temperature at which crystal growth is possible for a long time, which is preferable. The crystal direction in the second heat treatment is from bottom to top, from the substrate side to the surface side (also called the recrystallization direction), and is different from the crystal direction in the first heat treatment. Also, since the polycrystalline layer obtained in the first heat treatment is reheated in the second heat treatment, the crystallinity is further improved. In contrast, in the second heat treatment, since there is a flat polycrystalline layer serving as a seed, good crystallinity can be obtained by heating at the lowest temperature at which crystal growth is possible for a long time, which is preferable. The crystal direction in the second heat treatment is from bottom to top, from the substrate side to the surface side (also called the recrystallization direction), and is different from the crystal direction in the first heat treatment. The crystal direction in the second heat treatment is from bottom to top, from the substrate side to the surface side (also called the recrystallization direction), and is different from the crystal direction in the first heat treatment. Also, since the polycrystalline layer obtained in the first heat treatment is reheated in the second heat treatment, the crystallinity is further improved. Also, since the polycrystalline layer obtained in the first heat treatment is reheated in the second heat treatment, the crystallinity is further improved. Also, since the polycrystalline layer obtained in the first heat treatment is reheated in the second heat treatment, the crystallinity is further improved.

[0038] Figure 1(A) shows the state after the first heat treatment for crystallization is performed on the first oxide semiconductor layer formed on the base member 500. The first heat treatment is a heat treatment in an atmosphere of oxygen, nitrogen, or ultra-dry air at 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. Also, a heat treatment may be performed by raising the temperature in an inert atmosphere and switching to an atmosphere containing oxygen midway, or a heat treatment may be performed in an oxygen atmosphere. After the first heat treatment, the first oxide semiconductor layer is c-axis oriented perpendicular to the surface. Figure 1(A) shows the state after the first heat treatment for crystallization is performed on the first oxide semiconductor layer formed on the base member 500. The first heat treatment is a heat treatment in an atmosphere of oxygen, nitrogen, or ultra-dry air at 450°C or higher and 850°C or lower. Figure 1(A) shows the state after the first heat treatment for crystallization is performed on the first oxide semiconductor layer formed on the base member 500. The first heat treatment is a heat treatment in an atmosphere of oxygen, nitrogen, or ultra-dry air at 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. Figure 1(A) shows the state after the first heat treatment for crystallization is performed on the first oxide semiconductor layer formed on the base member 500. The first heat treatment is a heat treatment in an atmosphere of oxygen, nitrogen, or ultra-dry air at 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. Also, a heat treatment may be performed by raising the temperature in an inert atmosphere and switching to an atmosphere containing oxygen midway, or a heat treatment may be performed in an oxygen atmosphere. Figure 1(A) shows the state after the first heat treatment for crystallization is performed on the first oxide semiconductor layer formed on the base member 500. The first heat treatment is a heat treatment in an atmosphere of oxygen, nitrogen, or ultra-dry air at 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. Also, a heat treatment may be performed by raising the temperature in an inert atmosphere and switching to an atmosphere containing oxygen midway, or a heat treatment may be performed in an oxygen atmosphere. Figure 1(A) shows the state after the first heat treatment for crystallization is performed on the first oxide semiconductor layer formed on the base member 500. The first heat treatment is a heat treatment in an atmosphere of oxygen, nitrogen, or ultra-dry air at 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. Also, a heat treatment may be performed by raising the temperature in an inert atmosphere and switching to an atmosphere containing oxygen midway, or a heat treatment may be performed in an oxygen atmosphere. After the first heat treatment, the first oxide semiconductor layer is c-axis oriented perpendicular to the surface. It becomes the first oxide crystal member 501 which is a flat polycrystal.

[0039] Further, FIG. 1(B) is a cross-sectional view immediately after the formation of the second oxide semiconductor layer 502. The second oxide semiconductor layer 502 is formed by a sputtering method, and its metal oxide target is In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:2 [mole ratio] metal oxide target, or In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:4 [mole ratio] metal oxide target can be used. That's fine.

[0040] Further, FIG. 1(C) is a cross-sectional view after the second heat treatment. By the second heat treatment, crystal growth occurs upward toward the surface of the second oxide semiconductor layer 502 using the polycrystalline layer of the first oxide crystal member 501 as a seed, and the second oxide crystal member 503b is formed, and the crystal members have a c-axis orientation. orientation.

[0041] This second heat treatment can also be called dehydration or dehydrogenation that desorbs H, OH, etc. from the oxide semiconductor layer. When performing a heat treatment that raises the temperature in an inert atmosphere and then switches to an atmosphere containing oxygen midway, or when performing a heat treatment in an oxygen atmosphere, it can also be called an oxidation treatment. midway, or when performing a heat treatment in an oxygen atmosphere, it can also be called an oxidation treatment. be called.

[0042] Further, since the polycrystalline layer obtained by the first heat treatment is heated again by the second heat treatment, it becomes the third oxide crystal member 503a with further improved crystallinity.

[0043] The hydrogen concentration of the oxide semiconductor layer is 1×10 18 cm -3 or less, 1×1016 cm -3 Hereinafter, more preferably substantially 0. Also, the carrier density of the oxide semiconductor layer is 1×10 12 cm -3 less than, more preferably less than the measurement limit of 1.45×10 10 cm -3 is less than . That is, the carrier density of the oxide semiconductor layer is close to zero. Also, the band gap is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. Note that the measurement of the hydrogen concentration in the oxide semiconductor layer can be performed by secondary ion mass spectrometry (SIMS). The carrier density can be measured by Hall effect measurement. Also, for the measurement of a lower carrier density, it can be obtained from the measurement results of CV measurement (Capacitance-Voltage-Measurement) and Equation 1.

[0044]

Equation

[0045] Also, in FIG. 1(C), it can be said that a two-layer structure is formed in which a third oxide crystal member 503a and a second oxide crystal member 503b are laminated in this order in contact with the base member 500. The materials of the first oxide crystal member 501 and the second oxide crystal member 503b are not particularly limited as long as polycrystals with a c-axis orientation perpendicular to the surface can be obtained, and different materials or materials containing the same components may be used. Containing the same components means having the same elements.

[0046] .

[0046] When using an oxide semiconductor material containing the same components, as shown by the dotted line in FIG. 1(C), The boundary between the third oxide crystal member 503a and the second oxide crystal member 503b becomes unclear and forms a single-layer structure.

[0047] Thus, the polycrystalline layer composed of the stacked third oxide crystal member 503a and second oxide crystal member 503b can be crystallized in two heat treatment steps.

[0048] In FIG. 1(A), the plate-like crystal layer with relatively aligned crystal orientations on the surface of the first oxide semiconductor layer can be formed without being affected by the underlying member because it grows in the depth direction from the surface.

[0049] An example of the mechanism by which a crystal layer with relatively aligned crystal orientations is formed on the surface of the first oxide semiconductor layer, for example, an In-Ga-Zn-O film, will be described. Due to the heat treatment, zinc contained in the In-Ga-Zn -O film diffuses and accumulates near the surface, serving as seeds for crystal growth. The crystal growth is stronger in the lateral direction (parallel to the surface) than in the depth direction (perpendicular to the surface), resulting in the formation of a flat polycrystalline layer. That is, the a-b plane direction crystallizes more easily than the c axis direction. Also, the a-b planes of the respective crystals do not coincide. Moreover, above the surface of the In-Ga-Zn-O film is free space, and there is no crystal growth upward here. These facts are inferred from the fact that when measuring up to 450°C during TDS measurement, In and Ga are not detected, but zinc is detected as a peak especially around 300°C under vacuum heating conditions. Note that the TDS measurement is performed in a vacuum, and it has been confirmed that the desorption of zinc is detected from around 200°C.

[0050] ​​​​The oxide semiconductor film is formed in two steps. After forming a polycrystalline layer that serves as a seed for crystal growth, it is possible to form a thick plate-like crystal layer by performing crystal growth after film formation again. That is to say, the method disclosed in this specification is extremely useful.

[0051] Also, regardless of the material of the base member, it is useful to obtain a crystal layer having an a-b plane parallel to the surface and a c-axis orientation in the direction perpendicular to the surface. That is to say, the method disclosed in this specification is extremely useful.

[0052] In addition, devices using metal oxides, typically In-Ga-Zn-O films, are completely different from devices using single-crystalline Si devices, devices using SiC, and devices using GaN. That is to say, the method disclosed in this specification is extremely useful.

[0053] Wide-gap semiconductors such as SiC (3.26 eV) and GaN (3.39 eV) are known. However, SiC and GaN are expensive materials. Also, SiC and GaN require a processing temperature of 1500 °C or higher, and it is substantially impossible to form a thin film on a glass substrate. That is to say, the method disclosed in this specification is extremely useful.

[0054] In addition, SiC and GaN are only single crystals, and control in a pn junction is required, and a more perfect single crystal is required. Therefore, due to the incorporation of a small amount of impurities unintended in the manufacturing process, it becomes a donor or an acceptor, and there is a limit to the lower limit of the carrier concentration. On the other hand, metal oxides can utilize all crystal structures of amorphous, polycrystalline, or single crystal. Without using the control of the pn junction, φ against χ +1 / 2E g against χ MS +1 / 2Eg OS +1 / 2E g OS against χ MD +1 / 2Eg OS +1 / 2Eg OSand, using the work functions of the source and drain and the physical properties of the electron affinity and energy band width of the metal oxide, band control equivalent to a PN junction is performed, which is one of the characteristics of metal oxides.

[0055] The band gap of metal oxides, typically the In-Ga-Zn-O film, is also about three times wider than that of single-crystalline silicon, and the manufacturing cost can be lower than that of SiC, so it is an inexpensive material.

[0056] The band gap of In-Ga-Zn-O is 3.05 eV, and based on this value, the intrinsic carrier density is calculated. The energy distribution f(E) of electrons in a solid is known to follow the Fermi-Dirac statistics shown by the following equation.

[0057]

Equation

[0058] In an ordinary semiconductor where the carrier density is not extremely high (not degenerate), the following relational expression holds.

[0059]

Equation

[0060] Therefore, the Fermi-Dirac distribution in Equation (1) is approximated by the Boltzmann distribution equation shown by the following equation.

[0061]

Equation

[0062] Using Equation (3) to calculate the intrinsic carrier density (n i ) of the semiconductor, the following equation is obtained.

[0063] ​​​​ [Number]

[0064] Then, the effective density of states (Nc, Nv) of Si and In-Ga-Zn-O and the value of the band gap (Eg) were substituted into Equation (4) to calculate the intrinsic carrier density. The results are shown in Table 1. .

[0065] [Table 1]

[0066] It can be seen that In-Ga-Zn-O has an extremely low intrinsic carrier density compared to Si. When 3.05 eV is selected as the bandgap of IGZO, for Si and In-Ga-Zn- O, assuming that the Fermi-Dirac distribution law is approximately correct for the intrinsic carrier concentration, the former can be said to have a carrier density about 10 17 times larger than the latter.

[0067] Also, thin films of oxide semiconductors can be formed by sputtering at heating temperatures from room temperature to 400 °C, and the maximum process temperature can be set between 300 °C and 800 °C. When the maximum process temperature is set below the strain point of the glass, it is also possible to form on a large-area glass substrate. Therefore, for industrialization, it is important to be able to fabricate metal oxides with a wide bandgap at a maximum process temperature between 300 °C and 800 °C.

[0068] The metal oxides reported so far have only been amorphous, polycrystalline, or those that obtain single crystals by treatment at a high temperature of about 1500 °C. However, As shown in the record, after forming a plate-like polycrystal of a metal oxide, a thin-film polycrystal having a c-axis orientation at a relatively low temperature is formed by a method of crystal growth using the plate-like polycrystal of the metal oxide as a seed, and further, when a thick-film polycrystal is formed, wider industrial applications can be opened. In addition, in order to obtain a high-quality thick-film polycrystal, it is preferable that the flatness and smoothness of the substrate are high. This is because even slight unevenness of the substrate becomes local deviation of the c-axis, and as crystal growth progresses, it becomes a defect such as crystal transition due to the direction of the c-axis of adjacent crystals being different. and a thick-film polycrystal can be formed, wider industrial applications can be opened. In addition, in order to obtain a high-quality thick-film polycrystal, it is preferable that the flatness and smoothness of the substrate are high. This is because even slight unevenness of the substrate becomes local deviation of the c-axis, and as crystal growth progresses, it becomes a defect such as crystal transition due to the direction of the c-axis of adjacent crystals being different. and a thick-film polycrystal can be formed, wider industrial applications can be opened. In addition, in order to obtain a high-quality thick-film polycrystal, it is preferable that the flatness and smoothness of the substrate are high. This is because even slight unevenness of the substrate becomes local deviation of the c-axis, and as crystal growth progresses, it becomes a defect such as crystal transition due to the direction of the c-axis of adjacent crystals being different. and a thick-film polycrystal can be formed, wider industrial applications can be opened. In addition, in order to obtain a high-quality thick-film polycrystal, it is preferable that the flatness and smoothness of the substrate are high. This is because even slight unevenness of the substrate becomes local deviation of the c-axis, and as crystal growth progresses, it becomes a defect such as crystal transition due to the direction of the c-axis of adjacent crystals being different. and a thick-film polycrystal can be formed, wider industrial applications can be opened. In addition, in order to obtain a high-quality thick-film polycrystal, it is preferable that the flatness and smoothness of the substrate are high. This is because even slight unevenness of the substrate becomes local deviation of the c-axis, and as crystal growth progresses, it becomes a defect such as crystal transition due to the direction of the c-axis of adjacent crystals being different. and a thick-film polycrystal can be formed, wider industrial applications can be opened. In addition, in order to obtain a high-quality thick-film polycrystal, it is preferable that the flatness and smoothness of the substrate are high. This is because even slight unevenness of the substrate becomes local deviation of the c-axis, and as crystal growth progresses, it becomes a defect such as crystal transition due to the direction of the c-axis of adjacent crystals being different.

Advantages of the Invention

[0069] A transistor using an oxide semiconductor layer having a plate-like crystal layer can realize a transistor having a high field-effect mobility. In addition, a transistor having a low off-current can be realized. In addition, a so-called normally-off switching element can be realized, and a semiconductor device with low power consumption can be provided. A transistor using an oxide semiconductor layer having a plate-like crystal layer can realize a transistor having a high field-effect mobility. In addition, a transistor having a low off-current can be realized. In addition, a so-called normally-off switching element can be realized, and a semiconductor device with low power consumption can be provided. A transistor using an oxide semiconductor layer having a plate-like crystal layer can realize a transistor having a high field-effect mobility. In addition, a transistor having a low off-current can be realized. In addition, a so-called normally-off switching element can be realized, and a semiconductor device with low power consumption can be provided. A transistor using an oxide semiconductor layer having a plate-like crystal layer can realize a transistor having a high field-effect mobility. In addition, a transistor having a low off-current can be realized. In addition, a so-called normally-off switching element can be realized, and a semiconductor device with low power consumption can be provided.

Brief Description of the Drawings

[0070]

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[0071] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it can be easily understood by those skilled in the art that its form and details can be variously changed. Also, the present invention is not construed as being limited to the description content of the embodiments shown below.

[0072] (Embodiment 1) Embodiments of the present invention are shown in FIG. 4. FIG. 4(A) shows a pixel portion 1502 on a glass substrate 1501 , which incorporates gate drivers 1503 and 1504 and analog switches 150 5 for source line driving. The use of analog switches 1505 for source line driving is due to the following reasons. For example, in the case of a full high-definition display device, there are 5760 source signal lines of 1920xR GB. When the source driver is not formed on the same substrate, the terminals of the source driver are connected to these terminals respectively. Therefore, there is a problem that poor contact of the terminals is likely to occur due to mechanical shock or the like. Reducing the number of terminals is effective in reducing poor contact. Therefore, an analog switch array is formed on the same substrate, and each terminal of RGB is selectively connected to the source driver in a time-division manner for the purpose of reducing the number of terminals.

[0073] FIG. 4(B) shows an equivalent circuit of the analog switch 1505. In the example shown in FIG. 4(B), the number of terminals connected to the outside of the display device is 1920, which are the output terminals of the source driver, and 3 terminals for controlling the gates of the switch array, for a total of 1923 terminals, which can be reduced to about one-third. These are connected to FPCs 1506, 1507, 1508, and 1509. On the other hand, the source driver connected to the analog switch needs to operate at three times the speed compared to the case where time-division is performed, and the writing time to the source signal line needs to be reduced to one-third. In order to reduce the writing time to the source signal line, it is important to improve the current capacity of the transistors used in the analog switch.

[0074] FIG. 5(A) shows the timing when time-division is performed. If time-division is not performed ​​​​​​​​​​If the writing of the source line only needs to be performed during one line period, time division is performed. In such a case, the writing must be performed in a time of 1 / 3 or less of one line period. In recent years, in display devices, driving methods such as double speed and quadruple speed have become widespread in order to improve the characteristics of moving images. This is because although TV broadcasts are at normal speed, images are created between frames inside the TV to improve the fineness of the images. Therefore, the display device must operate at double speed or quadruple speed. Fig. 5(B) shows the respective times at normal speed, double speed, and quadruple speed.

[0075] For this reason, the display device must operate at double speed or quadruple speed. Fig. 5(B) shows the respective times at normal speed, double speed, and quadruple speed. In Fig. 5(A), the pulse width a of the gate clock corresponds to one horizontal line period, and the writing of the source line must be completed within this period. The value of a is 15.3 μs at normal speed (frame frequency 60 Hz), 7.63 μs at double speed (frame frequency 120 Hz), and 3.81 μs at quadruple speed (frame frequency 240 Hz) as shown in Fig. 5(B). The display device must complete the writing to the source line within this writing time.

[0076] By improving the mobility of transistors using oxide semiconductors, it becomes possible to satisfy these requirements. Such display devices are applicable to display devices configured using transistors such as liquid crystal display devices, organic EL display devices, and electronic paper.

[0077] (Embodiment 2) Fig. 6 shows an embodiment of a display device incorporating a source driver. Fig. 6(A) shows an example in which a pixel portion 1702, gate drivers 1703 and 1704, and a source driver 1705 are incorporated on a glass substrate 1701. The gate drivers 1703 and 1704 and the source driver 1 Signals are supplied to 705 from FPCs 1706 and 1707. Gate drivers 1703, 1704 are arranged on both the left and right sides of the display device. By driving the pixels, it is possible to drive with half the driving ability in the case of one side.

[0078] Also, FIG. 6(B) shows an example in which on a glass substrate 1711, a pixel portion 1712, gate drivers 1713 , 1714, 1715, 1716 are arranged above and below the display device, and source drivers 1717, 171 8, 1719, 1720 are arranged on the left and right. Signals are supplied to the gate drivers and source drivers from FPCs 1721, 1722, 1723, 1724. By arranging in this way, each driver only needs to have a driving ability to drive 1 / 4 of the display device, and display becomes possible. If the display device is a full vision specification, the driver can be driven if it has the ability of Q HD (quarter high vision). Therefore, according to the present invention, the field effect mobility of the transistor using the oxide semiconductor is improved. If it is 50 cm / Vs or more, preferably 100 cm / Vs, it becomes possible to drive a full high vision display device of about 100 inches at double speed. 2 / Vs or more, preferably 100 cm 2 / Vs, a full high vision display device of about 100 inches can be driven at double speed.

[0079] (Embodiment 3) The calculation results when an analog switch is used for source line driving are shown below. The calculation assumes a 100-inch liquid crystal display device and a frame frequency of 240 Hz (4 times speed). As described above, at 4 times speed, it is necessary to perform the writing of the source line in 0.7 μs or less. The transistor element size used for the sampling analog switch at this time is L / W = 3 μm / 1500 μm, and the field effect mobility is 100 cm / Vs.​​​​​2 / Vs and threshold value 1. It was set to 5V. Then, the sheet resistance of the source signal line was 0.01 Ω / □, and the source line resistance was 2. 08 KΩ, the source line capacitance was 18.5 pF, and the line width was 6 μm. And it is targeted that writing can be performed up to 99.9% of the expected value of the source line potential.

[0080] Fig. 7 shows the relationship between the rise time of the gate line and the size of the display device. When the upper limit of the delay time of the gate line is set to 0.5 μs, even for a 100-inch display, the delay time of the gate line can meet the requirements. In this calculation, the sheet resistance of the gate line is 0.1 Ω / □, the capacitance is 41.3 pF, and the line width is 23 μm.

[0081] Fig. 8 shows the result of the write calculation of the source line. Writing is performed while the sampling pulse is high, and it operates so that the input signal and the written source line potential approach each other. In Fig. 8, the sampling pulse, the input signal, and the potential of the point on the source line farthest from the input are shown. As shown in Fig. 8, it shows that 99.9% of the writing can be completed 0.2 μs after the rise of the input signal for the source line potential. In this way, by improving the mobility of the transistor using the oxide semiconductor, an analog switch for driving the source line is incorporated, and a 100-inch full high-definition display device can be driven at 4 times the speed. Here, the calculation was performed assuming the size of the display device is 100 inches, but it is not limited to this size, and it is possible for sizes of 100 inches or less. Moreover, if the field-effect mobility is further improved or the wiring resistance is reduced, it is also possible for sizes of more than 100 inches.

[0082] (Embodiment 4) Also shown are the calculation results when a shift register type source driver is used for source line driving. . A set-reset type shift register as shown in Fig. 9 was used for the shift register. Also , the source driver was assumed to be driven with an arrangement as shown in Fig. 6(B). Sampling is performed at 960 points simultaneously. To write one quarter of the full vision area with one source driver, the number of points to be sampled is 960 x RGB = 28 80 points. The number of stages of the shift register required to sample these 960 points simultaneously is 30 stages. The timing chart is shown in Fig. 10(A). Also, the period defined in Fig. 10(A) is shown in Fig. 10(B). The clock frequency of the source driver corresponds to the reciprocal of twice the period of B in Fig. 10(B). The required clock frequency is 579 kHz when the display device operates at 1x speed, 1.15 MHz at 2x speed, and 2.31 MHz at 4x speed. If the field effect mobility is 100 cm /

[0083] Vs, the shift register can operate under this condition. In this case, the allowable time to write to the source line is 0.43 μs at 1x speed, 0.22 μs at 2x speed, and 0. 11 μs at 4x speed. There is no problem with the capabilities of the source driver, but the delay time of the source line becomes a problem. Incidentally, the conditions of the source line at this time are such that when the display device is 100 inches, it is equivalent to driving a substantially 50-inch 2 / display. Therefore, the sheet resistance of the source signal line is 0.01 Ω / □, the source line resistance is 1.04 KΩ, and the source line capacitance is 9.3 pF, with a line width of 20 μm. Although there is no problem with the capabilities of the source driver, the delay time of the source line becomes a problem. Incidentally, the conditions of the source line at this time are such that when the display device is 100 inches, it is equivalent to driving a substantially 50-inch display. Therefore, the sheet resistance of the source signal line is 0.01 Ω / □, the source line resistance is 1.04 KΩ, and the source line capacitance is 9.3 pF, with a line width of 20 μm. 1.04 KΩ, and the source line capacitance is 9.3 pF, with a line width of 20 μm.

[0084] Fig. 11 shows the delay time of the source line. In the case of a 100-inch display, there is a wiring delay of 30 ns. Therefore, It is necessary to finish writing in about 60% of the allowable time. Therefore, it is difficult to write at 100 inches. Figure 11 shows data with the display device size set to 10 inches and the frame frequency quadrupled. Here, the potential at the point farthest from the input among the sampling pulse, input signal, and source line is shown. Writing is performed during the period when the sampling pulse is high, and it operates so that the input signal and the source line potential become the same. It reaches 99.9% of the input signal in about 0.07 μs from the rising edge of the input signal, indicating that quadruple-speed operation is possible at 10 inches.

[0085] Figure 12 shows the calculation results when the frame frequency is 120 Hz double-speed and the display device is 100 inches. The conditions other than the frequency are the same as described above. Here, the potential at the point farthest from the input among the sampling pulse, input signal, and source line is shown. Writing is performed during the period when the sampling pulse is high, and it operates so that the input signal and the source line potential become the same. It reaches 99.9% at about 0.13 μs from the rising edge of the input signal. In this case, even if the display device is 100 inches, it shows that 99.9% of the writing can be done within the specified time. 2 If the mobility is 100 cm / Vs, the source driver can be built in, and it is possible to operate even when the display size is 100 inches at double speed.

[0086] (Embodiment 5) In this embodiment, an example of the fabrication of a transistor is shown using FIGS. 1, 2, and 3.

[0087] First, after forming a conductive film on a substrate 400, which is a substrate having an insulating surface, a photomask A gate electrode layer 401 is provided by a photolithography process using a photoresist.

[0088] The substrate 400 is preferably a glass substrate that can be mass-produced. The glass substrate used as the plate 400 may be distorted if the temperature of the heat treatment to be performed in the subsequent process is high. The substrate 400 may be made of, for example, aluminosilicate. Glass materials such as borosilicate glass, aluminoborosilicate glass, and barium borosilicate glass In addition, the material contains more barium oxide (BaO) than boron oxide. By doing so, a more practical heat-resistant glass can be obtained. 2 O 3 Contains more BaO It is preferable to use a glass substrate containing the same.

[0089] In addition, an insulating layer serving as a base layer may be provided between the substrate 400 and the gate electrode layer 401. The layer has a function of preventing the diffusion of impurity elements from the substrate 400, and is made of silicon nitride, silicon oxide, A laminate structure of one or more layers selected from silicon nitride oxide or silicon oxynitride. It can be formed.

[0090] A metal conductive layer can be used as the gate electrode layer 401. The elements are selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or the elements mentioned above. It is preferable to use an alloy containing the above elements or an alloy combining the above elements. For example, A three-layer stack of an aluminum layer on a titanium layer, and a titanium layer on the aluminum layer. A layer structure, or an aluminum layer on a molybdenum layer and a molybdenum layer on the aluminum layer. Of course, the metal conductive layer may be a single layer or It may be a two-layer structure or a laminated structure of four or more layers. It is preferable to select a material for the pole layer 401 that can withstand the heat treatment temperature.

[0091] Next, a gate insulating layer 402 is formed on the gate electrode layer 401. The gate insulating layer 402 is A silicon oxide layer, a silicon nitride layer, a hafnium oxide layer, etc. are formed by using a plasma CVD method or a sputtering method. A silicon oxynitride layer, a silicon nitride oxide layer, or a silicon nitride oxide layer can be formed as a single layer or a stacked layer. For example, a silicon nitride film and a silicon oxide film are stacked. The thickness of the gate insulating layer 402 is 50 nm or more. The upper limit is 200 nm.

[0092] In this embodiment mode, the gate insulating layer 402 is formed by a high density plasma apparatus. Here, the high-density plasma device is 1×10 11 / cm 3 A plasma density of more than For example, a device that applies microwave power of 3kW to 6kW to generate plasma. This allows the deposition of an insulating film.

[0093] The chamber was filled with monosilane gas (SiH 4 ) and nitrous oxide (N 2 O) and rare A gas is introduced to generate high-density plasma at a pressure of 10 Pa to 30 Pa, and the plasma is then applied to insulating materials such as glass. An insulating film is formed on a substrate having a surface. Then, the supply of monosilane gas is stopped and the substrate is exposed to air. Nitrous oxide (N 2 O) and rare gas are introduced to perform plasma treatment on the insulating film surface. At least nitrous oxide (N 2 O) and rare gas are introduced to the insulating film surface. The plasma treatment is performed after the formation of the insulating film. An insulating film that is thin, for example, less than 100 nm, and can ensure reliability. .

[0094] When forming the gate insulating layer 402, the flow rate ratio of monosilane gas (SiH 4 ) and nitrous oxide (N 2 O) is in the range of 1:10 to 1:200. Also, as the rare gas introduced into the chamber, helium, argon, krypton, xenon, etc. can be used , but among them, it is preferable to use argon which is inexpensive.

[0095] In addition, the insulating film obtained by the high-density plasma device can form a film with a constant thickness, so it has excellent step coverage. Also, the insulating film obtained by the high-density plasma device can precisely control the thickness of the thin film.

[0096] The insulating film obtained through the above process sequence is significantly different from the insulating film obtained by the conventional parallel plate type PCVD device. When comparing the etching rates using the same etchant, it is 10% or more or 20% or more slower than the insulating film obtained by the parallel plate type PCVD device. The insulating film obtained by the high-density plasma device can be said to be a dense film.

[0097] In this embodiment, as the gate insulating layer 402, a silicon oxynitride film (also called SiOxNy, where x > y > 0) with a film thickness of 100 nm by a high-density plasma device is used.

[0098] Next, a first oxide semiconductor layer with a thickness of 2 nm or more and 15 nm or less is formed on the gate insulating layer 402. Also, the first oxide semiconductor layer is formed in an atmosphere of a rare gas (typically argon). In an oxygen atmosphere or in a mixed atmosphere of a rare gas (typically argon) and oxygen, sputtering can be performed by a method.

[0099] Further, it is preferable to remove moisture and the like remaining in the sputtering apparatus before, during, or after forming the oxide semiconductor film. To remove the residual moisture in the sputtering apparatus, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Further, as the exhaust means, a turbo pump with a cold trap added thereto may be used. The film formation chamber of the sputtering apparatus evacuated using a cryopump is evacuated of, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H 2O), etc., so that the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced. In this embodiment, as the first oxide semiconductor layer, an oxide semiconductor target (In-Ga- 2 Zn-O-based oxide semiconductor target (In 2O:Ga 2O:ZnO = 1:1:2 [molar ratio]) is used, the distance between the substrate and the target is 170 mm, the pressure is 0.4 Pa,

[0100] a first oxide semiconductor layer with a film thickness of 5 nm is formed in a direct current (DC) power supply of 0.5 kW, in an atmosphere of only oxygen, only argon, or an argon and oxygen atmosphere. Further, as the oxide semiconductor target, a target having a composition ratio of In 2 2O 3 :Ga 2 2O 3 :ZnO = 1:1:1 [molar ratio], or In 2O:Ga 2O:ZnO = 1:1:1 [molar ratio], or In 2O:Ga 2O:ZnO = 1:1:1 [molar ratio] is used, and a first oxide semiconductor layer with a film thickness of 5 nm is formed in an atmosphere of only oxygen, only argon, or an argon and oxygen atmosphere at a distance of 170 mm between the substrate and the target, a pressure of 0.4 Pa, 2 2O 3 :Ga 2 2O 3 :ZnO = 1:1:1 [molar ratio] has a composition ratio of the target, or In 2O:Ga 2 2O:ZnO = 1:1:1 [molar ratio] is used, and a first oxide semiconductor layer with a film thickness of 5 nm is formed in an atmosphere of only oxygen, only argon, or an argon and oxygen atmosphere at a distance of 170 mm between the substrate and the target, a pressure of 0.4 Pa, 3 :Ga2 O 3 :ZnO = 1:1:4 [molar ratio] can also be used as a target having a composition ratio of In this embodiment, since heat treatment is performed later to intentionally crystallize, it is preferable to use an oxide semiconductor target in which crystallization is likely to occur.

[0101] In addition, the relative density of the oxide semiconductor in the oxide semiconductor target is 80% or more, preferably 9 5% or more, more preferably 99.9% or more. When using a target with a high relative density, the impurity concentration in the formed oxide semiconductor film can be reduced, and a transistor with high electrical characteristics or reliability can be obtained.

[0102] Before forming the first oxide semiconductor layer, preheating treatment is preferably performed to remove moisture or hydrogen remaining in the inner wall of the sputtering apparatus, on the target surface, or in the target material. Examples of the preheating treatment include heating the inside of the film formation chamber to 200 °C to 600 °C under reduced pressure, or a method of repeatedly introducing and exhausting nitrogen or an inert gas while heating.

[0103] Next, the first heat treatment of the first oxide semiconductor layer is performed to crystallize at least a part thereof. The temperature of the first heat treatment is 450 °C or more and 850 °C or less. The heating time is 1 minute or more and 24 hours or less. The first oxide semiconductor layer 403, which is a polycrystalline layer grown from the surface by the first heat treatment, is formed (see Fig. 2(A)). Also, the crystal layer formed on the surface has an a - b plane on its surface and is c - axis oriented in a direction perpendicular to the surface. In this embodiment, an example is shown in which the entire first oxide semiconductor layer is made into crystals (also called co - growing crystals) by the first heat treatment. ​​​​​​​​

[0104] In the first heat treatment, it is preferable that nitrogen, oxygen, or noble gases such as helium, neon, and argon do not contain water, hydrogen, etc. Or, the purity of nitrogen, oxygen, or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N or more, preferably 7N or more. Also, the first heat treatment may be performed in a dry air atmosphere with H O of 20 ppm or less. In this embodiment, as the first heat treatment, heating treatment is performed at 700 °C for 1 hour in a dry air atmosphere. 2 In addition, when the temperature is raised during the first heat treatment, the inside of the furnace may be set to a nitrogen atmosphere, and when cooled, the atmosphere may be switched to an oxygen atmosphere. After dehydration or dehydrogenation is performed in a nitrogen atmosphere, the atmosphere can be switched to an oxygen atmosphere to supply oxygen into the first oxide semiconductor layer to make it of type I.

[0105] Next, on the first oxide semiconductor layer 403 which is a flat polycrystal, a second oxide semiconductor layer 4 04 with a film thickness thicker than at least the first oxide semiconductor layer 403 and in the film thickness range of 10 μm or less is formed (see Fig. 2(B)). Note that the film thickness of the second oxide semiconductor layer 404 may be determined by the implementer to be an optimal film thickness according to the device to be manufactured. For example, when manufacturing a bottom gate type

[0106] transistor, the total film thickness of the first oxide semiconductor layer 403 and the second oxide semiconductor layer 4 04 is set to be 10 nm or more and 200 nm or less. As the second oxide semiconductor layer 404, an In-Sn-Ga-Zn quaternary metal oxide is used.

[0107] Next, on the first oxide semiconductor layer 403 which is a flat polycrystal, a second oxide semiconductor layer 4 04 with a film thickness thicker than at least the first oxide semiconductor layer 403 and in the film thickness range of 10 μm or less is formed (see Fig. 2(B)). Note that the film thickness of the second oxide semiconductor layer 404 may be determined by the implementer to be an optimal film thickness according to the device to be manufactured. For example, when manufacturing a bottom gate type transistor, the total film thickness of the first oxide semiconductor layer 403 and the second oxide semiconductor layer 4 04 is set to be 10 nm or more and 200 nm or less. For example, when manufacturing a bottom gate type transistor, the total film thickness of the first oxide semiconductor layer 403 and the second oxide semiconductor layer 4 04 is 10 nm or more and 200 nm or less.

[0108] The second oxide semiconductor layer 404 is a quaternary metal oxide In-Sn-Ga-Zn -O films, and ternary metal oxide In-Ga-Zn-O films, In-Sn-Zn-O films, In-Al-Zn-O films, Sn-Ga-Zn-O films, Al-Ga-Zn-O films, Sn-A l-Zn-O systems, and binary metal oxide In-Zn-O films, Sn-Zn-O films, Al -Zn-O films, Zn-Mg-O films, Sn-Mg-O films, In-Mg-O films, and In-O films 、Sn-O films, Zn-O films and other oxide semiconductor films can be used.

[0109] In addition, the first oxide semiconductor layer 403 and the second oxide semiconductor layer 404 are preferably made of materials containing the same components, or having the same crystal structure and close lattice constants (mismatch is 1% or less ). When using materials containing the same components, crystal growth is likely to occur using the polycrystalline layer of the first oxide semiconductor layer 403 as a seed in the subsequent crystallization. Also when using materials containing the same components, the interfacial physical properties such as adhesion and electrical properties are also good. .

[0110] Next, a second heat treatment is performed to grow crystals using the crystal layer of the first oxide semiconductor layer 403 as a seed. The temperature of the second heat treatment is 450 °C or higher and 850 °C or lower, preferably 550 °C or higher and 650 °C or lower. Also, the heating time is 1 minute or longer and 24 hours or shorter. The second oxide semiconductor layer is crystallized by the second heat treatment. In this way, a plate-like crystal oxide semiconductor laminate 4 30 can be obtained (see Fig. 2(C)).

[0111] The plate-like crystal is preferably a single crystal with a c-axis orientation perpendicular to the surface of the oxide semiconductor layer. Also, even if it is not a single crystal, the a-axis and b-axis of each crystal are oriented in the channel formation region In addition, it is preferable that the oxide semiconductor layer is a polycrystalline body having a c-axis oriented perpendicular to the surface of the oxide semiconductor layer. Note that when the base surface of the oxide semiconductor layer has irregularities, the plate-like crystals become polycrystalline.

[0112] In addition, the steps of FIG. 2(A), FIG. 2(B), and FIG. 2(C) are explained in a generalized manner. In order to clarify the above, enlarged schematic diagrams are shown in FIG. 1(A), FIG. 1(B), and FIG. 1(C).

[0113] FIG. 1A shows a first heat treatment for crystallization on a base member 500. FIG. 1(A) corresponds to FIG. 2(A), and the oxide crystal member 501 is an underlying member. 500 corresponds to the gate insulating layer 402. FIG. 1B corresponds to FIG. 2B. 1C is a cross-sectional view immediately after the deposition of the second oxide semiconductor layer 502. FIG. 1C is a cross-sectional view of the semiconductor device after the second heat treatment. The third oxide crystal member 503a is made of a crystal layer having a higher degree of orientation. When the first oxide member and the second oxide member are made of oxide semiconductor materials containing the same components, As shown in FIG. 1(C), the second oxide crystal member 503a is grown on the crystal layer of the third oxide crystal member 503a as a nucleus. The crystals grow upwards towards the surface of the member, forming a second oxide crystal member 503b. The crystal members have a c-axis orientation. Therefore, the third oxide layer is shown by the dotted line in FIG. 1(C). The boundary between the first oxide crystal member and the second oxide crystal member becomes unclear. As a result, the inside of the second oxide member immediately after the film formation is highly purified and becomes a layer containing amorphous matter.

[0114] Next, an oxide semiconductor stack 43 including a first oxide semiconductor layer and a second oxide semiconductor layer is formed. 0 is processed into an island-shaped oxide semiconductor layer 431 by a photolithography process (see Fig. 2(D ).). Further, a resist mask for forming the island-shaped oxide semiconductor layer 431 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0115] Next, after a metal conductive film is formed on the gate insulating layer 402 and the island-shaped oxide semiconductor layer 431 by a sputtering method or the like, a resist mask is formed by a photolithography process, and selective etching is performed to form a metal electrode layer.

[0116] Subsequently, the metal conductive film that will become the source electrode and the drain electrode (including wiring formed in the same layer) is formed of a metal material such as Al, Cu, Cr, Ta, Ti, Mo, W, or an alloy material containing the metal material as a component. Further, a high melting point metal layer such as Cr, Ta, Ti, Mo, W is laminated on one or both of the lower side and the upper side of a metal layer such as Al, Cu. It may also be configured. Further, an Al material added with an element that prevents the generation of hillocks and whiskers generated in the Al film such as Si, Ti, Ta, W, Mo, Cr, Nd, Sc, Y can be used to improve the heat resistance.

[0117] For example, as the metal conductive film, a three-layer laminated structure in which an aluminum layer is laminated on a titanium layer and a titanium layer is laminated on the aluminum layer, or an aluminum layer is laminated on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer. It is preferably a three-layer laminated structure. Further, as the metal conductive film, a two-layer laminated structure in which an aluminum layer and a tungsten layer are laminated, a copper layer and a tantalum layer are laminated, or the like. ​​​​​​​A two-layer stacked structure with a gussten layer, or a two-layer stacked structure with an aluminum layer and a molybdenum layer can also be used. Of course, it may be a single layer or a stacked structure of four or more layers as the metal conductive film .

[0118] Next, the resist mask is removed, and a resist mask is formed by a photolithography process , and selective etching is performed to form the source electrode layer 405a and the drain electrode layer 405b , and then the resist mask is removed (see Fig. 2(E)). In this photolithography process, only a part of the island-shaped oxide semiconductor stack 431 may be etched, and it may become an oxide semiconductor layer having a groove (concave part).

[0119] Also, as shown in Fig. 2(E), it is also one of the features that the gate electrode layer 401 has a region overlapping with the source electrode layer 405a (or the drain electrode layer 405b). The end of the source electrode layer and the step of the gate insulating layer 402, that is, in the cross-sectional view, the region between the flat surface of the gate insulating layer and the change point to the tapered surface (here, the L OV region shown in Fig. 2(E)) . The L OV region is important to prevent carriers from flowing into the grain boundaries generated by the unevenness at the end of the gate electrode layer .

[0120] Also, on the side surface of the oxide semiconductor stack 432, the crystal layer in contact with the source electrode layer 405a or the drain electrode layer 405b may be in an amorphous state

[0121] Also, the resist mask for forming the source electrode layer 405a and the drain electrode layer 405b may be formed by an inkjet method . The resist mask may be formed by an inkjet method Since a photomask is not used, the manufacturing cost can be reduced.

[0122] In addition, in order to reduce the number of photomasks and the number of processes used in the photolithography process, a resist mask formed by a halftone mask, which is an exposure mask in which the transmitted light has multiple intensities, may be used for the etching process. The resist mask formed using the halftone mask has a shape with multiple film thicknesses and can be further deformed in shape by performing etching, so it can be used in multiple etching processes for processing into different patterns. Therefore, a resist mask corresponding to at least two or more different patterns can be formed by a single halftone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography processes can also be reduced, enabling simplification of the process. Next, an oxide insulating layer 407 serving as a protective insulating layer in contact with a part of the oxide semiconductor layer is formed. The oxide insulating layer 407 has a film thickness of at least 1 nm or more and can be formed by appropriately using a method that does not mix impurities such as water and hydrogen into the oxide insulating layer 407, such as a sputtering method. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the oxide insulating layer 407 using a sputtering method.

[0123] The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and is set to 100 °C in this embodiment. The film formation of the silicon oxide film by the sputtering method can be performed in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically argon) and oxygen.

[0124] Also, a silicon oxide target or silicon can be used as the target. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the oxide insulating layer 407 using a sputtering method. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and is set to 100 °C in this embodiment. The film formation of the silicon oxide film by the sputtering method can be performed in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically argon) and oxygen. In addition, a silicon oxide target or silicon can be used as the target. A simple target can be used. For example, a silicon target can be used to form silicon oxide in an oxygen and nitrogen atmosphere by sputtering. The oxide insulating layer 407 formed in contact with the low-resistance oxide semiconductor layer uses an inorganic insulating film, typically a silicon oxide film , a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film, etc. Furthermore, a protective insulating layer such as a silicon nitride film or an aluminum nitride film may be formed on the oxide insulating layer 407.

[0125] Also, a contact hole reaching the gate electrode layer 401 may be formed with respect to the oxide insulating layer 407 and the gate insulating layer 402, and a connection electrode electrically connected to the gate electrode layer 401 and applying a gate potential may be formed on the oxide insulating layer 407. Also, after forming the gate insulating layer 402, a contact hole reaching the gate electrode layer 401 may be formed, and a connection electrode made of the same material as the source electrode layer or the drain electrode layer may be formed thereon, and the oxide insulating layer 407 may be formed on the connection electrode . Then, a contact hole reaching the connection electrode may be formed in the oxide insulating layer 407, and after that, an electrode electrically connected to the connection electrode and applying a gate potential may be formed on the oxide insulating layer 407.

[0126] The transistor 470 is formed in the above steps (see Fig. 3(B)). Also, Fig. 3(A) shows an example of the top view of the transistor 470. Note that Fig. 3(B) corresponds to the cross-sectional view cut along the dashed line C1-C2 in Fig. 3(A).

[0127] The transistor 470 has a flat upper surface of the gate electrode layer in the channel formation region, and has an oxide member oriented perpendicular to the flat surface along the c-axis, and also has a source electrode layer or a drain electrode layer It is also one of the features that it overlaps even with the unevenness caused by the end of the gate electrode layer. Acid The oxide member (oxide semiconductor stack 432 in this embodiment) becomes polycrystalline with grain boundaries in the region where the concave portion hits when there are unevenness on the substrate side Therefore, by forming the Lo v region shown in Fig. 3(B), carriers can be prevented from flowing through the grain boundaries generated by the unevenness at the end of the gate electrode layer. Therefore, in the transistor 470, the source electrode layer or the drain electrode layer is provided so as to extend above the flat portion of the gate electrode and has an overlap (overlap) with the gate electrode layer layer.

[0128] Needless to say, the structure of the transistor 470 shown in Fig. 3(B) is not particularly limited Any top-gate type transistor or bottom-gate type transistor may be used. For example, in order to protect the etching damage during the formation of the source electrode layer and the drain electrode layer in Fig. 2(E), an oxide insulating layer overlapping the channel formation region may be provided as a channel stopper and used as a channel stop type transistor.

[0129] An electrode layer that can function as a back gate may be provided on the oxide insulating layer 407 The potential of the back gate can be a fixed potential, for example, 0V or the ground potential, and can be appropriately determined by the implementer. Also, by controlling the gate voltage applied to the back gate the threshold voltage can be controlled. Also, the threshold voltage can be made positive to function as an enhancement type transistor. Also, the threshold voltage can be made negative to function as a depletion type transistor. For example, enhancement ment ​​​​A combination of an n-type transistor and a depletion-type transistor is used to form an inverter circuit (hereinafter referred to as an EDMOS circuit), which can be used in a drive circuit. The drive circuit includes at least a logic circuit section and a switch section or a buffer section. The logic circuit section has a circuit configuration including the above EDMOS circuit. Also, the operating principle of a bottom-gate transistor using an oxide semiconductor will be described below. FIG. 13 shows a longitudinal sectional view of a transistor using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on a gate electrode (GE1) via a gate insulating film (GI), and a source electrode (S) and a drain electrode (D) are provided thereon. Also, an oxide insulating layer overlapping the channel formation region of the oxide semiconductor layer (OS) is provided on the source electrode (S) and the drain electrode (D). FIG. 14 shows an energy band diagram (schematic diagram) in the A-A' cross section shown in FIG. 13. FIG. 14(A) shows the case where the voltage between the source and the drain is set to an equipotential (VD = 0V), and FIG. 14(B) shows the case where a positive potential (VD>0) is applied to the drain with respect to the source. Also, the black circles (●) in FIG. 7 indicate electrons, and the white circles (○) indicate holes, each having a charge (-q, +q).

[0130] FIG. 15 shows an energy band diagram (schematic diagram) in the B-B' cross section in FIG. 13, showing the state when the gate voltage is 0V. FIG. 15(A) shows the state where a positive potential (+VG) is applied to the gate (G1), and carriers (electrons) flow between the source and the drain in the on state.

[0131] FIG. 13 shows a longitudinal sectional view of a transistor using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on a gate electrode (GE1) via a gate insulating film (GI), and a source electrode (S) and a drain electrode (D) are provided thereon. Also, an oxide insulating layer overlapping the channel formation region of the oxide semiconductor layer (OS) is provided on the source electrode (S) and the drain electrode (D).

[0132] FIG. 14 shows an energy band diagram (schematic diagram) in the A-A' cross section shown in FIG. 13. FIG. 14(A) shows the case where the voltage between the source and the drain is set to an equipotential (VD = 0V), and FIG. 14(B) shows the case where a positive potential (VD>0) is applied to the drain with respect to the source. Also, the black circles (●) in FIG. 7 indicate electrons, and the white circles (○) indicate holes, each having a charge (-q, +q).

[0133] FIG. 15 shows an energy band diagram (schematic diagram) in the B-B' cross section in FIG. 13, showing the state when the gate voltage is 0V. FIG. 15(A) shows the state where a positive potential ( +VG) is applied to the gate (G1), and carriers (electrons) flow between the source and the drain in the on state. ​​​​​It shows the state. Further, FIG. 15(B) shows the case where a negative potential (-VG) is applied to the gate (G1), and it is in the off state (minority carriers do not flow).

[0134] When the thickness of the oxide semiconductor is about 50 nm and the oxide semiconductor is highly purified, the doping concentration is 1×10 18 / cm 3 or less, the depletion layer spreads over the entire oxide semiconductor. That is, it can be regarded as a completely depleted state.

[0135] FIG. 16 shows the relationship between the vacuum level, the work function (φM) of the metal, and the electron affinity (χ) of the oxide semiconductor.

[0136] Since the metal is degenerate, the conduction band and the Fermi level coincide. On the other hand, conventional oxide semiconductors are generally n-type, and in that case, the Fermi level (Ef) is separated from the intrinsic Fermi level (Ei) located at the center of the band gap and is located closer to the conduction band. Note that hydrogen is known to be a donor in the oxide semiconductor and is one of the factors for n-type conversion.

[0137] In contrast, the oxide semiconductor according to the present invention removes hydrogen, which is an n-type impurity, from the oxide semiconductor and highly purifies it so that impurities other than the main components of the oxide semiconductor are not contained as much as possible. By doing so, it becomes more intrinsic (type I) or attempts to be intrinsic type. That is, instead of adding impurities to make it type I, by removing impurities such as hydrogen and water as much as possible, it is highly purified type I (intrinsic semiconductor) or approaching it. By doing so, the Fermi level (Ef) can be brought to the same level as the intrinsic Fermi level (Ei).

[0138] ​​​The oxide semiconductor has a band gap (Eg) of 3.05 eV to 3.15 eV . When the band gap (Eg) of the oxide semiconductor is 3.15 eV, the electron affinity (χ) is said to be 4.3 eV. The work function of titanium (Ti) constituting the source electrode and the drain electrode is almost equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface, a Schottky-type barrier is not formed for electrons.

[0139] That is, when the work function (φM) of the metal is equal to the electron affinity (χ) of the oxide semiconductor, when the two are in contact, an energy band diagram (schematic diagram) as shown in Fig. 14(A) is shown.

[0140] In Fig. 14(B), the black circles (●) indicate electrons. When a positive potential is applied to the drain, the electrons cross the barrier (h) and are injected into the oxide semiconductor and flow toward the drain. In this case, the height of the barrier (h) changes depending on the gate voltage and the drain voltage. When a positive drain voltage is applied, the height of the barrier in Fig. 14(A) without voltage application, that is, the height of the barrier (h) is smaller than half of the band gap (Eg).

[0141] At this time, the electrons move to the lowest energy-stable part on the oxide semiconductor side at the interface between the gate insulating film and the highly purified oxide semiconductor as shown in Fig. 15(A).

[0142] Also, in Fig. 15(B), when a negative potential (reverse bias) is applied to the gate electrode (G1), since the number of minority carriers, holes, is substantially zero, the current becomes an extremely small value close to zero.

[0143] ​By purifying to a high purity so as to contain as few impurities as possible other than the main component of the oxide semiconductor, it becomes intrinsic (type I) or substantially intrinsic, and the interface characteristics with the gate insulating film become apparent, so it is necessary to consider them separately from the characteristics of the bulk. Therefore, the gate insulating film needs to be one that can form a good interface with the oxide semiconductor. For example, an insulating film formed by a CVD method using high-density plasma generated at a power supply frequency in the VHF band to microwave band, or an insulating film formed by a sputtering method is preferably used.

[0144] By purifying the oxide semiconductor to a high purity while making the interface between the oxide semiconductor and the gate insulating film good, as characteristics of the transistor, even for an element with a channel width W of 1×10 4 μm and a channel length of 3 μm, the off-current is 10 -13 A or less, and the subthreshold swing value (S value) is 0.1 V / dec. (gate insulating film thickness 100 nm), and such characteristics are highly expected.

[0145] Thus, by purifying the oxide semiconductor to a high purity so as to contain as few impurities as possible other than the main component, a transistor with high mobility can be formed, and the operation of the transistor can be made good.

[0146] (Embodiment 6) Embodiment 5 showed the case of using an oxide semiconductor material containing the same components for the first oxide member and the second oxide member, but this embodiment shows the case of using oxide semiconductor materials with different components. In this embodiment, a metal oxide target of In:Zn = 1:1 [atomic ratio] not containing Ga is used.

[0147] An example is shown in which a first oxide semiconductor layer has a film thickness of 5 nm using a getter. In the case of a bottom gate type transistor, since the oxide of Ga is an insulator, the field effect mobility can be increased by using an In-Zn-O film rather than an In-Ga-Zn-O film as the first oxide semiconductor layer. can be increased.

[0148] Next, a first heat treatment is performed. Depending on conditions such as the material of the first oxide semiconductor layer and the base member 520, the heating temperature, and the heating time, a first oxide crystal member 531 that is polycrystalline is formed from the surface to grow crystal up to the interface of the base member 520 by the first heat treatment (see Fig. 17 (A)).

[0149] Examples of the base member 520 include an oxide layer, a metal layer, and a nitride layer. By the first heat treatment, regardless of the material of the base member, a first oxide crystal member 531 that is polycrystalline with relatively aligned crystal orientations is formed on the surface of the first oxide semiconductor layer, and crystal growth occurs in the depth direction from the surface. Also, the first oxide crystal member 531 is c-axis oriented in a direction perpendicular to the surface.

[0150] Next, Fig. 17(B) is a cross-sectional view immediately after forming a second oxide member 532 on the first oxide crystal member 531. In the present embodiment, as the second oxide member 532, an In-Ga-Zn-O-based oxide semiconductor target (In 2 O 3 :Ga 2 O 3 :ZnO = 1:1: 2 [mole ratio]) is used to form an In-Ga-Zn-O film with a film thickness of 50 nm.

[0151] Then, after forming the second oxide member 532, a second heat treatment is performed. The second heat treatment​​​​​​​​ By this method, crystal growth is performed as shown in FIG. 17(C). As shown in FIG. 17(C), crystal growth occurs upward toward the surface of the second oxide member using the crystal layer of the first oxide crystal member 531 as a seed, and the second oxide crystal member 533b is formed.

[0152] In addition, since the first oxide crystal member 531 obtained by the first heat treatment is heated again in the second heat treatment, it becomes the third oxide crystal member 533a with further improved crystallinity.

[0153] Since an oxide semiconductor material having a component different from that of the first oxide crystal member 531 is used as the second oxide crystal member 532, as shown in FIG. 17(C), a boundary between the third oxide crystal member 533a and the second oxide crystal member 533b is formed. Also, by the second heat treatment, most of the first oxide semiconductor layer, including the vicinity of the gate insulating layer interface, is made polycrystalline.

[0154] The structure of FIG. 17(C) can be said to be a two-layer structure in which the third oxide crystal member 533a and the second oxide crystal member 533b are laminated in this order in contact with the base member 520. By using different materials, the field-effect mobility of the transistor can be increased. Also, by using an In-Zn-O film that is more likely to crystallize than an In-Ga-Zn-O film as a seed for crystal growth, crystal growth can be efficiently performed upward thereon, and the In-Ga-Zn-O film can be made polycrystalline.

[0155] When the second oxide crystal member to be grown and the first oxide crystal member serving as the base are the same, it is called homoepitaxy. Also, when the second oxide crystal member to be grown and the first oxide crystal member serving as the base are different, it is called heteroepitaxy. In this embodiment, respectively ​ Both are possible depending on the selection of the material.

[0156] In addition, the conditions for the first heat treatment and the second heat treatment are within the range of the conditions described in Embodiment 5. to be.

[0157] In addition, this embodiment can be freely combined with Embodiment 5.

[0158] (Embodiment 7) In this embodiment, a transistor including a laminated oxide material having a c-axis oriented crystal layer is manufactured, and the transistor is used in a pixel portion and further in a driving circuit to manufacture a semiconductor device having a display function (also referred to as a display device). In addition, a transistor can be formed on the same substrate as the pixel portion for a part or the whole of the driving circuit to form a system-on-panel. The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, etc. In addition, a display medium whose contrast changes by an electric action such as electronic ink can also be applied. The display device includes a panel in a state where the display element is sealed. Further, regarding the element substrate corresponding to a form before the display element is completed in the process of manufacturing the display device, the element substrate includes means for supplying current to the display element for each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrode of the display element is formed. to be able to.

[0159] The display element is included in the display device. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, etc. In addition, a display medium whose contrast changes by an electric action such as electronic ink can also be applied. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, etc. In addition, a display medium whose contrast changes by an electric action such as electronic ink can also be applied. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, etc. In addition, a display medium whose contrast changes by an electric action such as electronic ink can also be applied. o Luminescence), organic EL, etc. are included. In addition, a display medium whose contrast changes by an electric action such as electronic ink can also be applied. The display medium whose contrast changes by an electric action such as electronic ink can also be applied.

[0160] In addition, the display device includes a panel in a state where the display element is sealed. Further, regarding the element substrate corresponding to a form before the display element is completed in the process of manufacturing the display device, the element substrate includes means for supplying current to the display element for each of a plurality of pixels. The element substrate may specifically be in a state where only the pixel electrode of the display element is formed. The element substrate includes means for supplying current to the display element for each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrode of the display element is formed, or It may be in a state after forming the conductive layer serving as the pixel electrode and before etching to form the pixel electrode, and any form is applicable. Moreover, the display device in this specification refers to an image display device and a display device.

[0161] In this embodiment, an example of a liquid crystal display device is shown as a semiconductor device which is one form of the present invention. First,

[0162] the appearance and cross section of a liquid crystal display panel corresponding to one form of the semiconductor device will be described with reference to FIG. 18. FIG. 18(A) is a top view of a panel in which transistors 4010, 4011 including a laminated oxide material having a c-axis oriented crystal layer formed on a first substrate 4001 as a semiconductor layer, and a liquid crystal element 4013 are sealed with a sealing material 4005 between the second substrate 4006, and FIG. 18(B) corresponds to a cross-sectional view taken along M-N in FIG. 18(A). A sealing material 4005 is provided so as to surround a pixel portion 4002, a signal line driving circuit 4003, and a scanning line driving circuit 4004 provided on the first substrate 4001. Also, a second substrate 4006 is provided on the pixel portion 4002, the signal line driving circuit 4003, and the scanning line driving circuit 4004. Therefore, the pixel portion 4002, the signal line driving circuit 4003, and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. On the other hand, the pixel portion 4002, the signal line driving circuit 4003, and the scanning line driving circuit 4004 provided on the first substrate 4001 have a plurality of transistors. In FIG. 18(B), the pixel... ... ...

[0163] A pixel portion 4002 provided on the first substrate 4001, a signal line driving circuit 4003, and a scanning line driving circuit 4004 are surrounded by a sealing material 4005. Also, a second substrate 4006 is provided on the pixel portion 4002, the signal line driving circuit 4003, and the scanning line driving circuit 4004. Thus, the pixel portion 4002, the signal line driving circuit 4003, and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Moreover, the pixel portion 4002, the signal line driving circuit 4003, and the scanning line driving circuit 4004 provided on the first substrate 4001 have a plurality of transistors. In FIG. 18(B), the pixel... ... ... ...

[0164] Moreover, the pixel portion 4002 provided on the first substrate 4001, the signal line driving circuit 4003, and the scanning line driving circuit 4004 have a plurality of transistors. In FIG. 18(B), The transistor 4010 included in the section 4002 and the transistor 4011 included in the scanning line driving circuit 4004 are exemplified. Insulating layers 4020 and 4021 are provided on the transistors 4010 and 4011. The transistors 4010 and 4011 can be applied to transistors including a c-axis oriented crystal layer shown in Embodiment 5. In this embodiment, the transistors 4010 and 4011 are n-channel transistors. On the insulating layer 4021, a conductive layer 4040 is provided at a position overlapping with the channel formation region of the oxide semiconductor layer of the transistor 4011 for the driving circuit. By providing the conductive layer 4040 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the transistor 4011 before and after the BT test can be reduced. Also, the potential of the conductive layer 4040 may be the same as or different from the gate electrode layer of the transistor 4011, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4040 may be GND, 0V, or in a floating state.

[0165] The transistors 4010 and 4011 can be applied to transistors including a c-axis oriented crystal layer shown in Embodiment 5. In this embodiment, the transistors 4010 and 4011 are n-channel transistors. In this embodiment, the transistors 4010 and 4011 are n-channel transistors. On the insulating layer 4021, a conductive layer 4040 is provided at a position overlapping with the channel formation region of the oxide semiconductor layer of the transistor 4011 for the driving circuit. By providing the conductive layer 4040 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the transistor 4011 before and after the BT test can be reduced. Also, the potential of the conductive layer 4040 may be the same as or different from the gate electrode layer of the transistor 4011, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4040 may be GND, 0V, or in a floating state.

[0166] On the insulating layer 4021, a conductive layer 4040 is provided at a position overlapping with the channel formation region of the oxide semiconductor layer of the transistor 4011 for the driving circuit. By providing the conductive layer 4040 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the transistor 4011 before and after the BT test can be reduced. Also, the potential of the conductive layer 4040 may be the same as or different from the gate electrode layer of the transistor 4011, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4040 may be GND, 0V, or in a floating state. On the insulating layer 4021, a conductive layer 4040 is provided at a position overlapping with the channel formation region of the oxide semiconductor layer of the transistor 4011 for the driving circuit. By providing the conductive layer 4040 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the transistor 4011 before and after the BT test can be reduced. Also, the potential of the conductive layer 4040 may be the same as or different from the gate electrode layer of the transistor 4011, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4040 may be GND, 0V, or in a floating state. By providing the conductive layer 4040 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the transistor 4011 before and after the BT test can be reduced. Also, the conductive layer 4040 may have the same potential as the gate electrode layer of the transistor 4011, or a different potential, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4040 may be GND, 0V, or in a floating state. Also, the conductive layer 4040 may have the same potential as the gate electrode layer of the transistor 4011, or a different potential, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4040 may be GND, 0V, or in a floating state. Also, the conductive layer 4040 may have the same potential as the gate electrode layer of the transistor 4011, or a different potential, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4040 may be GND, 0V, or in a floating state. Also, the potential of the conductive layer 4040 may be GND, 0V, or in a floating state.

[0167] Also, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, respectively. Also, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, respectively. The liquid crystal layer 4008 is sandwiched via the layers 4032 and 4033.

[0168] As the second substrate 4006, glass or plastic can be used. As for the plastic, an FRP (Fiberglass-Reinforced Plastics) board, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used.

[0169] Further, 4035 is a columnar spacer obtained by selectively etching an insulating layer, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that a spherical spacer may be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the transistor 4010. Further, using a common connection portion, the counter electrode layer 4031

[0170] and the common potential line can be electrically connected via conductive particles disposed between a pair of substrates. Note that the conductive particles are contained in the sealing material 4005. Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, in order to improve the temperature range, a liquid crystal composition in which 5 wt% or more of a chiral It is short as follows, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence.

[0171] In addition, when using a liquid crystal that exhibits a blue phase, rubbing treatment on the alignment film is also unnecessary. Therefore, electrostatic breakdown caused by the rubbing treatment can be prevented, and defects and damages of the liquid crystal display device during the manufacturing process can be reduced. Thus, it becomes possible to improve the productivity of the liquid crystal display device. In particular, a transistor using an oxide semiconductor layer may have its electrical characteristics significantly fluctuate due to the influence of static electricity and deviate from the design range. Therefore, using a liquid crystal material with a blue phase in a liquid crystal display device having a transistor using an oxide semiconductor layer is more effective.

[0172] Note that the liquid crystal display device shown in this embodiment is an example of a transmissive liquid crystal display device, but the liquid crystal display device can also be applied to a reflective liquid crystal display device or a transflective liquid crystal display device.

[0173] Also, in the liquid crystal display device shown in this embodiment, a polarizing plate is provided on the outside (viewing side) of the substrate, and an example of providing a coloring layer and an electrode layer used for the display element in this order on the inside is shown. However, the polarizing plate may be provided on the inside of the substrate. Also, the laminated structure of the polarizing plate and the coloring layer is not limited to this embodiment, and may be appropriately set according to the materials and manufacturing process conditions of the polarizing plate and the coloring layer. Also, a light-shielding layer that functions as a black matrix may be provided as necessary.

[0174] Also, in this embodiment, in order to reduce the surface unevenness of the transistor and improve the reliability of the transistor, the transistor is covered with an insulating layer ([[]] insulating layer 4020, insulating layer 4021) that functions as a protective layer or a planarizing insulating layer. Note that the protective layer is in the atmosphere ​​​ It is for preventing the intrusion of contaminating impurities such as floating organic substances, metallic substances, and water vapor, and a dense film is preferable. The protective layer may be formed as a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, or an aluminum nitride oxide layer by using a sputtering method. In this embodiment, although an example of forming the protective layer by a sputtering method is shown, it is not particularly limited and may be formed by various methods. Here, an insulating layer 4020 having a laminated structure is formed as the protective layer. Here, a silicon oxide layer is formed as the first layer of the insulating layer 402 0 by using a sputtering method. When a silicon oxide layer is used as the protective layer, it is effective in preventing hillock formation of the aluminum layer used as the source electrode layer and the drain electrode layer.

[0175] Further, an insulating layer is formed as the second layer of the protective layer. Here, a silicon nitride layer is formed as the second layer of the insulating layer 4020 by using a sputtering method. When a silicon nitride layer is used as the protective layer, it is possible to suppress ions such as sodium from entering the semiconductor region and changing the electrical characteristics of the transistor.

[0176] Also, an insulating layer 4021 is formed as a planarizing insulating layer. As the insulating layer 4021, a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. In addition to the above organic materials, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that by laminating a plurality of insulating layers formed of these materials, the insulating layer

[0177] ​​​​​​​​​4021 may be formed.

[0178] The siloxane-based resin corresponds to a resin containing an Si-O-Si bond formed from a siloxane-based material as a starting material. The siloxane-based resin may use an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. Further, the organic group may have a fluoro group. The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet ejection method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When forming the insulating layer 4021 using a material solution, annealing of the semiconductor layer (300°C to 400°C) may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device. The pixel electrode layer 4030 and the counter electrode layer 4031 can use a light-transmissive conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc.

[0179]

[0180]

[0181] ​​​​​​​​​​​​​​​The formed pixel electrode preferably has a sheet resistance of 10,000 Ω / sq or less and a light transmittance of 70% or more at a wavelength of 550 nm. Also, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less. As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or

[0182] its derivatives, or copolymers of two or more of these can be mentioned. Further, various signals and potentials supplied to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4 002 are supplied from the FPC 4018.

[0183] In this embodiment, the connection terminal electrode 4015 is formed from the same conductive layer as the pixel electrode layer 40

[0184] 30 of the liquid crystal element 4013, and the terminal electrode 4016 is formed from the same conductive layer as the source electrode layer and the drain electrode layer of the transistors 4010, 4011

[0185]

[0186] The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive layer 4019.

[0187] Also, in FIG. 18, an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present embodiment is not limited to this configuration. The scanning line driving circuit may be formed and mounted on the same substrate as the pixel portion 4002, or only a part of the signal line driving circuit or only a part of the scanning line driving circuit may be formed and mounted on the same substrate as the pixel portion 4002.

[0187] Also, if necessary, a color filter is provided corresponding to each pixel. Also, a first substrate 40 01 and a polarizing plate or a diffusion plate are provided outside the second substrate 4006. Also, the light of the backlight source is composed of a cold cathode tube or an LED to form a liquid crystal display module.

[0188] The liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (I n-Plane-Switching) mode, an FFS (Fringe Field S witching) mode, an MVA (Multi-domain Vertical A lignment) mode, a PVA (Patterned Vertical Alig nment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated B irefringence) mode, an FLC (Ferroelectric Liqui d Crystal) mode, an AFLC (AntiFerroelectric Liq uid Crystal) mode, etc.

[0189] By the above steps, a highly reliable liquid crystal display device can be manufactured.

[0190] Also, by using the manufacturing method of the laminated oxide material having the c-axis oriented crystal layer shown in Embodiment 5 to manufacture the transistors of the drive circuit of the liquid crystal display device, the normally-off of the transistors in the drive circuit unit can be realized, and power saving can be achieved.

[0191] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments as possible.

[0192] (Embodiment 8) With regard to the appearance and cross-section of a light-emitting display panel (also referred to as a light-emitting panel) corresponding to one form of a semiconductor device, it will be described with reference to FIG. 19. FIG. 19(A) shows a transistor and a light-emitting element including a laminated oxide material having a c-axis oriented crystal layer formed on a first substrate, sealed with a sealing material between the first substrate and a second substrate. FIG. 19(A) is a plan view of the panel, and FIG. 19(B) corresponds to a cross-sectional view taken along the line H-I of FIG. 19(A). A sealing material 4505 is provided so as to surround a pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b provided on the first substrate 4501. Further, a second substrate 4506 is provided on the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b. Thus, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. It is preferable to package (encase) with a highly airtight and low outgassing protective film (laminating film, ultraviolet curable resin film, etc.) or cover material so as not to be exposed to the outside air. Moreover, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b provided on the first substrate 4501 have a plurality of transistors. In FIG. 19(B), the transistor 4510 included in the pixel portion 4502 and the transistor 4509 included in the signal line driving circuit 4503a are illustrated as examples.

[0193] A pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b provided on the first substrate 4501 are surrounded by a sealing material 4505. A second substrate 4506 is provided on the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b. Therefore, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. In this way, it has high airtightness and is not exposed to the outside air, and it is preferable to package (encase) with a protective film (laminating film, ultraviolet curable resin film, etc.) or cover material with little outgassing. Moreover, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b provided on the first substrate 4501 have a plurality of transistors. In FIG. 19(B), the transistor 4510 included in the pixel portion 4502 and the transistor 4509 included in the signal line driving circuit 4503a are illustrated as examples. It is sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. In this way, it has high airtightness and is not exposed to the outside air, and it is preferable to package (encase) with a protective film (laminating film, ultraviolet curable resin film, etc.) or cover material with little outgassing. It is preferably packaged (encased) with a highly airtight and low outgassing protective film (laminating film, ultraviolet curable resin film, etc.) or cover material so as not to be exposed to the outside air.

[0194] Also, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b provided on the first substrate 4501 have a plurality of transistors. In FIG. 19(B), the transistor 4510 included in the pixel portion 4502 and the transistor 4509 included in the signal line driving circuit 4503a are illustrated as examples. In FIG. 19(B), the transistor 4510 included in the pixel portion 4502 and the transistor 4509 included in the signal line driving circuit 4503a are illustrated as examples. In FIG. 19(B), the transistor 4510 included in the pixel portion 4502 and the transistor 4509 included in the signal line driving circuit 4503a are illustrated as examples.

[0195] The transistors 4509 and 4510 have a c-axis oriented crystal layer as described in the fifth embodiment. A highly reliable transistor including a laminated oxide material can be applied. In this figure, the transistors 4509 and 4510 are n-channel transistors.

[0196] A channel of an oxide semiconductor layer of a transistor 4509 for a driver circuit is formed on the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping with the hole formation region. By placing the conductor layer at a position that overlaps with the channel formation region, The amount of change in the threshold voltage of the transistor 4509 can be reduced. 40 may have the same potential as the gate electrode layer of the transistor 4509 or may have a different potential. Alternatively, the conductive layer 4540 may function as a second gate electrode layer. may be GND, 0V, or floating.

[0197] The transistor 4509 is in contact with a semiconductor layer including a channel formation region as an insulating layer. The insulating layer 4541 is the oxide insulating layer 441 shown in Embodiment 5. The same materials and methods as those used in 07 may be used. In this embodiment, the insulating layer 4544 is covered with the insulating layer 4544, which functions as a planarizing insulating layer. The oxide insulating layer 407 described in Embodiment 5 is used as the edge layer 4541 by a sputtering method. A silicon oxide layer is formed.

[0198] In addition, an insulating layer 4544 is formed as a planarization insulating layer over the insulating layer 4541. The insulating layer 44 may be formed of the same material and by the same method as the insulating layer 4021 shown in the seventh embodiment. Okay. Here, acrylic is used as the insulating layer 4544.

[0199] Also, 4511 corresponds to a light-emitting element, and the first electrode layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. Note that the structure of the light-emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 45 12, and the second electrode layer 4513, but it is not limited to the shown structure. The structure of the light-emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light-emitting element 4511 and the like. This can be done.

[0200] The partition wall 4520 is formed using an organic resin layer, an inorganic insulating layer, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and it is preferably formed so that the side wall of the opening becomes an inclined surface formed with a continuous curvature.

[0201] The electroluminescent layer 4512 may be composed of a single layer or may be configured such that a plurality of layers are stacked. Either is fine.

[0202] A protective layer may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4511. As the protective layer, a silicon nitride layer, a silicon oxynitride layer, a DLC layer, etc. can be formed.

[0203] Also, various signals and potentials supplied to the signal line driving circuits 4503a, 4503b, the scanning line driving circuits 4504a, 4504b or the pixel portion 4502 are supplied from the FPCs 4518a, 4518 b.

[0204] The connection terminal electrode 4515 is formed of the same conductive layer as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed of the same conductive layer as the source electrode layer and the drain electrode layer of the transistors 4509 and 4510.

[0205] The connection terminal electrode 4515 is electrically connected to the terminal of the FPC 4518a through the anisotropic conductive layer 4519.

[0206] The second substrate located in the light extraction direction of the light from the light-emitting element 4511 must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

[0207] In addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used as the filler 4507, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler.

[0208] If necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light-emitting surface of the light-emitting element. A reflection preventing film may be provided on the polarizing plate or the circular polarizing plate. For example, an anti-glare treatment that diffuses the reflected light due to the surface unevenness and can reduce the reflection can be performed.

[0209] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured.

[0210] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is.

[0211] (Embodiment 9) An example of electronic paper is shown as one form of a semiconductor device.

[0212] A transistor including a laminated oxide material having a c-axis oriented crystal layer obtained by the method shown in Embodiment 5 may be used for electronic paper that drives electronic ink by using an element electrically connected to a switching element. Electronic paper is also called an electrophoretic display (electrophoretic display), and has advantages such as the same readability as paper, lower power consumption compared to other display devices, and the ability to be thin and lightweight.

[0213] Although various forms of electrophoretic displays are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or solute, and by applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other and only the color of the particles aggregated on one side is displayed. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (including colorless).

[0214] Thus, an electrophoretic display is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region.

[0215] What is obtained by dispersing the above microcapsules in a solvent is called electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also , color display is also possible by using color filters and particles having dyes.

[0216] Also, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, an active matrix substrate obtained by a transistor including a laminated oxide material having a c-axis oriented crystal layer in Embodiment 5 can be used. If a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, an active matrix substrate obtained by a transistor including a laminated oxide material having a c-axis oriented crystal layer in Embodiment 5 can be used. For example, an active matrix substrate obtained by a transistor including a laminated oxide material having a c-axis oriented crystal layer in Embodiment 5 can be used. For example, an active matrix substrate obtained by a transistor including a laminated oxide material having a c-axis oriented crystal layer in Embodiment 5 can be used. For example, an active matrix substrate obtained by a transistor including a laminated oxide material having a c-axis oriented crystal layer in Embodiment 5 can be used.

[0217] Note that the first particles and the second particles in the microcapsules may be made of a material selected from a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof. a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof. a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof.

[0218] FIG. 20 shows an active matrix type electronic paper as an example of a semiconductor device. As the transistor 581 used in the semiconductor device, it can be manufactured in the same manner as the transistor shown in Embodiment 5, and is a highly reliable transistor including a laminated oxide material having a c-axis oriented crystal layer. As the transistor 581 used in the semiconductor device, it can be manufactured in the same manner as the transistor shown in Embodiment 5, and is a highly reliable transistor including a laminated oxide material having a c-axis oriented crystal layer. As the transistor 581 used in the semiconductor device, it can be manufactured in the same manner as the transistor shown in Embodiment 5, and is a highly reliable transistor including a laminated oxide material having a c-axis oriented crystal layer. As the transistor 581 used in the semiconductor device, it can be manufactured in the same manner as the transistor shown in Embodiment 5, and is a highly reliable transistor including a laminated oxide material having a c-axis oriented crystal layer.

[0219] The electronic paper in FIG. 20 is an example of a display device using a twist ball display method. The twist ball display method is an electrode layer that uses spherical particles painted white and black as display elements. The twist ball display method is an electrode layer that uses spherical particles painted white and black as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles caused by the generation of light.

[0220] The transistor 581 is a bottom-gate transistor, and an insulating layer in contact with a semiconductor layer The source electrode layer or the drain electrode layer of the transistor 581 is covered with a first The electrode layer 587 is in contact with the insulating layers 583 and 585 through openings and is electrically connected. Between the first electrode layer 587 and the second electrode layer 588, there are a black area 590a and a white area A spherical particle 589 having a region 590b and including a cavity 594 filled with liquid around it. The spherical particle 589 is surrounded by a filling material such as resin. It is filled with filler material 595 (see FIG. 20).

[0221] The first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is a common potential The conductive particles disposed between the pair of substrates are electrically connected to the wires by using a common connection portion. The second electrode layer 588 and a common potential line can be electrically connected via the insulating layer 586 .

[0222] Also, instead of the twist ball, an electrophoretic element can be used. and a 10μm to 20μm diameter nanoparticle that contains positively charged white nanoparticles and negatively charged black nanoparticles. Microcapsules with a diameter of about 0 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, the microcapsules emit white light. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element applying the principle is an electrophoretic display element, which is generally called electronic paper. Since the electrophoretic display element has a higher reflectance than the liquid crystal display element, it does not require a backlight, has low power consumption, and can recognize the display portion even in a dim place. Also, even when no power is supplied to the display portion, it is possible to hold the image once displayed. Therefore, even when a semiconductor device with a display function (also simply referred to as a display device or a semiconductor device equipped with a display device) is separated from a radio wave transmission source, it is possible to save the displayed image.

[0223] Through the above steps, a highly reliable electronic paper can be manufactured.

[0224] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0225] (Embodiment 10) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include, for example, television devices (also referred to as TVs or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones (also referred to as mobile phones or mobile phone devices), portable game machines, portable information terminals, audio playback devices, and large game machines such as pachinko machines.

[0226] In this embodiment, an example of an electronic device equipped with the display device obtained in any one of Embodiments 7 to 9 will be described with reference to FIGS. 21 and 22.

[0227] FIG. 21(A) is a notebook personal computer manufactured by mounting at least a display device as a component, and includes a main body 3001, a housing 3002, a display unit 3003, a keyboard 3004, etc. The notebook personal computer has the liquid crystal display device shown in Embodiment 7.

[0228] FIG. 21(B) is a personal digital assistant (PDA) manufactured by mounting at least a display device as a component. The main body 3021 is provided with a display unit 3023, an external interface 3025, operation buttons 3024, etc. There is also a stylus 3022 as an accessory for operation. The PDA has the light-emitting display device shown in Embodiment 8.

[0229] FIG. 21(C) is an electronic book manufactured by mounting the electronic paper shown in Embodiment 9 as a component. FIG. 21(C) shows an electronic book 2700. For example, the electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are made into one electronic device by a shaft portion 2711, and can be opened and closed about the shaft portion 2711 as an axis. With such a configuration, it is possible to perform operations similar to those of a paper book.

[0230] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen, or may be configured to display different screens. When configured to display different screens, for example, an article is displayed on the right display unit (display unit 2705 in FIG. 21(C)), and the left ​​​​​​​​​​​​​​An image can be displayed on the display unit (display unit 2707 in FIG. 21(C)).

[0231] Also, FIG. 21(C) shows an example in which the housing 2701 is provided with an operation unit or the like. For example, the housing 2701 is provided with a power supply 2721, operation keys 2723, a speaker 2725, etc. By the operation keys 2723, pages can be sent. Note that the housing may be configured to be provided with a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (terminals connectable to various cables such as earphone terminals, USB terminals, or an AC adapter and a USB cable), a recording medium insertion part, etc. may be provided. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary.

[0232] Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. By wireless means, it is also possible to purchase and download desired book data, etc. from an electronic book server.

[0233] FIG. 21(D) is a mobile phone manufactured by mounting at least a display device as a component, and is composed of two housings, a housing 2800 and a housing 2801. On the housing 2801, there are a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, an external connection terminal 2808, etc. Also, on the housing 2801, there are a solar cell 2810 for charging a portable information terminal, an external memory slot 2811, etc. Also, the antenna is built inside the housing 2801.

[0234] ​​​​​In addition, the display panel 2802 is equipped with a touch panel, and a plurality of operation keys 2805 being displayed in Figure 21(D) are indicated by dotted lines. Note that a booster circuit for boosting the voltage output by the solar cell 2810 to the voltage required for each circuit is also implemented. The direction of the display changes appropriately according to the usage form. Also, since the camera lens 2807 is provided on the same plane as the display panel 2802, a video phone is possible. The speaker 2803 and the microphone 2804 are capable of not only voice calls but also video phones,

[0235] recording, playback, etc. Furthermore, the housing 2800 and the housing 2801 can be slid and changed from the state of being unfolded as shown in Figure 21(D) to an overlapping state, enabling miniaturization suitable for portability.

[0236] The external connection terminal 2808 can be connected to various cables such as an AC adapter and a USB cable, enabling charging and data communication with a personal computer, etc. Also, a recording medium can be inserted into the external memory slot 2811 to support storage and transfer of a larger amount of data.

[0237]

[0238]

[0239] In addition to the above functions, it may also be equipped with an infrared communication function, a television reception function, etc.

[0238] Figure 21(E) shows a digital camera manufactured by implementing at least the display device as a component, which is composed of a main body 3051, a display unit (A) 3057, an eyepiece unit 3053, an operation switch 3054,

[0239] ​FIG. 22 shows a television apparatus 9600. The television apparatus 9600 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display images. Here, a configuration is shown in which the housing 9601 is supported by a stand 9605.

[0240] The television apparatus 9600 can be operated by operation switches provided in the housing 9601 or by a separate remote controller 9610. Channel and volume operations can be performed by operation keys 9609 provided on the remote controller 9610, and the images displayed on the display unit 9603 can be operated. Further, the remote controller 9610 may be configured to include a display unit 9607 for displaying information output from the remote controller 9610.

[0241] Note that the television apparatus 9600 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts, and can be connected to a communication network by wire or wirelessly via the modem, thereby enabling one-way (from sender to receiver) or two-way (between sender and receiver or between receivers) information communication.

[0242] In the display unit 9603, a plurality of transistors shown in Embodiment 5 are arranged as pixel switching elements, and transistors with high mobility shown in Embodiment 5 are arranged as a driving circuit formed on the same insulating substrate as the display unit 9603.

[0243] This embodiment can be freely combined with any one of Embodiments 1 to 9.

Description of Reference Numerals

[0244] ​ 400 Substrate 401 Gate electrode layer 402 Gate insulating layer 403 First oxide semiconductor layer 404 Second oxide semiconductor layer 405a Source electrode layer 405b Drain electrode layer 407 Oxide insulating layer 430 Oxide semiconductor stack 431 Island-shaped oxide semiconductor stack 432 Oxide semiconductor stack 470 Transistor 500 Substrate member 501 First oxide crystal member 502 Oxide semiconductor layer 503a Oxide crystal member 503b Oxide crystal member 504 Layer containing amorphous 520 Substrate member 531 Oxide crystal member 532 Oxide member 533a Oxide crystal member 533b Oxide crystal member 580 Substrate 581 Transistor 583 Insulating layer 585 Insulating layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a Black region 590b White region 594 Cavity 595 Filling material 596 Substrate 1501 Glass substrate 1502 Pixel portion 1503 Gate driver 1504 Gate driver 1505 Analog switch 1506 FPC 1507 FPC 1508 FPC 1509 FPC 1701 Glass Substrate 1702 Pixel Section 1703 Gate Driver 1704 Gate Driver 1705 Source Driver 1706 FPC 1707 FPC 1711 Glass Substrate 1712 Pixel Section 1713 Gate Driver 1714 Gate Driver 1715 Gate Driver 1716 Gate Driver 1717 Source Driver 1718 Source Driver 1719 Source Driver 1720 Source Driver 1721 FPC 1722 FPC 1723 FPC 1724 FPC 2700 E-book 2701 Housing 2703 Housing 2705 Display Section 2707 Display Section 2711 Shaft Section 2721 Power Supply 2723 Operation Key 2725 Speaker 2800 Housing 2801 Housing 2802 Display Panel 2803 Speaker 2804 Microphone 2805 Operation Key 2806 Pointing Device 2807 Camera Lens 2808 External Connection Terminal 2810 Solar Cell 2811 External Memory Slot 3001 Main Body 3002 Housing 3003 Display unit 3004 Keyboard 3021 Main body 3022 Stylus 3023 Display unit 3024 Operation button 3025 External interface 3051 Main body 3053 Eyepiece 3054 Operation switch 3055 Display unit (B) 3056 Battery 3057 Display unit (A) 4001 Substrate 4002 Pixel section 4003 Signal line drive circuit 4004 Scanning line drive circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive layer 4020 Insulating layer 4021 Insulating layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulating layer 4033 Insulating layer 4035 Spacer 4040 Conductive layer 4501 Substrate 4502 Pixel section 4503a Signal line drive circuit 4503b Signal line drive circuit 4504a Scanning line drive circuit 4504b Scanning line drive circuit 4505 Sealing material 4506 Substrate 4507 Filling material 4509 Transistor 4510 Transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4518b FPC 4519 Anisotropic conductive layer 4520 Partition wall 4540 Conductive layer 4541 Insulating layer 4544 Insulating layer 9600 Television apparatus 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote control operation unit

Claims

[Claim 1] An active matrix display device having a plurality of pixels, a plurality of signal lines, and a plurality of scanning lines on an insulating substrate, On the insulating substrate, a field effect mobility of at least 50 cm ２ / Vs or more, a gate driver having the transistor as one component, and a source line driving analog switch; The display device includes an oxide semiconductor layer in the transistor.

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