Integrated circuit device, device, and manufacturing method

Abstract

To provide an integrated circuit device that can achieve appropriate lead-out wiring electrically connecting a pad and a circuit to each other, while arranging the circuit to be overlapped on the pad to achieve a reduction in the area.SOLUTION: An integrated circuit device 20 includes a pad 2 that has a shape having a longitudinal direction and short direction; a circuit 8 that overlaps the pad 2 in plan view and is electrically connected with the pad 2; lead-out wiring 5 that is led out from a longitudinal outer edge EDL of the pad 2 along the short direction DS of the pad 2; and a via group 6 that electrically connect the lead-out wiring 5 and wiring 7 of the circuit 8 to each other and do not overlap the pad 2 in plan view.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an integrated circuit device, a device, a manufacturing method, and the like.

Background Art

[0002] In an integrated circuit device, pads for external connection are provided. For example, Patent Document 1 discloses a method of forming pads provided along the side edge of an integrated circuit device in a rectangular shape having a long side along the vibration direction of ultrasonic waves during wire bonding. In Patent Document 1, a pad shape corresponding to a connection portion of wire bonding having a substantially elliptical shape that is long in the vibration direction of ultrasonic waves in a plan view is provided, thereby realizing miniaturization of the integrated circuit device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in a configuration such as that of Patent Document 1, when a circuit is arranged so as to overlap a pad in a plan view, no method for appropriately drawing out wiring to the circuit has been proposed.

Means for Solving the Problems

[0005] One aspect of the present disclosure relates to an integrated circuit device including a pad having a shape with a longitudinal direction and a lateral direction, a circuit that overlaps the pad in a plan view and is electrically connected to the pad, a lead-out wiring drawn from an outer edge on the longitudinal side of the pad along the lateral direction of the pad, and a via group that electrically connects the lead-out wiring and the wiring of the circuit and does not overlap the pad in the plan view.

[0006] Another aspect of the present disclosure is a method for manufacturing a device including an integrated circuit device and a package in which the integrated circuit device is housed, the method including a manufacturing process of the integrated circuit device and a mounting process of mounting the integrated circuit device on the package. In the manufacturing process, a pad having a shape with a longitudinal direction and a short-side direction, a circuit that overlaps the pad in a plan view and is electrically connected to the pad, a lead wiring drawn from an outer edge on the longitudinal side of the pad along the short-side direction of the pad, and a via group that electrically connects the lead wiring and the wiring of the circuit and does not overlap the pad in the plan view are formed on an active surface of the integrated circuit device. In the mounting process, bumps are formed on the pads of the integrated circuit device, the integrated circuit device is arranged such that the active surface faces a surface of the package, and the terminals provided on the surface of the package and the bumps formed on the pads are connected by ultrasonic bonding with the longitudinal direction of the pads as a vibration direction.

Brief Description of the Drawings

[0007]

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MODE FOR CARRYING OUT THE INVENTION

[0008] Hereinafter, the present embodiment will be described. Note that the present embodiment described below does not unduly limit the content described in the claims. Also, not all of the configurations described in the present embodiment are essential constituent elements.

[0009] 1. Lead wiring of pads FIG. 1 shows a cross-sectional view of the pad region of the integrated circuit device 20 of the present embodiment, and FIG. 2 shows a plan view of the pad region. The integrated circuit device 20 of the present embodiment includes pads 2, lead wirings 5, and via groups 6. As shown in FIG. 2, the pad 2 is a pad having a shape with a longitudinal direction and a lateral direction. For example, when the pad 2 is a quadrilateral, the pad 2 has a rectangular shape with a long side and a short side. Note that the shape of the pad 2 is not limited to a rectangle, and may be, for example, a shape including an ellipse or an oblong, such as a polygon having five or more sides such as a hexagon or an octagon, or a substantially elliptical shape. For example, the corner portion of the pad 2 may be chamfered, whereby stress concentration on the corner portion can be alleviated. Also, the region of the pad 2 is the region exposed on the active surface of the integrated circuit device 20 among the metal layers constituting the pad 2. For example, in FIG. 1, the pad 2 is constituted by a metal layer ALE such as aluminum in the uppermost layer. And among the metal layer ALE, the region of the opening portion exposed from the passivation film 3 which is an oxide film formed so as to cover the metal layer ALE becomes the region of the pad 2.

[0010] In FIGS. 1 and 2, a circuit 8 is provided which overlaps the pad 2 in a plan view and is electrically connected to the pad 2. The circuit 8 is, for example, a functional circuit having a predetermined function. The circuit is composed of, for example, a plurality of circuit elements. The circuit elements are active elements such as transistors and passive elements such as resistors and capacitors. For example, in FIG. 1, the circuit 8 includes an N-type transistor formed in a P-type well PWL and a P-type transistor formed in an N-type well NWL. Note that FIG. 1 schematically shows the arrangement relationship between the pad 2 and the circuit 8. Actually, the layout area of the transistors and the like of the circuit 8 with respect to the layout area of the pad 2 is sufficiently small, and the necessary number of circuit elements such as transistors constituting the circuit 8 are arranged below the pad 2.

[0011] The plan view is a plan view in the direction DR of FIG. 1, for example, a plan view seen from a direction orthogonal to the semiconductor substrate constituting the integrated circuit device 20. As shown in FIG. 2, the circuit 8 is arranged so as to overlap the pad 2 in a plan view. For example, when the direction DR toward the semiconductor substrate is the downward direction, the circuit 8 is arranged below the pad 2. The pad 2 and the circuit 8 are electrically connected via the lead-out wiring 5, the via group 6, and the like. By arranging the circuit 8 so as to overlap the pad 2 in a plan view in this way, a reduction in the layout area of the integrated circuit device 20 can be achieved.

[0012] Also, as shown in FIG. 2, the lead-out wiring 5 is a wiring drawn out from the outer edge EDL on the longitudinal side of the pad 2 along the short-side direction DS of the pad 2. For example, in FIG. 2, the outer edge EDL is the outer edge along the longitudinal direction DL of the pad 2, and the outer edge EDS is the outer edge along the short-side direction DS of the pad 2. When the pad 2 has a rectangular shape, the outer edge EDL on the longitudinal side is the long side of the pad 2, and the longitudinal direction DL is the direction along the long side. Also, the outer edge EDS on the short side is the short side of the pad 2, and the short-side direction DS is the direction along the short side. And as shown in FIG. 1, the lead-out wiring 5 is composed of the metal layer ALE on the same layer as the pad 2. For example, the lead-out wiring 5 is a wiring obtained by extending the metal layer ALE of the pad 2 along the short-side direction DS of the pad 2 and drawing it out.

[0013] The via group 6 electrically connects the lead-out wiring 5 and the wiring 7 of the circuit 8. And the via group 6 is provided so as not to overlap the pad 2 in a plan view. For example, the via group 6 that electrically connects the lead-out wiring 5 and the wiring 7 is not disposed below the pad 2, but is disposed below the lead-out wiring 5 drawn out from the outer edge EDL of the pad 2 in the short-side direction DS. For example, in FIGS. 1 and 2, the integrated circuit device 20 has five metal layers ALA to ALE. The metal layers ALA to ALE are, for example, metal layers of aluminum or an aluminum alloy. Note that the number of metal layers is not limited to five, and may be four or less or six or more. And the via group 6 includes a plurality of vias that connect between these metal layers. The via is also called a via wiring, for example, and is composed of a via hole and a metal plug. For example, the via group 6 includes a via that connects the metal layer ALE and the metal layer ALD, a via that connects the metal layer ALD and the metal layer ALC, a via that connects the metal layer ALC and the metal layer ALB, and the like. These plurality of vias are arranged side by side, for example, along the direction DR below the lead-out wiring 5. The via group 6 including these plurality of vias electrically connects the metal layer ALE constituting the lead-out wiring 5 and the metal layer ALB constituting the wiring 7. And one end of the wiring 7 is connected to the via of the via group 6, and the other end is electrically connected to the circuit 8. For example, the other end of the wiring 7 is connected to a circuit element constituting the circuit 8. For example, the wiring 7 is electrically connected to the drain, source, or gate of a transistor which is a circuit element, or one end of a resistor or capacitor which is a passive element. Although the wiring 7 composed of the metal layer ALB is shown in FIG. 1, the wiring for electrically connecting the via group 6 and the circuit 8 may be a wiring composed of other metal layers such as the metal layers ALA and ALC.

[0014] As described above, in the present embodiment, the circuit 8 is arranged so as to overlap the pad 2 in a plan view. Thereby, since the circuit 8 can be arranged by effectively using the area of the pad 2, miniaturization of the integrated circuit device 20 can be achieved. That is, by arranging the circuit 8 in the area of the pad 2, the integrated circuit device 20 can be miniaturized by the area of the circuit 8 compared to the case where the circuit 8 is arranged outside the area of the pad 2. Further, since the pad 2 has a shape having a longitudinal direction and a short-side direction, even when a force along the longitudinal direction of the pad 2 acts during mounting of the integrated circuit device 20, it is possible to suppress the occurrence of problems such as short circuits and disconnections of wirings. For example, when performing ultrasonic bonding as described later during mounting, by setting the vibration direction of the ultrasonic wave to be along the longitudinal direction of the pad 2, it becomes possible to suppress the occurrence of short circuits and the like of the wiring due to the vibration of the ultrasonic wave. And in the present embodiment, further, the lead wiring 5 is drawn out along the short-side direction DS of the pad 2 from the outer edge EDL on the longitudinal side of the pad 2, and the lead wiring 5 and the wiring 7 of the circuit 8 are electrically connected by the via group 6. By doing so, even when a force along the longitudinal direction of the pad 2 acts during mounting of the integrated circuit device 20, it is possible to suppress the risk of damage to the lead wiring 5 and the via group 6 and the occurrence of short circuits and disconnections. Therefore, it is possible to provide the integrated circuit device 20 that can suppress damage to the lead wiring 5 and the via group 6 for electrically connecting the pad 2 to the circuit 8 arranged so as to overlap the pad 2. That is, it becomes possible to realize an appropriate lead wiring 5 for electrically connecting the pad 2 and the circuit 8 while realizing miniaturization of the integrated circuit device 20 by arranging the circuit 8 so as to overlap the pad 2. As a method of a comparative example of the present embodiment, a method of providing a via directly under the pad 2 and connecting the pad 2 and the circuit 8 through this via is also conceivable. However, if a via is arranged directly under the pad 2, there is a risk of problems such as peeling of the metal layer ALE of the pad 2 and damage to the via. In this regard, in the present embodiment, since the via group 6 is provided at a location that does not overlap the pad 2 in a plan view, such problems can be prevented.

[0015] Also, as shown in FIG. 1, wiring 7 is wiring in metal layer ALB which is a layer below metal layer ALE of pad 2. A part of wiring 7 overlaps with pad 2 in a plan view. By providing such wiring 7, the lead wiring 5 from pad 2 is connected to one end of wiring 7 via via group 6, and the other end of wiring 7 is connected to circuit 8, so that pad 2 can be electrically connected to the circuit elements of circuit 8 arranged to overlap with pad 2. Therefore, circuit 8 electrically connected to pad 2 can be arranged to overlap with pad 2 in a plan view, and miniaturization of integrated circuit device 20 can be realized.

[0016] Also in FIG. 1, wiring 7 is wiring in metal layer ALB arranged with an interval of one layer or more from metal layer ALE of pad 2. For example, instead of metal layer ALD directly below metal layer ALE of pad 2, wiring 7 of circuit 8 is constituted by metal layer ALB arranged with an interval of one layer or more from metal layer ALE of pad 2. Although wiring 7 is constituted by metal layer ALB in FIG. 1, wiring 7 may be constituted by metal layer ALC or metal layer ALA arranged with an interval of one layer or more from metal layer ALE of pad 2. For example, if wiring 7 of circuit 8 is constituted by metal layer ALD directly below metal layer ALE of pad 2, when a load is applied to pad 2 during mounting or the like, wiring 7 may be damaged and problems such as disconnection may occur. In this regard, if wiring 7 of circuit 8 is constituted by metal layer ALB, metal layer ALC or metal layer ALA arranged with an interval of one layer or more from metal layer ALE of pad 2, it is possible to suppress wiring 7 from being damaged and problems from occurring, and reliability and the like can be improved. For example, in the present embodiment, since lead wiring 5 from pad 2 and wiring 7 are electrically connected by a plurality of vias in via group 6, it is possible to constitute wiring 7 of circuit 8 by metal layer ALB, metal layer ALC or metal layer ALA arranged with an interval of one layer or more from metal layer ALE of pad 2.

[0017] Also, as shown in FIG. 2, the lead wire 5 has a shape in which the longitudinal direction DL of the pad 2 is the longitudinal direction. For example, the lead wire 5 has a shape in which the longitudinal direction DL of the pad 2 is the longitudinal direction and the short side direction DS of the pad 2 is the short side direction. For example, in FIG. 2, the longitudinal direction DL of the pad 2 is the vertical direction on the paper surface, the short side direction DS of the pad 2 is the horizontal direction on the paper surface, and the pad 2 has a shape in which the length in the vertical direction is longer than the length in the horizontal direction. And for the lead wire 5 as well, similarly, it has a shape in which the length in the vertical direction is longer than the length in the horizontal direction. In this way, a lead wire 5 having a short length in the horizontal direction can be drawn out from the outer edge EDL on the longitudinal side of the pad 2, and the lead wire 5 can be connected to the wiring 7 of the circuit 8 via the via group 6. And by increasing the length of the lead wire 5 in the vertical direction, it becomes possible to increase the number of vias provided in the region of the lead wire 5, and it is possible to improve the resistance to static electricity and reduce the impedance of the wiring.

[0018] Also, as shown in FIG. 2, a plurality of vias in the via group 6 are arranged along the longitudinal direction of the lead wire 5. For example, in FIG. 2, a plurality of rows of via groups are provided along the longitudinal direction of the lead wire 5, and specifically, three rows of via groups are provided. Note that the number of rows of the via group is not limited to three rows, and may be one row or four or more rows. In this way, by arranging a plurality of vias in the via group 6 along the longitudinal direction of the lead wire 5, it becomes possible to increase the number of via groups 6 for electrically connecting the lead wire 5 and the wiring 7 of the circuit 8. Thereby, it is possible to improve the resistance to static electricity and reduce the impedance of the wiring, and it is possible to improve the reliability of the integrated circuit device 20.

[0019] Also, as shown at A1 and A2 in FIG. 2, the lead wiring 5 has a shape with chamfered corners in a plan view. For example, as shown at A1 and A2, by chamfering the corners of the lead wiring 5, it has a substantially rectangular shape with the longitudinal direction as the long side direction and the lateral direction as the short side direction on the plane of FIG. 2. In FIG. 2, the upper right corner shown at A1 and the lower right corner shown at A2 are chamfered. By forming the lead wiring 5 into a shape with chamfered corners in this way, for example, when static electricity is applied to the pad 2, it is possible to suppress the concentration of electric charges at the corners and the occurrence of destruction due to heat generation or the like. Thereby, the reliability of the integrated circuit device 20 and the like can be improved.

[0020] Also, the pad 2 of the present embodiment is, for example, an input pad PI to which an input signal is input as shown in FIG. 3. And the circuit 8 arranged so as to overlap the input pad PI in a plan view is an I / O circuit 22 to which an input signal is input from the input pad PI. The I / O circuit 22 includes an input buffer circuit or the like that buffers the input signal when the input signal is input, and outputs the buffered input signal to a circuit inside the integrated circuit device 20. In this way, the input signal to the input pad PI can be input to the I / O circuit 22 via the lead wiring 5, the via group 6, and the wiring 7. And the input pad PI has a shape having a longitudinal direction and a short side direction, and the lead wiring 5 is drawn out from the outer edge EDL on the longitudinal side of the input pad PI. Therefore, even when a force along the longitudinal direction of the input pad PI acts during mounting of the integrated circuit device 20 or the like, it is possible to suppress the occurrence of problems such as a short circuit or damage to the lead wiring 5 or the via group 6. Also, since the I / O circuit 22 can be arranged by effectively utilizing the area of the input pad PI, the integrated circuit device 20 can be made smaller in area compared to the case where the I / O circuit 22 is arranged outside the area of the input pad PI. In FIG. 3, an electrostatic protection circuit 21, a power supply stabilization capacitor, etc. are also arranged so as to overlap the input pad PI in a plan view. Thereby, further reduction in the area of the integrated circuit device 20 that effectively utilizes the area of the input pad PI can be realized.

[0021] Also, as shown in FIG. 4 for example, the pad 2 of this embodiment is an output pad PQ that outputs an output signal. And the circuit 8 arranged so as to overlap the output pad PQ in a plan view is an output buffer circuit 52 that outputs an output signal to the output pad PQ. The output buffer circuit 52 buffers, for example, an output signal from a circuit inside the integrated circuit device 20 and outputs it to the output pad PQ. In this way, the output signal from the output buffer circuit 52 can be output from the output pad PQ via the wiring 7, the via group 6, and the lead-out wiring 5. And the output pad PQ has a shape having a longitudinal direction and a short-side direction, and the lead-out wiring 5 is led out from the outer edge EDL on the longitudinal side of the output pad PQ. Therefore, even when a force along the longitudinal direction of the output pad PQ acts during mounting of the integrated circuit device 20 or the like, it is possible to suppress the occurrence of problems such as a short circuit or damage to the lead-out wiring 5 or the via group 6. Also, since the output buffer circuit 52 can be arranged by effectively utilizing the area of the output pad PQ, the integrated circuit device 20 can be made smaller in area. Also, when the output buffer circuit 52 outputs an output signal such as a high-frequency clock signal for example, the output buffer circuit 52 becomes a noise source. In this regard, in FIG. 4, since the output pad PQ is arranged so as to cover the output buffer circuit 52 that becomes a noise source, the metal layer of the output pad PQ becomes a shield layer, and it is possible to suppress the noise source from reaching other circuits of the integrated circuit device 20. Therefore, it is also possible to suppress a performance degradation of the integrated circuit device 20 caused by noise from the output buffer circuit 52.

[0022] Also, as shown in FIG. 5 for example, the pad 2 of this embodiment is a ground pad PGND to which ground is supplied. And the circuit 8 arranged so as to overlap the ground pad PGND in a plan view is a reference voltage generation circuit 62 that generates a reference voltage. The reference voltage generation circuit 62 generates a reference voltage that remains constant even when, for example, the power supply voltage or temperature changes. For example, the reference voltage generation circuit 62 generates a reference voltage for generating at least one of a bias current, a bias voltage, or a regulated power supply voltage. For example, the integrated circuit device 20 has an analog circuit, and the reference voltage generation circuit 62 generates a reference voltage for generating a bias current or a bias voltage of this analog circuit. Also, the integrated circuit device 20 has a regulator, and the regulator generates a regulated power supply voltage with a constant voltage obtained by stepping down the power supply voltage based on the reference voltage generated by the reference voltage generation circuit 62, and supplies the generated regulated power supply voltage to each circuit block of the integrated circuit device 20. With the layout arrangement as shown in FIG. 5, the ground voltage supplied to the ground pad PGND can be supplied to the reference voltage generation circuit 62 via the lead-out wiring 5, the via group 6, and the wiring 7. And the ground pad PGND has a shape having a longitudinal direction and a lateral direction, and since the lead-out wiring 5 is drawn out from the outer edge EDL on the longitudinal side of the ground pad PGND, even when a force along the longitudinal direction of the ground pad PGND acts, it is possible to suppress the occurrence of problems such as a short circuit of the wiring or damage to the lead-out wiring 5 or the like. Also, since the reference voltage generation circuit 62 can be arranged by effectively using the area of the ground pad PGND, the integrated circuit device 20 can be made smaller in area. Also, in FIG. 5, since the ground pad PGND is arranged so as to cover the reference voltage generation circuit 62, the metal layer of the ground pad PGND becomes a shield layer, and noise from other circuits of the integrated circuit device 20 is transmitted, and noise is superimposed on the reference voltage generated by the reference voltage generation circuit 62. It can be suppressed. Therefore, the reference voltage generation circuit 62 can generate a reference voltage with low noise, and it is also possible to suppress a decrease in the performance of the integrated circuit device 20 caused by noise superimposed on the reference voltage.

[0023] Also, in FIG. 6, the integrated circuit device 20 includes, along the short side DS of the pad 2, in addition to the lead wiring 5 drawn from the outer edge EDL on the long side of the pad 2, a second lead wiring 9 drawn from the outer edge EDS on the short side of the pad 2 along the long side DL of the pad 2. And the second lead wiring 9 is formed of the metal layer ALE on the same layer as the pad 2. For example, in the case of a power supply pad to which a power supply voltage is supplied, the power supply voltage supplied to the power supply pad may be supplied to each circuit of the integrated circuit device 20 by a plurality of lead wirings. In such a power supply pad or the like, as shown in FIG. 6, a second lead wiring 9 drawn from the outer edge EDS on the short side of the pad 2 may be provided. In this case, since the lead wiring 5 and the second lead wiring 9 supply the power supply voltage or the like at the same potential to each circuit of the integrated circuit device 20, even if a force or the like acts along the long side direction of the pad, it is considered that the possibility of a problem is small.

[0024] Next, the problems caused by ultrasonic bonding during the mounting of the integrated circuit device 20 will be described. In FIG. 7, bumps BMP are formed on the pad 2 of the integrated circuit device 20. These bumps BMP are, for example, called stud bumps and are used, for example, in flip chip mounting of the integrated circuit device 20. In the case of stud bumps, a ball is formed at the tip of a wire such as a gold wire, and after this ball is pressure-bonded to the upper surface of the pad 2 using heat or ultrasonic vibration or the like, the wire is cut. Thereby, as shown in FIG. 7, bumps BMP such as gold bumps can be formed near the center of the pad 2. Then, the integrated circuit device 20 in which the bumps BMP are formed on the pad 2 in this way is flip-mounted on the surface SF which is the mounting surface of the package 15 as shown in FIG. 14 described later. Specifically, the integrated circuit device 20 is arranged so that the other end of the bump BMP contacts the terminal TM formed on the surface SF of the package 15, and the terminal TM formed of gold or the like and the other end of the bump BMP are joined by ultrasonic vibration.

[0025] However, when performing ultrasonic bonding using such ultrasonic vibrations, as shown in FIG. 8, the bumps BMP formed on the pad 2 may spread in the vibration direction of the ultrasonic waves and protrude from the area of the pad 2. When such a situation occurs, at B1 in FIG. 8, the protruding bumps BMP come into contact with the passivation film 3 in FIG. 1, and cracks are generated. In the metal pad 2 that is softer than the passivation film 3, there is generally no problem even when a force due to ultrasonic vibrations is applied. However, when a force due to ultrasonic vibrations is applied to the hard passivation film 3, cracks are generated. Then, when the metal of the pad 2 contacts other wirings through the cracks, problems such as short circuits occur. In order to prevent the occurrence of such problems, in this embodiment, as shown in B2 of FIG. 8, the pad 2 is shaped such that the direction of the ultrasonic vibration is the longitudinal direction. Specifically, the pad 2 has a rectangular shape, for example, with the direction of the ultrasonic vibration being the long side direction. In this way, even when the shape of the bumps BMP in plan view becomes an elliptical shape due to ultrasonic vibrations, it is possible to suppress the bumps BMP from protruding from the pad 2, and it becomes possible to prevent problems such as short circuits in the wiring due to the occurrence of cracks as described above.

[0026] On the other hand, in the method of arranging the circuit 8 so as to overlap the pad 2, lead wirings 5 and via groups 6 for electrically connecting the pad 2 and the circuit 8 are required. However, if the lead wiring 5 from the pad 2 is drawn out from the outer edge EDS on the short side of the pad 2, stress may be applied to the lead wiring 5 and the via group 6 due to ultrasonic vibrations, and there is a risk of problems such as short circuits and disconnections. Therefore, in this embodiment, the pad 2 is shaped to have a longitudinal direction and a short side direction, and the lead wiring 5 is drawn out from the outer edge EDL on the long side of the pad 2, and a method is adopted in which the lead wiring 5 and the wiring 7 of the circuit 8 are electrically connected by the via group 6. In this way, even when the longitudinal direction of the pad 2 becomes the vibration direction of the ultrasonic vibrations, it is possible to prevent stress from being applied to the lead wiring 5 and the via group 6 due to the stress caused by the ultrasonic vibrations, and problems such as short circuits and disconnections from occurring.

[0027] As described above, in FIGS. 7 and 8, the pad 2 is a pad that is electrically connected to an external terminal by the bump BMP. Also, the bump BMP is ultrasonically bonded to the terminal. And the longitudinal direction DL of the pad 2 is the direction of the ultrasonic vibration of the ultrasonic bonding. In other words, the longitudinal direction DL of the pad 2 is the longitudinal direction of the bump BMP. In this way, as shown in FIG. 8, it becomes possible to suppress the occurrence of problems such as a short circuit due to the bump BMP protruding from the region of the pad 2. Also, since the lead wiring 5 is drawn out from the outer edge EDL on the longitudinal side of the pad 2, it is possible to suppress the stress caused by the ultrasonic vibration of the ultrasonic bonding from being applied to the lead wiring 5 and the via group 6, and to prevent the occurrence of problems such as a short circuit or a disconnection.

[0028] In the above, the case where problems such as a short circuit occur due to the ultrasonic vibration in the stud bump has been described, but the present embodiment is not limited to this. For example, ultrasonic vibration may be used in wire bonding, and in this case as well, the method of drawing out the lead wiring 5 from the outer edge EDL on the longitudinal side of the pad 2 with the longitudinal direction DL of the pad 2 being the direction of the ultrasonic vibration is effective. Also, the bump BMP may be a bump other than the stud bump, and even when stress is applied along a predetermined direction by some method other than ultrasonic bonding, the method of setting the longitudinal direction of the pad 2 to the predetermined direction and drawing out the lead wiring 5 from the outer edge EDL on the longitudinal side of the pad 2 is effective. Note that the phenomenon of the bump BMP protruding from the region of the pad 2 can also occur by forming the bump BMP on the pad 2 by ultrasonic bonding.

[0029] Also, the structure of the pad 2 is not limited to the structure shown in FIG. 1, and various structures can be adopted. FIG. 9 is a cross-sectional view showing another structural example of the pad 2. In FIG. 9, conductive layers 92, 93, and 94 are formed on the pad metal 91 by, for example, plating or the like. The conductive layer 92 is formed of a material having good bonding properties with the pad metal 91 formed of aluminum or an aluminum alloy, and is formed of, for example, nickel or a nickel alloy. The conductive layer 92 has a thickness of, for example, 2 μm to 10 μm. By increasing the thickness of the conductive layer 92 in this way, even when a large load is applied when bonding a bump or a bonding wire to the pad 2, it becomes difficult for this load to be transmitted below the pad 2. Therefore, it is possible to prevent a situation in which a defect occurs in the circuit 8 provided below the pad 2 due to the load applied when bonding a bump or a bonding wire. The conductive layer 93 is interposed between the conductive layer 92 and the conductive layer 94, functions as a barrier layer that enhances the adhesion between the conductive layers 92 and 94 and prevents the conductive layer 92 from diffusing into the conductive layer 94. The conductive layer 93 is formed of a material having good adhesion to both the conductive layer 92 and the conductive layer 94, and is formed of, for example, palladium or a palladium alloy. Note that the conductive layer 93 may be provided as necessary, and can be omitted, for example, when the adhesion between the conductive layer 92 and the conductive layer 94 is good. The conductive layer 94 functions as a connection layer with a bump or a bonding wire. The conductive layer 94 is formed of a material having a low contact resistance with a bump or a bonding wire, and is formed of, for example, gold or a gold alloy. By using the pad 2 having the structure as shown in FIG. 9, it is possible to protect the circuit 8 under the pad against the load during mounting when bonding a bump or a bonding wire to the pad 2, and to bond the bump or the bonding wire with a low contact resistance, thereby facilitating mounting and improving reliability.

[0030] 2. Integrated Circuit Device Next, a specific example of the integrated circuit device 20 of the present embodiment will be described. FIG. 10 is a diagram showing a configuration example of the integrated circuit device 20 of the present embodiment. Note that the integrated circuit device 20 is not limited to the configuration of FIG. 10, and various modifications such as omitting some of its components or adding other components are possible. In the following, the case where the device of the present embodiment in which the integrated circuit device 20 is incorporated is the oscillator 4 will be mainly taken as an example for description, but the device of the present embodiment is not limited to the oscillator 4.

[0031] The integrated circuit device 20 in FIG. 10 includes an oscillation circuit 30. The integrated circuit device 20 can also include an output circuit 50, a power supply circuit 60, a logic circuit 70, a temperature compensation circuit 80, a temperature sensor circuit 90, a power supply pad PVDD, a ground pad PGND, a clock pad PCK, an output enable pad POE, pads PX1 and PX2 for connecting a resonator. An example of the device of the present embodiment, the oscillator 4, includes a resonator 10 and the integrated circuit device 20. The resonator 10 is electrically connected to the integrated circuit device 20. For example, the resonator 10 and the integrated circuit device 20 are electrically connected using internal wiring, bonding wires, or metal bumps inside a package that houses the resonator 10 and the integrated circuit device 20.

[0032] The vibrator 10 is an element that generates mechanical vibrations by an electrical signal. The vibrator 10 can be realized by a vibrating piece such as a crystal vibrating piece. For example, the vibrator 10 can be realized by a crystal vibrating piece that undergoes thickness-shear vibration with a cut angle such as AT cut or SC cut, a tuning fork type crystal vibrating piece, or a double tuning fork type crystal vibrating piece. For example, the vibrator 10 may be a vibrator built in a temperature compensated crystal oscillator (TCXO) without a thermostatic chamber, or may be a vibrator built in a thermostatic chamber type crystal oscillator (OCXO) with a thermostatic chamber. Alternatively, the vibrator 10 may be a vibrator built in an oscillator of SPXO (Simple Packaged Crystal Oscillator). Note that the vibrator 10 of the present embodiment can also be realized by various vibrating pieces such as a vibrating piece other than a thickness-shear vibration type, a tuning fork type, or a double tuning fork type, or a piezoelectric vibrating piece formed of a material other than crystal. For example, as the vibrator 10, a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) vibrator as a silicon vibrator formed using a silicon substrate, or the like may be employed.

[0033] The integrated circuit device 20 is an IC (Integrated Circuit) manufactured by, for example, a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate.

[0034] The oscillation circuit 30 is a circuit that oscillates the vibrator 10. For example, the oscillation circuit 30 is electrically connected to the pads PX1 and PX2, and generates an oscillation signal OSC by oscillating the vibrator 10. The pad PX1 is a first vibrator connection pad, and the pad PX2 is a second vibrator connection pad. For example, the oscillation circuit 30 can be realized by a driving circuit for oscillation provided between the pad PX1 and the pad PX2 and active elements such as capacitors and resistors. The driving circuit can be realized by, for example, a CMOS inverter circuit or a bipolar transistor. The driving circuit is the core circuit of the oscillation circuit 30, and the driving circuit oscillates the vibrator 10 by voltage-driving or current-driving the vibrator 10. As the oscillation circuit 30, various types of oscillation circuits such as an inverter type, a Pierce type, a Colpitts type, or a Hartley type can be used. Further, a variable capacitance circuit is provided in the oscillation circuit 30, and the oscillation frequency can be adjusted by adjusting the capacitance of this variable capacitance circuit. The variable capacitance circuit can be realized by a variable capacitance element such as a varactor, for example. For example, the variable capacitance circuit can be realized by a variable capacitance element whose capacitance is controlled based on a temperature compensation voltage. Alternatively, the variable capacitance circuit may be realized by a capacitor array and a switch array connected to the capacitor array. Also, the connection in this embodiment is an electrical connection. An electrical connection means that electrical signals are communicably connected, and it is a connection through which information can be transmitted by electrical signals. The electrical connection may be a connection via passive elements or the like.

[0035] The output circuit 50 outputs a clock signal CKQ based on the oscillation signal OSC. The output circuit 50 includes an output buffer circuit 52. The output buffer circuit 52 outputs the signal obtained by buffering the oscillation signal OSC as the clock signal CKQ to the clock pad PCK. Then, this clock signal CKQ is output to the outside via the external terminal TCK of the oscillator 4. For example, the output circuit 50 outputs the clock signal CKQ in a single-ended CMOS signal format. Note that the output circuit 50 may output the clock signal CKQ in a signal format other than CMOS. For example, the output circuit 50 may output a differential clock signal to the outside in a signal format such as LVDS (Low Voltage Differential Signaling), PECL (Positive Emitter Coupled Logic), HCSL (High Speed Current Steering Logic), or differential CMOS (Complementary MOS).

[0036] The power supply circuit 60 is supplied with the power supply voltage VDD from the power supply pad PVDD and the ground voltage from the ground pad PGND, and supplies various power supply voltages for the internal circuits of the integrated circuit device 20 to the internal circuits. For example, the power supply circuit 60 supplies a regulated power supply voltage based on the power supply voltage VDD to the oscillation circuit 30 and the like. The power supply circuit 60 includes a reference voltage generation circuit 62 and a regulator 64. The reference voltage generation circuit 62 generates and outputs a reference voltage. The reference voltage generation circuit 62 can be realized by, for example, a bandgap reference circuit, a circuit using the gate work function difference, or a circuit using the threshold voltage difference by changing the channel impurity concentration. The regulator 64 is supplied with the power supply voltage VDD and generates various regulated power supply voltages. For example, the regulator 64 generates a regulated power supply voltage with a constant voltage obtained by stepping down the power supply voltage VDD based on the reference voltage generated by the reference voltage generation circuit 62, and supplies the generated regulated power supply voltage to each circuit block of the integrated circuit device 20.

[0037] The logic circuit 70 is a control circuit that performs various control processes. For example, the logic circuit 70 controls the overall operation of the integrated circuit device 20 or controls the operation sequence of the integrated circuit device 20. For example, the logic circuit 70 controls each circuit block of the integrated circuit device 20, such as the oscillation circuit 30, the output circuit 50, the power supply circuit 60, or the temperature compensation circuit 80. The logic circuit 70 can be realized by a circuit of an ASIC (Application Specific Integrated Circuit) with automatic placement and wiring, such as a gate array.

[0038] The temperature compensation circuit 80 performs temperature compensation on the oscillation signal OSC of the oscillation circuit 30. The temperature compensation of the oscillation signal OSC is the temperature compensation of the oscillation frequency of the oscillation circuit 30. Specifically, the temperature compensation circuit 80 performs temperature compensation based on the temperature detection information from the temperature sensor circuit 90. For example, the temperature compensation circuit 80 generates a temperature compensation voltage VCP based on the temperature detection voltage VT from the temperature sensor circuit 90, and outputs the generated temperature compensation voltage VCP to the oscillation circuit 30 to perform temperature compensation on the oscillation signal OSC of the oscillation circuit 30. For example, the temperature compensation circuit 80 performs temperature compensation by outputting a temperature compensation voltage VCP that becomes the capacitance control voltage of the variable capacitance circuit included in the oscillation circuit 30. In this case, the variable capacitance circuit of the oscillation circuit 30 is realized by a variable capacitance element such as a varactor. Temperature compensation is a process of suppressing and compensating for fluctuations in the oscillation frequency due to temperature variations. For example, the temperature compensation circuit 80 performs analog temperature compensation by polynomial approximation. For example, when the temperature compensation voltage for compensating the frequency-temperature characteristics of the vibrator 10 is approximated by a polynomial, the temperature compensation circuit 80 performs analog temperature compensation based on the coefficient information of the polynomial. Note that the temperature compensation circuit 80 may perform digital temperature compensation.

[0039] The temperature sensor circuit 90 is a sensor circuit that detects temperature. Specifically, the temperature sensor circuit 90 outputs a temperature-dependent voltage that changes according to the ambient temperature as the temperature detection voltage VT. For example, the temperature sensor circuit 90 generates the temperature detection voltage VT using a circuit element with temperature dependence. Specifically, the temperature sensor circuit 90 outputs a temperature detection voltage VT whose voltage value changes depending on temperature by using the temperature dependence of the forward voltage of the PN junction. As the forward voltage of the PN junction, for example, the base-emitter voltage of a bipolar transistor can be used. When performing digital temperature compensation processing, the temperature sensor circuit 90 measures the temperature such as the ambient temperature and outputs the result as temperature detection data.

[0040] The integrated circuit device 20 also includes a power supply pad PVDD, a ground pad PGND, a clock pad PCK, an output enable pad POE, and pads PX1 and PX2 for connecting a resonator. These pads are, for example, terminals of the integrated circuit device 20 which is a semiconductor chip.

[0041] The power supply pad PVDD is a pad to which the power supply voltage VDD is supplied. For example, the power supply voltage VDD from an external power supply device is supplied to the power supply pad PVDD. The ground pad PGND is a terminal to which the ground voltage GND is supplied. GND can also be called VSS, and the ground voltage is, for example, the ground potential. In this embodiment, the ground is described as GND as appropriate. The clock pad PCK is a pad from which the clock signal CKQ is output. For example, the clock signal CKQ based on the oscillation signal OSC in the oscillation circuit 30 is output externally from the clock pad PCK. The output enable pad POE is a pad for controlling the output enable of the clock signal CKQ. Specifically, the output enable control of the clock signal CKQ is performed based on the output enable signal OE input via the output enable pad POE. For example, the logic circuit 70 receives the output enable signal OE from the output enable pad POE and performs the output enable control of the clock signal CKQ in the output circuit 50.

[0042] The power supply pad PVDD, the ground pad PGND, the clock pad PCK, and the output enable pad POE are electrically connected to the external terminals TVDD, TGND, TCK, and TOE for external connection of the oscillator 4, respectively. For example, they are electrically connected using internal wiring of the package, bonding wires, metal bumps, or the like. Then, the external terminals TVDD, TGND, TCK, and TOE of the oscillator 4 are electrically connected to an external device. Also, the pads PX1 and PX2 are pads for connecting the vibrator 10. For example, the pad PX1 is electrically connected to one end of the vibrator 10, and the pad PX2 is electrically connected to the other end of the vibrator 10. For example, using internal wiring of the package that houses the vibrator 10 and the integrated circuit device 20, bonding wires, metal bumps, or the like, the vibrator 10 and the pads PX1 and PX2 of the integrated circuit device 20 are electrically connected.

[0043] Fig. 11 shows a configuration example of the reference voltage generation circuit 62. The reference voltage generation circuit 62 in Fig. 11 includes an N-type transistor TD1, resistors RD1, RD2, RD3, bipolar transistors BP1, and BP2 provided between the VDD node and the GND node. The reference voltage generation circuit 62 also includes P-type transistors TD2 and TD3 to which the bias voltage VB is input to the gate, and a bipolar transistor BP3 provided between the drain node of the transistor TD2 and the GND node. The reference voltage generation circuit 62 is a bandgap reference circuit that generates and outputs a reference voltage VREF based on a bandgap voltage. For example, let the base-emitter voltages of the PNP-type bipolar transistors BP1 and BP2 be VBE1 and VBE2, and ΔVBE = VBE1 - VBE2. The reference voltage generation circuit 62 outputs a reference voltage VREF such that, for example, VREF = K × ΔVBE + VBE2. K is set by the resistance values of the resistors RD1 and RD2. For example, since VBE2 has a negative temperature characteristic and ΔVBE has a positive temperature characteristic, by adjusting the resistance values of the resistors RD1 and RD2, a reference voltage VREF with a constant voltage independent of temperature can be generated. And the generated reference voltage VREF becomes a constant voltage with respect to the ground voltage.

[0044] Fig. 12 shows another configuration example of the reference voltage generation circuit 62. The reference voltage generation circuit 62 in Fig. 12 is also a bandgap reference circuit, and includes N-type transistors TE1 and TE2, P-type transistors TE3, TE4, and TE5, resistors RE1 and RE2, and diodes DI1, DI2, and DI3 having PN junctions. Since the N-type transistors TE1 and TE2 form a current mirror circuit, and the P-type transistors TE3, TE4, and TE5 also form a current mirror circuit, the currents flowing through these transistors are almost equal. Also, the source voltages of the N-type transistors TE1 and TE2 are almost equal. Also, the number of parallel connections of the PN junctions in the diode DI2 is formed to be M times the number of parallel connections of the PN junctions in the diode DI1. Therefore, when the saturation current of the diode DI1 is Is, the saturation current of the diode DI2 is M×Is. Here, assuming the current flowing through the transistors TE3, TE4, and TE5 is I, the voltages across both ends of the diodes DI1, DI2, and DI3 are Vd1, Vd2, and Vd3 respectively, and the resistance values of the resistors RE1 and RE2 are R1 and R2, the reference voltage VREF generated by the reference voltage generation circuit 62 is expressed as in the following formula (1).

[0045] VREF = I·R2 + Vd3 =(R2 / R1)·(kT / q)·In(M) + Vd3 (1)

[0046] Here, k is the Boltzmann constant, T is the absolute temperature, and q is the charge of an electron. Differentiating the above formula (1) with respect to the absolute temperature T results in the following formula (2).

[0047] dVREF / dT=(R2 / R1)·(k / q)·In(M) + Vd3 / dT (2)

[0048] In the above formula (2), the term Vd3 / dT has a negative temperature characteristic. Correspondingly, by adjusting the value of (R2 / R1)·(k / q)·In(M) to a positive value, the value of the above formula (2) can be made zero, and a reference voltage VREF with temperature dependence canceled can be generated. Note that the reference voltage generation circuit 62 is not limited to the configurations shown in FIGS. 11 and 12. For example, circuits with various configurations such as a circuit that generates the reference voltage VREF using the work function difference voltage of transistors can be used.

[0049] In the above, the device of this embodiment is the oscillator 4, and a configuration example of the integrated circuit device 20 incorporated in this oscillator 4 has been described. However, this embodiment is not limited thereto. For example, the device of this embodiment may be a sensor device such as a gyro sensor or an acceleration sensor, a display device that displays an image on a display panel, a communication device that communicates according to a predetermined communication standard, a drive device that drives a predetermined mechanism of a printer, or a power supply device that supplies and controls power. And the integrated circuit device 20 of this embodiment is not limited to being incorporated in the oscillator 4, and may be an IC (Integrated Circuit) incorporated in the above-described sensor device, display device, communication device, or power supply device. For example, when the device is a gyro sensor, the integrated circuit device 20 can include a drive circuit that drives the vibrator of the gyro sensor and a detection circuit that detects a sensor signal from the vibrator. When the device is an acceleration sensor, the integrated circuit device 20 can include a drive circuit and a detection circuit for an acceleration sensor element realized by (MEMS Micro Electro Mechanical Systems) or the like. When the sensor is a display device, the integrated circuit device 20 can include a drive circuit for the display panel and a logic circuit that processes display data. When the sensor is a communication device, the integrated circuit device 20 can include a physical layer circuit, a link layer circuit, and a logic circuit for communication. Thus, circuits with various configurations can be adopted as the integrated circuit device 20.

[0050] 3. Layout Arrangement FIG. 13 shows an example of the layout arrangement of the integrated circuit device 20 of FIG. 10. The outer shape of the integrated circuit device 20 includes a side SD1 and a side SD2 facing the side SD1. The side SD1 is the first side, the side SD2 is the second side, and the side SD2 is the opposite side of the side SD1. The outer shape of the integrated circuit device 20 also includes a side SD3 and a side SD4 that intersect the side SD1 and the side SD2. The side SD3 is the third side, the side SD4 is the fourth side, and the side SD4 is the opposite side of the side SD3. The outer shape of the integrated circuit device 20 is the outer shape of, for example, a rectangular semiconductor chip that is the integrated circuit device 20. For example, the sides SD1, SD2, SD3, and SD4 are the sides of the substrate of the semiconductor chip. The semiconductor chip is also called a silicon die. Here, the direction from the side SD1 to the side SD2 is defined as DR1, and the direction from the side SD3 to the side SD4 is defined as DR2. Also, the opposite direction of the direction DR1 is defined as the direction DR3, and the opposite direction of the direction DR2 is defined as the direction DR4. The directions DR1, DR2, DR3, and DR4 are the first direction, the second direction, the third direction, and the fourth direction, respectively.

[0051] As shown in FIG. 13, the integrated circuit device 20 is provided with a ground pad PGND, a power supply pad PVDD, a clock pad PCK, and an output enable pad POE. The power supply pad PVDD and the clock pad PCK are arranged along the side SD1. The clock pad PCK is arranged, for example, at the first corner where the side SD1 and the side SD4 intersect. The output enable pad POE and the ground pad PGND are arranged along the side SD2. The ground pad PGND is arranged, for example, at the second corner where the side SD2 and the side SD4 intersect. The temperature sensor circuit 90 is arranged, for example, at the third corner where the side SD2 and the side SD3 intersect. Note that the temperature sensor circuit 90 may be arranged so as to overlap the output enable pad POE in a plan view, for example.

[0052] Here, the output enable pad POE corresponds to the input pad PI in FIG. 3, and the clock pad PCK corresponds to the output pad PQ in FIG. 4. Also, the ground pad PGND is the ground pad PGND in FIG. 5. The output enable pad POE, clock pad PCK, ground pad PGND, and power supply pad PVDD arranged in the integrated circuit device 20 are pads having a shape with a longitudinal direction and a lateral direction as described in FIG. 1 and the like, and specifically, they are rectangular pads. For example, these pads have the direction DR1 as the longitudinal direction and the direction DR2 as the lateral direction. That is, the integrated circuit device 20 includes a plurality of pads having the direction DR1 as the longitudinal direction and the direction DR2 as the lateral direction. And the direction DR1 is, for example, the vibration direction of the ultrasonic wave described in FIG. 8. In other words, the integrated circuit device 20 includes a pad and a second pad as a plurality of pads, and the pad and the second pad each have a shape with a longitudinal direction and a lateral direction. And the longitudinal direction of the pad and the longitudinal direction of the second pad are the same direction DR1, and the direction DR1 is the vibration direction of the ultrasonic wave.

[0053] Also, the integrated circuit device 20 is provided with pads PX1 and PX2 for connecting the vibrator. The pads PX1 and PX2 for connecting the vibrator are arranged along the side SD3. For example, an oscillation circuit 30 is arranged along the side SD3, and the pads PX1 and PX2 for connecting the vibrator are arranged in the region of this oscillation circuit 30. Also, the output circuit 50 is arranged along the side SD1, and the power supply circuit 60 is arranged along the side SD4. And the logic circuit 70 is arranged between the oscillation circuit 30 and the power supply circuit 60. Also, the temperature compensation circuit 80 is arranged between the oscillation circuit 30 and the output circuit 50, and the logic circuit 70 is arranged between the temperature compensation circuit 80 and the side SD2.

[0054] In FIG. 13, the reference voltage generation circuit 62 is arranged so as to overlap the ground pad PGND in a plan view. That is, as described in FIG. 5, the reference voltage generation circuit 62 is arranged below the ground pad PGND. By doing so, due to the shielding effect of the ground pad PGND, the transmission of high-frequency noise to the reference voltage generation circuit 62 is suppressed, and it is possible to prevent the potential fluctuation from occurring in the reference voltage generated by the reference voltage generation circuit 62 and the accuracy of the clock frequency from being reduced. Further, since the reference voltage generation circuit 62 can be arranged by effectively using the arrangement region of the ground pad PGND, the reduction in the area of the integrated circuit device 20 can be realized. Among the power supply circuits 60, the circuits other than the reference voltage generation circuit 62 are arranged along, for example, the side SD4 without overlapping the ground pad PGND in a plan view.

[0055] Also in FIG. 13, the output buffer circuit 52 is arranged so as to overlap the clock pad PCK in a plan view. That is, as described in FIG. 4, the output buffer circuit 52 is arranged below the clock pad PCK. Among the output circuits 50, the circuits other than the output buffer circuit 52 are arranged along, for example, the side SD1 without overlapping the clock pad PCK in a plan view.

[0056] By arranging the clock pad PCK and the output buffer circuit 52 to overlap in a plan view in this way, a clock signal CKQ from the output buffer circuit 52 can be output to the clock pad PCK arranged directly above it through a short-path clock wiring route. As a result, the impedance of the clock wiring can be minimized, and potential fluctuations caused by the impedance can be suppressed. Since the output buffer circuit 52 needs to drive a large external load, it has a high driving ability. For this reason, if the impedance of the clock wiring is high, its potential fluctuation also becomes large, and the signal quality of the clock signal CKQ deteriorates. In this regard, if the clock pad PCK and the output buffer circuit 52 are arranged to overlap in a plan view, the route of the clock wiring connecting the output buffer circuit 52 and the clock pad PCK can be made a short-path route, and the impedance of the clock wiring can be minimized. Therefore, deterioration of the signal quality of the clock signal CKQ can be suppressed. Also, since the output buffer circuit 52 has a high driving ability so that it can drive an external load, the generated high-frequency noise is large, and the output buffer circuit 52 and the clock pad PCK to which the clock signal CKQ is output become high-frequency noise sources. In this regard, if the clock pad PCK and the output buffer circuit 52 are arranged to overlap in a plan view, such high-frequency noise sources can be grouped and arranged in one place. As a result, it becomes possible to easily implement measures such as layout arrangements to reduce the adverse effects of noise from this high-frequency noise source.

[0057] As shown in FIG. 13, the outer shape of the integrated circuit device 20 includes a side SD1 and a side SD2 facing the side SD1. On the side SD1, an output buffer circuit 52 and a clock pad PCK are arranged, and on the side SD2, a reference voltage generation circuit 62 and a ground pad PGND are arranged. The side SD1 is the first side, and the side SD2 is the second side. For example, the output buffer circuit 52 and the clock pad PCK are arranged closer to the side SD1 than to the side SD2. Also, the reference voltage generation circuit 62 and the ground pad PGND are arranged closer to the side SD2 than to the side SD1. For example, the output buffer circuit 52 and the clock pad PCK are arranged in a first region between the side SD1 and the center line between the side SD1 and the side SD2, and the reference voltage generation circuit 62 and the ground pad PGND are arranged in a second region between the side SD2 and the center line between the side SD1 and the side SD2. In this way, the output buffer circuit 52 and the clock pad PCK, which are high-frequency noise sources, are arranged on the side SD1 side, while the reference voltage generation circuit 62 and the ground pad PGND, which need to avoid high-frequency noise, are arranged on the side SD2 side. As a result, it becomes possible to increase the distance between the output buffer circuit 52 and the clock pad PCK, which are high-frequency noise sources, and the reference voltage generation circuit 62 and the ground pad PGND. Therefore, it is possible to suppress the transmission of high-frequency noise from the output buffer circuit 52 and the clock pad PCK to the reference voltage generation circuit 62 and the ground pad PGND, and prevent deterioration of the accuracy of the clock frequency caused by high-frequency noise.

[0058] In addition, the outer shape of the integrated circuit device 20 includes a side SD3 which is a third side intersecting with sides SD1 and SD2, and the oscillation circuit 30 is provided on the side of SD3. For example, the oscillation circuit 30 is provided along the side SD3. Specifically, the oscillation circuit 30 is arranged such that, for example, the long side of the oscillation circuit 30 is along the side SD3. By arranging the oscillation circuit 30 on the side of SD3 in this way, the distance between the output buffer circuit 52 etc. arranged on the side of SD1 and the oscillation circuit 30 can be increased, and the situation where the high-frequency noise of the output buffer circuit 52 is superimposed on the oscillation signal OSC and the oscillation characteristics deteriorate can be prevented. Also, by arranging the oscillation circuit 30 on the side of SD3, the distance between the reference voltage generation circuit 62 etc. arranged on the side of SD2 and the oscillation circuit 30 can be increased, and the situation where the oscillation noise from the oscillation circuit 30 is superimposed on the reference voltage etc. of the reference voltage generation circuit 62 and the accuracy of the clock frequency decreases can be prevented.

[0059] In addition, the integrated circuit device 20 includes a temperature compensation circuit 80 for performing temperature compensation of the oscillation frequency of the oscillation signal OSC. And as shown in FIG. 13, the temperature compensation circuit 80 is provided between the oscillation circuit 30 and the clock pad PCK. For example, the temperature compensation circuit 80 is provided on the side of the direction DR2 of the oscillation circuit 30, and the clock pad PCK is provided on the side of the direction DR2 of the temperature compensation circuit 80. By providing the temperature compensation circuit 80 between the oscillation circuit 30 and the clock pad PCK in this way, the region between the oscillation circuit 30 and the clock pad PCK can be effectively utilized, and the temperature compensation circuit 80 can be arranged, enabling an efficient layout arrangement. Also, the distance between the clock pad PCK which is a noise source and the oscillation circuit 30 can be increased, and the transmission of noise from the clock pad PCK to the oscillation circuit 30 can be suppressed. Also, the temperature compensation circuit 80 can be arranged in the vicinity of the oscillation circuit 30, and the temperature compensation voltage VCP from the temperature compensation circuit 80 can be input to the oscillation circuit 30 through a short-path signal path, enabling the temperature compensation of the oscillation frequency.

[0060] 4. Oscillator Fig. 14 shows a structural example of an oscillator 4 which is an example of the device of this embodiment. The oscillator 4 includes a vibrator 10, an integrated circuit device 20, and a package 15 that houses the vibrator 10 and the integrated circuit device 20. The package 15 is formed of, for example, ceramic or the like, has an accommodation space inside, and the vibrator 10 and the integrated circuit device 20 are accommodated in this accommodation space. The accommodation space is hermetically sealed and is preferably in a depressurized state close to a vacuum state. The package 15 can preferably protect the vibrator 10 and the integrated circuit device 20 from impacts, dust, heat, moisture, etc.

[0061] The package 15 has a base 16 and a lid 17. Specifically, the package 15 is composed of a base 16 that supports the vibrator 10 and the integrated circuit device 20, and a lid 17 joined to the upper surface of the base 16 so as to form an accommodation space between the lid 17 and the base 16. The vibrator 10 is supported via terminal electrodes on a stepped portion provided inside the base 16. The integrated circuit device 20 is disposed on a surface SF which is the inner bottom surface of the base 16. Specifically, the integrated circuit device 20 is disposed such that the active surface faces the inner bottom surface of the base 16. The active surface is the surface on which circuit elements of the integrated circuit device 20 are formed. Bumps BMP are formed on pads 2 which are terminals of the integrated circuit device 20. The integrated circuit device 20 is supported on the surface SF of the base 16 via conductive bumps BMP. The conductive bumps BMP are metal bumps such as gold bumps, for example. One end of the bump BMP is connected to the pad 2 of the integrated circuit device 20, and the other end of the bump BMP is connected to a terminal TM provided on the surface SF which is the mounting surface of the integrated circuit device 20. Thereby, the pad 2 of the integrated circuit device 20 is electrically connected to external terminals 18, 19 which are external connection terminals of the oscillator 4, and to the vibrator 10 via the bumps BMP, terminals TM, and internal wiring. The external terminals 18, 19 are formed on the outer bottom surface of the package 15. The external terminals 18, 19 are connected to an external device via external wiring. The external wiring is, for example, wiring formed on a circuit board on which an external device is mounted. Thereby, the integrated circuit device 20 can output a clock signal or the like to the external device.

[0062] When the integrated circuit device 20 is flip-mounted on the surface SF of the package 15 in FIG. 14, the ultrasonic bonding described in FIG. 8 is used. Specifically, ultrasonic bonding is used when connecting the other end of the bump BMP, one end of which is connected to the pad 2 of the integrated circuit device 20, to the terminal TM on the surface SF of the package 15. In this case, in the present embodiment, the pad 2 in which the direction of ultrasonic vibration in ultrasonic bonding is in the longitudinal direction DL is arranged in the integrated circuit device 20. This can suppress the occurrence of problems such as wiring short circuits caused by ultrasonic vibration. Also, along the short side direction DS of the pad 2, the lead wiring 5 is drawn out from the outer edge EDL on the longitudinal side of the pad 2, and the lead wiring 5 is electrically connected to the wiring 7 of the circuit 8 below the pad 2 via the via group 6. This can suppress the occurrence of problems caused by stress applied to the lead wiring 5 and the via group 6 due to ultrasonic vibration or the like.

[0063] As described above, the device such as the oscillator 4 of the present embodiment includes the integrated circuit device 20, the package 15 in which the integrated circuit device 20 is housed, the terminal TM provided on the surface SF of the package 15, and the bump BMP that electrically connects the terminal TM and the pad 2 of the integrated circuit device 20. In this way, the pad 2 of the integrated circuit device 20 and the terminal TM provided on the surface SF of the package 15 can be electrically connected via the bump BMP, and it becomes possible to output a signal from the integrated circuit device 20 to the terminal TM or input a signal from the terminal TM to the integrated circuit device 20. And even when the integrated circuit device 20 is mounted on the surface SF of the package 15 in this way, by making the pad 2 have a shape with a longitudinal direction and drawing out the lead wiring 5 of the pad 2 from the outer edge EDL on the longitudinal side, the occurrence of various problems described above can be suppressed.

[0064] For example, as described with reference to FIG. 8, the bump BMP is connected to the terminal TM by ultrasonic bonding, and the longitudinal direction of the pad 2 is the direction of ultrasonic vibration in ultrasonic bonding. In this way, even when stress of ultrasonic vibration in ultrasonic bonding is applied, by forming the pad 2 into a shape having a longitudinal direction and pulling out the lead wiring 5 of the pad 2 from the outer edge EDL on the longitudinal side, it becomes possible to suppress the occurrence of problems caused by ultrasonic vibration.

[0065] Further, the device of the present embodiment includes a vibrator 10 housed in a package 15 as shown in FIG. 14, and as shown in FIG. 10, the integrated circuit device 20 includes an oscillation circuit 30 that vibrates the vibrator 10 to generate an oscillation signal OSC. Thereby, as the device of the present embodiment, an oscillator 4 as described with reference to FIGS. 10 and 14 can be realized. Then, by forming the pad 2 of the integrated circuit device 20 incorporated in the oscillator 4 into a shape having a longitudinal direction and pulling out the lead wiring 5 of the pad 2 from the outer edge EDL on the longitudinal side, an oscillator 4 capable of suppressing the occurrence of various problems described above can be realized, and the reliability of the oscillator 4 can be improved.

[0066] Note that the device of the present embodiment is not limited to the oscillator 4 as shown in FIG. 14, and may be a device such as a sensor device, a display device, a communication device, or a power supply device as described above.

[0067] FIG. 15 is a manufacturing process diagram showing an example of a manufacturing method of the device of the present embodiment. The manufacturing method of the present embodiment is a manufacturing method of a device including an integrated circuit device 20 and a package 15 in which the integrated circuit device 20 is housed, and includes a manufacturing process S1 of the integrated circuit device 20 and processes S2, S3, and S4 which are mounting processes of the integrated circuit device 20 on the package 15.

[0068] In manufacturing process S1, a pad 2, a circuit 8 electrically connected to the pad 2, a lead wiring 5 of the pad 2, and a via group that electrically connects the lead wiring 5 and a wiring 7 of the circuit 8 are formed on the active surface of the integrated circuit device 20. The active surface is a formation region of circuit elements. As described with reference to FIGS. 1, 2, etc., the pad 2 is a pad having a shape with a longitudinal direction and a lateral direction, and the circuit 8 overlaps the pad 2 in a plan view and is electrically connected to the pad 2. The lead wiring 5 is drawn from the outer edge EDL on the longitudinal side of the pad 2 along the lateral direction DS of the pad 2. The via group 6 electrically connects the lead wiring 5 and the wiring 7 of the circuit 8 and is provided at a position that does not overlap the pad 2 in a plan view. The manufacturing process S1 of the integrated circuit device 20 is realized by a semiconductor process. The semiconductor process includes a film formation process such as a conductive film or an insulating film, a lithography process for patterning using a resist or the like, an etching process for removing an unnecessary oxide film or the like, an ion implantation process for implanting impurities and activating them by heat treatment, etc. Since these are well-known, detailed descriptions are omitted.

[0069] In the mounting process after the manufacturing process S1 of the integrated circuit device, a bump BMP is formed on the pad 2 of the integrated circuit device 20 (process S2). For example, a bump BMP called a stud bump is formed. Note that the bump BMP is not limited to a stud bump. Next, as described with reference to FIG. 14, the integrated circuit device 20 is arranged so that the active surface faces the surface SF of the package 15 (process S3). Then, the terminal TM provided on the surface SF of the package 15 and the bump BMP formed on the pad 2 are connected by ultrasonic bonding with the longitudinal direction of the pad 2 as the vibration direction (process S4). For example, a gold bump BMP and a terminal TM that is a gold-plated electrode are rubbed against each other and joined using ultrasonic vibration. As the distance between the bonding interfaces approaches due to the amplitude of the ultrasonic wave, the metal atoms of each other diffuse, and they are joined by this metal diffusion. This enables joining at a low temperature between the bump BMP and the terminal TM.

[0070] According to the manufacturing method of the present embodiment in this way, the pad 2 of the integrated circuit device 20 and the terminal TM provided on the surface of the package 15 can be joined using ultrasonic vibration. Also in this case, in the present embodiment, the pad 2 of the integrated circuit device 20 has a shape with a longitudinal direction, and since the lead wiring 5 of the pad 2 is drawn out from the outer edge EDL on the longitudinal side, it becomes possible to effectively suppress the occurrence of problems caused by stress due to ultrasonic vibration.

[0071] As described above, the integrated circuit device of the present embodiment includes a pad having a shape with a longitudinal direction and a lateral direction, a circuit that overlaps the pad in a plan view and is electrically connected to the pad, a lead wiring drawn out from the outer edge on the longitudinal side of the pad along the lateral direction of the pad, and a via group that electrically connects the lead wiring and the wiring of the circuit and does not overlap the pad in a plan view.

[0072] In the present embodiment, the circuit is arranged so as to overlap the pad in a plan view. Therefore, the circuit can be arranged by effectively using the area of the pad, and miniaturization of the integrated circuit device can be realized. Further, the pad has a shape with a longitudinal direction and a lateral direction, and since the lead wiring drawn out along the lateral direction of the pad from the outer edge on the longitudinal side of the pad and the wiring of the circuit are electrically connected by the via group, it is also possible to suppress the occurrence of problems such as those caused by a force acting along the longitudinal direction of the pad. Therefore, it becomes possible to provide an integrated circuit device or the like that can realize an appropriate lead wiring for electrically connecting the pad and the circuit while arranging the circuit so as to overlap the pad and realizing miniaturization of the integrated circuit device.

[0073] Also in the present embodiment, the wiring is wiring of a metal layer lower than the metal layer of the pad, and the wiring may partially overlap the pad in a plan view.

[0074] In this way, the lead wiring from the pad is connected to one end of the wiring via the via group, and the other end of the wiring is connected to the circuit element of the circuit, so that the pad can be electrically connected to the circuit element of the circuit arranged so as to overlap the pad.

[0075] In this embodiment, the wiring may be wiring of a metal layer disposed with a space of one layer or more from the metal layer of the pad.

[0076] In this way, when a load is applied to the pad, it is possible to suppress the wiring from being damaged and a problem from occurring.

[0077] In this embodiment, the lead wiring may have a shape in which the longitudinal direction of the pad is the longitudinal direction.

[0078] In this way, a lead wiring having a short length in the lateral direction can be drawn out from the outer edge on the longitudinal side of the pad, and the lead wiring can be electrically connected to the wiring of the circuit via the via group.

[0079] In this embodiment, a plurality of vias of the via group may be provided side by side along the longitudinal direction of the lead wiring.

[0080] In this way, it is possible to increase the number of via groups for electrically connecting the lead wiring and the circuit wiring.

[0081] In this embodiment, the lead wiring may have a shape in which the corner portion is chamfered in a plan view.

[0082] In this way, when static electricity or the like is applied to the pad, it is possible to suppress the charge from concentrating on the corner portion and a problem from occurring.

[0083] In this embodiment, the pad may be an input pad to which an input signal is input, and the circuit may be an I / O circuit to which an input signal is input from the input pad.

[0084] In this way, the input signal to the input pad can be input to the I / O circuit via the lead wiring, the via group, and the wiring, and the small area of the integrated circuit device that effectively utilizes the area of the input pad can be realized.

[0085] Also, in this embodiment, the pad may be an output pad that outputs an output signal, and the circuit may be an output buffer circuit that outputs the output signal to the output pad.

[0086] In this way, the output signal from the output buffer circuit can be output from the output pad via the wiring, via the via group, and via the lead-out wiring. Also, a decrease in the performance of the integrated circuit device caused by noise from the output buffer circuit can be suppressed.

[0087] Also, in this embodiment, the pad may be a ground pad to which ground is supplied, and the circuit may be a reference voltage generation circuit that generates a reference voltage.

[0088] In this way, the ground voltage supplied to the ground pad can be supplied to the reference voltage generation circuit via the lead-out wiring, via the via group, and via the wiring. Also, the ground pad can become a shield layer, suppressing noise from other circuits of the integrated circuit device from being transmitted and superimposed on the reference voltage generated by the reference voltage generation circuit.

[0089] Also, in this embodiment, it includes a second lead-out wiring drawn from the outer edge on the short side of the pad along the longitudinal direction of the pad, and the second lead-out wiring may be constituted by a metal layer on the same layer as the pad.

[0090] In this way, depending on the pad, there may be a pad from which the second lead-out wiring is drawn from the outer edge on the short side of the pad.

[0091] Also, in this embodiment, it includes a second pad having a shape with a longitudinal direction and a short-side direction, and the longitudinal direction of the pad and the longitudinal direction of the second pad may be the same direction.

[0092] In this way, when bonding the integrated circuit device to the package, ultrasonic vibration for ultrasonic bonding can be applied along the longitudinal direction of the pad and the second pad, and stress caused by the ultrasonic vibration can be prevented from being applied to the extraction wiring and via group.

[0093] The present embodiment also relates to a device including a package in which an integrated circuit device is housed, terminals provided on the surface of the package, and bumps that electrically connect the terminals and pads of the integrated circuit device.

[0094] In this way, the pads of the integrated circuit device and the terminals provided on the surface of the package can be electrically connected via the bumps, and the occurrence of defects due to forces acting along the longitudinal direction of the pads can also be suppressed.

[0095] In the present embodiment, the bumps are ultrasonically bonded to the terminals, and the longitudinal direction of the pads may be the longitudinal direction of the bumps.

[0096] In this way, the occurrence of defects caused by stress of ultrasonic vibration in ultrasonic bonding can be suppressed.

[0097] In the present embodiment, a vibrator housed in the package may be included, and the integrated circuit device may include an oscillation circuit that vibrates the vibrator to generate an oscillation signal.

[0098] In this way, a highly reliable oscillator that can suppress the occurrence of various defects can be realized.

[0099] The present embodiment is also a method for manufacturing a device including an integrated circuit device and a package in which the integrated circuit device is housed, and includes a manufacturing process of the integrated circuit device and a mounting process of mounting the integrated circuit device on the package. In the manufacturing process, pads having a shape with a longitudinal direction and a lateral direction, a circuit that overlaps the pads in a plan view and is electrically connected to the pads, a lead wiring drawn from an outer edge on the longitudinal side of the pads along the lateral direction of the pads, and via groups that electrically connect the lead wiring and the wiring of the circuit and do not overlap the pads in a plan view are formed on the active surface of the integrated circuit device. In the mounting process, bumps are formed on the pads of the integrated circuit device, the integrated circuit device is arranged so that the active surface faces the surface of the package, and the terminals provided on the surface of the package and the bumps formed on the pads are connected by ultrasonic bonding with the longitudinal direction of the pads as the vibration direction.

[0100] According to such a manufacturing method, the pads of the integrated circuit device and the terminals provided on the surface of the package can be joined using ultrasonic vibration. And since the pads of the integrated circuit device have a shape with a longitudinal direction and the lead wiring of the pads is drawn from the outer edge on the longitudinal side of the pads, it becomes possible to suppress the occurrence of defects caused by stress due to ultrasonic vibration. Therefore, it becomes possible to provide a manufacturing method capable of realizing an appropriate lead wiring that electrically connects the pads while realizing miniaturization of the integrated circuit device by arranging the circuit so as to overlap the pads.

[0101] Although the present embodiment has been described in detail as above, those skilled in the art will easily understand that many modifications can be made without substantially departing from the novel matters and effects of the present disclosure. Therefore, all such modified examples are intended to be included in the scope of the present disclosure. For example, in the specification or the drawings, a term described at least once together with a broader or synonymous different term can be replaced with the different term at any place in the specification or the drawings. Also, all combinations of the present embodiment and the modified examples are included in the scope of the present disclosure. Further, the integrated circuit device, the configuration, operation, manufacturing method, etc. of the device are not limited to those described in the present embodiment, and various modifications can be made.

Description of Symbols

[0102] 2…Pad, 3…Passivation film, 4…Oscillator, 5…Lead wiring, 6…Via group, 7…Wiring, 8…Circuit, 9…Second lead wiring, 10…Vibrator, 15…Package, 16…Base, 17…Lid, 18…External terminal, 19…External terminal, 20…Integrated circuit device, 21…Electrostatic protection circuit, 22…Input / output circuit, 30…Oscillation circuit, 50…Output circuit, 52…Output buffer circuit, 60…Power supply circuit, 62…Reference voltage generation circuit, 64…Regulator, 70…Logic circuit, 80…Temperature compensation circuit, 90…Temperature sensor circuit, 91…Pad metal, 92, 93, 94…Conductive layer, ALA~ALE…Metal layer, BMP…Bump, BP1, BP2, BP3…Bipolar transistor, CKQ…Clock signal, DI1, DI2, DI3…Diode, DL…Longitudinal direction, DR, DR1, DR2, DR3, DR4…Direction, DS…Transverse direction, EDL, EDS…Outer edge, OE…Output enable signal, OSC…Oscillation signal, PCK…Clock pad, PGND…Ground pad, PI…Input pad, POE…Output enable pad, PQ…Output pad, PVDD…Power supply pad, PX1…Pad, PX2…Pad, RD1~RD3, RE1, RE2…Resistor, SD1~SD4…Side, SF…Surface, TD1~TD3, TE1~TE5…Transistor, TM…Terminal, TCK, TGND, TOE, TVDD…External terminal, VB…Bias voltage, VCP…Temperature compensation voltage, VDD…Power supply voltage, VREF…Reference voltage, VT…Temperature detection voltage

Claims

1. A pad having a shape having a longitudinal direction and a lateral direction; a circuit overlapping the pad in a plan view and electrically connected to the pad; a lead-out wiring extending in the short direction of the pad and led out from an outer edge of the long side of the pad; a via group that electrically connects the lead-out wiring and the wiring of the circuit and does not overlap the pad in the plan view; 1. An integrated circuit device comprising:

2. 2. The integrated circuit device of claim 1, the wiring is a wiring in a metal layer below a metal layer of the pad, The wiring has a portion overlapping with the pad in the plan view.

3. 3. The integrated circuit device of claim 2, 4. An integrated circuit device, comprising: a first metal layer and a second metal layer, the first metal layer being spaced apart from the first metal layer by at least one layer;

4. 4. The integrated circuit device according to claim 1, The integrated circuit device according to claim 1, wherein the lead-out wiring has a shape whose longitudinal direction coincides with the longitudinal direction of the pad.

5. 5. The integrated circuit device according to claim 4, an integrated circuit device, wherein a plurality of vias in the via group are arranged side by side along the longitudinal direction of the lead-out wiring;

6. 6. The integrated circuit device according to claim 1, The integrated circuit device is characterized in that the lead-out wiring has a shape with chamfered corners in the plan view.

7. 7. The integrated circuit device according to claim 1, the pad is an input pad to which an input signal is input, The circuit is an I / O circuit to which the input signal is input from the input pad.

8. 7. The integrated circuit device according to claim 1, the pad is an output pad for outputting an output signal, The integrated circuit device, wherein the circuit is an output buffer circuit that outputs the output signal to the output pad.

9. 7. The integrated circuit device according to claim 1, the pad is a ground pad to which a ground is supplied, The integrated circuit device is characterized in that the circuit is a reference voltage generating circuit that generates a reference voltage.

10. 7. The integrated circuit device according to claim 1, a second lead-out wiring led out from an outer edge of a short side of the pad along the longitudinal direction of the pad, The integrated circuit device according to claim 1, wherein the second lead-out wiring is made of the same metal layer as the pad.

11. 11. The integrated circuit device according to claim 1, a second pad having a shape having a longitudinal direction and a lateral direction; an integrated circuit device, wherein the longitudinal direction of the first pad and the longitudinal direction of the second pad are the same direction;

12. An integrated circuit device according to any one of claims 1 to 9; a package in which the integrated circuit device is housed; A terminal provided on a surface of the package; a bump electrically connecting the terminal and the pad of the integrated circuit device; A device comprising:

13. 13. The device of claim 12, the bump is ultrasonically bonded to the terminal; A device, characterized in that the longitudinal direction of the pad is the longitudinal direction of the bump.

14. 14. The device according to claim 12 or 13, a vibrator housed in the package; The device, wherein the integrated circuit device includes an oscillator circuit that vibrates the oscillator to generate an oscillation signal.

15. 1. A method for manufacturing a device including an integrated circuit device and a package in which the integrated circuit device is housed, comprising the steps of: A manufacturing process for the integrated circuit device; a mounting step of mounting the integrated circuit device in the package; Including, In the manufacturing process, a pad having a shape having a longitudinal direction and a lateral direction, a circuit overlapping the pad in a plan view and electrically connected to the pad, a lead-out wiring drawn out from an outer edge of the longitudinal side of the pad along the lateral direction of the pad, and a group of vias electrically connecting the lead-out wiring and the wiring of the circuit and not overlapping the pad in the plan view, formed on an active surface of the integrated circuit device; In the mounting step, forming bumps on the pads of the integrated circuit device; placing the integrated circuit device with the active surface facing a surface of the package; A manufacturing method comprising connecting a terminal provided on a surface of the package to the bump formed on the pad by ultrasonic bonding in which the longitudinal direction of the pad is the vibration direction.

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