Circuit device

Abstract

To provide a circuit device or the like capable of reducing noise generated from a differential signal bus.SOLUTION: A circuit device 20 for driving a differential-signal bus includes: a high-side transistor TA1 provided between a node of a power source and a first output terminal TQ1 connected to the differential-signal bus; a low-side transistor TA2 provided between a node of the ground and a second output terminal TQ2 connected to the differential-signal bus; and a drive circuit 30 that outputs a first drive signal to one of a gate of the high-side transistor TA1 and a gate of the low-side transistor TA2, and outputs a second drive signal to the other of the gate of the high-side transistor TA1 and the gate of the low-side transistor TA2. The drive circuit 30 includes: a first delay circuit 40 that sets a first delay time that is a delay time of rising of the second drive signal; and a second delay circuit 50 that sets a second delay time that is the delay time of falling of the second drive signal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a circuit device and the like.

Background Art

[0002] For example, in in - vehicle networks, FA networks, etc., differential signal buses defined by CAN (Controller Area Network), LVDS (Low voltage differential signaling), FlexRay, etc. are used. The differential signal bus is a bus of a method called a two - wire differential signal method or a differential transmission method. CAN is described in, for example, Patent Document 1.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In in - vehicle devices, FA devices, etc., it is desired to suppress the influence that the devices receive from noise, and it is necessary to reduce the noise generated from the differential signal bus.

Means for Solving the Problems

[0005] One aspect of the present disclosure is a circuit device for driving a differential signal bus, including a high-side transistor provided between a power supply node and a first output terminal connected to the differential signal bus, a low-side transistor provided between a ground node and a second output terminal connected to the differential signal bus, and a driving circuit that outputs a first driving signal to one of the gates of the high-side transistor and the low-side transistor and outputs a second driving signal to the other of the gates of the high-side transistor and the low-side transistor. The driving circuit includes a first delay circuit that sets a first delay time, which is a rising delay time of the second driving signal, and a second delay circuit that sets a second delay time, which is a falling delay time of the second driving signal, and relates to a circuit device including the same.

Brief Description of the Drawings

[0006]

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Mode for Carrying Out the Invention

[0007] Hereinafter, this embodiment will be described. Note that the embodiment described below does not unduly limit the content described in the claims. Also, not all of the configurations described in this embodiment are essential constituent elements.

[0008] 1. Circuit device FIG. 1 shows a configuration example of the circuit device 20 of this embodiment. The circuit device 20 realizes a differential signal transceiver that drives the differential signal bus BS. The differential signal bus BS has a first bus line for the high-side output signal DH and a second bus line for the low-side output signal DL.

[0009] As shown in FIG. 1, the circuit device 20 of this embodiment that drives the differential signal bus BS includes a high-side transistor TA1, a low-side transistor TA2, and a drive circuit 30. The high-side transistor TA1 is provided between the power supply node NV and the first output terminal TQ1. The low-side transistor TA2 is provided between the ground node NG and the second output terminal TQ2. The first output terminal TQ1 and the second output terminal TQ2 are connected to the differential signal bus BS. Specifically, for the transistor TA1, for example, the source is connected to the power supply node NV and the drain is connected to the first output terminal TQ1. For the transistor TA2, for example, the source is connected to the ground node NG and the drain is connected to the second output terminal TQ2. The node NV is a node to which VDD, which is a high-potential-side power supply, is supplied, and the node NG is a node to which ground, which is a low-potential-side power supply, is supplied. In this embodiment, the ground is appropriately described as GND. GND can also be referred to as VSS.

[0010] Note that the circuit device 20 of this embodiment is not limited to the configuration of FIG. 1, and various modifications can be made, such as omitting some of these components, adding other components, or replacing some components with other components. For example, circuit elements such as resistors for setting the voltage level may be provided between the node NV and the transistor TA1 or between the node NG and the transistor TA2, or circuit elements such as diodes for preventing reverse current may be provided between the transistor TA1 and the first output terminal TQ1 or between the transistor TA2 and the second output terminal TQ2.

[0011] Transistors TA1 and TA2 are transistors for driving differential signal bus BS. The high-side transistor TA1 drives the first bus line of the high-side output signal DH of differential signal bus BS. The first output terminal TQ1 is connected to the high-side first bus line, and transistor TA1 drives the first bus line of output signal DH via the first output terminal TQ1. The low-side transistor TA2 drives the second bus line of the low-side output signal DL of differential signal bus BS. The second output terminal TQ2 is connected to the low-side second bus line, and transistor TA2 drives the second bus line of output signal DL via the second output terminal TQ2. Transistor TA1 is, for example, a P-type transistor, and transistor TA2 is, for example, an N-type transistor. It should be noted that modified implementations such as using N-type transistors as transistors TA1 and TA2 or using P-type transistors as transistors TA1 and TA2 are also possible.

[0012] Drive circuit 30 outputs a first drive signal to one of the gates of the high-side transistor TA1 and the low-side transistor TA2, and outputs a second drive signal to the other of the gates of the high-side transistor TA1 and the low-side transistor TA2. Drive circuit 30 can be referred to as a differential signal transmission circuit. For example, in FIG. 1, drive circuit 30 outputs drive signal GH as the first drive signal to the gate of the high-side transistor TA1, and outputs drive signal GL as the second drive signal to the gate of the low-side transistor TA2. For example, drive circuit 30 receives the input of transmission data signal TXD and outputs drive signals GH and GL. For example, drive circuit 30 buffers transmission data signal TXD and outputs drive signals GH and GL. For example, drive signal GL is a signal obtained by inverting the signal level of drive signal GH.

[0013] In the following, a case will be described by taking as an example the case where the drive signal GH output to the high-side transistor TA1 by the drive circuit 30 is the first drive signal, and the drive signal GL output to the low-side transistor TA2 is the second drive signal. However, the drive signal GL output to the low-side transistor TA2 may be the first drive signal, and the drive signal GL output to the high-side transistor TA1 may be the second drive signal.

[0014] And in the present embodiment, the drive circuit 30 includes a first delay circuit 40 and a second delay circuit 50. The first delay circuit 40 sets a first delay time, which is the rising delay time of the second drive signal, and the second delay circuit 50 sets a second delay time, which is the falling delay time of the second drive signal. For example, as shown in FIG. 2, the first delay circuit 40 sets the rising delay time trgl of the drive signal GL, which is the second drive signal, and the second delay circuit 50 sets the falling delay time tfgl of the drive signal GL, which is the second drive signal. The delay time trgl is the first delay time, and the delay time tfgl is the second delay time. As described above, the high-side drive signal GH may be the second drive signal, and the first delay circuit 40 and the second delay circuit 50 may set the rising delay time and the falling delay time of the drive signal GH.

[0015] As described above, in the present embodiment, the drive circuit 30 outputs drive signals GH and GL, which are the first drive signal and the second drive signal, to the transistors TA1 and TA2 on the high side and the low side. Thereby, the differential signal bus BS is driven by the high-side transistor TA1 provided between the power supply node NV and the first output terminal TQ1 and the low-side transistor TA2 provided between the ground node NG and the second output terminal TQ2. Then, by the first delay circuit 40 and the second delay circuit 50 of the drive circuit 30, the rise delay time trgl and the fall delay time tfgl of, for example, the drive signal GL, which is the second drive signal, are adjusted separately. In this way, by appropriately adjusting the delay times trgl and tfgl, it becomes possible to reduce the noise generated from the differential signal bus BS. For example, even when there are differences in driving ability, parasitic capacitance, etc. between the high-side transistor TA1 and the low-side transistor TA2, it becomes possible to effectively reduce noise such as EMI (Electromagnetic Interference). That is, when the driving ability and parasitic capacitance of the high-side transistor TA1 and the low-side transistor TA2 are different, an imbalance occurs in the waveforms of the output signals DH and DL from the first output terminal TQ1 and the second output terminal TQ2, and this causes noise to be generated in the differential signal bus BS. In this regard, in the present embodiment, since the first delay circuit 40 and the second delay circuit 50 can adjust the rise delay time trgl and the fall delay time tfgl of the drive signal GL separately, it becomes possible to reduce the imbalance in the waveforms of the output signals DH and DL and reduce the noise generated from the differential signal bus BS. As a result, it becomes possible to reduce the influence on devices such as in-vehicle devices and FA devices in which the circuit device 20 is incorporated from the noise.

[0016] 2. Specific configuration example Next, a specific example of the circuit device 20 of the present embodiment will be described. Here, a specific example of the circuit device 20 when the differential signal bus BS is a CAN bus will be described, but the present embodiment is not limited to this, and the differential signal bus BS may be a bus of another system such as LVDS.

[0017] For example, FIG. 3 is an explanatory diagram of a CAN used in in-vehicle devices and the like, and FIG. 4 is a diagram showing the signal waveform of the CAN. As shown in FIG. 3, in the CAN, for example, node 1 and node n are connected by a CAN bus. Each of node 1 and node n is provided with a transceiver realized by the circuit device 20 of the present embodiment. The CAN bus, which is a differential signal bus BS, is composed of a first bus line for the output signal CANH on the high side and a second bus line for the output signal CANL on the low side. A termination resistor RT1 is provided between one end of the first bus line and one end of the second bus line, and a termination resistor RT2 is provided between the other end of the first bus line and the other end of the second bus line. The resistance values of the termination resistors RT1 and RT2 are, for example, 120 Ω.

[0018] And in the CAN bus, as shown in FIG. 4, during the dominant period, for example, the transistor TA1 on the high side and the transistor TA2 on the low side are both turned on. As a result, the output signal CANH on the high side becomes, for example, 3.5 V, and the output signal CANL on the low side becomes, for example, 1.5 V. 3.5 V corresponds to the high level of the output signal CANH on the high side, and 1.5 V corresponds to the low level of the output signal CANL on the low side. Also, during the recessive period, for example, the transistor TA1 on the high side and the transistor TA2 on the low side are both turned off. As a result, both the output signal CANH on the high side and the output signal CANL on the low side become 2.5 V, which is an intermediate voltage. 2.5 V corresponds to the low level of the output signal CANH on the high side and also corresponds to the high level of the output signal CANL on the low side. In this way, in the CAN, in both the dominant period and the recessive period, the sum of the output signal CANH on the high side and the output signal CANL on the low side is constant at 5 V, thereby suppressing the generation of EMI noise.

[0019] Fig. 5 shows a specific configuration example of the present embodiment. In Fig. 5, the circuit device 20 includes a high-side transistor TA1, a low-side transistor TA2, a drive circuit 30, and a storage unit 90. The circuit device 20 can also include, for example, a first output terminal TQ1 and a second output terminal TQ2 as pads of an IC.

[0020] The high-side transistor TA1 is a P-type transistor, and a drive signal GH from the drive circuit 30 is input to the gate of the transistor TA1. The low-side transistor TA2 is an N-type transistor, and a drive signal GL from the drive circuit 30 is input to the gate of the transistor TA2.

[0021] The drive circuit 30 includes a first delay circuit 40 and a second delay circuit 50. The first delay circuit 40 includes a first delay unit 42 and an OR circuit. The first delay unit 42 receives the transmission data signal TXD as an input signal and outputs a signal D1 obtained by delaying the signal TXD. The OR circuit receives the signal TXD and the signal D1 from the first delay unit 42 and outputs a signal Q1. The second delay circuit 50 includes a second delay unit 52, an AND circuit AN, and an inverter circuit IVA. The second delay unit 52 receives the signal Q1 from the first delay circuit 40 as an input signal and outputs a signal D2 obtained by delaying the signal Q1. The AND circuit AN receives the signal Q1 and the signal D2 from the second delay unit 52 and outputs a signal Q2. The inverter circuit IVA outputs, as the drive signal GL, a signal obtained by inverting the signal level of the signal Q2.

[0022] The storage unit 90 stores delay setting information SDL1 and SDL2. Then, the first delay circuit 40 and the second delay circuit 50 set the delay time of the drive signal GL based on the delay setting information SDL1 and SDL2 stored in the storage unit 90. Then, the drive signals GH and GL from the drive circuit 30 are input to the gates of the transistors TA1 and TA2, and output signals CANH and CANL are output from the first output terminal TQ1 and the second output terminal TQ2. These output signals CANH and CANL correspond to the output signals DH and DL in Fig. 1.

[0023] Note that the circuit device 20 of this embodiment is not limited to the configuration of FIG. 5, and various modifications can be made, such as omitting some of these components, adding other components, or replacing some components with other components. For example, similar to the case of FIG. 1 described above, a diode for preventing reverse flow or a resistor for setting the voltage level may be provided. Further, circuits other than the first delay circuit 40 and the second delay circuit 50 may be provided in the drive circuit 30. Further, the drive circuit 30 may output a signal obtained by buffering the transmission data signal TXD by a buffer circuit (not shown) to the gate of the transistor TA1 as the drive signal GH.

[0024] FIG. 6 is an example of signal waveforms for explaining the operation of the circuit device 20 in FIG. 5. The signal TXD input to the drive circuit 30 is delayed by a delay time DL1 by the first delay unit 42 of the first delay circuit 40 and input to the OR logic circuit as the signal D1. Then, the OR logic circuit outputs a signal Q1 corresponding to the logical sum of the signal TXD and the signal D1. The signal Q1 is a signal whose fall time is delayed by the delay time DL1 with respect to the signal TXD. Then, the signal Q1 is delayed by a delay time DL2 by the second delay unit 52 of the second delay circuit 50 and input to the AND logic circuit as the signal D2. Then, the AND logic circuit outputs a signal Q2 corresponding to the logical product of the signal Q1 and the signal D2. The signal Q2 is a signal whose fall time is delayed by the delay time DL1 and whose rise time is delayed by the delay time DL2 with respect to the signal TXD. Then, the signal obtained by inverting the signal Q2 by the inverter circuit IVA is input as the drive signal GL to the gate of the transistor TA2. By doing so, the drive circuit 30 can output a drive signal GL whose rise delay time is set to trgl and whose fall delay time is set to tfgl with respect to the signal TXD. Here, the delay time trgl corresponds to the delay time DL1 in the first delay unit 42, and the delay time tfgl corresponds to the delay time DL2 in the second delay unit 52. Also, the drive signal GL is a signal whose rising edge is delayed by the delay time tfgl from one of the falling edge and the rising edge of the signal TXD, and whose falling edge is delayed by the delay time tfgl from the other of the falling edge and the rising edge of the signal TXD. In FIG. 6, one edge of the signal TXD is a falling edge and the other edge is a rising edge, but one edge may be a rising edge and the other edge may be a falling edge.

[0025] FIG. 7 shows an example of a signal waveform in a comparative example of the present embodiment. In the comparative example, the first delay circuit 40 and the second delay circuit 50 as in the present embodiment are not provided. For example, a signal obtained by inverting and buffering a signal TXD by a first buffer circuit is output as a drive signal GL, and a signal obtained by buffering the drive signal GL by a second buffer circuit is output as a drive signal GH. The delay times trgl and tfgl in FIG. 7 correspond to the delay times in the first buffer circuit described above, and the delay times trgh and tfgh correspond to the delay times in the second buffer circuit described above. These delay times trgl, tfgl, trgh, and tfgh are approximately equal and are short delay times of about several nsec.

[0026] FIG. 8 shows an example of a signal waveform in the present embodiment. In the present embodiment, by providing the first delay circuit 40 and the second delay circuit 50 in the drive circuit 30, the rise and fall delay times trgl and tfgl of the drive signal GL can be set individually. For example, the delay time trgl is set by the delay time DL1 in the first delay unit 42 of the first delay circuit 40, and the delay time tfgl is set by the delay time DL2 in the second delay unit 52 of the second delay circuit 50. Therefore, unlike the comparative example in FIG. 7, the delay times trgl and tfgl can be set to different lengths. Note that the fall and rise delay times tfgh and trgh of the drive signal GH are approximately equal. For example, when a buffer circuit that buffers the signal TXD and outputs the drive signal GH is provided, it is the delay time in this buffer circuit.

[0027] FIG. 9 shows a configuration example of each delay unit of the first delay unit 42 and the second delay unit 52. In FIG. 9, each delay unit of the first delay unit 42 and the second delay unit 52 includes a plurality of buffer circuits BF1, BF2, BF3, BF4, BF5 and a switch circuit SW. Each of the buffer circuits BF1 to BF5 receives a signal from the previous buffer circuit and outputs the signal to the subsequent buffer circuit. These buffer circuits can be configured by, for example, a two-stage inverter circuit or the like.

[0028] In FIG. 9, the switch circuit SW is controlled based on the delay setting information SDL1 or the delay setting information SDL2 to select the output signal of the buffer circuit BF3, the buffer circuit BF4, or the buffer circuit BF5, and output it as the signal QDL. The signal QDL corresponds to the signals D1 and D2 in FIG. 5. For example, the switch circuit SW of the first delay unit 42 of the first delay circuit 40 is controlled based on the delay setting information SDL1, and the switch circuit SW of the second delay unit 52 of the second delay circuit 50 is controlled based on the delay setting information SDL2.

[0029] For example, when the signal of the delay setting information SDL1 is active, the switch circuit SW of the first delay unit 42 selects the output signal of the buffer circuit BF3 and outputs it as the signal QDL (signal D1). Also, when the signal of the delay setting information SDL2 is active, the switch circuit SW of the second delay unit 52 selects the output signal of the buffer circuit BF5 and outputs it as the signal QDL (signal D2). In this way, it becomes possible to make the delay time DL2 in the second delay unit 52 longer than the delay time DL1 in the first delay unit 42. Thereby, it becomes possible to make the fall delay time tfgl of the drive signal GL longer than the rise delay time trgl of the drive signal GL.

[0030] Alternatively, when the signal of the delay setting information SDL1 is active, the switch circuit SW of the first delay unit 42 selects the output signal of the buffer circuit BF5 and outputs it as the signal QDL. Also, when the signal of the delay setting information SDL2 is active, the switch circuit SW of the second delay unit 52 selects the output signal of the buffer circuit BF3 and outputs it as the signal QDL. In this way, it becomes possible to make the delay time DL2 in the second delay unit 52 shorter than the delay time DL1 in the first delay unit 42. Thereby, it becomes possible to make the fall delay time tfgl of the drive signal GL shorter than the rise delay time trgl of the drive signal GL.

[0031] Also, as shown in FIG. 5, the high-side transistor provided between the node NV of VDD and the first output terminal TQ1 is a P-type transistor. Also, the low-side transistor TA2 provided between the node NG of GND and the second output terminal TQ2 is an N-type transistor. These transistors TA1 and TA2 are, for example, MOS transistors. Then, a drive signal GH is input to the gate of the high-side transistor TA1 as, for example, a first drive signal, and a drive signal GL is input to the gate of the low-side transistor TA1 as, for example, a second drive signal.

[0032] As described above, in FIG. 5, the low-side transistor TA2 is an N-type transistor, and the drive circuit 30 outputs the drive signal GL, which is a second drive signal, to the gate of the N-type transistor TA2. By doing so, the rise delay time trgl and the fall delay time tfgl of the drive signal GL can be set by the first delay circuit 40 and the second delay circuit 50, so that the waveform imbalance between the output signals CANH and CANL from the first output terminal TQ1 and the second output terminal TQ2 can be reduced. As a result, when noise is generated due to the waveform imbalance between the output signals CANH and CANL, the rise delay time trgl and the fall delay time tfgl of the drive signal GL input to the gate of the N-type transistor TA2 can be set to effectively reduce the noise.

[0033] For example, as shown in FIG. 6, the length of the delay time trgl which is the first delay time and the length of the delay time tfgl which is the second delay time are different. That is, the rising delay time trgl and the falling delay time tfgl of the drive signal GL which is the second drive signal are set to different lengths. For example, in the period when the drive signal GL rises and the period when it falls, the waveforms of the output signals CANH and CANL output from the first output terminal TQ1 and the second output terminal TQ2 via the transistors TA1 and TA2 become different. During the period when the transistors TA1 and TA2 are on, the differences in the driving capabilities etc. of the transistors TA1 and TA2 affect the waveforms of the output signals CANH and CANL, and during the period when the transistors TA1 and TA2 are off, the differences in the parasitic capacitances etc. of the transistors TA1 and TA2 affect the waveforms of the output signals CANH and CANL. Therefore, by making the length of the delay time trgl and the length of the delay time tfgl different, the imbalance of the waveforms of the output signals CANH and CANL can be reduced, and the noise caused by the waveform imbalance can be reduced.

[0034] Also, in FIG. 5, the first delay circuit 40 of the drive circuit 30 sets the rising delay time trgl of the drive signal GL shown in FIG. 6 based on the delay setting information SDL1. That is, when the delay time DL1 in the first delay unit 42 is set by the delay setting information SDL1, the delay time trgl is set. The delay setting information SDL1 is the first delay setting information, and the delay time trgl is the first delay time. Also, the second delay circuit 50 of the drive circuit 30 sets the falling delay time tfgl of the drive signal GL based on the delay setting information SDL2. That is, when the delay time DL2 in the second delay unit 52 is set by the delay setting information SDL2, the delay time tfgl is set. The delay setting information SDL2 is the second delay setting information, and the delay time tfgl is the second delay time. In this way, the first delay circuit 40 can set the trgl, which is the first delay time of the drive signal GL, which is the second drive signal, based on the SDL1, which is the first delay setting information. Also, the second delay circuit 50 can set the tfgl, which is the second delay time of the drive signal GL, based on the SDL2, which is the second delay setting information. Therefore, based on the delay setting information SDL1 and SDL2, it becomes possible to set the rising delay time trgl and the falling delay time tfgl of the drive signal GL to an arbitrary length. As a result, when noise occurs due to differences in the driving capabilities and parasitic capacitances of the transistors TA1 and TA2, by setting the delay setting information SDL1 and SDL2 to values corresponding to the differences in the driving capabilities and parasitic capacitances, etc., it becomes possible to effectively reduce the noise.

[0035] Also, as shown in FIG. 5, the circuit device 20 includes a storage unit 90 that stores SDL1, which is first delay setting information, and SDL2, which is second delay setting information. The storage unit 90 is a non-volatile storage unit that can maintain the stored content even when power is not supplied, for example. As the storage unit 90, a non-volatile memory, a fuse circuit, or the like can be used, for example. The non-volatile memory is, for example, an EPROM, an EEPROM, or a ROM. The fuse circuit is a circuit that stores information according to the setting information of the fuse element. For example, in the fuse circuit, information corresponding to the cut or non-cut state of the fuse element made of metal or polysilicon is stored. By providing the storage unit 90 that stores the delay setting information SDL1 and SDL2 in this way, the first delay circuit 40 and the second delay circuit 50 can set the rise delay time trgl and the fall delay time tfgl of the drive signal GL based on the delay setting information SDL1 and SDL2 read from the storage unit 90. That is, by setting the delay times DL1 and DL2 in the first delay unit 42 and the second delay unit 52 based on the delay setting information SDL1 and SDL2, the delay times trgl and tfgl can be set. As a result, by storing the delay setting information SDL1 and SDL2 with values corresponding to differences in the driving capabilities and parasitic capacitances of the transistors TA1 and TA2 in the storage unit 90, it becomes possible to effectively reduce the noise. For example, the writing of the delay setting information SDL1 and SDL2 to the storage unit 90 is performed during the manufacturing or inspection of the circuit device 20 or the device including the circuit device 20.

[0036] Also, as shown in FIG. 5, the first delay circuit 40 includes a first delay unit 42 that delays the input signal of the first delay circuit 40, and an OR circuit that outputs the logical sum of the input signal and the signal D1 from the first delay unit 42. In FIG. 5, the input signal of the first delay circuit 40 is the signal TXD of the transmission data. According to the first delay circuit 40 having such a configuration, for example, a signal Q1 corresponding to the logical sum of the input signal and the signal D1 obtained by delaying the input signal of the first delay circuit 40 by the delay time DL1 by the first delay unit 42 can be output from the OR circuit. As a result, as shown in FIG. 6, for example, the delay time of the drive signal GL can be set by the delay time DL1 of the first delay unit 42 of the first delay circuit 40.

[0037] Also, as shown in FIG. 5, the second delay circuit 50 includes a second delay unit 52 that delays the input signal of the second delay circuit 50, and an AND circuit that outputs the logical product of the input signal of the second delay circuit 50 and the signal D2 from the second delay unit 52. Also in FIG. 5, the second delay circuit 50 includes an inverter circuit IVA that inverts the signal level of the signal Q2 from the AND circuit. In FIG. 5, the input signal of the second delay circuit 50 is the signal Q1 from the first delay circuit 40. According to the second delay circuit 50 having such a configuration, for example, a signal Q2 corresponding to the logical product of the input signal and the signal D2 obtained by delaying the input signal of the second delay circuit 50 by the delay time DL2 by the second delay unit 52 can be output from the AND circuit. As a result, for example, the delay time of the drive signal GL can be set by the delay time DL2 of the second delay unit 52 of the second delay circuit 50.

[0038] 3. Measurement of Noise In a differential signal bus system such as CAN, there are requirement specifications for noise such as EMI. For example, FIG. 10 shows a configuration example of a noise measurement system 100 in CAN. The measurement system 100 in FIG. 10 includes a common mode choke coil 210, resistors RB1, RB2, RB3, RB4, RB5, and capacitors CB1, CB2. The common mode choke coil 210 includes coils L1, L2. For coils L1, L2 of the common mode choke coil 210, signals PH, PL from the first output terminal TQ1 and the second output terminal TQ2 of the circuit device 20 are input to one end, and output signals CANH, CANL are output from the other end. The high-frequency noise of signals PH, PL is removed by the common mode choke coil 210. Also, resistors RB1, RB2, RB3 and capacitors CB1, CB2 form an adder circuit, and a signal corresponding to the sum of the output signals CANH, CANL is output as signal OUT. Resistors RB4, RB5 correspond to termination resistors.

[0039] FIG. 11 is an example of a signal waveform during measurement in a comparative example. In the comparative example, since the first delay circuit 40 and the second delay circuit 50 as in the present embodiment are not provided, noise as shown in A1 occurs in the signal OUT corresponding to the sum of the output signals CANH, CANL. That is, as described with reference to FIG. 4 in CAN, the noise of EMI is reduced by making the sum of the output signals CANH, CANL become 2.5V corresponding to the intermediate voltage during the dominant period and the recessive period. However, in the comparative example where the adjustment of the delay time by the first delay circuit 40 and the second delay circuit 50 is not performed, for example, in A2 of FIG. 11, the output signals CANH, CANL have an unbalanced waveform that is not symmetric with respect to 2.5V. For this reason, the signal OUT corresponding to the sum of the output signals CANH, CANL does not become a constant voltage of 2.5V, and noise as shown in A1 appears, which causes EMI. Although noise also occurs in A3 of FIG. 11, it is less noise compared to A1.

[0040] FIG. 12 shows an example of a signal waveform during measurement in the present embodiment. In the present embodiment, a first delay circuit 40 and a second delay circuit 50 are provided, and the rising delay time trgl and the falling delay time tfgl of the drive signal GL are individually adjusted. As a result, as shown in A4 of FIG. 12, noise can be reduced compared to A1 of FIG. 11. That is, by adjusting the delay times trgl and tfgl by the first delay circuit 40 and the second delay circuit 50, for example, in A5 of FIG. 12, the waveforms of the output signals CANH and CANL can be balanced so as to be symmetric with respect to, for example, 2.5V. Therefore, as shown in A4, the noise in the signal OUT corresponding to the sum of the output signals CANH and CANL can be reduced compared to A1 of FIG. 11. Although noise also occurs in A6 of FIG. 12, it is less noise compared to A4.

[0041] FIG. 13 shows the simulation results of the noise characteristics. The upper side shows the noise characteristics of the comparative example, and the lower side shows the noise characteristics of the present embodiment. In FIG. 13, the horizontal axis is the frequency (KHz), and the vertical axis is the noise level (dBuV). In the comparative example, as shown in B1, the maximum noise level is about 65 dBuV, whereas in the present embodiment, as shown in B2, the maximum noise level is about 41 dBuV, and the noise level is sufficiently reduced. Thus, in the present embodiment, by adjusting the delay times trgl and tfgl by the first delay circuit 40 and the second delay circuit 50, the noise level can be reduced compared to the comparative example in which the first delay circuit 40 and the second delay circuit 50 are not provided.

[0042] 4. Other Configuration Examples FIG. 14 shows another configuration example of the circuit device 20 of the present embodiment. In FIG. 14, in addition to the first delay circuit 40 and the second delay circuit 50, a third delay circuit 60 is further provided for the drive circuit 30. The third delay circuit 60 sets a third delay time which is the delay time of both the rising edge and the falling edge of the drive signal GL which is the second drive signal. For example, the third delay circuit 60 sets a delay time DL3 which is the third delay time of FIG. 15 described later based on the delay setting information SDL3 from the storage unit 90. Specifically, for example, fine adjustment of the delay times trgl and tfgl is performed by the first delay circuit 40 and the second delay circuit 50, and coarse adjustment of the delay times trgl and tfgl is performed by the third delay circuit 60. For example, in FIG. 14, the signal Q1 from the first delay circuit 40 is input to the subsequent second delay circuit 50, the signal Q2 from the second delay circuit 50 is input to the subsequent third delay circuit 60, and the signal Q3 from the third delay circuit 60 is input to the transistor TA2 as the drive signal GL. Note that the arrangement configuration of the first delay circuit 40, the second delay circuit 50, and the third delay circuit 60 is not limited to this, and various modifications such as providing the third delay circuit 60 in the previous stage of the first delay circuit 40 or the second delay circuit 50 are possible.

[0043] FIG. 15 is an example of a signal waveform for explaining the operation of the circuit device 20 of FIG. 14. As shown in FIG. 15, the rising delay time trgl of the drive signal GL is set by the third delay time DL3 by the third delay circuit 60 and the first delay time DL1 by the first delay circuit 40. For example, the delay time trgl is coarsely adjusted by the delay time DL3 set by the third delay circuit 60 and finely adjusted by the delay time DL1 set by the first delay circuit 40. The delay time DL3 used for coarse adjustment is longer than the delay time DL1 used for fine adjustment. Also, the delay time DL1 used for fine adjustment can be adjusted with higher resolution than the delay time DL3 used for coarse adjustment.

[0044] Also, as shown in FIG. 15, the fall delay time tfgl of the drive signal GL is set by the third delay time DL3 by the third delay circuit 60 and the second delay time DL2 by the second delay circuit 50. For example, the delay time tfgl is roughly adjusted by the delay time DL3 set by the third delay circuit 60 and finely adjusted by the delay time DL2 set by the second delay circuit 50. The delay time DL3 used for the rough adjustment is longer than the delay time DL2 used for the fine adjustment. Also, the delay time DL2 used for the fine adjustment can be adjusted with higher resolution than the delay time DL3 used for the rough adjustment.

[0045] Thus, in this embodiment, the drive circuit 30 is provided with a third delay circuit 60 that sets the third delay time, which is the delay time for both the rise and fall of the drive signal GL. In this way, both the rise delay time trgl and the fall delay time tfgl of the drive signal GL can be commonly adjusted by the third delay circuit 60. For example, the rise delay time trgl and the fall delay time tfgl can be individually adjusted by the first delay circuit 40 and the second delay circuit 50, and the delay times trgl and tfgl can be commonly adjusted by the third delay circuit 60.

[0046] Also, the third delay circuit 60 sets a third delay time for a signal whose first delay time is set by the first delay circuit 40 and whose second delay time is set by the second delay circuit 50. For example, in FIG. 15, the first delay circuit 40 sets DL1 which is the first delay time, and the third delay circuit 60 sets DL3 which is the third delay time. Also, the second delay circuit 50 sets DL2 which is the second delay time, and the third delay circuit 60 sets DL3 which is the third delay time. In this way, it becomes possible to roughly adjust the rising delay time trgl of the drive signal GL by the delay time DL3 of the third delay circuit 60 while finely adjusting it by the delay time DL1 of the first delay circuit 40. Also, it becomes possible to roughly adjust the falling delay time tfgl of the drive signal GL by the delay time DL3 of the third delay circuit 60 while finely adjusting it by the delay time DL2 of the second delay circuit 50.

[0047] FIG. 16 shows a configuration example of the third delay circuit 60. In FIG. 16, the third delay circuit 60 is composed of a capacitance circuit 62 having a capacitor CGD and a capacitor CGS. The capacitor CGD is provided between the drain and the gate of the transistor TA2. For example, the capacitor CGD is provided between the gate and the drain of the transistor TA2. The capacitor CGS is provided between the gate and the source of the transistor TA2.

[0048] FIG. 17 is an example of a signal waveform for explaining the operation of the third delay circuit 60 in FIG. 16. The waveform of the drive signal GL is dulled by the capacitance circuit 62 having the capacitors CGD and CGS and is input to the gate of the transistor TA2 as a gate drive signal. As a result, as shown in FIG. 17, the gate of the transistor TA2 is driven by a gate drive signal that is substantially delayed by the delay time DL3.

[0049] FIG. 18 shows another configuration example of the third delay circuit 60. In FIG. 18, the third delay circuit 60 is constituted by a capacitive circuit 62 having a capacitor CD and a resistor RD. Also with such a capacitive circuit 62, the gate of the transistor TA2 can be driven by a gate drive signal delayed by a delay time DL3 in the same manner as in FIG. 17.

[0050] Thus, the third delay circuit 60 includes a capacitive circuit 62 that delays the drive signal GL which is the second drive signal. In this way, the capacitor of the capacitive circuit 62 smoothes the drive signal GL, sets the delay time of the drive signal GL, and enables it to be input to the gate of the transistor TA2.

[0051] FIG. 19 shows another configuration example of the circuit device 20 of the present embodiment. In FIG. 19, the drive circuit 30 includes a delay correction circuit 80 that corrects the delay time of the first delay circuit 40 and the delay time of the second delay circuit 50. For example, in FIG. 19, the delay time DL1 of the first delay circuit 40 is set based on the delay setting information SDL1 from the storage unit 90, and the delay time DL2 of the second delay circuit 50 is set based on the delay setting information SDL2 from the storage unit 90. Then, the delay correction circuit 80 corrects the delay times DL1 and DL2 thus set, for example, by outputting delay correction information DC1 and DC2 to the first delay circuit 40 and the second delay circuit 50. In this way, in a situation where the imbalance between the output signals CANH and CANL from the first output terminal TQ1 and the second output terminal TQ2 cannot be appropriately eliminated with the set delay times DL1 and DL2, the delay correction circuit 80 can correct the delay times DL1 and DL2 to appropriate delay times. Therefore, the delay times DL1 and DL2 are corrected to appropriate delay times according to the situation, the imbalance between the output signals CANH and CANL is reduced, and noise can be reduced.

[0052] Specifically, the delay correction circuit 80 corrects the delay times DL1 and DL2 of the first delay circuit 40 and the second delay circuit 50 based on, for example, temperature detection information or the monitoring results of the output signals CANH and CANL of the high-side transistor TA1 and the low-side transistor TA2. For example, the delay correction circuit 80 outputs delay correction information DC1 and DC2 based on temperature detection information from a temperature sensor (not shown) to the first delay circuit 40 and the second delay circuit 50, thereby correcting the delay times DL1 and DL2 to appropriate delay times according to the detected temperature. Alternatively, the delay correction circuit 80 outputs delay correction information DC1 and DC2 based on the monitoring results of the output signals CANH and CANL by the monitoring circuit 70 shown in FIG. 21 described later to the first delay circuit 40 and the second delay circuit 50, thereby correcting the delay times DL1 and DL2 to appropriate delay times according to the monitoring results. For example, when the environmental temperature changes, the delay times DL1 and DL2 may change from the delay times appropriate for noise reduction. Even in such a case, the delay correction circuit 80 can correct the delay times DL1 and DL2 to appropriate delay times according to the environmental temperature. Alternatively, due to changes over time or the like, when the characteristics of the transistors TA1 and TA2 change, the waveforms of the output signals CANH and CANL change, and the delay times DL1 and DL2 may change from the delay times appropriate for noise reduction. Even in such a case, the delay correction circuit 80 can correct the delay times DL1 and DL2 to appropriate delay times according to the output signals CANH and CANL.

[0053] For example, FIG. 20 is a diagram showing the temperature dependence of EMI noise. As shown in FIG. 20, the peak value of the EMI noise changes according to the temperature. Even in this case, the delay correction circuit 80 can set the delay times DL1 and DL2 to appropriate delay times for noise reduction by correcting the delay times DL1 and DL2 of the first delay circuit 40 and the second delay circuit 50 based on the temperature detection information.

[0054] FIG. 21 is a configuration example of a monitoring circuit 70 that monitors the output signals CANH and CANL. This monitoring circuit 70 is provided in the circuit device 20.

[0055] As shown in FIG. 21, the monitor circuit 70 includes operational amplifiers OP1, OP2, OP3, resistors RC1, RC2, RC3, and an AND circuit. The inverted input terminal (first input terminal) of operational amplifier OP1 receives the output signals CANH and CANL respectively via resistors RC1 and RC2. The non-inverted input terminal (second input terminal) of operational amplifier OP1 is set to ground, for example. A resistor RC3 is provided between the output terminal and the inverted input terminal of operational amplifier OP1. Then, the signal SUM from operational amplifier OP1 is input to the inverted input terminals of operational amplifiers OP2 and OP3. The signal SUM is the added signal of the output signals CANH and CANL and corresponds to the sum of the output signals CANH and CANL. The high-potential-side determination voltage VHR is input to the non-inverted input terminal of operational amplifier OP2, and the low-potential-side determination voltage VLR is input to the non-inverted input terminal of operational amplifier OP3. The AND circuit outputs, as the monitor result signal CMP, a signal corresponding to the logical product of the signal HSJ output from operational amplifier OP2 and the inverted signal of the signal LSJX output from operational amplifier OP3.

[0056] FIG. 22 is an example of signal waveforms for explaining the operation of the monitor circuit 70 in FIG. 21. E1 is an example of the waveform of the signal SUM when the noise level is high, and E2 is an example of the waveform of the signal SUM when the noise level is low. The signal SUM corresponds to the sum of the output signals CANH and CANL.

[0057] When the noise level is high, as shown by E3 in FIG. 22, when the voltage of the signal SUM exceeds the determination voltage VHR on the high potential side, as shown by E4, the signal HSJ becomes a low level at the active level, and as shown by E5, the signal CMP of the monitor result becomes a low level at the active level. Also, as shown by E6, when the voltage of the signal SUM falls below the determination voltage VLR on the low potential side, as shown by E7, the signal LSJX becomes a high level at the active level, and as shown by E8, the signal CMP of the monitor result becomes a low level at the active level. On the other hand, when the noise level is low, the signal CMP of the monitor result remains at a high level which is the non-active level. Thus, according to the monitor circuit 70 of FIG. 21, the noise level of the signal SUM corresponding to the sum of the output signals CANH and CANL can be monitored and output as the signal CMP of the monitor result. Then, the delay correction circuit 80 of FIG. 19 receives this signal CMP of the monitor result and corrects the delay times DL1 and DL2, so that the noise caused by the imbalance of the output signals CANH and CANL can be reduced.

[0058] As described above, the circuit device of the present embodiment is a circuit device that drives a differential signal bus, and includes a high-side transistor provided between a power supply node and a first output terminal connected to the differential signal bus, and a low-side transistor provided between a ground node and a second output terminal connected to the differential signal bus. The circuit device also includes a drive circuit that outputs a first drive signal to one of the gates of the high-side transistor and the gates of the low-side transistor, and outputs a second drive signal to the other of the gates of the high-side transistor and the gates of the low-side transistor. The drive circuit includes a first delay circuit that sets a first delay time which is the rising delay time of the second drive signal, and a second delay circuit that sets a second delay time which is the falling delay time of the second drive signal.

[0059] According to this embodiment, the drive circuit outputs a first drive signal and a second drive signal to one of the high-side transistor and the low-side transistor and to the other. Thereby, the differential signal bus is driven by the high-side transistor provided between the power supply node and the first output terminal and the low-side transistor provided between the ground node and the second output terminal. Then, by the first delay circuit and the second delay circuit of the drive circuit, the first delay time of the rising edge and the second delay time of the falling edge of the second drive signal are adjusted separately. In this way, by appropriately adjusting the first delay time and the second delay time, it becomes possible to reduce the noise generated from the differential signal bus.

[0060] Also, in this embodiment, the first delay circuit may set the first delay time based on the first delay setting information, and the second delay circuit may set the second delay time based on the second delay setting information.

[0061] In this way, based on the first delay setting information and the second delay setting information, it becomes possible to set the first delay time of the rising edge and the second delay time of the falling edge of the second drive signal to an arbitrary length, and it becomes possible to reduce the noise generated from the differential signal bus.

[0062] Also, in this embodiment, it may include a storage unit that stores the first delay setting information and the second delay setting information.

[0063] In this way, the first delay circuit and the second delay circuit can set the first delay time of the rising edge and the second delay time of the falling edge of the second drive signal to an appropriate delay time based on the first delay setting information and the second delay setting information read from the storage unit.

[0064] Also, in this embodiment, the low-side transistor is an N-type transistor, and the drive circuit may output the second drive signal to the gate of the N-type transistor.

[0065] By doing so, the first delay time of the rising edge and the second delay time of the falling edge of the second drive signal can be set by the first delay circuit and the second delay circuit, reducing the waveform imbalance of the output signals from the first output terminal and the second output terminal and enabling reduction of noise in the differential signal bus.

[0066] Also, in this embodiment, the length of the first delay time and the length of the second delay time may be different.

[0067] By doing so, the waveform imbalance of the output signals from the first output terminal and the second output terminal can be reduced, enabling reduction of noise caused by the waveform imbalance.

[0068] Also, in this embodiment, the first delay circuit may include a first delay unit that delays the input signal of the first delay circuit and a logical sum circuit that outputs the logical sum of the input signal and the output signal of the first delay unit.

[0069] By doing so, the first delay time of the second drive signal can be set according to the delay time of the first delay unit of the first delay circuit 40.

[0070] Also, in this embodiment, the second delay circuit may include a second delay unit that delays the input signal of the second delay circuit and a logical product circuit that outputs the logical product of the input signal and the output signal of the second delay unit.

[0071] By doing so, the second delay time of the second drive signal can be set according to the delay time of the second delay unit of the second delay circuit.

[0072] Also, in this embodiment, the drive circuit may include a third delay circuit that sets a third delay time which is the delay time for both the rising edge and the falling edge of the second drive signal.

[0073] By doing so, both the first delay time of the rising edge and the second delay time of the falling edge of the second drive signal can be commonly adjusted by the third delay circuit.

[0074] Also, in the present embodiment, the third delay circuit may set a third delay time for a signal whose first delay time is set by the first delay circuit and whose second delay time is set by the second delay circuit.

[0075] In this way, it becomes possible to roughly adjust the first delay time of the rising edge of the second drive signal by the third delay time of the third delay circuit while finely adjusting it by the delay time of the first delay circuit. Also, it becomes possible to roughly adjust the second delay time of the falling edge of the second drive signal by the third delay time of the third delay circuit while finely adjusting it by the delay time of the second delay circuit.

[0076] Also, in the present embodiment, the third delay circuit may include a capacitance circuit that delays the second drive signal.

[0077] In this way, the second drive signal is dulled by the capacitance of the capacitance circuit, the delay time of the second drive signal is set, and it can be input to the gate of the transistor.

[0078] Also, in the present embodiment, the drive circuit may include a delay correction circuit that corrects the delay time of the first delay circuit and the delay time of the second delay circuit.

[0079] In this way, in a situation where the imbalance of the output signals from the first output terminal and the second output terminal cannot be appropriately eliminated at the set delay time, the delay correction circuit can correct the delay time of the first delay circuit and the delay time of the second delay circuit to appropriate delay times.

[0080] Also, in the present embodiment, the delay correction circuit may correct the delay time of the first delay circuit and the delay time of the second delay circuit based on temperature detection information or the monitoring result of the output signals of the high-side transistor and the low-side transistor.

[0081] In this way, even when the delay time of the first delay circuit and the delay time of the second delay circuit change from the delay time appropriate for noise reduction, the delay correction circuit can correct the delay time of the first delay circuit and the delay time of the second delay circuit to the appropriate delay time according to the output signal.

[0082] Although the present embodiment has been described in detail as above, those skilled in the art will easily understand that many modifications can be made without substantially departing from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, in the specification or drawings, a term described at least once together with a broader or synonymous different term can be replaced with the different term at any location in the specification or drawings. Also, all combinations of the present embodiment and the modifications are included within the scope of the present disclosure. Further, the configuration, operation, etc. of the circuit device are not limited to those described in the present embodiment, and various modifications can be implemented.

Explanation of Reference Numerals

[0083] 20... Circuit device, 30... Driving circuit, 40... First delay circuit, 42... First delay unit, 50... Second delay circuit, 52... Second delay unit, 60... Third delay circuit, 62... Capacitance circuit, 70... Monitor circuit, 80... Delay correction circuit, 90... Storage unit, 100... Measurement system, 210... Common mode choke coil, AN, AND... Logical product circuit, BF1~BF5... Buffer circuit, BS... Differential signal bus, CANH, CANL... Output signal, CB1, CB2, CD, CGD, CGS... Capacitor, DC1, DC2... Delay correction information, DH, DL... Output signal, DL1, DL2, DL3... Delay time, GH, GL... Driving signal, IVA... Inverter circuit, L1, L2... Coil, NV, NG... Node, OP1~OP3... Operational amplifier, OR... Logical sum circuit, RB1~RB5, RC1~RC3, RD... Resistor, RT1, RT2... Terminal resistor, SDL1, SDL2, SDL3... Delay setting information, SW... Switch circuit, TA1, TA2... Transistor, TQ1... First output terminal, TQ2... Second output terminal, TXD... Signal, VHR, VLR... Judgment voltage, trgl, tfgl, trgh, tfgh... Delay time

Claims

1. A circuit device for driving a differential signal bus, comprising: a high-side transistor provided between a power supply node and a first output terminal connected to the differential signal bus; a low-side transistor provided between a ground node and a second output terminal connected to the differential signal bus; a drive circuit configured to output a first drive signal to one of the gates of the high-side transistor and the low-side transistor and output a second drive signal to the other of the gates of the high-side transistor and the low-side transistor; wherein the drive circuit includes: a first delay circuit configured to set a first delay time which is a rising delay time of the second drive signal; a second delay circuit configured to set a second delay time which is a falling delay time of the second drive signal. A circuit device, characterized in that it comprises the above.

2. The circuit device according to claim 1, wherein: the first delay circuit is configured to set the first delay time based on first delay setting information; the second delay circuit is configured to set the second delay time based on second delay setting information. A circuit device, characterized in that it has the above configuration.

3. The circuit device according to claim 2, further comprising a storage unit configured to store the first delay setting information and the second delay setting information.

4. The circuit device according to any one of claims 1 to 3, wherein: the low-side transistor is an N-type transistor; the drive circuit is configured to output the second drive signal to the gate of the N-type transistor. A circuit device, characterized in that it has the above configuration.

5. The circuit device according to any one of claims 1 to 3, wherein the length of the first delay time is different from the length of the second delay time.

6. The circuit device according to any one of claims 1 to 3, wherein the first delay circuit includes: a first delay unit configured to delay an input signal of the first delay circuit; a logical sum circuit configured to output a logical sum of the input signal and an output signal of the first delay unit. A circuit device, characterized in that it comprises the above.

7. The circuit device according to any one of claims 1 to 3, wherein the second delay circuit includes: a second delay unit configured to delay an input signal of the second delay circuit; a logical product circuit configured to output a logical product of the input signal and an output signal of the second delay unit. A circuit device, characterized in that it comprises the above.

8. ​ ​ ​ ​ ​ ​ In the circuit device according to any one of claims 1 to 3, the drive circuit includes a third delay circuit that sets a third delay time which is the delay time of both the rise and fall of the second drive signal, and is characterized by the circuit device.

9. In the circuit device according to claim 8, the third delay circuit is characterized by setting the third delay time for a signal in which the first delay time is set by the first delay circuit and the second delay time is set by the second delay circuit, and is characterized by the circuit device.

10. In the circuit device according to claim 8, the third delay circuit includes a capacitive circuit that delays the second drive signal, and is characterized by the circuit device.

11. In the circuit device according to any one of claims 1 to 3, the drive circuit includes a delay correction circuit that corrects the delay time of the first delay circuit and the delay time of the second delay circuit, and is characterized by the circuit device.

12. In the circuit device according to claim 11, the delay correction circuit corrects the delay time of the first delay circuit and the delay time of the second delay circuit based on temperature detection information or a monitoring result of output signals of the transistor on the high side and the transistor on the low side, and is characterized by the circuit device.

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