Display device

Abstract

To suppress deterioration of display quality.SOLUTION: A display device 11 comprises: a switching element 24; a first electrode 25 connected to the switching element 24; first wiring 27 connected to the switching element 24, located on a lower layer side from the first electrode 25, and transmitting an image signal supplied to the first electrode 25; a second electrode 38 located on an upper layer side from the first wiring 27, having a reflective layer 38B that reflects light and has an uneven surface 38S; a third electrode 37 located on the lower layer side from the first electrode 25 and the upper layer side from the first wiring 27, disposed so as to overlap at least each of the first electrode 25 and the first wiring 27, and set to a common potential; a first insulating film 35 interposed between the first electrode 25 and the third electrode 37; and a second insulating film 34 located on the upper layer side from the first wiring 27, disposed on the lower layer side to the third electrode 37, having a film thickness greater than that of the first insulating film 35.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The technology disclosed in this specification relates to a display device.

Background Art

[0002] Conventionally, as an example of a display device, the one described in Patent Document 1 below is known. Patent Document 1 describes a reflective liquid crystal display element as a display device. The reflective liquid crystal display element described in Patent Document 1 includes a reflector, a counter substrate facing the reflector, and a liquid crystal layer sandwiched between the reflector and the counter substrate. The reflector has a photosensitive resin layer provided on a glass substrate, the surface layer portion of which is a plurality of uneven surfaces inclined in a certain direction, and a reflective film provided on the photosensitive resin layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the reflective liquid crystal display element described in Patent Document 1 mentioned above, although the reflective film having an uneven surface functions as a pixel electrode, there is no configuration for holding the potential of the reflective film charged with the driving of the TFT. To hold the potential of the reflective film, for example, a common electrode that overlaps the reflective film via an insulating film may be provided, and a method of forming a holding capacitor between the reflective film and the common electrode may be adopted. However, in the reflective liquid crystal display element described in Patent Document 1 mentioned above, when a configuration of providing a common electrode that overlaps the reflective film having an uneven surface via an insulating film is adopted, the common electrode has an uneven shape following the reflective film. For this reason, there has been a problem that it is difficult to keep the distance between the common electrode and the reflective film constant over the entire area. If the distance between the common electrode and the reflective film varies, the holding capacitor may not be stabilized, and the display quality may deteriorate.

[0005] The technology described in this specification has been completed based on the above circumstances, and an object thereof is to suppress a decrease in display quality.

Means for Solving the Problems

[0006] (1) The display device related to the technology described in this specification includes a switching element, a first electrode connected to the switching element, a first wiring connected to the switching element, located on the lower layer side of the first electrode, and transmitting an image signal supplied to the first electrode, a second electrode located on the upper layer side of the first wiring, having a reflective layer that reflects light, and the reflective layer having an uneven surface, and a third electrode located on the upper layer side of the first wiring and on the lower layer side of the first electrode, arranged to overlap at least each of the first electrode and the first wiring, and having a common potential, a first insulating film interposed between the first electrode and the third electrode, and a second insulating film located on the upper layer side of the first wiring, arranged on the lower layer side of the third electrode, and having a larger film thickness than the first insulating film.

[0007] (2) Further, in addition to the above (1), the display device may be provided with a third insulating film, wherein the second electrode is disposed on the upper layer side of the first electrode, interposed between the second electrode and the first electrode, and having a film thickness larger than that of the first insulating film.

[0008] (3) Further, in addition to the above (2), the display device includes a fourth electrode disposed opposite to the second electrode with a space therebetween and having a common potential, and a liquid crystal layer interposed between the second electrode and the fourth electrode. The second electrode is disposed so as to overlap the first electrode, and a first contact hole for connecting the second electrode to the first electrode may be provided and opened at a position where the third insulating film overlaps both the second electrode and the first electrode.

[0009] (4) Further, in addition to the above (1), the display device may be provided with a fourth insulating film, wherein the second electrode is disposed on the lower layer side of the second insulating film, located on the upper layer side of the first wiring, disposed on the lower layer side of the second electrode, and having a film thickness larger than that of the first insulating film.

[0010] (5) Further, in addition to the above (4), the second electrode may have the common potential.

[0011] (6) Further, in addition to the above (5), a plurality of the first electrodes may be arranged side by side with a space therebetween, and the second electrode may be disposed in a range straddling the plurality of first electrodes.

[0012] (7) Further, in addition to any one of (4) to (6) above, the display device includes a fifth electrode disposed on the lower layer side with respect to the second insulating film and on the upper layer side with respect to the fourth insulating film. The second electrode has a transparent electrode film disposed on the lower layer side with respect to the reflective layer. The fifth electrode is part of the transparent electrode film, and is disposed so as to overlap a part of the switching element and a part of the first electrode. In the fourth insulating film, at a position overlapping both the switching element and the fifth electrode, a second contact hole for connecting the fifth electrode to the switching element is provided and opened. In the second insulating film, at a position overlapping both the first electrode and the fifth electrode, a third contact hole for connecting the first electrode to the fifth electrode may be provided and opened.

[0013] (8) Further, in addition to (7) above, the display device may include a sixth electrode disposed opposite to the first electrode with a space therebetween and having a common potential, and a liquid crystal layer interposed between the first electrode and the sixth electrode.

[0014] (9) Further, in addition to any one of (1) to (8) above, the display device includes a second wiring connected to the switching element, intersecting the first wiring, and transmitting a scanning signal, a fifth insulating film disposed on the upper layer side with respect to the first wiring and on the lower layer side with respect to the second wiring, and a third wiring disposed on the lower layer side with respect to the fifth insulating film and overlapping the second wiring. In the fifth insulating film, at a position overlapping both the second wiring and the third wiring, a fourth contact hole for connecting the second wiring to the third wiring may be provided and opened.

Advantages of the Invention

[0015] According to the technology described in this specification, a decrease in display quality can be suppressed.

Brief Description of the Drawings

[0016]

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Mode for Carrying Out the Invention

[0017] <Embodiment 1> Embodiment 1 will be described with reference to FIGS. 1 to 11. In this embodiment, a transflective liquid crystal display device 10 will be exemplified. Note that the X-axis, Y-axis, and Z-axis are shown in part of each drawing, and are drawn so that the directions of the respective axes are the directions shown in each drawing. Also, the upper side of FIGS. 1, 4, 5, 8, and 11 is the front side, and the lower side of the same figure is the back side.

[0018] As shown in FIG. 1, the transflective liquid crystal display device 10 includes a transflective liquid crystal panel (display device) 11 that displays an image, and a backlight device (lighting device) that irradiates light onto the liquid crystal panel 11. The transflective liquid crystal panel 11 can perform both a reflective display that reflects external light (ambient light, environmental light) for display and a transmissive display that transmits light (backlight light) irradiated from the backlight device for display. The external light used in the reflective display includes sunlight, indoor lighting, and the like. In the liquid crystal panel 11, the central portion of the screen is a display area where an image is displayed, and the frame-shaped outer peripheral portion surrounding the display area of the screen is a non-display area where no image is displayed. The backlight device is disposed on the back side (lower side shown in FIG. 1) with respect to the liquid crystal panel 11, and has a light source (e.g., an LED) that emits white light (white light) and an optical member that converts the light from the light source into planar light by imparting an optical action to the light, and the like.

[0019] As shown in FIG. 1, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21. The front side (front surface side) of the pair of substrates 20 and 21 is the counter substrate (second substrate, CF substrate) 20, and the back side (back surface side) is the array substrate (first substrate) 21. Both the counter substrate 20 and the array substrate 21 are formed by laminating various films on the inner surface side of glass substrates (substrates) 20GS and 21GS made of a glass material. As the glass material used for each of the glass substrates 20GS and 21GS, for example, alkali-free glass or the like is used. A predetermined interval is provided between the pair of substrates 20 and 21, and a liquid crystal layer 22 is provided therebetween. The liquid crystal layer 22 contains liquid crystal molecules, which are substances whose optical properties change with the application of an electric field. A seal portion 23 for sealing the liquid crystal layer 22 is provided between the outer peripheral ends of the pair of substrates 20 and 21. The seal portion 23 is made of a photocurable resin material, a thermosetting resin material, or the like, and is formed in a frame shape (endless ring shape) so as to surround the liquid crystal layer 22. Polarizing plates 14 are attached to the outer surface sides of both substrates 20 and 21, respectively.

[0020] As shown in FIG. 1, the opposing substrate 20 is shorter in the Y-axis direction than the array substrate 21 in the Y-axis direction. The opposing substrate 20 is bonded to the array substrate 21 such that one end in the Y-axis direction is aligned. Therefore, the other end of the array substrate 21 in the Y-axis direction is an exposed portion 21A that protrudes laterally and is exposed with respect to the opposing substrate 20. A driver (signal supply unit) 12 and a flexible substrate 13 for supplying various signals related to the display function described below are mounted on the exposed portion 21A.

[0021] The driver 12 is composed of an LSI chip having a drive circuit inside. As shown in FIG. 1, the driver 12 is COG (Chip On Glass) mounted on the exposed portion 21A of the array substrate 21. The driver 12 processes various signals transmitted by the flexible substrate 13. The flexible substrate 13 is configured to form a plurality of wiring patterns on a base material made of a synthetic resin material (for example, a polyimide-based resin, etc.) having insulation and flexibility. One end side of the flexible substrate 13 is connected to the exposed portion 21A of the array substrate 21, and the other end side is connected to an external circuit board (such as a control board). The driver 12 and the flexible substrate 13 supply various signals (such as a scan signal, an image signal, etc.) to the backplane circuit (gate wiring 26, source wiring 27, etc.) provided in the liquid crystal panel 11.

[0022] The outline of the configuration provided in the display area of the array substrate 21 will be described with reference to FIGS. 2 and 3. As shown in FIGS. 2 and 3, at least a TFT (transistor, switching element) 24 and a pixel electrode (first electrode) 25 are provided on the inner surface side in the display area of the array substrate 21. A plurality of the TFTs 24 and pixel electrodes 25 are arranged at intervals along the X-axis direction and the Y-axis direction and provided in a matrix (row and column) form. Around these TFTs 24 and pixel electrodes 25, gate wirings (second wirings, scanning wirings) 26 and source wirings (first wirings, image wirings, signal wirings) 27 that are orthogonal (cross) to each other are disposed. The gate wiring 26 extends along the X-axis direction, and a plurality of them are arranged at intervals in the Y-axis direction. The gate wiring 26 is configured to transmit a scanning signal for driving the TFT 24. The source wiring 27 extends along the Y-axis direction, and a plurality of them are arranged at intervals in the X-axis direction. The source wiring 27 is configured to transmit an image signal for charging the pixel electrode 25. The pixel electrode 25, together with a color filter 28 described below, constitutes a pixel that is a display unit. The TFT 24, the gate wiring 26, and the source wiring 27 constitute a backplane circuit for driving the pixels.

[0023] The outline of the configuration provided in the display area of the counter substrate 20 will be described with reference to FIG. 4. As shown in FIG. 4, on the inner surface side of the display area AA of the counter substrate 20, three-color color filters 28 that exhibit blue (B), green (G), and red (R) are provided. A plurality of color filters 28 that exhibit different colors are arranged side by side so as to be adjacent in the X-axis direction. A plurality of color filters 28 that exhibit different colors extend along the Y-axis direction. In this way, a plurality of color filters 28 that exhibit different colors are arranged in a stripe pattern of vertical stripes as a whole. These color filters 28 are arranged so as to overlap with each pixel electrode 25 on the array substrate 21 side in a planar view. The color filter 28 and the pixel electrode 25 that overlap each other constitute a pixel that is a display unit. A plurality of color filters 28 that exhibit different colors are arranged so that their boundaries (color boundaries) overlap with the source wiring 27. An overcoat film 29 is provided on the upper layer side (liquid crystal layer 22 side) of the color filter 28 for flattening. The overcoat film 29 is arranged in a solid state over almost the entire area of the counter substrate 20.

[0024] On the upper layer side of the overcoat film 29, as shown in FIG. 4, a counter electrode (fourth electrode) 30 is provided. The counter electrode 30 has a viscous shape similar to that of the overcoat film 29 and is provided over at least the entire display region. The counter electrode 30 is made of a transparent electrode material. A common potential is supplied to the counter electrode 30. Therefore, an electric field is generated between the counter electrode 30 and the pixel electrode 25 charged by the TFT 24, and it is possible to control the alignment state of the liquid crystal molecules contained in the liquid crystal layer 22 by this electric field. The liquid crystal panel 11 according to the present embodiment has a display mode of VA (Vertical Alignment) mode. The VA mode is a display mode in which liquid crystal molecules are vertically aligned with respect to the main surface of the glass substrate, and the alignment state of the liquid crystal molecules is switched by a vertical electric field. Further, on the upper layer side of the counter electrode 30, a spacer 31 protruding toward the array substrate 21 side is provided (see FIG. 2). The spacer 31 is configured such that the protruding tip surface can contact the inner surface of the array substrate 21, and thereby it is possible to maintain the interval between the pair of substrates 20 and 21, that is, the cell gap (the thickness of the liquid crystal layer 22). Note that, on the innermost surface (uppermost layer) of both substrates 20 and 21 that is in contact with the liquid crystal layer 22, alignment films for aligning the liquid crystal molecules contained in the liquid crystal layer 22 are respectively formed.

[0025] Next, various films laminated on the inner surface side of the array substrate 21 will be described with reference to FIGS. 4 and 5. As shown in FIGS. 4 and 5, on the array substrate 21, in order from the lower layer side (glass substrate 21GS side), a first metal film (first conductive film), a gate insulating film (fifth insulating film) 32, a semiconductor film, a second metal film (second conductive film), an interlayer insulating film 33, a first planarization film (second insulating film, first organic insulating film) 34, a first transparent electrode film (third conductive film), an inter-electrode insulating film (first insulating film) 35, a second transparent electrode film (fourth conductive film), a second planarization film (third insulating film, second organic insulating film) 36, a third transparent electrode film (fifth conductive film), a third metal film (sixth conductive film), and an alignment film are laminated and formed.

[0026] The first metal film, the second metal film, and the third metal film are each a single-layer film made of one type of metal material selected from among copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different types of metal materials, and thus have conductivity, light reflectivity, and light-shielding properties. The first metal film constitutes the gate wiring 26, the gate electrode 24A of the TFT 24, etc. The second metal film constitutes the source wiring 27, the source electrode 24B and the drain electrode 24C of the TFT 24, etc. The third metal film constitutes a part of the reflection electrode 38 to be described later. The semiconductor film is made of a thin film using a semiconductor material such as an oxide semiconductor as a material, and constitutes the semiconductor part 24D etc. in the TFT 24. The first transparent electrode film, the second transparent electrode film, and the third transparent electrode film are made of a transparent electrode material (for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), etc.). The first transparent electrode film constitutes the common electrode 37 to be described later. The second transparent electrode film constitutes the pixel electrode 25, etc. The third transparent electrode film constitutes a part of the reflection electrode 38 to be described later.

[0027] The gate insulating film 32, the interlayer insulating film 33, and the inter-electrode insulating film 35 are each silicon nitride (SiN x ) and silicon oxide (SiO 2It is made of an inorganic insulating material such as []. The first planarization film 34 and the second planarization film 36 are made of an organic insulating material such as PMMA (acrylic resin), for example. The first planarization film 34 and the second planarization film 36 have a thickness greater than the thicknesses of the gate insulating film 32, the interlayer insulating film 33, and the inter-electrode insulating film 35 made of an inorganic insulating material, and are, for example, about 1 μm to 3 μm. The structure (common electrode 37) composed of the first transparent electrode film located on the upper layer side thereof is planarized by the first planarization film 34. The degree of freedom regarding the cross-sectional shape of the structure (reflective electrode 38) composed of the first transparent electrode film located on the upper layer side thereof is ensured by the second planarization film 36. The gate insulating film 32 keeps the first metal film on the lower layer side and the semiconductor film and the second metal film on the upper layer side in an insulated state. The interlayer insulating film 33 and the first planarization film 34 keep the semiconductor film and the second metal film on the lower layer side and the first transparent electrode film on the upper layer side in an insulated state. The inter-electrode insulating film 35 keeps the first transparent electrode film on the lower layer side and the second transparent electrode film on the upper layer side in an insulated state. The second planarization film 36 keeps the second transparent electrode film on the lower layer side and the third transparent electrode film on the upper layer side in an insulated state.

[0028] The structure of TFT24 will be described in detail with reference to FIGS. 5 and 6. FIG. 6 shows a pixel array in the same range as FIG. 3. In FIG. 6, the first metal film and the second metal film provided on the array substrate 21 are shown in different mesh patterns. As shown in FIGS. 5 and 6, TFT24 has a gate electrode 24A made of the first metal film. The gate electrode 24A branches from the gate wiring 26. Specifically, the gate electrode 24A is formed by extending a part of the gate wiring 26 along the Y-axis direction toward the pixel electrode 25 to be connected, and has a substantially vertically long rectangular shape when viewed in plan. A scanning signal transmitted through the gate wiring 26 is supplied to the gate electrode 24A. TFT24 has a source electrode 24B made of the second metal film. The source electrode 24B branches from the source wiring 27. Specifically, the source electrode 24B is formed by extending a part of the source wiring 27 along the X-axis direction toward the pixel electrode 25 to be connected, then bending it toward the gate wiring 26 and extending it along the Y-axis direction, and has a substantially L-shaped when viewed in plan. A part of the source electrode 24B on the extending tip side from the source wiring 27 (the right side part in FIG. 6) is connected to a semiconductor part 24D described below and is arranged to overlap the gate electrode 24A.

[0029] As shown in FIGS. 5 and 6, TFT24 has a drain electrode 24C made of the second metal film. The drain electrode 24C generally extends in an island shape along the Y-axis direction as a whole. One end (the lower side in FIG. 6) of it is connected to a semiconductor part 24D described below at a position spaced apart from the source electrode 24B in the X-axis direction and is arranged to overlap the gate electrode 24A. The other end (the upper side in FIG. 6) of the drain electrode 24C has a horizontally long rectangular shape, and this is connected to the pixel electrode 25. Note that the drain electrode 24C is arranged to overlap the pixel electrode 25 over its entire area. A pixel contact hole CH1 is formed at an opening at a position overlapping both the other end of the drain electrode 24C and a part of the pixel electrode 25 among the interlayer insulating film 33 and the first planarization film 34. The pixel electrode 25 is connected to the drain electrode 24C through the pixel contact hole CH1.

[0030] As shown in FIGS. 5 and 6, the TFT 24 has a semiconductor portion 24D made of a semiconductor film. The semiconductor portion 24D has a substantially square shape when viewed in plan. One end (the left side in FIG. 6) of the semiconductor portion 24D in the X-axis direction is connected to the source electrode 24B, and the other end (the right side in FIG. 6) in the X-axis direction is connected to the drain electrode 24C. The semiconductor portion 24D is disposed so as to overlap the gate electrode 24A with a gate insulating film 32 interposed therebetween. When the TFT 24 is turned on based on the scanning signal supplied to the gate electrode 24A, the image signal supplied from the source wiring 27 to the source electrode 24B is supplied to the drain electrode 24C through the semiconductor portion 24D. As a result, the pixel electrode 25 is charged to the potential based on the image signal.

[0031] The configuration of the pixel electrode 25 will be described in detail with reference to FIGS. 4, 7, and 8. FIG. 7 shows a pixel array in the same range as FIG. 3. In FIG. 7, the second transparent electrode film provided on the array substrate 21 is shown in a hatched pattern. As shown in FIG. 7, the pixel electrode 25 is disposed in a region surrounded by the gate wiring 26 and the source wiring 27, and has a substantially vertically long square planar shape. The pixel electrode 25 is disposed so as to overlap substantially the entire area of the TFT 24. The pixel electrode 25 is made of the second transparent electrode film and is located on the upper layer side of both the gate wiring 26 and the source wiring 27 as shown in FIGS. 4 and 8. As shown in FIGS. 7 and 8, the dimension of the pixel electrode 25 in the Y-axis direction is slightly larger than the arrangement interval of the gate wiring 26. Therefore, the pixel electrode 25 partially overlaps the gate wiring 26, and the outer edge portion along the X-axis direction is located closer to the center in the line width direction (Y-axis direction) of the gate wiring 26 than the side edge portion of the gate wiring 26. As shown in FIGS. 4 and 7, the dimension of the pixel electrode 25 in the X-axis direction is substantially equal to the arrangement interval of the source wiring 27. Therefore, the outer edge portion of the pixel electrode 25 along the Y-axis direction is disposed so as to overlap the side edge portion of the source wiring 27.

[0032] As shown in FIGS. 4 and 8, the array substrate 21 is provided with a common electrode (third electrode, holding capacitance electrode) 37 for forming a holding capacitance with the pixel electrode 25. Hereinafter, the configuration of the common electrode 37 will be described in detail with reference to FIGS. 4, 5, 8, and 9. FIG. 9 shows a pixel array in the same range as FIG. 3. In FIG. 9, the first transparent electrode film provided on the array substrate 21 is shown in a mesh pattern. As shown in FIGS. 4, 8, and 9, the common electrode 37 is disposed in a solid state over substantially the entire display area. The common electrode 37 is made of a first transparent electrode film and is disposed so as to overlap the lower layer side of all the pixel electrodes 25 disposed in the display area with an inter-electrode insulating film 35 interposed therebetween. The common electrode 37 made of the first transparent electrode film is located on the upper layer side of both the gate wiring 26 and the source wiring 27. Since the common electrode 37 also exists in the region (inter-pixel region) between adjacent pixel electrodes 25 in the X-axis direction and the Y-axis direction, it is disposed so as to overlap the gate wiring 26 and the source wiring 27. A common potential signal, which is set to a common potential (reference potential) by a backplane circuit, is supplied to the common electrode 37. Since the common electrode 37 set to the common potential is disposed so as to overlap the pixel electrode 25 charged by the TFT 24 with the inter-electrode insulating film 35 interposed therebetween, a holding capacitance is formed between the pixel electrode 25 and the common electrode 37. By using this holding capacitance, the potential of the charged pixel electrode 25 can be favorably held. Further, as shown in FIG. 5, a first opening 37A for passing the pixel electrode 25 is provided at a position of the common electrode 37 that overlaps the pixel contact hole CH1. A short circuit between the pixel electrode 25 and the common electrode 37 is avoided by the first opening 37A.

[0033] Thus, in this embodiment, as shown in FIGS. 4 and 5, a common electrode 37 having a common potential is disposed at a position above the source wiring 27 and below the pixel electrode 25, so that the parasitic capacitance that may occur between the source wiring 27 and the pixel electrode 25 can be suppressed. Moreover, since the first planarization film 34, which is located above the source wiring 27 and disposed below the common electrode 37, has a greater film thickness than the inter-electrode insulating film 35, the flatness of the common electrode 37 located above the first planarization film 34 is sufficiently ensured. By ensuring the flatness of the common electrode 37, the flatness of the pixel electrode 25 disposed above the common electrode 37 via the inter-electrode insulating film 35 is also ensured. Therefore, compared with the case where a common electrode is provided to overlap with a reflective layer having an uneven surface via an insulating film as in the prior art, variations in the distance between the pixel electrode 25 and the common electrode 37 are less likely to occur. As a result, the holding capacitance formed between the pixel electrode 25 and the common electrode 37 is stabilized, and thus the display quality is less likely to deteriorate.

[0034] As shown in FIGS. 4 and 8, the array substrate 21 is provided with a reflective electrode (second electrode) 38 for performing reflective display using external light. Hereinafter, the configuration of the reflective electrode 38 will be described in detail with reference to FIGS. 4, 5, 8, and 10. FIG. 10 shows a pixel array in the same range as FIG. 3. In FIG. 10, the third transparent electrode film and the third metal film provided on the array substrate 21 are shown in different mesh patterns. As shown in FIG. 5, the reflective electrode 38 has a laminated structure including a transparent electrode layer 38A and a reflective layer 38B laminated on the upper layer side of the transparent electrode layer 38A. The transparent electrode layer 38A is made of a third transparent electrode film and can efficiently transmit light. The reflective layer 38B is made of a third metal film and can efficiently reflect light. Thus, the reflective electrode 38 is disposed on the upper layer side of the pixel electrode 25 made of the second transparent electrode film. The cross-sectional shape of the reflective electrode 38 is uneven, and the reflective layer 38B disposed on the surface layer thereof has an uneven surface 38S. The uneven surface 38S includes a plurality of convex portions 38S1 and concave portions 38S2, and these convex portions 38S1 and concave portions 38S2 are alternately repeated and arranged in the uneven surface 38S. Such a cross-sectional shape of the reflective electrode 38 reflects the cross-sectional shape of the second planarization film 36 that is the base of the reflective electrode 38. To make the cross-sectional shape of the second planarization film 36 uneven, for example, the material of the second planarization film 36 may be a photosensitive organic insulating material, and the formed second planarization film 36 may be exposed and developed using a halftone mask or a grayscale mask having a pattern reflecting the uneven shape. Thus, since the reflective layer 38B of the reflective electrode 38 has the uneven surface 38S, external light can be diffusely reflected, thereby realizing a display close to paper white. Note that the alignment film disposed on the upper layer side of the reflective electrode 38 has an uneven cross-sectional shape following the reflective electrode 38.

[0035] As shown in FIG. 10, the reflective electrode 38 is disposed in a region surrounded by the gate wiring 26 and the source wiring 27, and has a substantially rectangular shape with a vertically long planar shape. The reflective electrode 38 has a dimension in the Y-axis direction slightly larger than the arrangement pitch of the gate wiring 26, and a dimension in the X-axis direction substantially equal to the arrangement pitch of the source wiring 27. That is, the reflective electrode 38 has substantially the same size as the pixel electrode 25 when viewed in the plane, and is arranged so as to overlap the pixel electrode 25 in the plane over substantially the entire area. Then, as shown in FIG. 5, the reflective electrode 38 is connected to the pixel electrode 25. An electrode-to-electrode contact hole (first contact hole) CH2 is formed in the second planarization film 36 interposed between the transparent electrode layer 38A constituting the reflective electrode 38 and the pixel electrode 25. The electrode-to-electrode contact hole CH2 is disposed at a position (specifically, on the right side of FIG. 5 with respect to the pixel contact hole CH1) that overlaps both the transparent electrode layer 38A and the pixel electrode 25 in the second planarization film 36. The reflective electrode 38 has the same potential as the pixel electrode 25 when the transparent electrode layer 38A is connected to the pixel electrode 25 through the electrode-to-electrode contact hole CH2. Therefore, when the pixel electrode 25 is charged as the TFT 24 is driven, the reflective electrode 38 is also charged to the same potential as the pixel electrode 25, and the pixel electrode 25 forms a holding capacitance with the common electrode 37, so that the potential of the reflective electrode 38 is also well held. Since the reflective electrode 38 is arranged closer to the liquid crystal layer 22 than the alignment film on the array substrate 21, an electric field with sufficient strength is generated between the reflective electrode 38 and the counter electrode 30 facing each other across the liquid crystal layer 22. By controlling the alignment state of the liquid crystal molecules contained in the liquid crystal layer 22 by this electric field, the amount of light emitted toward the front side of the liquid crystal panel 11 during display is controlled for each pixel, and thus a predetermined image can be displayed in the display area. Note that an opening 30A is provided at a position overlapping the electrode-to-electrode contact hole CH2 in the counter electrode 30 provided on the counter substrate 20 as a structure for regulating the alignment of the liquid crystal molecules contained in the liquid crystal layer 22.

[0036] As shown in FIGS. 4, 8, and 10, the reflective electrode 38 has a transmissive opening 38C formed by partially cutting out the reflective layer 38B. The transmissive opening 38C is provided in the reflective layer 38B of the reflective electrode 38 but not formed in the transparent electrode layer 38A. The transmissive opening 38C is located near the center of the reflective electrode 38 in the X-axis direction and is arranged at a position sandwiching the electrode-to-electrode contact hole CH2 between the pixel-to-pixel contact hole CH1 in the Y-axis direction. The transmissive opening 38C has a substantially square planar shape with its four corners cut obliquely. Light irradiated from the backlight device toward the liquid crystal panel 11 can pass through the transparent electrode layer 38A and exit to the front side through the transmissive opening 38C in the reflective layer 38B. Thereby, in addition to the reflective display using external light, it becomes possible to perform a transmissive display using the light from the backlight device.

[0037] Thus, in the present embodiment, as shown in FIGS. 4, 5, and 8, since the reflective electrode 38 is arranged on the upper layer side of the pixel electrode 25, the reflected light by the reflective layer 38B of the reflective electrode 38 does not pass through the pixel electrode 25. Therefore, the light can be reflected by the reflective layer 38B of the reflective electrode 38 with low loss and used for image display. Since the film thickness of the second planarization film 36 arranged on the lower layer side of the reflective electrode 38 is larger than the film thickness of the inter-electrode insulating film 35, the certainty that the cross-sectional shape of the second planarization film 36 is formed as designed is increased. Therefore, the reproducibility regarding the shape of the uneven surface 38S of the reflective layer 38B of the reflective electrode 38 is high.

[0038] As shown in FIGS. 4 and 11, the array substrate 21 is provided with redundant wiring (third wiring) 39 connected to the source wiring 27. Hereinafter, the configuration of the redundant wiring 39 will be described in detail with reference to FIGS. 4, 6, and 11. As shown in FIGS. 4 and 11, the redundant wiring 39 is made of a first metal film and is arranged to overlap the source wiring 27 to be connected. As shown in FIG. 6, the redundant wiring 39 extends along the Y-axis direction so as to be parallel to the source wiring 27. The redundant wiring 39 has a line width larger than that of the source wiring 27, for example, about three times. The redundant wiring 39 is arranged to be concentric with the source wiring 27 in the line width direction (X-axis direction), and has a central portion overlapping the source wiring 27 and a pair of side portions sandwiching the central portion. Therefore, in the redundant wiring 39, a pair of side portions sandwiching the central portion are arranged to be non-overlapping with the source wiring 27 and to overlap the pixel electrode 25 and the reflective electrode 38. The redundant wiring 39 has a length from a position above the portion where the source electrode 24B branches in the source wiring 27 shown in FIG. 6 to a position below the portion where it intersects the gate wiring 26 shown in FIG. 6.

[0039] Between the redundant wiring 39 made of the first metal film and the source wiring 27 made of the second metal film, as shown in FIG. 11, an inter-wiring contact hole (fourth contact hole) CH3 is formed to open in the gate insulating film 32. The inter-wiring contact hole CH3 is disposed at a position overlapping both the redundant wiring 39 and the source wiring 27 in the gate insulating film 32. Two inter-wiring contact holes CH3 are provided at positions overlapping both ends of the redundant wiring 39 in the length direction (Y-axis direction). The source wiring 27 is connected to both ends of the redundant wiring 39 in the length direction through the two inter-wiring contact holes CH3. Therefore, for example, even if a disconnection occurs in a portion between the two inter-wiring contact holes CH3 in the source wiring 27, the image signal transmitted from the signal supply source side (driver 12 side) rather than the disconnection portion in the source wiring 27 can be transmitted to the signal supply destination side (the side opposite to the driver 12 side) by the redundant wiring 39. Thereby, the redundancy of the source wiring 27 can be ensured. Further, since the redundant wiring 39 is wider than the source wiring 27, it is possible to block the light that tries to pass between adjacent pixels in the X-axis direction during the transmissive display. Thereby, it is possible to suppress the color mixture that may occur between pixels presenting different colors.

[0040] As described above, in the present embodiment, as shown in FIG. 4, since the holding capacitor is formed by the pixel electrode 25 and the common electrode 37 located in a layer different from the redundant wiring 39, it is possible to freely set the formation ranges of the pixel electrode 25 and the common electrode 37 regardless of the presence of the redundant wiring 39. Therefore, if an electrode having the same potential as the pixel electrode 25 is provided in the same layer (second metal film) as the source wiring 27, and an electrode having a common potential is provided in the same layer (first metal film) as the gate wiring 26 so as to overlap the electrode to form a holding capacitor, the overlapping area of the pixel electrode 25 and the common electrode 37 can be increased as compared with the case. Thereby, since the holding capacitor formed between the pixel electrode 25 and the common electrode 37 can be increased, the potential of the pixel electrode 25 can be held more stably.

[0041] Further, as shown in FIG. 8, the array substrate 21 is provided with a gas vent hole 40 for discharging the gas generated from the first planarization film 34. Hereinafter, the configuration of the gas vent hole 40 will be described in detail with reference to FIGS. 7 to 9. The gas vent hole 40 is provided in the common electrode 37, the inter-electrode insulating film 35, and the pixel electrode 25 intervening between the first planarization film 34 and the second planarization film 36. Specifically, the gas vent hole 40 is configured by the second opening 37B provided in the common electrode 37, the third opening 35A provided in the inter-electrode insulating film 35, and the fourth opening 25A provided in the pixel electrode 25 communicating with each other. The second opening 37B and the fourth opening 25A have substantially the same opening area, while the third opening 35A has a smaller opening area than the second opening 37B and the fourth opening 25A. As shown in FIGS. 7 and 9, the gas vent hole 40 is disposed at a position adjacent to the drain electrode 24C and the semiconductor portion 24D of the TFT 24 in a plan view. That is, the gas vent hole 40 is disposed at a position that does not overlap at least with the source wiring 27, and the second opening 37B of the common electrode 37 is also arranged so as not to overlap at least with the source wiring 27. Thereby, the electric field generated from the source wiring 27 can be sufficiently shielded by the common electrode 37. Here, when the organic insulating materials of the first planarization film 34 and the second planarization film 36 are, for example, acrylic resin materials, gases such as ethylene gas and propane gas can be released from the first planarization film 34 and the second planarization film 36 over time after film formation. When gas is generated from the first planarization film 34, the gas can be discharged to the second planarization film 36 side through the second opening 37B, the third opening 35A, and the fourth opening 25A constituting the above-described gas vent hole 40. The gas generated from the first planarization film 34 and the second planarization film 36 can be discharged to the liquid crystal layer 22 side from the portion of the second planarization film 36 not covered by the reflective electrode 38. Thereby, the gas generated from the first planarization film 34 and the second planarization film 36 can be discharged.

[0042] As described above, the liquid crystal panel (display device) 11 of the present embodiment includes a TFT (switching element) 24, a pixel electrode (first electrode) 25 connected to the TFT 24, a source wiring (first wiring) 27 connected to the TFT 24, located on the lower layer side of the pixel electrode 25, and transmitting an image signal supplied to the pixel electrode 25, a reflective electrode (second electrode) 38 located on the upper layer side of the source wiring 27, having a reflective layer 38B that reflects light and the reflective layer 38B having an uneven surface 38S, a common electrode (third electrode) 37 located on the lower layer side of the pixel electrode 25 and on the upper layer side of the source wiring 27, arranged to overlap at least each of the pixel electrode 25 and the source wiring 27 and having a common potential, an inter-electrode insulating film (first insulating film) 35 interposed between the pixel electrode 25 and the common electrode 37, and a first planarization film (second insulating film) 34 located on the upper layer side of the source wiring 27, arranged on the lower layer side with respect to the common electrode 37 and having a larger film thickness than the inter-electrode insulating film 35.

[0043] When the TFT 24 is driven, the pixel electrode 25 is charged to a potential based on the image signal transmitted by the source wiring 27. Since the pixel electrode 25 is arranged to overlap with the common electrode 37 having a common potential via the inter-electrode insulating film 35, a holding capacitance is formed between the pixel electrode 25 and the common electrode 37. By using this holding capacitance, the potential of the charged pixel electrode 25 can be held well. On the other hand, by reflecting light by the reflective layer 38B of the reflective electrode 38, an image can be displayed using external light. Since the reflective layer 38B of the reflective electrode 38 has an uneven surface 38S, external light can be diffusely reflected, thereby realizing a display close to paper white.

[0044] A common electrode 37 having a common potential is disposed at a position above the source wiring 27 and below the pixel electrode 25, so that the parasitic capacitance that may occur between the source wiring 27 and the pixel electrode 25 can be suppressed. And, the first planarization film 34 located above the source wiring 27 and disposed below the common electrode 37 has a larger film thickness than the inter-electrode insulating film 35, so that the flatness of the common electrode 37 located above the first planarization film 34 is sufficiently ensured. By ensuring the flatness of the common electrode 37, the flatness of the pixel electrode 25 disposed above the common electrode 37 via the inter-electrode insulating film 35 is also ensured. Therefore, compared with the case where a common electrode is provided to overlap a reflective layer having an uneven surface via an insulating film as in the prior art, the variation in the distance between the pixel electrode 25 and the common electrode 37 is less likely to occur. As a result, the holding capacitance formed between the pixel electrode 25 and the common electrode 37 is stabilized, and thereby the display quality is less likely to deteriorate.

[0045] Also, the reflective electrode 38 is disposed at a position above the pixel electrode 25, and includes a second planarization film (third insulating film) 36 that is interposed between the reflective electrode 38 and the pixel electrode 25 and has a larger film thickness than the inter-electrode insulating film 35. Since the reflective electrode 38 is disposed at a position above the pixel electrode 25, the reflected light from the reflective layer 38B of the reflective electrode 38 does not transmit through the pixel electrode 25. Therefore, the light can be reflected by the reflective layer 38B of the reflective electrode 38 with low loss and used for image display. Since the film thickness of the second planarization film 36 disposed below the reflective electrode 38 is larger than the film thickness of the inter-electrode insulating film 35, the reproducibility of the shape of the uneven surface 38S of the reflective layer 38B of the reflective electrode 38 is improved.

[0046] Also provided are a counter electrode (fourth electrode) 30 that is arranged to face the reflective electrode 38 with a space therebetween and has a common potential, and a liquid crystal layer 22 interposed between the reflective electrode 38 and the counter electrode 30. The reflective electrode 38 is arranged to overlap with the pixel electrode 25. In the second planarization film 36, at a position overlapping both the reflective electrode 38 and the pixel electrode 25, an inter-electrode contact hole (first contact hole) CH2 for connecting the reflective electrode 38 to the pixel electrode 25 is provided and opened. The reflective electrode 38 is connected to the pixel electrode 25 through the inter-electrode contact hole CH2 of the second planarization film 36. Since the reflective electrode 38 has the same potential as the pixel electrode 25, an electric field with sufficient strength can be generated between the reflective electrode 38 and the counter electrode 30. Thereby, the alignment state of the liquid crystal molecules contained in the liquid crystal layer 22 can be favorably controlled by using the electric field generated between the reflective electrode 38 and the counter electrode 30.

[0047] Also, a gate wiring (second wiring) 26 that is connected to the TFT 24, intersects the source wiring 27, and transmits a scanning signal, a gate insulating film (fifth insulating film) 32 that is disposed on the upper layer side with respect to the source wiring 27 and on the lower layer side with respect to the gate wiring 26, and a redundant wiring (third wiring) 39 that is disposed on the lower layer side with respect to the gate insulating film 32 and overlaps the gate wiring 26. Among the gate insulating film 32, a wiring contact hole (fourth contact hole) CH3 that connects the gate wiring 26 to the redundant wiring 39 is provided to open at a position that overlaps both the gate wiring 26 and the redundant wiring 39. When the scanning signal transmitted to the gate wiring 26 is supplied to the TFT 24, the TFT 24 is driven. The source wiring 27 is connected to the redundant wiring 39 through the wiring contact hole CH3 of the gate insulating film 32. If a disconnection occurs in the source wiring 27, an image signal can be transmitted by the redundant wiring 39. Thereby, the redundancy of the source wiring 27 can be ensured. Further, since a holding capacitor is formed by the pixel electrode 25 and the common electrode 37 that are located in a layer different from the redundant wiring 39, it is possible to freely set the formation ranges of the pixel electrode 25 and the common electrode 37 regardless of the presence of the redundant wiring 39. Therefore, compared with the case where a holding capacitor is formed by providing an electrode having the same potential as the pixel electrode 25 in the same layer as the source wiring 27 and providing an electrode having the same common potential in the same layer as the gate wiring 26 so as to overlap the electrode, the overlapping area of the pixel electrode 25 and the common electrode 37 can be increased. Thereby, the holding capacitor formed between the pixel electrode 25 and the common electrode 37 can be increased.

[0048] <Embodiment 2> Embodiment 2 will be described with reference to FIGS. 12 to 19. In this Embodiment 2, a case is shown in which the stacking order of each film on the inner surface side of the array substrate 121 is changed, and the configurations of the pixel electrode 125, the common electrode 137, the reflective electrode 138, etc. are changed. Note that redundant descriptions of the same structures, operations, and effects as those in the above-described Embodiment 1 are omitted.

[0049] With reference to FIGS. 13 and 14, the lamination order of various films laminated on the inner surface side of the array substrate 121 constituting the liquid crystal panel 111 according to this embodiment will be described. As shown in FIGS. 13 and 14, on the array substrate 121, in order from the lower layer side, a first metal film, a gate insulating film (fifth insulating film) 132, a semiconductor film, a second metal film, an interlayer insulating film 133, a first planarization film (fourth insulating film) 134, a first transparent electrode film, a third metal film, a second planarization film (second insulating film) 136, a second transparent electrode film, an inter-electrode insulating film (first insulating film) 135, a third transparent electrode film, and an alignment film are laminated.

[0050] As shown in FIGS. 12 and 13, the reflective electrode 138 according to this embodiment is provided so as to be located on the lower layer side of the pixel electrode 125 and the common electrode 137. Specifically, the reflective electrode 138 is disposed on the upper layer side with respect to the first planarization film 134 and on the lower layer side with respect to the second planarization film 136. As shown in FIGS. 13, 15, and 16, the reflective electrode 138 is composed of a transparent electrode layer 138A made of a first transparent electrode film and a reflective layer 138B made of a third metal film. In this embodiment, a common potential signal that is set to a common potential by a backplane circuit is supplied to the reflective electrode 138. Accordingly, the reflective electrode 138 is disposed substantially solidly over substantially the entire display area. The reflective electrode 138 is located on the upper layer side of both the gate wiring 126 and the source wiring 127. Since the reflective electrode 138 also exists in the region (inter-pixel region) between adjacent pixel electrodes 125 in the X-axis direction and the Y-axis direction, it is disposed so as to overlap the gate wiring 126 and the source wiring 127. The cross-sectional shape of the reflective electrode 138 is uneven, and the reflective layer 138B disposed on the surface layer thereof has an uneven surface 138S. Such a cross-sectional shape of the reflective electrode 138 reflects the cross-sectional shape of the first planarization film 134, which is the base of the reflective electrode 138. To make the cross-sectional shape of the first planarization film 134 uneven, for example, the material of the first planarization film 134 may be a photosensitive organic insulating material, and the formed first planarization film 134 may be exposed and developed using a halftone mask or a grayscale mask having a pattern in which an uneven shape is reflected. Further, as shown in FIG. 13, the reflective electrode 138 has a transmission opening 138C by partially cutting out the transparent electrode layer 138A in addition to the reflective layer 138B. The transmission opening 138C is formed by non-formed portions of the transparent electrode layer 138A and the reflective layer 138B that constitute the reflective electrode 138.

[0051] As shown in FIGS. 13, 14, and 17, the pixel electrode 125 according to this embodiment is made of a third transparent electrode film. Thus, since the pixel electrode 125 is arranged closer to the liquid crystal layer 122 than the alignment film on the array substrate 121, an electric field with sufficient strength is generated between the pixel electrode 125 and the counter electrode 130 facing each other across the liquid crystal layer 122. By controlling the alignment state of the liquid crystal molecules contained in the liquid crystal layer 122 with this electric field, the amount of light emitted toward the front side of the liquid crystal panel 111 during display is controlled for each pixel, and thus a predetermined image can be displayed in the display area.

[0052] As shown in FIGS. 13 to 15, the pixel electrode 125 made of a third transparent electrode film is connected to the drain electrode 124C made of a second metal film via an intermediate electrode (fifth electrode) 41 existing in the middle in the stacking direction (Z-axis direction). The intermediate electrode 41 is made of a part of the first transparent electrode film. That is, the intermediate electrode 41 is located in the same layer as the transparent electrode layer 138A constituting the reflective electrode 138. Note that since the intermediate electrode 41 made of a part of the first transparent electrode film does not include the third metal film constituting the reflective electrode 138, it can transmit light and avoid a situation of short-circuiting with the reflective electrode 138 due to the remaining film of the third metal film (reflective layer 138B). As shown in FIG. 15, the intermediate electrode 41 is located and arranged within the transmission opening 138C in the reflective electrode 138, forming an island shape surrounded by the opening edge of the transmission opening 138C. The intermediate electrode 41 has a substantially vertically long rectangular shape when viewed in plan, and is arranged to overlap both the drain electrode 124C and the pixel electrode 125 which are the connection targets. In other words, the drain electrode 124C is provided such that a part thereof enters the transmission opening 138C. Specifically, one end side portion (the lower side portion in FIG. 15) of the intermediate electrode 41 in the Y-axis direction overlaps the drain electrode 124C and the pixel electrode 125, and the other end side portion (the upper side portion in FIG. 15) in the Y-axis direction does not overlap the drain electrode 124C and overlaps the pixel electrode 125.

[0053] Between the intermediate electrode 41 and the drain electrode 124C, an interlayer insulating film 133 and a first planarization film 134 are formed with openings in communication with a first pixel contact hole (second contact hole) CH4 as shown in FIGS. 13 and 14. The first pixel contact hole CH4 is disposed at a position overlapping both the intermediate electrode 41 and the drain electrode 124C among the interlayer insulating film 133 and the first planarization film 134. The intermediate electrode 41 is connected to the drain electrode 124C through the first pixel contact hole CH4. In the second planarization film 136 and the inter-electrode insulating film 135 interposed between the pixel electrode 125 and the intermediate electrode 41, a second pixel contact hole (third contact hole) CH5 is formed with an opening in communication therewith. The second pixel contact hole CH5 is disposed at a position overlapping both the pixel electrode 125 and the intermediate electrode 41 among the second planarization film 136 and the inter-electrode insulating film 135 (specifically, on the right side of FIG. 14 with respect to the first pixel contact hole CH4), although it does not overlap with the drain electrode 124C. The pixel electrode 125 is connected to the intermediate electrode 41 through the second pixel contact hole CH5. Thus, the pixel electrode 125 is connected to the drain electrode 124C of the TFT 124 through the intermediate electrode 41. Note that the second planarization film 136 and the inter-electrode insulating film 135 have a shape in which the cross-sectional shape of the second pixel contact hole CH5 is smoother than the cross-sectional shape of the first pixel contact hole CH4 in the interlayer insulating film 133 and the first planarization film 134. Thereby, when applying the material of the alignment film to the innermost surface of the array substrate 121 during manufacturing, the material of the alignment film easily flows into the second pixel contact hole CH5, so that the certainty of uniformly coating the alignment film is increased. Further, the opening 130A of the counter electrode (sixth electrode) 130 provided in the counter substrate 120 is disposed at a position overlapping the first pixel contact hole CH4.

[0054] As shown in FIGS. 13, 16, and 18, the common electrode 137 according to this embodiment is made of a second transparent electrode film. The common electrode 137 made of the second transparent electrode film is disposed to overlap the lower layer side of a plurality of pixel electrodes 125 with an inter-electrode insulating film 135 therebetween. Thereby, a holding capacitance is formed between the common electrode 137 having a common potential and the pixel electrode 125 charged by the TFT 124, so that the potential of the charged pixel electrode 125 can be held well. Further, as shown in FIGS. 13 and 16, a first opening 137A for passing the pixel electrode 125 is provided at a position of the common electrode 137 that overlaps with the second pixel contact hole CH5.

[0055] As shown in FIGS. 13 and 16, these pixel electrodes 125 and the common electrode 137 are located on the upper layer side of the second planarization film 136 and are planarized by the second planarization film 136 having a larger film thickness than the inter-electrode insulating film 135. Therefore, it is possible to avoid the uneven surface 138S of the reflective layer 138B constituting the reflective electrode 138 from being reflected in the cross-sectional shapes of the pixel electrode 125 and the common electrode 137. In this way, since the flatness of the pixel electrode 125 and the common electrode 137 is sufficiently ensured, compared with the case where a common electrode that overlaps via an insulating film with a reflective layer having an uneven surface is provided as in the prior art, the distance between the pixel electrode 125 and the common electrode 137 is less likely to vary. Thereby, the holding capacitance formed between the pixel electrode 125 and the common electrode 137 is stabilized, and thereby the display quality is less likely to deteriorate. In particular, in this embodiment, the pixel electrode 125 is disposed on the top layer of the array substrate 121 next to the alignment film, and the uneven surface 138S of the reflective layer 138B of the reflective electrode 138 is prevented from being exposed on the top layer next to the alignment film. Therefore, it is suitable for suppressing the volume fluctuation of the liquid crystal layer 122.

[0056] Moreover, in this embodiment, as shown in FIGS. 13 and 16, a reflective electrode 138 having a common potential is disposed at a position above the source wiring 127 and below the pixel electrode 125 in addition to a common electrode 137 having a common potential. Therefore, the electric field generated from the source wiring 127 can be doubly shielded by the common electrode 137 and the reflective electrode 138. As a result, the parasitic capacitance that may occur between the source wiring 127 and the pixel electrode 125 can be further suppressed.

[0057] Further, as shown in FIG. 19, the gas vent hole 140 according to the present embodiment is provided in the common electrode 137 and the inter-electrode insulating film 135 located on the upper layer side of the second planarization film 136. Specifically, the gas vent hole 140 is configured by the second opening 137B provided in the common electrode 137 and the third opening 135A provided in the inter-electrode insulating film 135 communicating with each other. As shown in FIGS. 17 and 18, the gas vent hole 140 is disposed at a position that overlaps the gate wiring 126 in a plan view, that is, at a position between two adjacent pixel electrodes 125 in the Y-axis direction. A plurality of gas vent holes 140 are arranged at intervals along the X-axis direction on the gate wiring 126, and the arrangement interval is set to be about half of the arrangement interval of the source wiring 127. Specifically, the gas vent hole 140 is disposed at a position overlapping the intersection of the gate wiring 126 and the source wiring 127 and at an intermediate position between two adjacent source wirings 127 in the X-axis direction. Thus, since the gas vent hole 140 according to the present embodiment is located between two adjacent pixel electrodes 125 in the Y-axis direction, it is difficult to visually recognize display defects caused by the gas vent hole 140. Here, as shown in FIGS. 13 and 14, the gas generated from the first planarization film 134 is discharged to the second planarization film 136 side through the transmission opening 138C of the reflective electrode 138. As shown in FIG. 19, the gas generated from the first planarization film 134 and the second planarization film 136 passes through the second opening 137B and the third opening 135A that form the gas vent hole 140 in the second planarization film 136, and then passes between two adjacent pixel electrodes 125 in the Y-axis direction and is discharged to the liquid crystal layer 122 side. Thereby, the gas generated from the first planarization film 134 and the second planarization film 136 can be discharged.

[0058] As described above, the liquid crystal panel 111 of the present embodiment includes a TFT 124, a pixel electrode 125 connected to the TFT 124, a source wiring 127 connected to the TFT 124, located on the lower layer side of the pixel electrode 125, and transmitting an image signal supplied to the pixel electrode 125, a reflective electrode 138 having a reflective layer 138B that reflects light and is located on the upper layer side of the source wiring 127, and the reflective layer 138B has an uneven surface 138S, a common electrode 137 located on the lower layer side of the pixel electrode 125 and on the upper layer side of the source wiring 127, arranged to overlap at least each of the pixel electrode 125 and the source wiring 127 and having a common potential, an inter-electrode insulating film 135 interposed between the pixel electrode 125 and the common electrode 137, a second planarization film (second insulating film) 136 located on the upper layer side of the source wiring 127, arranged on the lower layer side with respect to the common electrode 137, and having a film thickness larger than that of the inter-electrode insulating film 135.

[0059] When the TFT 124 is driven, the pixel electrode 125 is charged to a potential based on the image signal transmitted by the source wiring 127. Since the pixel electrode 125 is arranged to overlap with the common electrode 137 having a common potential via the inter-electrode insulating film 135, a holding capacitance is formed between the pixel electrode 125 and the common electrode 137. By using this holding capacitance, the potential of the charged pixel electrode 125 can be held well. On the other hand, by reflecting light by the reflective layer 138B of the reflective electrode 138, an image can be displayed using external light. Since the reflective layer 138B of the reflective electrode 138 has an uneven surface 138S, external light can be diffusely reflected, thereby realizing a display close to paper white.

[0060] Since the common electrode 137 having a common potential is disposed at a position that is above the source wiring 127 and below the pixel electrode 125, it is possible to suppress the parasitic capacitance that may occur between the source wiring 127 and the pixel electrode 125. And, the second planarization film 136 that is located above the source wiring 127 and disposed below the common electrode 137 has a larger film thickness than the inter-electrode insulating film 135, so the flatness of the common electrode 137 located above the second planarization film 136 is sufficiently ensured. By ensuring the flatness of the common electrode 137, the flatness of the pixel electrode 125 disposed above the common electrode 137 via the inter-electrode insulating film 135 is also ensured. Therefore, compared with the case where a common electrode is provided to overlap a reflective layer having an uneven surface via an insulating film as in the prior art, it is difficult for the distance between the pixel electrode 125 and the common electrode 137 to vary. As a result, the holding capacitance formed between the pixel electrode 125 and the common electrode 137 is stabilized, and thereby it is difficult for the display quality to deteriorate.

[0061] Also, the reflective electrode 138 is disposed below the second planarization film 136, located above the source wiring 127, and includes a first planarization film (fourth insulating film) 134 that is disposed below the reflective electrode 138 and has a larger film thickness than the inter-electrode insulating film 135. Since the reflective electrode 138 is disposed below the second planarization film 136, the uneven surface 138S of the reflective layer 138B of the reflective electrode 138 is planarized by the second planarization film 136. Compared with the case where the reflective electrode is disposed above the pixel electrode 125, it is possible to avoid the uneven surface 138S of the reflective layer 138B being exposed at the uppermost layer. Also, since the film thickness of the first planarization film 134 disposed below the reflective electrode 138 is larger than the film thickness of the inter-electrode insulating film 135, the reproducibility regarding the shape of the uneven surface 138S of the reflective layer 138B of the reflective electrode 138 is improved.

[0062] Further, the reflective electrode 138 is set to a common potential. Since the reflective electrode 138 and the common electrode 137, both of which are set to the common potential, are arranged at positions that are on the upper layer side of the source wiring 127 and on the lower layer side of the pixel electrode 125, the parasitic capacitance that may occur between the source wiring 127 and the pixel electrode 125 can be further suppressed.

[0063] Also, a plurality of pixel electrodes 125 are arranged side by side with intervals therebetween, and the reflective electrode 138 is arranged in a range straddling the plurality of pixel electrodes 125. The reflective electrode 138 is arranged so as to overlap the plurality of pixel electrodes 125 and is also arranged in a region between two adjacent pixel electrodes 125. In this way, if compared with the case where a plurality of reflective electrodes are provided so as to individually overlap the plurality of pixel electrodes 125, the amount of reflected light by the reflective layer 138B increases, which is suitable for improving the luminance of the display image.

[0064] Also, an intermediate electrode (fifth electrode) 41 is provided on the lower layer side with respect to the second planarization film 136 and on the upper layer side with respect to the first planarization film 134. The reflective electrode 138 has a transparent electrode layer 138A disposed on the lower layer side with respect to the reflective layer 138B. The intermediate electrode 41 is part of the transparent electrode layer 138A, and is disposed so as to overlap a part of the TFT 124 and a part of the pixel electrode 125. In the first planarization film 134, at a position overlapping both the TFT 124 and the intermediate electrode 41, a first pixel contact hole (second contact hole) CH4 for connecting the intermediate electrode 41 to the TFT 124 is provided to open. In the second planarization film 136, at a position overlapping both the pixel electrode 125 and the intermediate electrode 41, a second pixel contact hole (third contact hole) CH5 for connecting the pixel electrode 125 to the intermediate electrode 41 is provided to open. The intermediate electrode 41 is connected to a part of the TFT 124 through the first pixel contact hole CH4 of the first planarization film 134, and a part of the pixel electrode 125 is connected to the intermediate electrode 41 through the second pixel contact hole CH5 of the second planarization film 136. Since the intermediate electrode 41 disposed to overlap the pixel electrode 125 is part of the transparent electrode layer 138A, light can be transmitted therethrough. Also, since the intermediate electrode 41 does not have the reflective layer 138B, a situation of short-circuiting with the reflective electrode 138 due to the remaining film of the reflective layer 138B can be avoided.

[0065] Also, a counter electrode (sixth electrode) 130 that is disposed to face the pixel electrode 125 with a space therebetween and has a common potential, and a liquid crystal layer 122 interposed between the pixel electrode 125 and the counter electrode 130 are provided. An electric field with sufficient strength can be generated between the pixel electrode 125 connected to the TFT 124 via the intermediate electrode 41 and the counter electrode 130. Thereby, the alignment state of the liquid crystal molecules contained in the liquid crystal layer 122 can be favorably controlled by utilizing the electric field generated between the pixel electrode 125 and the counter electrode 130. Since the uneven surface 138S of the reflective layer 138B of the reflective electrode 138 is prevented from being exposed on the outermost layer, it is suitable for suppressing the volume fluctuation of the liquid crystal layer 122.

[0066] <Other Embodiments> The technology disclosed in this specification is not limited to the embodiments described by the above description and drawings. For example, the following embodiments are also included in the technical scope.

[0067] (1) The specific planar shape, size as viewed in the plane, etc. of the pixel electrodes 25 and 125 can be appropriately changed other than as shown in the drawings.

[0068] (2) The specific arrangement, number of installations, planar shape, size as viewed in the plane, etc. of the transmission openings 38C and 138C in the reflective electrodes 38 and 138 can be appropriately changed other than as shown in the drawings.

[0069] (3) The arrangement, size as viewed in the plane, etc. of each electrode 24A, 24B, 24C, 124C and the semiconductor part 24D constituting the TFTs 24 and 124 can be appropriately changed other than as shown in the drawings.

[0070] (4) The specific arrangement, number of installations, planar shape, size as viewed in the plane, etc. of the degassing holes 40 and 140 can be appropriately changed other than as shown in the drawings. For example, in the configuration described in Embodiment 1, the degassing hole 40 may be arranged at a position overlapping the gate wiring 26. For example, in the configuration described in Embodiment 2, all the degassing holes 140 may be arranged at positions that overlap the gate wiring 126 but do not overlap the source wiring 127.

[0071] (5) It is also possible to omit the degassing holes 40 and 140.

[0072] (6) The specific line width, length dimension, etc. of the redundant wiring 39 can be appropriately changed other than as shown in the drawings. For example, the line width of the redundant wiring 39 may be about the same as that of the source wirings 27 and 127.

[0073] (7) It is also possible to omit the redundant wiring 39.

[0074] (8) The liquid crystal panels 11 and 111 may be reflective types other than the transflective type. When the liquid crystal panels 11 and 111 are of the reflective type, the backlight device can be omitted.

[0075] (9) As described in (8) above, when the liquid crystal panels 11 and 111 are of the reflective type, the transparent electrode layers 38A and 138A can be omitted from the reflective electrodes 38 and 138, and the reflective electrodes 38 and 138 can be composed only of the reflective layers 38B and 138B. In the configuration described in Embodiment 2, when the first transparent electrode film constituting the transparent electrode layer 138A is omitted, the intermediate electrode 41 may be composed of a part of the third metal film.

[0076] (10) As described in (8) above, when the liquid crystal panels 11 and 111 are of the reflective type, the pixel electrodes 25 and 125 and the common electrodes 37 and 137 can be composed of a metal film instead of a transparent electrode film.

[0077] (11) As described in (8) above, when the liquid crystal panel 11 is of the reflective type, in the configuration described in Embodiment 1, the transmission opening 38C can be omitted from the reflective electrode 38.

[0078] (12) The material of the semiconductor film constituting the semiconductor portion 24D may be amorphous silicon, polysilicon (LTPS), or the like.

[0079] (13) The color filter 28 may be omitted from the counter substrates 20 and 120, and a transflective liquid crystal panel 11 or 111 for monochrome display may be used. Also, the color filter 28 may not be omitted from the counter substrates 20 and 120, and the specific types and numbers of colors in the color filter 28 may be changed.

[0080] (14) The color filter 28 may be provided on the array substrates 21 and 121 instead of the counter substrates 20 and 120.

[0081] (15) The operation mode of the liquid crystal panels 11 and 111 may be an IPS (In-Plane Switching) mode or the like.

Explanation of Reference Numerals

[0082] 11,111… Liquid crystal panel (display device), 22,122… Liquid crystal layer, 24,124… TFT (switching element), 25,125… Pixel electrode (first electrode), 26,126… Gate wiring (second wiring), 27,127… Source wiring (first wiring), 30… Counter electrode (fourth electrode), 32,132… Gate insulating film (fifth insulating film), 34… First planarization film (second insulating film), 35,135… Inter-electrode insulating film (first insulating film), 36… Second planarization film (third insulating film), 37,137… Common electrode (third electrode), 38,138… Reflective electrode (second electrode), 38B,138B… Reflective layer, 38S,138S… Concave-convex surface, 39… Redundant wiring (third wiring), 41… Intermediate electrode (fifth electrode), 130… Counter electrode (sixth electrode), 134… First planarization film (fourth insulating film), 136… Second planarization film (second insulating film), 138A… Transparent electrode layer, CH2… Inter-electrode contact hole (first contact hole), CH3… Inter-wiring contact hole (fourth contact hole), CH4… First pixel contact hole (second contact hole), CH5… Second pixel contact hole (third contact hole)

Claims

1. A switching element, a first electrode connected to the switching element, a first wiring connected to the switching element, located on a lower layer side than the first electrode, and transmitting an image signal supplied to the first electrode, a second electrode located on an upper layer side than the first wiring, having a reflective layer that reflects light, and the reflective layer having an uneven surface, a third electrode located on a lower layer side than the first electrode and on an upper layer side than the first wiring, arranged to overlap at least each of the first electrode and the first wiring, and having a common potential, a first insulating film interposed between the first electrode and the third electrode, a second insulating film located on an upper layer side than the first wiring, arranged on a lower layer side with respect to the third electrode, and having a larger film thickness than the first insulating film, a display device comprising the same.

2. The second electrode is arranged to be located on an upper layer side than the first electrode, The display device according to claim 1, further comprising a third insulating film interposed between the second electrode and the first electrode and having a larger film thickness than the first insulating film.

3. a fourth electrode arranged to face the second electrode with a gap therebetween and having a common potential, a liquid crystal layer interposed between the second electrode and the fourth electrode, The second electrode is arranged to overlap the first electrode, In the third insulating film, at a position overlapping both the second electrode and the first electrode, a first contact hole connecting the second electrode to the first electrode is provided and opened. The display device according to claim 2.

4. The second electrode is arranged to be located on a lower layer side with respect to the second insulating film, The display device according to claim 1, further comprising a fourth insulating film located on an upper layer side than the first wiring, arranged on a lower layer side with respect to the second electrode, and having a larger film thickness than the first insulating film.

5. The second electrode has the common potential. The display device according to claim 4.

6. A plurality of the first electrodes are arranged side by side with a gap therebetween, The second electrode is arranged in a range straddling the plurality of first electrodes. The display device according to claim 5.

7. Comprising a fifth electrode arranged on a lower layer side with respect to the second insulating film and on an upper layer side with respect to the fourth insulating film, The second electrode has a transparent electrode film arranged on a lower layer side with respect to the reflective layer, The fifth electrode is formed of a part of the transparent electrode film, overlaps a part of the switching element, and is arranged to overlap a part of the first electrode. Of the fourth insulating film, at a position overlapping both the switching element and the fifth electrode, a second contact hole for connecting the fifth electrode to the switching element is provided and opened. The display device according to any one of claims 4 to 6, wherein a third contact hole for connecting the first electrode to the fifth electrode is provided and opened at a position of the second insulating film that overlaps both the first electrode and the fifth electrode.

8. A sixth electrode that is arranged to face the first electrode with a space therebetween and has a common potential, And a liquid crystal layer interposed between the first electrode and the sixth electrode. The display device according to claim 7.

9. A second wiring that is connected to the switching element, intersects the first wiring, and transmits a scanning signal, A fifth insulating film that is arranged on the upper layer side with respect to the first wiring and on the lower layer side with respect to the second wiring, And a third wiring that is arranged to overlap the second wiring on the lower layer side with respect to the fifth insulating film. The display device includes: The display device according to any one of claims 1 to 6, wherein a fourth contact hole for connecting the second wiring to the third wiring is provided and opened at a position of the fifth insulating film that overlaps both the second wiring and the third wiring.

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