Multilayer ceramic electronic component

Abstract

To provide a multilayer ceramic electronic component, capable of suppressing occurrence of structural defects.SOLUTION: A multilayer ceramic electronic component includes: an element body including a plurality of dielectric layers and a plurality of internal electrode layers that are provided via the plurality of dielectric layers and that are alternately derived to two end faces facing each other; and a pair of side margins sandwiching the element body in a third direction that is orthogonal to a first direction where the plurality of internal electrode layers face each other and a second direction where the two end surfaces face each other. The side margins each include: a first region provided from a portion in contact with an end in the third direction of one internal electrode layer of two adjacent internal electrode layers among the plurality of internal electrode layers to a portion in contact with an end in the third direction of another internal electrode layer; and a second region that is provided outside the first region in the third direction and that has an average grain diameter larger than that in the first region.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic electronic component.

Background Art

[0002] In high-frequency communication systems typified by mobile phones, multilayer ceramic electronic components such as multilayer ceramic capacitors (MLCC: Multi-Layer Ceramic Capacitor) are used (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a voltage is applied to the dielectric layer, an electrostriction phenomenon (inverse piezoelectric phenomenon) occurs. The electrostriction phenomenon is a phenomenon in which mechanical displacement occurs due to expansion in the direction of the applied electric field. When the electrostriction phenomenon occurs, structural defects such as cracks may occur in regions with low mechanical strength. There is a problem that the occurrence of structural defects leads to a decrease in breakdown voltage and withstand voltage.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide a multilayer ceramic electronic component capable of suppressing the occurrence of structural defects.

Means for Solving the Problems

[0006] The multilayer ceramic electronic component according to the present invention includes a body having a plurality of dielectric layers and a plurality of internal electrode layers provided through the plurality of dielectric layers and alternately drawn out on two end faces facing each other, and a pair of side margins sandwiching the body in a third direction orthogonal to a first direction in which the plurality of internal electrode layers face each other and a second direction in which the two end faces face each other. The side margin includes a first region provided from a portion in contact with an end portion in the third direction of one of the internal electrode layers to a portion in contact with an end portion in the third direction of the other internal electrode layer among two adjacent internal electrode layers of the plurality of internal electrode layers, and a second region provided outside the first region in the third direction and having an average grain diameter larger than the average grain diameter of the first region.

[0007] In the above multilayer ceramic electronic component, the first region may be provided across the outermost internal electrode layer on one side in the first direction to the outermost internal electrode layer on the other side among the plurality of internal electrode layers.

[0008] In the above multilayer ceramic electronic component, the average grain diameter in the first region may be 50 nm or less.

[0009] In the above multilayer ceramic electronic component, the average grain diameter in the first region may be 10 nm or more.

[0010] In the above multilayer ceramic electronic component, the average grain diameter in the second region may be 100 nm or more.

[0011] In the above multilayer ceramic electronic component, the average grain diameter in the second region may be 500 nm or less.

[0012] In the above multilayer ceramic electronic component, the average grain diameter in the first region may be 50 times or less the average grain diameter in the second region.

[0013] In the above multilayer ceramic electronic component, the average grain diameter in the first region may be two times or more the average grain diameter in the second region.

[0014] In the above multilayer ceramic electronic component, the average grain diameter in the first region may be smaller than the average grain diameter in the dielectric layer.

[0015] The above multilayer ceramic electronic component includes a pair of external electrodes provided at both ends of the element body in the second direction, and the plurality of internal electrode layers are alternately connected to the pair of external electrodes. In a region from an end of any one of the internal electrode layers in the second direction to the unconnected external electrode, a third region provided in contact with any one of the internal electrode layers and a fourth region provided outside the third region in the second direction and having an average grain diameter larger than the average grain diameter of the third region may be provided.

Advantages of the Invention

[0016] According to the present invention, a multilayer ceramic electronic component capable of suppressing the occurrence of structural defects can be provided.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Embodiments for Carrying Out the Invention

[0018] Hereinafter, embodiments will be described with reference to the drawings.

[0019] (First Embodiment) FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to the first embodiment. FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1. FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a stacked chip 10 having a substantially rectangular parallelepiped shape, and external electrodes 20a and 20b provided on two end faces facing each other in the X-axis direction in the stacked chip 10. Among the four surfaces of the stacked chip 10 other than the two end faces, the two surfaces other than the upper and lower surfaces in the stacking direction are referred to as side surfaces. The external electrodes 20a and 20b extend to the upper surface, lower surface, and two side surfaces in the stacking direction of the stacked chip 10. However, the external electrodes 20a and 20b are spaced apart from each other.

[0020] In FIGS. 1 to 3, the Z-axis direction (first direction) is the stacking direction and is the direction in which each internal electrode layer faces. The X-axis direction (second direction) is the direction in which the two end faces of the stacked chip 10 face each other and is the direction in which the external electrode 20a and the external electrode 20b face each other. The Y-axis direction (third direction) is the width direction of the internal electrode layer and is the direction in which two side surfaces other than the two end faces among the four side surfaces of the stacked chip 10 face each other. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other.

[0021] The multilayer chip 10 includes a body 40 in which a dielectric layer 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 are alternately laminated. The edges of each internal electrode layer 12 are alternately led out to the end face provided with the external electrode 20a of the body 40 and the end face provided with the external electrode 20b. Thereby, each internal electrode layer 12 is alternately electrically connected to the external electrode 20a and the external electrode 20b. Further, in the body 40, an internal electrode layer 12 is disposed on the outermost layer in the stacking direction of the stacked portion of the dielectric layer 11 and the internal electrode layer 12, and the upper and lower surfaces of the stacked portion are covered by a cover layer 13. The cover layer 13 is mainly composed of a ceramic material. For example, the cover layer 13 may have the same composition as the dielectric layer 11 or may have a different composition.

[0022] The size of the multilayer ceramic capacitor 100 is, for example, a length of 0.25 mm, a width of 0.125 mm, and a height of 0.125 mm, or a length of 0.4 mm, a width of 0.2 mm, and a height of 0.2 mm, or a length of 0.6 mm, a width of 0.3 mm, and a height of 0.3 mm, or a length of 1.0 mm, a width of 0.5 mm, and a height of 0.5 mm, or a length of 3.2 mm, a width of 1.6 mm, and a height of 1.6 mm, or a length of 4.5 mm, a width of 3.2 mm, and a height of 2.5 mm, but is not limited to these sizes.

[0023] The internal electrode layer 12 is mainly composed of a base metal such as nickel (Ni), copper (Cu), tin (Sn), or an alloy containing these. As the internal electrode layer 12, a noble metal such as platinum (Pt), palladium (Pd), silver (Ag), gold (Au), or an alloy containing these may be used. The average thickness of each layer of the internal electrode layer 12 in the Z-axis direction is, for example, 1.0 μm or less, 0.5 μm or less, or 0.2 μm or less. The thickness of the internal electrode layer 12 can be measured by observing a cross section of the multilayer ceramic capacitor 100 with an SEM (scanning electron microscope), measuring the thicknesses of 10 points each for 10 different layers of the internal electrode layer 12, and deriving the average value of all the measurement points.

[0024] The dielectric layer 11 is, for example, of the general formula ABO 3It is mainly composed of a ceramic material having a perovskite structure represented by. Note that the perovskite structure deviates from the stoichiometric composition and contains ABO 3-α . For example, as the ceramic material, barium titanate (BaTiO 3 ), calcium zirconate (CaZrO 3 ), calcium titanate (CaTiO 3 ), strontium titanate (SrTiO 3 ), magnesium titanate (MgTiO 3 ), Ba that forms a perovskite structure 1-x-y Ca x Sr y Ti 1-z Zr z O 3 (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1), etc., can be selected and used from at least one of them. Ba 1-x-y Ca x Sr y Ti 1-z Zr z O 3 are barium strontium titanate, barium calcium titanate, barium zirconate, barium titanium zirconate, calcium titanium zirconate, and barium calcium titanium zirconate, etc. For example, in the dielectric layer 11, the main component ceramic is contained at 90 at% or more. The thickness of the dielectric layer 11 is, for example, 1.0 μm or less, 0.5 μm or less, and 0.2 μm or less. The thickness of the dielectric layer 11 can be measured by observing the cross section of the multilayer ceramic capacitor 100 with an SEM (scanning electron microscope), measuring the thickness of 10 points each for 10 different dielectric layers 11, and deriving the average value of all the measurement points.

[0025] An additive may be added to the dielectric layer 11. Examples of the additive to the dielectric layer 11 include oxides of zirconium (Zr), hafnium (Hf), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), or oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0026] As illustrated in FIG. 2, in the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other, capacitance is generated in the multilayer ceramic capacitor 100. Therefore, the region where the capacitance is generated is referred to as the capacitance portion 14. That is, the capacitance portion 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0027] A region where the internal electrode layers 12 connected to the external electrode 20a face each other without passing through the internal electrode layer 12 connected to the external electrode 20b is referred to as an end margin 15. Also, a region where the internal electrode layers 12 connected to the external electrode 20b face each other without passing through the internal electrode layer 12 connected to the external electrode 20a is also the end margin 15. That is, the end margin 15 is a region where the internal electrode layers 12 connected to the same external electrode face each other without passing through the internal electrode layer 12 connected to a different external electrode. The end margin 15 is a region where no capacitance is generated.

[0028] As illustrated in FIG. 3, in the laminated chip 10, a pair of side margins 30 sandwich the element body 40 from the Y-axis direction. Thereby, the pair of side margins 30 cover the end portions (end portions in the Y-axis direction) on both side surfaces of the element body 40.

[0029] FIG. 4(a) is an enlarged cross-sectional view near the external electrode 20a. FIG. 4(b) is an enlarged cross-sectional view near the external electrode 20b. In FIGS. 4(a) and 4(b), the hatching is omitted. As illustrated in FIGS. 4(a) and 4(b), the external electrodes 20a and 20b have a structure in which a plating layer 22 is provided on the base layer 21. The base layer 21 is mainly composed of nickel, copper, or the like. The base layer 21 may contain ceramic particles or a glass component as a co-material. The plating layer 22 is mainly composed of a metal such as nickel, copper, aluminum, zinc, tin, or an alloy of two or more of these. The plating layer 22 may be a plating layer of a single metal component or a plurality of plating layers of different metal components. For example, the plating layer 22 has a structure in which a first plating layer 23, a second plating layer 24, and a third plating layer 25 are formed in order from the base layer 21 side. The first plating layer 23 is, for example, a copper plating layer. The second plating layer 24 is, for example, a nickel plating layer. The third plating layer 25 is, for example, a tin plating layer.

[0030] As illustrated in FIG. 5, when a voltage is applied to the dielectric layer 11, an electrostrictive phenomenon (converse piezoelectric phenomenon) occurs as indicated by the arrow. The electrostrictive phenomenon is a phenomenon in which mechanical displacement occurs due to expansion in the direction of the applied electric field (Z-axis direction). When the electrostrictive phenomenon occurs, structural defects such as cracks may occur in a region with low strength. For example, since the adhesion between the internal electrode layer 12 mainly composed of metal and the side margin 30 mainly composed of ceramic is low, there is a possibility that structural defects may occur near the interface between the internal electrode layer 12 and the side margin 30. The occurrence of structural defects causes a problem of reducing the breakdown voltage and the withstand voltage. The multilayer ceramic capacitor 100 according to the present embodiment has a configuration capable of suppressing the occurrence of structural defects.

[0031] FIG. 6 is an enlarged view of the YZ cross section. As illustrated in FIG. 6, the side margin 30 includes a first region 31 in contact with the base body 40, and a second region 32 located outside the first region 31 in the Y-axis direction. The first region 31 has a structure in which a plurality of ceramic grains 41 are sintered. The second region 32 has a structure in which a plurality of ceramic grains 42 are sintered. The average grain diameter of the ceramic grains 41 in the first region 31 is smaller than the average grain diameter of the ceramic grains 42 in the second region 32.

[0032] The first region 31 is provided at least from a portion in contact with an end portion in the Y-axis direction of one of the internal electrode layers 12 adjacent to each other to a portion in contact with an end portion in the Y-axis direction of the other internal electrode layer 12. The second region 32 is provided so as to cover the range where the first region 31 is provided in the Z-axis direction.

[0033] Since the grain diameter in the first region 31 is small, the number of grain boundaries increases in the first region 31, and the mechanical strength of the first region 31 increases. Since such a region with high mechanical strength is provided at least across two adjacent internal electrode layers, the adhesion between the internal electrode layer 12 and the first region 31 is maintained, and the occurrence of structural defects can be suppressed. If the overall grain diameter of the side margin 30 is small, there may occur a problem that the adhesion is impaired due to the difference in particle diameter from the dielectric layer (when there is a shrinkage difference between particles after firing). On the other hand, in the present embodiment, since the second region 32 having a larger grain diameter is provided outside the first region 31, this problem can be suppressed.

[0034] If the grain diameter in the first region 31 is not sufficiently small, there is a possibility that the number of grain boundaries will not increase sufficiently. Therefore, it is preferable to set an upper limit for the average grain diameter in the first region 31. In the present embodiment, the average grain diameter in the first region 31 is preferably 50 nm or less, more preferably 40 nm or less, and even more preferably 30 nm or less.

[0035] Further, the average grain diameter in the first region 31 is preferably 0.5 times or less, more preferably 0.4 times or less, and even more preferably 0.3 times or less, with respect to the average grain diameter in the second region 32.

[0036] If the average grain diameter in the first region 31 is too small, the surface may be too smooth, and the adhesion may be impaired in the second region forming step. Therefore, it is preferable to provide a lower limit for the average grain diameter in the first region 31. In the present embodiment, the average grain diameter in the first region 31 is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 30 nm or more.

[0037] Further, the average grain diameter in the first region 31 is preferably 0.1 times or more, more preferably 0.2 times or more, and even more preferably 0.3 times or more, with respect to the average grain diameter in the second region 32.

[0038] If the grain diameter in the second region 32 is not sufficiently large, there is a possibility of chipping. Therefore, it is preferable to provide a lower limit for the average grain diameter in the second region 32. In the present embodiment, the average grain diameter in the second region 32 is preferably 100 nm or more, more preferably 200 nm or more.

[0039] If the average grain diameter in the second region 32 is too large, the impact resistance may be lowered. Therefore, it is preferable to provide an upper limit for the average grain diameter in the second region 32. In the present embodiment, the average grain in the second region 32 is preferably 500 nm or less, more preferably 400 nm or less.

[0040] For example, in the side margin 30, the boundary between the first region 31 and the second region 32 is located at a position that is half, one-third, or one-fourth of the thickness of the side margin 30 in the Y-axis direction from the internal electrode layer 12.

[0041] For example, in the Y-axis direction, the thickness of the first region 31 is 1 μm or more and 150 μm or less. Also, in the Y-axis direction, the thickness of the second region 32 is 150 μm or more and 300 μm or less.

[0042] The average grain diameter in the first region 31 and the second region 32 can be measured by exposing the cross-section by polishing, determining the field of view of the SEM for imaging, measuring the maximum value of the diameter of each grain with image software or the like, and dividing by the number of grains.

[0043] Note that the first region 31 is provided at least across two adjacent internal electrode layers 12, and it is preferably provided from the portion in contact with the lowermost internal electrode layer 12 to the portion in contact with the uppermost internal electrode layer 12.

[0044] As illustrated in FIG. 6, the dielectric layer 11 has a structure in which ceramic grains 43 are sintered. The average grain diameter of the first region 31 is preferably smaller than the average grain diameter of the ceramic grains 43 in the dielectric layer 11. This is because the mechanical strength is enhanced.

[0045] Subsequently, a method for manufacturing the multilayer ceramic capacitor 100 will be described. FIG. 7 is a diagram illustrating the flow of a method for manufacturing the multilayer ceramic capacitor 100.

[0046] (Raw material powder production process) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site element and the B-site element contained in the dielectric layer 11 are usually ABO 3It is included in the dielectric layer 11 in the form of a sintered body of particles. For example, barium titanate is a tetragonal crystal compound having a perovskite structure and exhibits a high relative dielectric constant. This barium titanate can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate. As methods for synthesizing the main component ceramic of the dielectric layer 11, various conventional methods are known. For example, the solid phase method, the sol-gel method, the hydrothermal method, etc. are known. In the present embodiment, any of these can be employed.

[0047] A predetermined additive compound is added to the obtained ceramic raw material powder according to the purpose. Examples of the additive compound include oxides of zirconium, hafnium, magnesium, manganese, molybdenum, vanadium, chromium, rare earth elements (yttrium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium and ytterbium), or oxides containing cobalt, nickel, lithium, boron, sodium, potassium or silicon, or glasses containing cobalt, nickel, lithium, boron, sodium, potassium or silicon.

[0048] For example, a compound containing an additive compound is wet-mixed with the ceramic raw material powder, dried and pulverized to prepare a ceramic material. For example, with respect to the ceramic material obtained as described above, the particle size may be adjusted by pulverization treatment as necessary, or the particle size may be adjusted by combining with a classification treatment. Through the above steps, a dielectric material is obtained.

[0049] Next, a first side margin material for forming the first region 31 is prepared. The first side margin material contains the powder of the main component ceramic of the first region 31. As the powder of the main component ceramic, for example, the powder of the main component ceramic of the dielectric material can be used. A predetermined additive compound is added according to the purpose.

[0050] Next, prepare a second side margin material for forming the second region 32. The second side margin material contains powder of the main component ceramic of the second region 32. As the powder of the main component ceramic, for example, powder of the main component ceramic of a dielectric material can be used. Add a predetermined additive compound according to the purpose.

[0051] Make the particle size of the first side margin material smaller than that of the second side margin material.

[0052] (Coating process) Next, add a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer to the obtained raw material powder and perform wet mixing. Using the obtained slurry, coat and dry a ceramic green sheet 51 on a substrate by, for example, the die coater method or the doctor blade method. The substrate is, for example, a polyethylene terephthalate (PET) film. The figure illustrating the coating process is omitted.

[0053] (Internal electrode formation process) Next, by printing a metal conductive paste for forming an internal electrode containing an organic binder on the surface of the ceramic green sheet 51 by screen printing, gravure printing, etc., an internal electrode pattern 52 for the internal electrode layer is arranged. To the metal conductive paste, in addition to nickel, ceramic particles are added as a co-material. The main component of the ceramic particles is not particularly limited, but it is preferably the same as the main component ceramic of the dielectric layer 11. The ceramic green sheet 51 on which the internal electrode pattern 52 is printed is referred to as a lamination unit.

[0054] (Pressing process) Thereafter, as illustrated in FIG. 8, stack the lamination units. For example, set the number of stacked layers of the internal electrode pattern 52 to 100 to 500 layers. Stack a cover sheet 53 on the top and bottom of the laminate formed by stacking the lamination units by a predetermined number (for example, 2 to 10 layers) and perform thermocompression bonding.

[0055] (Cutting process) Thereafter, both ends of the ceramic laminate in the Y-axis direction are cut along the XZ plane.

[0056] (Side margin pasting process) Next, a binder such as ethyl cellulose and an organic solvent such as terpineol are added to the first side margin material obtained in the raw material powder production process, and kneaded with a roll mill to form a first side margin sheet 54, which is pasted on both sides of the ceramic laminate in the Y-axis direction as illustrated in FIG. 8. Also, a binder such as ethyl cellulose and an organic solvent such as terpineol are added to the second side margin material obtained in the raw material powder production process, and kneaded with a roll mill to form a second side margin sheet 55, which is pasted on the first side margin sheet 54 as illustrated in FIG. 8.

[0057] (Firing process) The ceramic laminate thus obtained is subjected to a debinding treatment in an N 2 atmosphere, and then a metal paste that will become the base layers 21 of the external electrodes 20a and 20b is applied by the dipping method, and firing is performed for 5 minutes to 10 hours in a reducing atmosphere with an oxygen partial pressure of 10 -5 ~10 -8 atm and a temperature range of 900°C to 1300°C.

[0058] (Re-oxidation treatment process) In order to return oxygen to the partially reduced main-phase ceramic material of the dielectric layer 11 fired in a reducing atmosphere, heat treatment is sometimes performed in a mixed gas of N 2 and water vapor at about 1000°C, or in the atmosphere at 500°C to 700°C. This process is called the re-oxidation treatment process.

[0059] (Plating process) Thereafter, a metal coating such as copper, nickel, or tin is formed on the base layer 21 by plating to form a plating layer 22. Through the above processes, the multilayer ceramic capacitor 100 is completed.

[0060] According to the manufacturing method according to this embodiment, since the particle size of the first side margin material is made smaller than the particle size of the second side margin material, the average grain diameter of the first region 31 obtained from the first side margin sheet 54 can be made smaller than the average grain diameter of the second region 32 obtained from the second side margin sheet 55.

[0061] In addition, when there is no difference in particle size between the first side margin material and the second side margin material, by including more of the material that promotes grain growth in the second side margin material than in the first side margin material, or by including more of the material that suppresses grain growth in the first side margin material than in the second side margin, the average grain diameter of the first region 31 obtained from the first side margin sheet 54 can be made smaller than the average grain diameter of the second region 32 obtained from the second side margin sheet 55.

[0062] (Modification example) FIG. 9 is a diagram schematically depicting one of the internal electrode layers 12 included in the stacked chip 10 and its surroundings in a plan view (XY plane) when viewed in the Z-axis direction. As illustrated in FIG. 9, in a region at the same height as the internal electrode layer 12 in the Z-axis direction, a portion corresponding to the end margin described in FIG. 2 may include a third region 15a having a small average grain diameter and a fourth region 15b provided outside the third region 15a and having an average grain diameter larger than that of the third region 15a. According to this configuration, since the grain diameter in the third region 15a is small, the number of grain boundaries increases in the third region 15a, and the mechanical strength of the third region 15a increases. Thereby, even when electrostrain occurs, the generation of structural defects can be suppressed. Further, since the fourth region 15b having a larger grain diameter is provided outside the third region 15a, an effect of ensuring the adhesion of the side margin can be obtained.

[0063] In each of the above embodiments, a multilayer ceramic capacitor has been described as an example of the multilayer ceramic electronic component, but it is not limited thereto. For example, other multilayer ceramic electronic components such as varistors and thermistors may be used.

[0064] As described above in detail with respect to the embodiments of the present invention, the present invention is not limited to such specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

Description of Reference Numerals

[0065] 10 Multilayer chip 11 Dielectric layer 12 Internal electrode layer 13 Cover layer 14 Capacitance section 15 End margin 15a Third region 15b Fourth region 20a, 20b External electrodes 30 Side margin 31 First region 32 Second region 40 Element body 51 Ceramic green sheet 52 Internal electrode pattern 53 Cover sheet 54 First side margin sheet 55 Second side margin sheet 100 Multilayer ceramic capacitor

Claims

1. An element body having a plurality of dielectric layers, and a plurality of internal electrode layers provided through the plurality of dielectric layers and alternately drawn out on two end faces facing each other; A pair of side margins sandwiching the element body in a third direction orthogonal to a first direction in which the plurality of internal electrode layers face each other and a second direction in which the two end faces face each other; The side margin includes a first region provided from a portion in contact with an end portion of one of the internal electrode layers in the third direction to a portion in contact with an end portion of the other internal electrode layer in the third direction among two adjacent internal electrode layers of the plurality of internal electrode layers, and a second region provided outside the first region in the third direction and having an average grain diameter larger than an average grain diameter of the first region. A multilayer ceramic electronic component.

2. The multilayer ceramic electronic component according to claim 1, wherein the first region is provided across the outermost internal electrode layer on one side in the first direction to the outermost internal electrode layer on the other side among the plurality of internal electrode layers.

3. The multilayer ceramic electronic component according to claim 1, wherein an average grain diameter in the first region is 50 nm or less.

4. The multilayer ceramic electronic component according to claim 1, wherein an average grain diameter in the first region is 10 nm or more.

5. The multilayer ceramic electronic component according to claim 1, wherein an average grain diameter in the second region is 100 nm or more.

6. The multilayer ceramic electronic component according to claim 1, wherein an average grain diameter in the second region is 500 nm or less.

7. The multilayer ceramic electronic component according to claim 1, wherein an average grain diameter in the first region is 0.5 times or less of an average grain diameter in the second region.

8. The multilayer ceramic electronic component according to claim 1, wherein an average grain diameter in the first region is 0.1 times or more of an average grain diameter in the second region.

9. The multilayer ceramic electronic component according to claim 1, wherein an average grain diameter in the first region is smaller than an average grain diameter in the dielectric layer.

10. Comprising a pair of external electrodes provided at both ends of the element body in the second direction, The plurality of internal electrode layers are alternately connected to the pair of external electrodes. In a region from an end of any one of the internal electrode layers in the second direction to the unconnected external electrode, a third region provided in contact with any one of the internal electrode layers, and a fourth region provided outside the third region in the second direction and having an average grain diameter larger than the average grain diameter of the third region, the multilayer ceramic electronic component according to claim 1.

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