Display device

Abstract

To provide a display device that offers an improved lighting ratio of light-emitting elements.SOLUTION: A display device according to an embodiment of the present invention comprises: a substrate including a plurality of sub pixels; a first lower assembly electrode provided in the plurality of sub pixels; a first assembly line provided in the plurality of sub pixels and on a layer different from that of the first lower assembly electrode; a light-emitting element provided on the first lower assembly electrode and the first assembly line, including a first electrode, a semiconductor layer, and a second electrode; and a second lower assembly electrode provided between the first lower assembly electrode and the light emitting element and electrically connected to the first electrode or the second electrode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This specification relates to a display device, and more particularly, to a display device in which LEDs (Light Emitting Diodes) are self-assembled.

Background Art

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light emitting display devices (OLEDs) that emit light by themselves, and liquid crystal display devices (LCDs) that require a separate light source.

[0003] The application range of display devices is diverse, not only for computer monitors and TVs but also for personal mobile devices. Research is underway on display devices that have a large display area while having a reduced volume and weight.

[0004] In recent years, display devices including LEDs (Light Emitting Diodes) have attracted attention as next-generation display devices. Since LEDs are made of inorganic substances rather than organic substances, they have excellent reliability and a longer lifespan compared to liquid crystal display devices and organic light emitting display devices. In addition, LEDs not only have a fast lighting speed, but also have excellent luminous efficiency, strong shock resistance, excellent stability, and can display high-brightness images.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by this specification is to provide a display device that improves the lighting rate of a light emitting element by arranging a lower assembly electrode that directly contacts the light emitting element below the light emitting element and connecting it to a power supply wiring.

[0006] The problems of this specification are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problem

[0007] In order to solve the problems as described above, a display device according to an embodiment of the present specification includes a substrate including a plurality of sub-pixels, a first lower assembly electrode disposed on the plurality of sub-pixels, a first assembly wiring disposed on the plurality of sub-pixels and disposed in a layer different from the first lower assembly electrode, a light-emitting element disposed on the first lower assembly electrode and the first assembly wiring and including a first electrode, a semiconductor layer, and a second electrode, and a second lower assembly electrode disposed between the first lower assembly electrode and the light-emitting element and electrically connected to the first electrode or the second electrode. Thereby, the assembly rate of the light-emitting element can be improved, the resistance of the power supply wiring can be reduced, and the lighting rate can be improved.

[0008] In order to solve the problems as described above, a display device according to another embodiment of the present specification includes a substrate including a plurality of sub-pixels, a first assembly wiring and a second assembly wiring arranged side by side on the plurality of sub-pixels, a light-emitting element disposed to overlap the first assembly wiring or the second assembly wiring, and a first lower auxiliary electrode and a second lower auxiliary electrode that overlap one of the first assembly wiring and the second assembly wiring and the light-emitting element below the light-emitting element. Thereby, the assembly rate of the light-emitting element can be improved, the resistance of the power supply wiring can be reduced, and the lighting rate can be improved.

[0009] Specific matters of other embodiments are included in the detailed description and the drawings.

Advantages of the Invention

[0010] According to the embodiments of the present specification, the intensity of the electric field for assembling the light-emitting element can be improved by arranging the assembly electrodes disposed inside the assembly grooves in different layers from each other.

[0011] And, according to the embodiments of the present specification, the light-emitting element can be fixed to the substrate even after the assembly of the light-emitting element by making the first electrode of the light-emitting element and the lower assembly electrode in direct contact.

[0012] According to the embodiments of this specification, by connecting the auxiliary electrode to the power supply wiring, the resistance of the power supply wiring can be reduced, and the lighting rate of the light-emitting element can be improved.

[0013] According to the embodiments of this specification, by disposing the light-emitting element in the planarization layer, the thickness of the planarization layer disposed on the light-emitting element can be reduced.

[0014] The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present invention.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6a

Figure 6b

Modes for Carrying Out the Invention

[0016] The advantages, features, and the methods for achieving them of this specification will become clear by referring to the embodiments described in detail hereinafter together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed hereinafter, but is configured in various different forms. Merely, these embodiments are provided so that the disclosure of this specification becomes complete and to fully inform those with ordinary knowledge in the technical field to which this specification pertains of the scope of the invention. This specification is only defined by the scope of the claims.

[0017] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, so this specification is not limited to the matters illustrated. Throughout the specification, the same reference signs refer to the same components. Also, when explaining this specification, if it is determined that a detailed description of related known technologies may muddy the gist of this specification, the detailed description thereof will be omitted. When terms such as "including", "having", "being made" as mentioned in this specification are used, other parts can be added as long as "only" is not used. When a component is expressed in the singular, it includes the case of including a plurality unless there are specific descriptions to the contrary.

[0018] When interpreting a component, it is interpreted as including an error range even without separate explicit descriptions.

[0019] When it is an explanation about the positional relationship, for example, when the positional relationship between two parts is described such as "on", "above", "below", "next to", etc., as long as "immediately" or "directly" is not used, one or more other parts may be positioned between the two parts.

[0020] An element or layer being referred to as "on" another element or layer includes both the case of being immediately above another element and the case of having another layer or another element intervening therebetween.

[0021] Also, although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical idea of this specification.

[0022] Throughout the specification, the same reference numerals refer to the same components.

[0023] The area and thickness of each configuration shown in the drawings are shown for convenience of explanation, and this specification is not necessarily limited to the area and thickness of the shown configuration.

[0024] The respective features of the various embodiments of this specification can be partially or wholly combined or combined with each other, enabling various interlocks and drives technically, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0025] Hereinafter, with reference to the accompanying drawings, various embodiments of the present invention will be described in detail.

[0026] FIG. 1 is a schematic plan view of a display device according to an embodiment of this specification.

[0027] In FIG. 1, for convenience of explanation, only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC among the various components of the display device 100 are shown.

[0028] Referring to FIG. 1, the display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD that supply various signals to the display panel PN, and a timing controller TC that controls the gate driver GD and the data driver DD.

[0029] The display panel PN is configured to display images for the user and includes a plurality of sub-pixels SP. A plurality of scan lines SL and a plurality of data lines DL intersect with each other in the display panel PN, and each of the plurality of sub-pixels SP is connected to the scan line SL and the data line DL. In addition, each of the plurality of sub-pixels SP may be connected to a high-potential power supply line VL1, a low-potential power supply line VL2, a reference line VL3, etc.

[0030] The plurality of sub-pixels SP are the minimum units that make up the screen, and each of the plurality of sub-pixels SP includes a light-emitting element and a pixel circuit for driving it. The plurality of light-emitting elements may be defined differently depending on the type of the display panel PN. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting element may be an LED (Light-emitting Diode) or a micro LED (Micro Light-emitting Diode).

[0031] The gate driver GD supplies a plurality of scan signals SCAN to the plurality of scan lines SL according to a plurality of gate control signals GCS provided from the timing controller TC. In FIG. 1, one gate driver GD is shown as being disposed at a distance from one side of the display panel PN, but the number and arrangement of the gate drivers GD are not limited thereto.

[0032] The data driver DD converts the video data RGB input from the timing controller TC into a data voltage Vdata using a reference gamma voltage according to a plurality of data control signals DCS provided from the timing controller TC. The data driver DD can supply the converted data voltage Vdata to the plurality of data lines DL.

[0033] The timing controller TC aligns the video data RGB input from the outside and supplies it to the data driving unit DD. The timing controller TC can generate a gate control signal GCS and a data control signal DCS by using a synchronization signal input from the outside, for example, a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal. Then, the timing controller TC supplies the generated gate control signal GCS and data control signal DCS to the gate driving unit GD and the data driving unit DD respectively, and can control the gate driving unit GD and the data driving unit DD.

[0034] In the following, the display panel PN of the display device 100 according to an embodiment of the present specification will be described in more detail.

[0035] FIG. 2 is a schematic plan view of a display panel included in a display device according to an embodiment of the present specification. In FIG. 2, for convenience of explanation, only the substrate 110, a plurality of pixels PX, pads, and wirings among various components of the display device 100 are shown.

[0036] The substrate 110 is a configuration for supporting various components included in the display panel PN and may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, or the like. Further, the substrate 110 may include a polymer or plastic and may be made of a material having flexibility.

[0037] The substrate 110 can be divided into a display area and a non-display area. The display area is an area where a plurality of pixels PX are arranged and an image is displayed. The plurality of pixels PX can include at least two or more sub-pixels. In the drawing, the plurality of pixels PX are shown as including three sub-pixels SP1, SP2, and SP3, but it is not limited thereto. The three sub-pixels include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. In the following, any one of the three sub-pixels may also be denoted as SP.

[0038] Each of the plurality of sub-pixels SP is an individual unit that emits light, and a light-emitting element 120 and a pixel circuit are arranged in each of the plurality of sub-pixels SP. A unit pixel including three sub-pixels SP1, SP2, and SP3 may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or may include at least two sub-pixels that emit light among a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, but is not limited thereto. The unit pixel may also include at least two or more sub-pixels including the light-emitting element with the lowest efficiency among a red light-emitting element, a green light-emitting element, and a blue light-emitting element.

[0039] The display device 100 according to an embodiment of the present specification includes a first sub-pixel SP1 that emits red light, a second sub-pixel SP2 that emits green light, and a third sub-pixel SP3 that emits blue light, and the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be arranged side by side in a row direction.

[0040] As mentioned above, the display area is an area where a plurality of unit pixels are arranged, and the non-display area is an area where no video is displayed and no plurality of unit pixels are arranged, that is, an area where a gate driving unit GD, wirings, pads for applying signals to the wirings, etc. for driving a plurality of sub-pixels SP arranged in the display area are arranged.

[0041] The gate driving unit GD supplies a gate signal to a plurality of sub-pixels SP through a gate wiring GL. The gate signal includes a scan signal and a light-emitting signal. The scan signal is provided through a scan wiring SL, and the light-emitting signal is provided through a light-emitting wiring EL. And the scan wiring SL and the light-emitting wiring EL may be collectively referred to as a gate wiring GL.

[0042] The gate driving unit GD includes a scan driver that provides a scan signal and a light-emitting driver that provides a light-emitting signal.

[0043] In the display device 100 according to an embodiment of the present specification, the gate driving unit GD is separated into a plurality of regions on the substrate 110 and may be arranged between a plurality of pixels PX.

[0044] In the display device 100 according to an embodiment of the present specification, the light-emitting element may be an LED (light emitting diode, an inorganic light-emitting element). Since the LED is excellent in luminous efficiency, the area occupied by the LED based on the sub-pixel SP region may be very small. Therefore, an LED and a pixel circuit for driving the same are arranged for each sub-pixel SP, and the gate driving unit GD may be arranged in the non-display region for at least one sub-pixel SP or at least one unit pixel.

[0045] The gate driving unit GD in FIG. 2 is arranged for every two unit pixels and can provide a gate signal to the sub-pixel SP arranged in the same row as the gate driving unit GD. For example, the gate driving unit GD may be arranged between the blue light-emitting sub-pixel and the red light-emitting sub-pixel. However, it is not limited thereto, and the arrangement density of the gate driving unit GD may be changed depending on the case.

[0046] And the scan driver and the light-emitting driver included in the gate driving unit GD are arranged in the same row but may be arranged in different regions respectively.

[0047] The data driving unit DD converts video data into data signals and supplies the converted data signals to the sub-pixels SP through the data lines DL. The data driving unit DD may be formed on the back surface of the substrate 110 or on a separate substrate. When the data driving unit DD is formed on one surface of a separate substrate, the data driving unit DD can be attached so that the other surface without the data driving unit DD faces the back surface of the substrate 110. In order to electrically connect the front and back surfaces of the substrate 110 or to electrically connect the front surface of the substrate 110 and the other surface of the separate substrate, side wirings are arranged on the side surface of the substrate 110 or on the substrate 110 and the separate substrate. Therefore, the data driving unit arranged on the back surface of the substrate 110 or the other surface of the separate substrate can supply data signals to the sub-pixels SP through the side wirings.

[0048] As described above, in the display device 100 according to an embodiment of the present specification, the gate driving unit GD can be disposed between adjacent unit pixels on the substrate 110. However, the present invention is not limited thereto, and the gate driving unit GD may be disposed on one side or both sides of the substrate 110.

[0049] On the other hand, the gate wiring GL can be disposed in the row direction on the substrate 110, and the data line DL can be disposed in the column direction. The gate wiring GL and the data line DL are disposed in all the sub-pixels SP and provide signals to the pixel circuits disposed in the sub-pixels SP.

[0050] Pad regions PA1 and PA2 on which pads are disposed are formed on both sides of the substrate 110, that is, on the upper and lower portions of the substrate 110 in the column direction. In this case, the pad region formed on the upper portion of the substrate 110 is referred to as a first pad region PA1, and the pad region formed on the lower portion of the substrate 110 is referred to as a second pad region PA2. In the substrate 110, the first pad region PA1 and the second pad region PA2 are regions facing each other.

[0051] In the first pad region PA1, a data pad DP connected to the data wiring DL, a gate pad GP connected to the gate driving unit GD, a high potential voltage pad VP1 connected to the high potential voltage wiring VL1, and a reference voltage pad VP3 connected to the reference voltage wiring VL3 can be disposed. In this case, the data pads are disposed in the same number as the number of sub-pixels SP included in the unit pixel.

[0052] Wiring for providing various clock signals, wiring for providing a gate low voltage, wiring for providing a gate high voltage, etc. are disposed in the gate driving unit GD so that signals can be transmitted. The gate driving units GD are arranged side by side in the column direction, and the wiring for transmitting signals to the gate driving units GD is aligned with the gate driving units GD. The wiring for transmitting signals to the gate driving unit GD is referred to as gate driving wiring GDSL. The gate driving wiring GDSL is disposed in the column direction and is connected to the gate pad GP disposed in the first pad region PA1 so as to receive signals from the gate pad GP.

[0053] The high-potential voltage wiring VL1 can be arranged in the column direction for each unit pixel or for each sub-pixel SP. In the drawing, it is shown as being arranged on the left / right side for each unit pixel PX, but it is not limited to this. The high-potential voltage wiring VL1 arranged in the column direction supplies a high-potential voltage to a plurality of sub-pixels SP through the high-potential voltage pad VP1 in the first pad region PA1. A plurality of high-potential voltage wirings VL1 arranged in the column direction are connected to the auxiliary high-potential voltage wiring AVL1 arranged in the row direction to form a mesh structure. The auxiliary high-potential voltage wiring AVL1 can be arranged for every row or for a plurality of rows in which the sub-pixels SP are arranged. The auxiliary high-potential voltage wiring AVL1 can prevent the voltage drop of the high-potential voltage wiring VL1 and supply a high-potential voltage to a plurality of sub-pixels SP.

[0054] In the second pad region PA2, a low-potential voltage pad VP2 connected to the low-potential voltage wiring can be arranged. In this case, the assembly wiring AL for self-assembling the light-emitting element is used as the low-potential voltage wiring after the light-emitting element is assembled.

[0055] For the assembly wiring AL, two assembly wirings can be arranged in the column direction for each sub-pixel SP. The assembly wiring AL includes a first assembly wiring 122 and a second assembly wiring 123. The assembly wiring AL arranged in the column direction supplies a low-potential voltage to a plurality of sub-pixels SP through the low-potential voltage pad VP2 in the second pad region PA2. A plurality of low-potential voltage pads VP2 are arranged, but can be arranged for at least every two assembly wirings.

[0056] The plurality of assembled wirings AL arranged in the column direction are connected to the auxiliary low potential voltage wiring AAL arranged in the row direction before being connected to the low potential voltage pad VP2. In the drawing, the auxiliary low potential voltage wiring AAL is shown only on one side surface of the substrate 110, but is not limited thereto, and may be arranged on at least one side surface of the substrate 110. Further, wirings for connecting the plurality of assembled wirings AL may be arranged in the row direction for every all rows or a plurality of rows in which the sub-pixels SP are arranged. Therefore, the auxiliary low potential voltage wiring AAL can prevent the voltage drop of the assembled wiring AL and provide a low potential voltage to the plurality of sub-pixels SP.

[0057] The reference voltage wiring VL3 can be arranged in the column direction for each one unit pixel arranged in the row direction. The reference voltage wiring VL3 arranged in the column direction provides a reference voltage to the unit pixel through separately arranged row direction wirings. The reference voltage wiring VL3 is connected to the reference voltage pad VP3 arranged in the first pad region PA1, and a reference voltage is provided to the plurality of reference voltage wirings VL3 through the reference voltage pad VP3.

[0058] The display panel PN included in the display device 100 according to an embodiment of the present specification can grind and remove the edges of the substrate 110 to reduce the bezel. The bezel is an edge region of the substrate 110 where the sub-pixels SP are not arranged. During grinding, a part of the pads and wirings arranged at the edges of the substrate 110 is removed, and the size of the substrate 110 becomes smaller, and the display panel PN can be configured to the size of the final substrate 110F.

[0059] Specifically, most of the pads arranged in the first pad region PA1 and the second pad region PA2 may be removed from the final substrate 110F, and only a part or a trace of the pads may remain.

[0060] In the following, for a more detailed description of the plurality of sub-pixels SP, reference is made to FIG. 2 together.

[0061] FIG. 3 is an enlarged plan view of a display device according to an embodiment of the present specification. FIG. 4 is a cross-sectional view taken along line A-A' and B-B' of FIG. 3. FIG. 5 is a cross-sectional view taken along line A-A' and C-C' of FIG. 3. Referring to FIG. 3, each of the plurality of sub-pixels SP includes a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor Cst, and one or more light-emitting elements LED. In FIG. 3, for the sake of simplicity of the drawing, the hatching of the first cladding layer 122b, the second cladding layer 123b, the pixel electrode PE, and the light-emitting element LED is omitted, and the illustration of the contact electrode CE is omitted.

[0062] Referring to FIGS. 3 and 4, the plurality of sub-pixels SP include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 includes a light-emitting element LED and a pixel circuit and can emit light independently. For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a blue sub-pixel, but is not limited thereto.

[0063] The display panel PN includes a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, a first passivation layer 114, a first planarization layer 115, a second passivation layer 116, a third passivation layer 117, and a second planarization layer 118.

[0064] A high-potential power supply wiring VL1, a plurality of data wirings DL, a reference wiring VL3, an assembly wiring AL, a light-shielding layer LS, and a first capacitor electrode SC1 are disposed on the substrate 110.

[0065] The high-potential power supply wiring VL1 is a wiring that transmits a high-potential power supply voltage to each of the plurality of sub-pixels SP. The plurality of high-potential power supply wirings VL1 can transmit the high-potential power supply voltage to the second transistors T2 of each of the plurality of sub-pixels SP. The high-potential power supply wiring VL1 can extend along the column direction among the plurality of sub-pixels SP. For example, the high-potential power supply wiring VL1 can be arranged along the column direction between the first sub-pixel SP1 and the third sub-pixel SP3. And the high-potential power supply wiring VL1 can transmit the high-potential power supply voltage to each of the plurality of sub-pixels SP arranged in the row direction through the auxiliary high-potential power supply wiring AVL1 described later. In this case, the high-potential voltage wiring VL1 can be referred to as the first power supply wiring. And the column direction can be referred to as the first direction, and the row direction can be referred to as the second direction.

[0066] The plurality of data wirings DL are wirings that transmit a data voltage Vdata to each of the plurality of sub-pixels SP. The plurality of data wirings DL can be connected to the first transistors T1 of each of the plurality of sub-pixels SP. The plurality of data wirings DL can extend along the column direction among the plurality of sub-pixels SP. For example, the data wiring DL extending in the column direction between the first sub-pixel SP1 and the high-potential power supply wiring VL1 transmits the data voltage Vdata to the first sub-pixel SP1, the data wiring DL arranged between the first sub-pixel SP1 and the second sub-pixel SP2 transmits the data voltage Vdata to the second sub-pixel SP2, and the data wiring DL arranged between the third sub-pixel SP3 and the high-potential power supply wiring VL1 can transmit the data voltage Vdata to the third sub-pixel SP3.

[0067] The reference wiring VL3 is a wiring that transmits a reference voltage to each of the plurality of sub-pixels SP. The reference wiring VL3 can be connected to the third transistor T3 of each of the plurality of sub-pixels SP. The reference wiring VL3 can extend along the column direction among the plurality of sub-pixels SP. For example, the reference wiring VL3 can extend along the column direction between the second sub-pixel SP2 and the third sub-pixel SP3. Then, the third drain electrodes DE3 of the third transistors T3 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 adjacent to the reference wiring VL3 can extend in the row direction and be electrically connected to the reference wiring VL3. In this case, the reference voltage wiring VL3 can be referred to as the third power supply wiring.

[0068] A light-shielding layer LS is disposed on the substrate 110 in each of the plurality of sub-pixels SP. The light-shielding layer LS can block light incident on the transistor below the substrate 110 to minimize leakage current. For example, the light-shielding layer LS can block light incident on the second active layer ACT2 of the second transistor T2 which is a driving transistor.

[0069] A first capacitor electrode SC1 is disposed on the substrate 110 in each of the plurality of sub-pixels SP. The first capacitor electrode SC1 can form a storage capacitor Cst together with other capacitor electrodes. The first capacitor electrode SC1 can be formed integrally with the light-shielding layer LS.

[0070] A buffer layer 111 is disposed on the high-potential power supply wiring VL1, the plurality of data wirings DL, the reference wiring VL3, the light-shielding layer LS, and the first capacitor electrode SC1. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be composed of, for example, a single layer or a multi-layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 may be omitted depending on the type of the substrate 110 or the type of the transistor, and is not limited thereto.

[0071] First, a first transistor T1 is disposed on a buffer layer 111 for each of a plurality of sub-pixels SP. The first transistor T1 is a transistor that transmits a data voltage Vdata to a second gate electrode GE2 of a second transistor T2. The first transistor T1 can be turned on by a scan signal from a scan wiring SL, and the data voltage Vdata can be transmitted from a data wiring DL through the turned-on first transistor T1 to the second gate electrode GE2 of the second transistor T2. Therefore, the first transistor T1 can be referred to as a switching transistor.

[0072] The first transistor T1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0073] The first active layer ACT1 is disposed on the buffer layer 111. The first active layer ACT1 can be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0074] A gate insulating layer 112 is disposed on the first active layer ACT1. The gate insulating layer 112 is an insulating layer for insulating the first active layer ACT1 and the first gate electrode GE1, and can be composed of a single layer or a multi-layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0075] The first gate electrode GE1 is disposed on the gate insulating layer 112. The first gate electrode GE1 can be electrically connected to the scan wiring SL. The first gate electrode GE1 can be composed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0076] An interlayer insulating layer 113 is disposed on the first gate electrode GE1. Contact holes for connecting the first source electrode SE1 and the first drain electrode DE1 to the first active layer ACT1 are formed in the interlayer insulating layer 113, respectively. The interlayer insulating layer 113 is an insulating layer for protecting the structure below the interlayer insulating layer 113, and may be composed of a single layer or a multilayer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0077] A first source electrode SE1 and a first drain electrode DE1 electrically connected to the first active layer ACT1 are disposed on the interlayer insulating layer 113. The first drain electrode DE1 may be connected to the data wiring DL and the first active layer ACT1, and the first source electrode SE1 may be connected to the first active layer ACT1 and the second gate electrode GE2 of the second transistor T2. The first source electrode SE1 and the first drain electrode DE1 may be composed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0078] A second transistor T2 is disposed on the buffer layer 111 in each of the plurality of sub-pixels SP. The second transistor T2 is a transistor that supplies a driving current to the light-emitting element LED. The second transistor T2 can be turned on to control the driving current flowing through the light-emitting element LED. Therefore, the second transistor T2 that controls the driving current may be referred to as a driving transistor.

[0079] The second transistor T2 includes a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0080] A second active layer ACT2 is disposed on the buffer layer 111. The second active layer ACT2 may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0081] A gate insulating layer 112 is disposed on the second active layer ACT2, and a second gate electrode GE2 is disposed on the gate insulating layer 112. The second gate electrode GE2 can be electrically connected to the first source electrode SE1 of the first transistor T1. The second gate electrode GE2 can be composed of, but is not limited to, a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0082] The size of the second active layer ACT2 can vary depending on the type of the light-emitting element LED connected to the second transistor T2. In this case, since the type of the light-emitting element LED means the type of light emitted, the size of the second active layer ACT2 can vary depending on a red light-emitting element, a green light-emitting element, or a blue light-emitting element. Since the larger the size of the second active layer ACT2, the larger the driving current, the size of the second active layer ACT2 can be determined by the efficiency of the light-emitting element LED.

[0083] For example, in FIG. 3, the size of the second active layer ACT2 disposed in the first sub-pixel SP1 is the largest, the size of the second active layer ACT2 disposed in the second sub-pixel SP2 is smaller than the size of the second active layer ACT2 disposed in the first sub-pixel SP1, and the size of the second active layer ACT2 disposed in the third sub-pixel SP3 is smaller than the size of the second active layer ACT2 disposed in the second sub-pixel SP2. In this case, the light-emitting element LED disposed in the first sub-pixel SP1 may be a red light-emitting element, the light-emitting element LED disposed in the second sub-pixel SP2 may be a green light-emitting element, and the light-emitting element LED disposed in the third sub-pixel SP3 may be a blue light-emitting element, but is not limited thereto.

[0084] An interlayer insulating layer 113 is disposed on the second gate electrode GE2, and a second source electrode SE2 and a second drain electrode DE2, which are electrically connected to the second active layer ACT2, are disposed on the interlayer insulating layer 113. The second drain electrode DE2 can be electrically connected to the second active layer ACT2 and the high potential power supply wiring VL1, and the second source electrode SE2 can be electrically connected to the second active layer ACT2 and the light emitting element LED. The second source electrode SE2 and the second drain electrode DE2 can be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0085] A third transistor T3 is disposed on the buffer layer 111 in each of the plurality of sub-pixels SP. The third transistor T3 is a transistor for compensating the threshold voltage of the second transistor T2. The third transistor T3 is connected between the second source electrode SE2 of the second transistor T2 and the reference wiring VL3. The third transistor T3 can be turned on to transmit a reference voltage to the second source electrode SE2 of the second transistor T2 to sense the threshold voltage of the second transistor T2. Therefore, the third transistor T3 for sensing the characteristics of the second transistor T2 can be referred to as a sensing transistor.

[0086] The third transistor T3 includes a third active layer ACT3, a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3.

[0087] A third active layer ACT3 is disposed on the buffer layer 111. The third active layer ACT3 can be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0088] A gate insulating layer 112 is disposed on the third active layer ACT3, and a third gate electrode GE3 is disposed on the gate insulating layer 112. The third gate electrode GE3 can be electrically connected to the scan wiring SL. The third gate electrode GE3 can be composed of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0089] An interlayer insulating layer 113 is disposed on the third gate electrode GE3, and a third source electrode SE3 and a third drain electrode DE3 that are electrically connected to the third active layer ACT3 are disposed on the interlayer insulating layer 113. The third drain electrode DE3 can be electrically connected to the third active layer ACT3 and the reference wiring RL, and the third source electrode SE3 can be electrically connected to the third active layer ACT3 and the second source electrode SE2 of the second transistor T2. The third source electrode SE3 and the third drain electrode DE3 can be composed of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0090] Both the first transistor T1 and the third transistor T3 shown in FIG. 3 are transistors connected to and controlled by the scan wiring SL, but are not limited thereto, and the pixel circuit can include a transistor connected to the light-emitting wiring EL.

[0091] Next, a second capacitor electrode SC2 is disposed on the gate insulating layer 112. The second capacitor electrode SC2 is one of the electrodes forming the storage capacitor Cst and can be disposed so as to overlap the first capacitor electrode SC1. The second capacitor electrode SC2 can be integrally formed with the second gate electrode GE2 of the second transistor T2 and can be electrically connected to the second gate electrode GE2. The first capacitor electrode SC1 and the second capacitor electrode SC2 can be disposed apart from each other with the buffer layer 111 and the gate insulating layer 112 interposed therebetween.

[0092] Then, a plurality of scan wirings SL, an auxiliary high-potential power supply wiring AVL1, a first lower assembly electrode 121, and a third capacitor electrode SC3 are arranged on the interlayer insulating layer 113.

[0093] First, the scan wiring SL is a wiring that transmits a scan signal SCAN to each of the plurality of sub-pixels SP. The scan wiring SL can extend in the row direction across the plurality of sub-pixels SP. The scan wiring SL can be electrically connected to the first gate electrode GE1 of the first transistor T1 and the third gate electrode GE3 of the third transistor T3 of each of the plurality of sub-pixels SP.

[0094] The auxiliary high-potential power supply wiring AVL1 is arranged on the interlayer insulating layer 113. The auxiliary high-potential power supply wiring AVL1 can extend in the row direction and be arranged across the plurality of sub-pixels SP. The auxiliary high-potential power supply wiring AVL1 can be electrically connected to the second drain electrode DE2 of the second transistor T2 of each of the plurality of sub-pixels SP arranged along the row direction and the high-potential power supply wiring VL1 extending in the column direction.

[0095] The first lower assembly electrode 121 is arranged on the interlayer insulating layer 113. The first lower assembly electrode 121 can be partially formed in a region of the sub-pixel SP that overlaps with the light-emitting element LED. The first lower assembly electrode 121 is arranged to overlap with the light-emitting element LED and the second assembly wiring 123 described later, and is electrically connected to the second assembly wiring 123. The first lower assembly electrode 121 is a component arranged in each of the plurality of sub-pixels SP and is not shared with other sub-pixels SP.

[0096] A third capacitor electrode SC3 is disposed on the interlayer insulating layer 113. The third capacitor electrode SC3 is an electrode that forms the storage capacitor Cst, and can be disposed so as to overlap the first capacitor electrode SC1 and the second capacitor electrode SC2. The third capacitor electrode SC3 is integrally formed with the second source electrode SE2 of the second transistor T2 and can be electrically connected to the second source electrode SE2. And the second source electrode SE2 can also be electrically connected to the first capacitor electrode SC1 through contact holes formed in the interlayer insulating layer 113 and the buffer layer 111. Therefore, the first capacitor electrode SC1 and the third capacitor electrode SC3 can be electrically connected to the second source electrode SE2 of the second transistor T2.

[0097] The storage capacitor Cst can store the potential difference between the second gate electrode GE2 and the second source electrode SE2 of the second transistor T2 while the light-emitting element LED emits light, so that a constant current is supplied to the light-emitting element LED. The storage capacitor Cst is formed on the substrate 110, includes a first capacitor electrode SC1 connected to the second source electrode SE2, a second capacitor electrode SC2 formed on the buffer layer 111 and the gate insulating layer 112 and connected to the second gate electrode GE2, and a third capacitor electrode SC3 formed on the interlayer insulating layer 113 and connected to the second source electrode SE2, and can store the voltage between the second gate electrode GE2 and the second source electrode SE2 of the second transistor T2.

[0098] A first passivation layer 114 is disposed on the first transistor T1, the second transistor T2, the third transistor T3, and the storage capacitor Cst. The first passivation layer 114 is an insulating layer for protecting the structure below the first passivation layer 114, and can be composed of a single layer or a multi-layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0099] A first planarization layer 115 is disposed on the first passivation layer 114. The first planarization layer 115 can planarize the upper part of a substrate 110 on which a plurality of transistors T1, T2, T3 and a storage capacitor Cst are disposed. The first planarization layer 115 may be configured as a single layer or a multi-layer, and may be made of, for example, a photoresist or an acrylic-based organic material, but is not limited thereto.

[0100] The first planarization layer 115 and the first passivation layer 114 include an assembly groove LH1 for disposing a light-emitting element LED. The first planarization layer 115 and the first passivation layer 114 cover an edge of the first lower assembly electrode 121 to expose a part of the first lower assembly electrode 121. The assembly groove LH1 is a region where the first planarization layer 115 and the first passivation layer 114 are removed, and a part of the first lower assembly electrode 121 and a part of the interlayer insulating layer 113 are exposed. The assembly groove LH1 may be formed in the same pattern as the pattern of the light-emitting element LED disposed in the assembly groove LH1. However, the size of the assembly groove LH1 is substantially the same as or larger than the size of the light-emitting element LED so that the light-emitting element LED can be disposed in the assembly groove LH1.

[0101] A second passivation layer 116 is disposed on the first planarization layer 115. Specifically, the second passivation layer 116 is disposed not only on the first planarization layer 115 but also on the first lower assembly electrode 121 and the interlayer insulating layer 113 disposed in the assembly groove LH1. The second passivation layer 116 is an insulating layer for protecting the structure below the second passivation layer 116, and may be configured as a single layer or a multi-layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0102] A connection electrode 120, a plurality of first assembly wirings 122, and a plurality of second assembly wirings 123 are disposed on the second passivation layer 116.

[0103] First, connection electrodes 120 are disposed for each of the plurality of sub-pixels SP. The connection electrode 120 is an electrode that electrically connects the second transistor T2 and the pixel electrode PE. The connection electrode 120 can be electrically connected to the second source electrode SE2 and the third capacitor electrode SC3 through contact holes formed in the second passivation layer 116, the first planarization layer 115, and the first passivation layer 114.

[0104] The connection electrode 120 may have a multilayer structure including a first connection layer 120a and a second connection layer 120b. The first connection layer 120a is disposed on the second passivation layer 116, and the second connection layer 120b covering the first connection layer 120a is disposed. The second connection layer 120b can be disposed so as to entirely surround the upper surface and the side surface of the first connection layer 120a. The second connection layer 120b is made of a material more resistant to corrosion than the first connection layer 120a, and can minimize a short circuit defect due to migration between wirings adjacent to the first connection layer 120a during the manufacture of the display device 100. For example, the first connection layer 120a may be made of a conductive material such as copper (Cu) and chromium (Cr), and the second connection layer 120b may be made of molybdenum (Mo), molybdenum titanium (MoTi), etc., but is not limited thereto.

[0105] A plurality of assembled wirings AL are arranged on the second passivation layer 116. Specifically, the plurality of assembled wirings AL are arranged on the first planarization layer 115 disposed around the assembly groove LH1. The plurality of assembled wirings AL are wirings that transmit a low-potential power supply voltage to the light-emitting element LED. The plurality of assembled wirings AL can extend in the column direction in each of the plurality of sub-pixels SP. For example, a pair of assembled wirings AL spaced apart from each other at regular intervals can be arranged in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The pair of assembled wirings AL includes a first assembled wiring 122 and a second assembled wiring 123. Either one of the first assembled wiring 122 and the second assembled wiring 123 is arranged to overlap with the first lower assembled electrode 121. In FIG. 4, the second assembled wiring 123 is shown as being arranged to overlap with the first lower assembled electrode 121, but it is not limited thereto.

[0106] Each of the plurality of assembled wirings AL includes a conductive layer and a cladding layer. The conductive layer is arranged on the second passivation layer 116, and the cladding layer that covers all of the upper surface and the side surface of the conductive layer is arranged on the conductive layer. Specifically, a first conductive layer 122a and a second conductive layer 123a are arranged on the second passivation layer 116, and a first cladding layer 122b and a second cladding layer 123b are arranged on the first conductive layer 122a and the second conductive layer 123a. For example, the first conductive layer 122a and the second conductive layer 123a can be made of a conductive material such as copper (Cu) and chromium (Cr). And the first cladding layer 122b and the second cladding layer 123b can be made of a material more resistant to corrosion than the first conductive layer 122a and the second conductive layer 123a, for example, molybdenum (Mo), molybdenum titanium (MoTi), etc., but it is not limited thereto.

[0107] Specifically, the first cladding layer 122b covers the upper surface and the side surface of the first conductive layer 122a and is also disposed on the side surface of the first planarization layer 115 and inside the assembly groove LH1. The first cladding layer 122b disposed inside the assembly groove LH1 overlaps with the light-emitting element LED. The first cladding layer 122b disposed on the side surface of the first planarization layer 115 and inside the assembly groove LH1 may be disposed only in a region that does not entirely cover the side surface of the first planarization layer 115 and inside the assembly groove LH1 and corresponds to less than half. And the second cladding layer 123b covers the upper surface and the side surface of the second conductive layer 123a and is not disposed on the side surface of the first planarization layer 115 and inside the assembly groove LH1.

[0108] By disposing the first cladding layer 122b and the first lower assembly electrode 121 disposed inside the assembly groove LH1 in different layers from each other, the distance between the first cladding layer 122b and the first lower assembly electrode 121 can be reduced. The smaller the distance between the assembly electrodes disposed inside the assembly groove LH1 for assembling the light-emitting element LED, the greater the electric field strength and the better the assembly force can be improved. When the first cladding layer 122b and the first lower assembly electrode 121 are disposed in the same layer, there is a limit to reducing the distance between the first cladding layer 122b and the first lower assembly electrode 121. Therefore, in the display device 100 according to an embodiment of the present specification, by disposing the first cladding layer 122b and the first lower assembly electrode 121 that are disposed inside the assembly groove LH1 and form an electric field in different layers from each other, the assembly force for assembling the light-emitting element LED can be improved.

[0109] The second conductive layer 123a disposed on each of the plurality of sub-pixels SP is electrically connected to the first lower assembly electrode 121 through the wiring contact electrode LCE. The wiring contact electrode LCE is disposed in the wiring contact hole LH2 formed in the second passivation layer 116, the first planarization layer 115, and the first passivation layer 114. The wiring contact hole LH2 can be formed through two contact hole formation processes. The first wiring contact hole LH2a can be formed through the first contact hole formation process, and the second wiring contact hole LH2b can be formed through the second contact hole formation process. The first wiring contact hole LH2a is a contact hole formed in the first planarization layer 115 and the first passivation layer 114, and the second wiring contact hole LH2b is a contact hole formed in the second passivation layer 116. That is, the wiring contact hole LH2 can include the first wiring contact hole LH2a and the second wiring contact hole LH2b. In this case, the size of the first wiring contact hole LH2a may be larger than the size of the second wiring contact hole LH2b for alignment of the first wiring contact hole LH2a and the second wiring contact hole LH2b.

[0110] On one side, a second lower assembly electrode 125 is disposed on the second passivation layer 116. The second lower assembly electrode 125 can be formed of the same material by the same process as the first cladding layer 122b, the second cladding layer 123b, and the second connection layer 120b. The second lower assembly electrode 125 is disposed inside the assembly groove LH1 and makes direct contact with the light-emitting element LED. Then, the second lower assembly electrode 125 is separated from the first cladding layer 122b and is partially disposed overlapping the first lower assembly electrode 121. Before the light-emitting element LED is disposed, the second lower assembly electrode 125 can be coupled with the signal applied through the first lower assembly electrode 121 in a floating state and serve as an assembly wiring. Not only the assembly wiring AL but also any of the first lower assembly electrode 121 electrically connected to the assembly wiring AL and the second lower assembly electrode 125 coupled with the first lower assembly electrode 121 can form an electric field for self-assembling the light-emitting element LED.

[0111] A third passivation layer 117 is disposed on the connection electrode 120 and the assembly wiring AL. Specifically, the third passivation layer 117 exposes all of the second lower assembly electrode 125 and a part of the assembly wiring AL to the outside. The third passivation layer 117 is an insulating layer for protecting the configuration below the third passivation layer 117 and can be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0112] Next, a plurality of light-emitting elements LED are arranged on the third passivation layer 117 and the second lower assembly electrode 125. The light-emitting element LED is arranged inside the assembly groove LH1. One or more light-emitting elements LED are arranged in one sub-pixel SP. The light-emitting element LED is an element that emits light by current. The light-emitting element LED can include light-emitting elements LED that emit red light, green light, blue light, etc., and various hues of light including white can be realized by these combinations. Also, various hues of light can be realized by using a light-emitting element LED that emits light of a specific hue and a light conversion member that converts light from the light-emitting element LED into light of another hue. The light-emitting element LED is electrically connected between the second transistor T2 and the assembly wiring AL, and can emit light by receiving a driving current from the second transistor T2.

[0113] At this time, the plurality of light-emitting elements LED arranged in one sub-pixel SP can be connected in parallel. That is, one electrode of each of the plurality of light-emitting elements LED can be connected to the source electrode of the same second transistor T2, and the other electrode can be connected to the same assembly wiring AL.

[0114] On the other hand, the light-emitting elements LED arranged in each of the plurality of sub-pixels SP can have different structures from each other. For example, the light-emitting element LED can include a first light-emitting element 130 and a second light-emitting element 140. The first light-emitting element 130 can be arranged in the first sub-pixel SP1 among the plurality of sub-pixels SP, and the second light-emitting element 140 can be arranged in the second sub-pixel SP2 and the third sub-pixel SP3 among the plurality of sub-pixels SP. However, the type of the light-emitting element LED is exemplary, and only one of the first light-emitting element 130 or the second light-emitting element 140 can be used as the light-emitting element LED, or other types of light-emitting elements LED can be used, and it is not limited thereto. Also, in FIGS. 4 and 5, for convenience of explanation, it is shown that two light-emitting elements LED are arranged in each of the plurality of sub-pixels SP, but the number of light-emitting elements LED arranged in each of the plurality of sub-pixels SP is not limited thereto.

[0115] Referring to FIG. 4, among a plurality of light-emitting elements LED, the first light-emitting element 130 includes a first semiconductor layer 131, a light-emitting layer 132, a second semiconductor layer 133, a first electrode 134, a second electrode 135, and a sealing layer 136.

[0116] The first semiconductor layer 131 is disposed on the third passivation layer 117, and the second semiconductor layer 133 is disposed on the first semiconductor layer 131. The first semiconductor layer 131 and the second semiconductor layer 133 may be layers formed by doping a specific substance with n-type and p-type impurities. For example, the first semiconductor layer 131 and the second semiconductor layer 133 may be layers doped with p-type or n-type impurities in substances such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. And the p-type impurity may be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium (Ge), tin (Sn), etc., but is not limited thereto.

[0117] A part of the first semiconductor layer 131 may be disposed to protrude outside the second semiconductor layer 133. The upper surface of the first semiconductor layer 131 may be composed of a portion overlapping with the lower surface of the second semiconductor layer 133 and a portion disposed outside the lower surface of the second semiconductor layer 133. However, the sizes and shapes of the first semiconductor layer 131 and the second semiconductor layer 133 can be variously deformed and are not limited thereto.

[0118] The light-emitting layer 132 is disposed between the first semiconductor layer 131 and the second semiconductor layer 133. The light-emitting layer 132 can receive the supply of holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133 and emit light. The light-emitting layer 132 may be formed in a single-layer or multi-quantum well (MQW) structure, and may be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), etc., but is not limited thereto.

[0119] A first electrode 134 is disposed to surround the lower surface and side surfaces of the first semiconductor layer 131. The first electrode 134 is an electrode for electrically connecting the first light-emitting element 130 and the assembly wiring AL. The first electrode 134 can be formed of a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0120] A second electrode 135 is disposed on the upper surface of the second semiconductor layer 133. The second electrode 135 is an electrode for electrically connecting the pixel electrode PE, which will be described later, and the second semiconductor layer 133. The second electrode 135 can be formed of a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0121] A sealing layer 136 is disposed to surround at least a part of the first semiconductor layer 131, the light-emitting layer 132, the second semiconductor layer 133, the first electrode 134, and the second electrode 135. The sealing layer 136 is made of an insulating material and can protect the first semiconductor layer 131, the light-emitting layer 132, and the second semiconductor layer 133. The sealing layer 136 can be disposed to cover the light-emitting layer 132, a part of the side surface of the first semiconductor layer 131 adjacent to the light-emitting layer 132, and a part of the side surface of the second semiconductor layer 133 adjacent to the light-emitting layer 132. The first electrode 134 and the second electrode 135 can be exposed from the sealing layer 136, and the chip contact electrode CCE and the pixel electrode PE, which are formed later, can be electrically connected to the first electrode 134 and the second electrode 135.

[0122] Referring to FIG. 5, the second light-emitting element 140 includes a first semiconductor layer 141, a light-emitting layer 142, a second semiconductor layer 143, a first electrode 144, a second electrode 145, and a sealing layer 146. The first semiconductor layer 141, the light-emitting layer 142, the second semiconductor layer 143, the second electrode 145, and the sealing layer 146 of the second light-emitting element 140 may be substantially the same as the first semiconductor layer 131, the light-emitting layer 132, the second semiconductor layer 133, the second electrode 135, and the sealing layer 136 of the first light-emitting element 130. However, the second light-emitting element 140 is different only in the structure of the first electrode 144 compared with the first light-emitting element 130, and the other configurations are substantially the same.

[0123] The first electrode 144 of the second light-emitting element 140 is disposed so as to be in contact with only the lower surface of the first semiconductor layer 141. Compared with the first light-emitting element 130 in which the first electrode 134 covers both the lower surface and the side surface of the first semiconductor layer 131, in the second light-emitting element 140, since the first electrode 144 is disposed only on the lower surface of the first semiconductor layer 141, the side surface of the first semiconductor layer 141 of the second light-emitting element 140 can be exposed from the first electrode 144. Therefore, the chip contact electrode CCE can be electrically connected to the second light-emitting element 140 in contact with the side surface of the first semiconductor layer 141 and the side surface of the first electrode 144.

[0124] Next, an adhesive layer may be disposed between the plurality of light-emitting elements LED, the third passivation layer 117, and the second lower assembly electrode 125. The adhesive layer may be an organic film that temporarily fixes the light-emitting element LED during the self-assembly process of the light-emitting element LED. When manufacturing the display device 100, if an organic film covering the light-emitting element LED is formed, a part of the organic film is filled in the space between the light-emitting element LED, the third passivation layer 117, and the second lower assembly electrode 125, and the light-emitting element LED can be temporarily fixed on the third passivation layer 117 and the second lower assembly electrode 125. Thereafter, even if the organic film is removed, a part of the organic film that has penetrated below the light-emitting element LED remains without being removed and can become the adhesive layer. The adhesive layer may be made of an organic substance, for example, a photoresist or an acrylic-based organic substance, but is not limited thereto.

[0125] A chip contact electrode CCE is arranged on the side surface of the light-emitting element LED. The chip contact electrode CCE is an electrode for electrically connecting the light-emitting element LED and the assembly wiring AL. It is also arranged on the upper part of the assembly wiring AL where the third passivation layer 117 is not arranged and on the second passivation layer 116 arranged on the side surface of the assembly groove LH1. The chip contact electrode CCE can also cover the edge part of the assembly wiring AL. The chip contact electrode CCE is arranged so as to surround at least a part of the first semiconductor layers 131 and 141 and the first electrodes 134 and 144 of the light-emitting element LED, and can electrically connect the first semiconductor layers 131 and 141 and the first electrodes 134 and 144 to the assembly wiring AL. In this case, the chip contact electrode CCE is also connected to the second lower assembly electrode 125. By also connecting the second lower assembly electrode 125 that directly contacts the lower surface of the first electrodes 134 and 144 to electrically connect the second assembly wiring 123 and the light-emitting element LED, the contact resistance of the second assembly wiring 123 can be reduced. Thereby, the lighting rate of the light-emitting element LED can be improved. The lighting rate may mean the ratio of the number of light-emitting element LEDs that emit light normally among all the light-emitting element LEDs arranged on the display panel.

[0126] Next, a second planarization layer 118 is arranged on the light-emitting element LED and the chip contact electrode CCE. The second planarization layer 118 planarizes the upper part of the substrate 110 on which the light-emitting element LED is arranged, and can fix the light-emitting element LED on the substrate 110 together with the adhesive layer. The light-emitting element LED included in the display device 100 according to an embodiment of the present specification is arranged inside the assembly groove LH1 formed in the first planarization layer 115, thereby reducing the thickness of the second planarization layer 118 and enabling a single-layer configuration. However, it is not limited to this, and the second planarization layer 118 may be configured as a single layer or a multi-layer, and may be made of, for example, a photoresist or an acrylic-based organic substance, but is not limited to this.

[0127] A protective layer 119 is disposed on the second planarization layer 118 and the light-emitting element LED. The protective layer 119 is disposed in a region excluding a part of the second electrodes 135 and 145 of the light-emitting element LED. The protective layer 119 is an insulating layer for protecting the structure below the protective layer 119, and may be composed of a single layer or a multilayer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0128] A pixel electrode PE is disposed on the protective layer 119. The pixel electrode PE is an electrode for electrically connecting the plurality of light-emitting elements LED and the connection electrode 120. The pixel electrode PE can be electrically connected to the light-emitting element LED, the connection electrode 120, and the second transistor T2 through a contact hole formed in the second planarization layer 118. Therefore, the second electrodes 135 and 145 of the light-emitting element LED, the connection electrode 120, and the second source electrode SE2 of the second transistor T2 can be electrically connected to each other through the pixel electrode PE. The pixel electrode PE can be composed of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0129] In the display device 100 according to an embodiment of the present specification, a pair of assembly wirings AL disposed in each of the plurality of sub-pixels SP, a first lower assembly electrode 121 connected to one of the pair of assembly wirings AL, and a second lower assembly electrode 125 disposed so as to overlap the first lower assembly electrode 121 are electrodes for self-assembling the light-emitting element LED. During the manufacture of the display device 100, the first lower assembly electrode 121 and the second lower assembly electrode 125 can form an electric field together with the pair of assembly wirings AL to self-assemble the light-emitting element LED.

[0130] Hereinafter, with reference to FIGS. 6a to 6b, a method for self-assembling the light-emitting element LED of the display device 100 according to an embodiment of the present specification will be described.

[0131] FIG. 6A and FIG. 6B are cross-sectional views for explaining a manufacturing process of a display device according to an embodiment of the present specification.

[0132] First, referring to FIG. 6A, a buffer layer 111 and an interlayer insulating layer 113 are formed on a substrate 110, and a first lower assembly electrode 121 is formed on the interlayer insulating layer 113.

[0133] Next, a first passivation layer 114, a first planarization layer 115, and a second passivation layer 116 are sequentially formed on the first lower assembly electrode 121, and an assembly electrode AL and a second lower assembly electrode 125 are formed on the second passivation layer 116.

[0134] The second assembly wiring 123, the first lower assembly electrode 121, and the second lower assembly electrode 125 can function as a pair of low-potential power supply wirings after the manufacturing of the display device 100 is completed. During the manufacturing process of the display device 100, different voltages are applied to two adjacent assembly electrodes AL, and after the manufacturing process of the display device 100 is completed, the same low-potential power supply voltage can be applied to two adjacent assembly electrodes AL.

[0135] The first assembly wiring 122 disposed on the second passivation layer 116 includes a first conductive layer 122a and a first cladding layer 122b covering the first conductive layer 122a.

[0136] The second assembly wiring 123 is disposed on the second passivation layer 116. The second assembly wiring 123 includes a second conductive layer 123a and a second cladding layer 123b covering the second conductive layer 123a. The second conductive layer 123a of the second assembly wiring 123 can be electrically connected to the first lower assembly electrode 125 through contact holes formed in the second passivation layer 116, the first planarization layer 115, and the first passivation layer 114. Therefore, the formation of the assembly electrode including the assembly wiring AL and the lower assembly electrodes 121 and 125 can be completed.

[0137] Next, a third passivation layer 117 is formed on the assembled electrode AL, and an organic layer DAL having an opening DALH is formed on the third passivation layer 117. The opening DALH of the organic layer DAL may correspond to the region where the light-emitting element LED is self-assembled. The opening DALH of the organic layer DAL may overlap the assembled wiring AL and the lower assembled electrodes 121, 125. The organic layer DAL is removed after the self-assembly of the light-emitting element LED is completed and does not exist in the display device 100 completed during the manufacturing process.

[0138] The substrate 110 on which the organic layer DAL is formed and the light-emitting element LED are placed inside a chamber filled with a fluid, and an alternating voltage can be applied to the assembled electrode including the assembled wiring AL and the lower assembled electrodes 121, 125 to form an electric field. For example, the same voltage is applied to the second assembled wiring 123 and the first lower assembled electrode 121, and the second lower assembled electrode 125 is coupled to the first lower assembled electrode 121 so that a voltage is also formed on the second lower assembled electrode 125, which can play the role of the assembled electrode. An electric field can be formed between the first assembled wiring 122 and the second assembled wiring 123, the first lower assembled electrode 121, and the second lower assembled electrode 125.

[0139] The light-emitting element LED can be dielectrically polarized by the electric field and have a polarity. Then, the dielectrically polarized light-emitting element LED can move or be fixed in a specific direction by dielectrophoresis (DEP), that is, by the electric field. Therefore, a plurality of light-emitting element LEDs can be self-assembled inside the opening DALH above the assembled wiring AL and the lower assembled electrodes 121, 125 using dielectrophoresis.

[0140] After the light-emitting element LED is self-assembled inside the opening DALH, the first electrodes 134, 144 of the light-emitting element LED and the second lower assembled electrode 125 are in contact with each other and conduct electricity, and the second lower assembled electrode 125 is in a state of being integrated with the first electrodes 134, 144. As a result, the light-emitting element LED can be stably fixed to the substrate 110 even after being self-assembled.

[0141] Finally, once the self-assembly of the light-emitting element LED is completed, the organic layer DAL can be removed, and other components such as the second planarization layer 118 and the pixel electrode PE can be formed to complete the manufacturing process of the display device 100.

[0142] On the other hand, the dielectrophoretic force is proportional to the size of the light-emitting element LED and the strength of the electric field. The larger the size of the light-emitting element LED or the stronger the electric field strength, the stronger the dielectrophoresis acts and the assembly rate can be improved.

[0143] Therefore, in the display device 100 according to an embodiment of the present specification, in order to increase dielectrophoresis, the strength of the electric field can be increased. As described above, by arranging the first lower assembly electrode 121 and the first cladding layer 122b in different layers from each other, the distance between the first lower assembly electrode 121 and the first cladding layer 122b can be narrowed to increase the strength of the electric field and improve the self-assembly rate.

[0144] Embodiments of the present invention can also be described as follows.

[0145] According to an aspect of the present invention, a display device includes a substrate including a plurality of sub-pixels, a first lower assembly electrode disposed in the plurality of sub-pixels, a first assembly wiring disposed in the plurality of sub-pixels and disposed in a layer different from the first lower assembly electrode, a light-emitting element disposed on the first lower assembly electrode and the first assembly wiring and including a first electrode, a semiconductor layer, and a second electrode, and a second lower assembly electrode disposed between the first lower assembly electrode and the light-emitting element and electrically connected to the first electrode or the second electrode.

[0146] According to another feature of the present specification, the first lower assembly electrode and the second lower assembly electrode can be electrically connected.

[0147] According to other features of this specification, the first assembled wiring and the first electrode can be electrically connected. And the display device further includes a chip contact electrode connecting the first assembled wiring and the first electrode, and the chip contact electrode can contact the side surface of the light-emitting element. Also, the first assembled wiring can be connected to a low-potential power supply pad to which a low-potential power supply is applied.

[0148] According to other features of this specification, the display device further includes a planarization layer covering a part of the first lower assembled electrode and including an assembly groove, and a light-emitting element can be arranged in the assembly groove. The display device further includes a second assembled wiring arranged on the planarization layer, and the second assembled wiring can be connected to the first lower assembled electrode through a contact hole in the planarization layer. And the second assembled wiring can be connected to a low-potential power supply pad to which a low-potential power supply is applied. Also, the first assembled wiring includes a first conductive layer arranged on the planarization layer and a first cladding layer covering the first conductive layer, and the second assembled wiring can include a second conductive layer arranged on the planarization layer and a second cladding layer covering the second conductive layer.

[0149] According to another aspect of the present invention, the display device includes a substrate including a plurality of sub-pixels, a first assembled wiring and a second assembled wiring arranged side by side with the plurality of sub-pixels, a light-emitting element arranged to overlap the first assembled wiring or the second assembled wiring, and a first lower auxiliary electrode and a second lower auxiliary electrode that overlap one of the first assembled wiring and the second assembled wiring and the light-emitting element below the light-emitting element.

[0150] According to other features of this specification, the first assembled wiring and the second assembled wiring can be shared by a plurality of sub-pixels arranged in a first direction on the substrate.

[0151] According to other features of this specification, the display device further includes a low-potential voltage pad arranged on one surface of the substrate to which a low-potential power supply is applied, and the first assembled wiring and the second assembled wiring can be connected to the low-potential voltage pad.

[0152] According to other features of this specification, there are a plurality of light-emitting elements, and at least two light-emitting elements can be arranged in each of the plurality of sub-pixels.

[0153] According to other features of this specification, it can further include a driving transistor arranged on the substrate and electrically connected to the light-emitting element. And the driving transistors are arranged in each of the plurality of sub-pixels, and the sizes of the driving transistors arranged in at least two sub-pixels can be different from each other.

[0154] According to other features of this specification, the light-emitting element includes a first electrode, a semiconductor layer, and a second electrode, and the second lower auxiliary electrode is arranged between the first lower auxiliary electrode and the light-emitting element and can be in contact with the first electrode or the second electrode.

[0155] As described above, with reference to the accompanying drawings, the embodiments of the present invention have been described in more detail. However, the present invention is not necessarily limited to such embodiments, and can be variously modified and implemented within the scope not departing from the technical idea of the present invention. Therefore, the embodiments disclosed in the present invention are not for limiting the technical idea of the present invention, but for explaining it, and the scope of the technical idea of the present invention is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all aspects and not restrictive. The protection scope of the present invention should be interpreted according to the following claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of the rights of the present invention.

Explanation of Reference Numerals

[0156] 100 Display device 110 Substrate 120 Connection electrode

Claims

1. a substrate including a plurality of sub-pixels; A transistor disposed in each of the plurality of sub-pixels; a first insulating layer disposed over the transistor; a plurality of light-emitting elements disposed in each of the plurality of sub-pixels, the light-emitting elements being spaced apart from the transistors and disposed in the assembly grooves of the first insulating layer in a first direction; a first assembly wiring and a second assembly wiring arranged in the first direction on the first insulating layer; the first assembly wiring and the second assembly wiring are disposed on both sides of the plurality of light emitting elements, A display device, wherein the first assembly wiring includes a first conductive layer and a first cladding layer, and the second assembly wiring includes a second conductive layer and a second cladding layer.

2. the first cladding layer covers an upper surface and a side surface of the first conductive layer; The display device according to claim 1 , wherein the second cladding layer covers an upper surface and a side surface of the second conductive layer.

3. The display device according to claim 1 , wherein the first cladding layer is disposed on a side of the assembly groove of the first insulating layer and extends below the plurality of light emitting elements.

4. The display device of claim 1 , wherein the second conductive layer is connected to a first lower assembly electrode through a contact hole in the first insulating layer.

5. The display device according to claim 4 , wherein the first lower assembly electrode is disposed to extend below the plurality of light-emitting elements.

6. The display device according to claim 1 , further comprising a chip contact electrode disposed on the first assembly wiring and the second assembly wiring.

7. The display device according to claim 6 , wherein the chip contact electrodes are arranged on side surfaces of the plurality of light-emitting elements and electrically connect the first semiconductor layers and first electrodes of the plurality of light-emitting elements to the first and second assembly wirings.

8. The display device of claim 1 , further comprising a second insulating layer disposed over the first insulating layer and the plurality of light emitting elements.

9. The display device according to claim 8 , further comprising a pixel electrode disposed on the second insulating layer and electrically connected to the plurality of light emitting elements through contact holes in the second insulating layer.

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