DC / DC converter

Abstract

To maintain the average value of coil current constant without depending on an input-output condition.SOLUTION: A DC / DC converter includes an oscillator that generates a lamp signal and an inversion lamp signal having reverse polarity and repeating rise / drop and reset in a common period, a comparator that compares an analog signal, the lamp signal, and the inversion lamp signal, a logic operation unit that performs logic operation on the comparison result and generates a step-down control signal and a step-up control signal of a step up and down type switch output stage, a current detection unit that samples the coil current of the switch output stage and generates a current sensing signal, and a timing control unit that performs timing control so as to sample the coil current at a reset timing of the lamp signal and the inversion lamp signal. The step-down control signal and the step-up control signal turn on / off step-down and step-up output transistors and a synchronization rectifying transistor. Using the current sensing signal, output feedback control of a current mode control system is performed.SELECTED DRAWING: Figure 29

Description

Technical Field

[0001] The invention disclosed in this specification relates to a DC / DC converter.

Background Art

[0002] Conventionally, as a power supply means for various applications, a DC / DC converter (so-called switching power supply) that turns an output transistor on / off to generate a desired output voltage from an input voltage has been used.

[0003] As an example of the prior art related to the above, Patent Document 1 and Patent Document 2 can be cited.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, as an output feedback control method of a DC / DC converter, a current mode control method that detects both an output voltage and a coil current to perform output feedback control is widely known in general. However, in the conventional current mode control method (peak value detection type or bottom value detection type), the average coil current fluctuates depending on input / output conditions, so there is a risk of adversely affecting various operations of the DC / DC converter (such as overcurrent protection operation and light load detection operation).

[0006] In view of the above problems found by the inventors of the present application, the invention disclosed in this specification aims to provide a DC / DC converter capable of maintaining a constant average value of the coil current without depending on input / output conditions.

Means for Solving the Problem

[0007] The DC / DC converter disclosed in this specification samples the coil current of the switch output stage at the center timing of the on-period or off-period of the switch output stage, and performs output feedback control in a current mode control method using a current sense signal corresponding to the sampling value, thereby generating a desired output voltage from the input voltage.

[0008] Also, the DC / DC converter disclosed in this specification includes a comparator that compares an analog signal and a first ramp signal to generate a control signal for the switch output stage, a current detection unit that samples the coil current of the switch output stage at a timing corresponding to a timing control signal to generate a current sense signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the center timing of the on-period or off-period of the switch output stage using a second ramp signal having a slew rate twice that of the first ramp signal. By performing output feedback control in a current mode control method using the current sense signal, it is configured to generate a desired output voltage from the input voltage.

[0009] Also, the DC / DC converter disclosed in this specification includes a comparator that compares a first analog signal and a ramp signal to generate a control signal for the switch output stage, a current detection unit that samples the coil current of the switch output stage at a timing corresponding to a timing control signal to generate a current sense signal, an average value generation unit that generates a second analog signal having a simple average value of the signal value of the first analog signal and the start value or end value of the ramp signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the center timing of the on-period or off-period of the switch output stage using the ramp signal and the second analog signal. By performing output feedback control in a current mode control method using the current sense signal, it is configured to generate a desired output voltage from the input voltage.

[0010] Also, the DC / DC converter disclosed in this specification includes a comparator that compares a first analog signal and a first ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, an average value generation unit that generates a second analog signal having a weighted average value of the signal value of the first analog signal and the starting value or the ending value of the first ramp signal, and a timing control unit that generates the timing control signal so that the sampling of the coil current is performed at the center timing of the on period or the off period of the switch output stage using a second ramp signal having a slew rate different from that of the first ramp signal and the second analog signal. By performing output feedback control in a current mode control method using the current sense signal, it is configured to generate a desired output voltage from an input voltage.

[0011] Also, the DC / DC converter disclosed in this specification includes an oscillator that generates a triangular-wave ramp signal with an equal up / down slew rate, a comparator that compares an analog signal and the ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, and a timing control unit that generates the timing control signal so that the sampling of the coil current is performed at the timing when the ramp signal takes a peak value or a bottom value. By performing output feedback control in a current mode control method using the current sense signal, it is configured to generate a desired output voltage from an input voltage.

[0012] In addition, the DC / DC converter disclosed in this specification includes an oscillator that generates a sawtooth-shaped ramp signal and an inverted ramp signal that have opposite polarities to each other and repeat rising, falling, and resetting in a common switching period, a first comparator and a second comparator that respectively compare an analog signal with the ramp signal and the inverted ramp signal to generate a first comparison signal and a second comparison signal, a logic operation unit that generates a control signal for a switch output stage by performing a logic operation using the first comparison signal and the second comparison signal, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, and a timing control unit that generates the timing control signal so that the sampling of the coil current is performed at the reset timing of the ramp signal and the inverted ramp signal. By performing output feedback control in a current mode control method using the current sense signal, it is configured to generate a desired output voltage from an input voltage.

[0013] In addition, the DC / DC converter disclosed in this specification includes a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, and a timing control unit that generates the timing control signal so that the sampling of the coil current is performed at the center timing of the off period of the switch output stage using a first internal signal and a second internal signal generated by itself in synchronization with the on / off control of the switch output stage. By performing output feedback control in a current mode control method using the current sense signal, it is configured to generate a desired output voltage from an input voltage.

[0014] In addition, other features, elements, steps, advantages, and characteristics of the present invention will become more apparent from the following detailed description of the best mode and the accompanying drawings related thereto.

Effects of the Invention

[0015] According to the invention disclosed in this specification, it is possible to provide a DC / DC converter that can maintain the average value of the coil current constant regardless of input / output conditions.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0017] <First Embodiment> FIG. 1 is a circuit diagram showing a first embodiment of a DC / DC converter. The DC / DC converter 1 of this embodiment is a step-down switching power supply that generates a desired output voltage Vo from an input voltage Vi and supplies this to a load (such as a CPU [central processing unit], not shown). It includes a switch output stage 10, a feedback voltage generation unit 20, an error amplifier 30, a phase compensation unit 40, a current detection unit 50, a differential amplifier 60, an oscillator 70, a PWM [pulse width modulation] comparator 80, a driver 90, a clamper 100, a light load detection comparator 110, and a timing control unit 120.

[0018] Note that, in addition to the circuit elements described above, other protection circuits (such as a step-down protection circuit, an overvoltage protection circuit, a temperature protection circuit, etc.) may be appropriately incorporated into the DC / DC converter 1.

[0019] The switch output stage 10 is of the step-down type that steps down the input voltage Vi to generate a desired output voltage Vo, and includes an output transistor 11 (a PMOSFET [P channel type metal oxide semiconductor field effect transistor] in this figure), a synchronous rectification transistor 12 (an NMOSFET [N channel type MOSFET] in this figure), a coil 13, and a capacitor 14.

[0020] The source of the output transistor 11 is connected to the applied end of the input voltage Vi. The drain of the output transistor 11 is connected to the first end of the coil 13. The gate of the output transistor 11 is connected to the applied end of the gate signal G1. The output transistor 11 turns off when the gate signal G1 is at a high level and turns on when the gate signal G1 is at a low level.

[0021] The source of the synchronous rectification transistor 12 is connected to the ground terminal (= the terminal to which the ground voltage GND is applied). The drain of the synchronous rectification transistor 12 is connected to the first terminal of the coil 13. The gate of the synchronous rectification transistor 12 is connected to the terminal to which the gate signal G2 is applied. The synchronous rectification transistor 12 turns on when the gate signal G2 is at a high level and turns off when the gate signal G2 is at a low level.

[0022] In addition, when a high voltage is applied to the switch output stage 10, high-voltage-resistant elements such as power MOSFETs, IGBTs [insulated gate bipolar transistors], and SiC transistors may be used as the output transistor 11 and the synchronous rectification transistor 12, respectively.

[0023] The output transistor 11 and the synchronous rectification transistor 12 are turned on / off complementarily according to the gate signals G1 and G2. By such on / off operation, a rectangular-wave switch voltage Vsw that is pulse-driven between the input voltage Vi and the ground voltage GND is generated at the first terminal of the coil 13. Note that the above-mentioned term "complementary" includes not only the case where the on / off states of the output transistor 11 and the synchronous rectification transistor 12 are completely reversed, but also the case where a dead time (simultaneous off period) is provided for both transistors.

[0024] Also, when integrating the components of the DC / DC converter 1 into an IC, the output transistor 11 and the synchronous rectification transistor 12 may be built in the IC or externally attached. Also, the output transistor 11 can be replaced with an NMOSFET. However, in that case, it is necessary to increase the high level of the gate signal G1 higher than the input voltage Vi using a bootstrap circuit or the like. Also, it is possible to use a rectifying diode instead of the synchronous rectification transistor 12.

[0025] The coil 13 and the capacitor 14 form an LC filter that rectifies and smoothes the switch voltage Vsw to generate the output voltage Vo. Note that the first end of the coil 13 is connected to the drains of the output transistor 11 and the synchronous rectification transistor 12 respectively (= the applied ends of the switch voltage Vsw), as described above. The second end of the coil 13 and the first end of the capacitor 14 are both connected to the applied end of the output voltage Vo. The second end of the capacitor 14 is connected to the ground end.

[0026] The feedback voltage generation unit 20 includes resistors 21 and 22 connected in series between the applied end and the ground end of the output voltage Vo, and outputs a feedback voltage FB (a divided voltage of the output voltage Vo) corresponding to the output voltage Vo from the connection node between the two resistors. Note that when the output voltage Vo is within the input dynamic range of the error amplifier 30, the feedback voltage generation unit 20 may be omitted and the output voltage Vo may be directly input to the error amplifier 30.

[0027] The error amplifier 30 is a current output type transconductance amplifier (so-called gm amplifier), and generates an error current signal I30 corresponding to the difference between the feedback voltage FB input to the inverting input terminal (-) and the first reference voltage REF1 input to the non-inverting input terminal (+) (= corresponding to the target setting value of the output voltage Vo). The error current signal I30 flows in the positive direction (= the direction from the error amplifier 30 to the phase compensation unit 40) when the feedback voltage FB is lower than the first reference voltage REF1, and flows in the negative direction (= the direction from the phase compensation unit 40 to the error amplifier 30) when the feedback voltage FB is higher than the first reference voltage REF1.

[0028] The phase compensation unit 40 includes a resistor 41 and a capacitor 42 connected in series between the output terminal of the error amplifier 30 and the ground terminal, and generates an error voltage signal COMP in response to the input of the error current signal I30. Note that by appropriately setting the resistance value of the resistor 41 and the capacitance value of the capacitor 42, the phase of the error voltage signal COMP can be compensated to prevent oscillation of the output feedback loop.

[0029] The current detection unit 50 samples the coil current IL flowing through the coil 13 at a timing according to the timing control signal ST, and generates a current sense signal ISNS according to the sampling value. The current sense signal ISNS may be, for example, a voltage signal that becomes higher as the sampling value of the coil current IL is larger, and conversely, becomes lower as the sampling value of the coil current IL is smaller.

[0030] The differential amplifier 60 generates a first analog signal VC1 according to the difference between the error voltage signal COMP input to the non-inverting input terminal (+) and the current sense signal ISNS input to the inverting input terminal (-). The first analog signal VC1 decreases as the current sense signal ISNS is higher, and increases as the current sense signal ISNS is lower. That is, the first analog signal VC1 decreases as the coil current IL is larger, and increases as the coil current IL is smaller. Thus, in the DC / DC converter 1 of the present embodiment, a current mode control method is adopted in which both the output voltage Vo and the coil current IL are detected to perform output feedback control.

[0031] The oscillator 70 generates a first ramp signal VR1 of a ramp waveform (a sawtooth waveform in the present embodiment) that is pulse-driven at a predetermined switching period T (and thus a predetermined switching frequency fsw (= 1 / T)).

[0032] The PWM comparator 80 compares the first analog signal VC1 input to the non-inverting input terminal (+) with the first ramp signal VR1 input to the inverting input terminal (-) to generate a first comparison signal CMP1 (corresponding to the control signal of the switch output stage 10). The first comparison signal CMP1 becomes high when the first analog signal VC1 is higher than the first ramp signal VR1, and becomes low when the first analog signal VC1 is lower than the first ramp signal VR1. That is, the on-duty Don of the switch output stage 10 (= ton / T, that is, the ratio of the on-period ton to the switching period T) becomes larger as the first analog signal VC1 is higher, and conversely, becomes smaller as the first analog signal VC1 is lower.

[0033] Driver 90 includes a NAND gate 91 and an AND gate 92, and generates gate signals G1 and G2 (corresponding to the drive signals of the switch output stage 10 respectively) according to the first comparison signal CMP1. Specifically, the NAND gate 91 outputs the negative logical product operation signal of the sleep control signal XSLP and the first comparison signal CMP1 as the gate signal G1. Also, the AND gate 92 outputs the logical product operation signal of the sleep control signal XSLP and the first comparison signal CMP1 with inverted input as the gate signal G2.

[0034] Therefore, when the sleep control signal XSLP is at a high level (the logical level during wake-up), the gate signals G1 and G2 basically become the logical inverse signals of the first comparison signal CMP1. More specifically, when the first comparison signal CMP1 is at a high level, both the gate signals G1 and G2 become low levels, so the output transistor 11 turns on and the synchronous rectification transistor 12 turns off. Conversely, when the first comparison signal CMP1 is at a low level, both the gate signals G1 and G2 become high levels, so the output transistor 11 turns off and the synchronous rectification transistor 12 turns on.

[0035] On the other hand, when the sleep control signal XSLP is at a low level (the logical level during sleep), the gate signal G1 becomes high level regardless of the first comparison signal CMP1, and the gate signal G2 becomes low level regardless of the first comparison signal CMP1. Therefore, both the output transistor 11 and the synchronous rectification transistor 12 turn off.

[0036] In this way, the DC / DC converter 1 of this embodiment has a function of shifting to a sleep mode (output stop state) by turning off both the output transistor 11 and the synchronous rectification transistor 12 when the sleep control signal XSLP is at a low level.

[0037] The clamp 100 applies over current protection (OCP) or negative current protection (NCP) to the coil current IL (and thus the load current flowing through the load) by limiting the error voltage signal COMP to below a predetermined upper limit value or above a predetermined lower limit value.

[0038] As described above, in the DC / DC converter 1 of this embodiment, the current sense signal ISNS corresponding to the coil current IL is fed back to the differential amplifier 60. Therefore, when the error voltage signal COMP increases, the coil current IL increases, and when the error voltage signal COMP decreases, the coil current IL decreases. Thus, the magnitude of the coil current IL can be controlled according to the error voltage signal COMP.

[0039] Conversely, when the coil current IL increases, the on-duty Don decreases, so the output voltage Vo decreases and the error voltage signal COMP increases. When the coil current IL decreases, the on-duty Don increases, so the output voltage Vo increases and the error voltage signal COMP decreases. That is, it can be said that the error voltage signal COMP has information regarding the magnitude (current value) of the coil current IL. Therefore, by applying a limit to the error voltage signal COMP using the clamp 100, it becomes possible to indirectly limit the coil current IL.

[0040] The light load detection comparator 110 compares the error voltage signal COMP input to the non-inverting input terminal (+) with the second reference voltage REF2 (corresponding to the light load detection threshold value) input to the inverting input terminal (-) to generate a sleep control signal XSLP. The sleep control signal XSLP becomes high level (= the logic level at wake-up) when the error voltage signal COMP is higher than the second reference voltage REF2, and becomes low level (= the logic level at sleep) when the error voltage signal COMP is lower than the second reference voltage REF2.

[0041] In this way, the sleep control signal XSLP becomes low when the coil current IL (and thus the load current) decreases until the error voltage signal COMP falls below the second reference voltage REF2. Therefore, when the DC / DC converter 1 is lightly loaded, the switching operation of the switch output stage 10 is stopped, so that the efficiency at light load can be significantly improved.

[0042] The timing control unit 120 generates a timing control signal ST for determining the sampling timing of the coil current IL in the current detection unit 50. Next, an operation example of the timing control unit 120 (a method for generating the timing control signal ST) will be described in detail.

[0043] <Timing control unit> FIG. 2 is a waveform diagram showing a first operation example (peak value detection type) of the timing control unit 120. In order from the top, the input voltage Vi, the coil current IL, and the timing control signal ST are depicted. In the first operation example of this figure, the timing control signal ST is generated so as to sample the peak value Ip (maximum value) of the coil current IL. Therefore, in the DC / DC converter 1, output feedback control is applied so as to maintain the peak value Ip of the coil current IL constant.

[0044] FIG. 3 is a waveform diagram showing a second operation example (bottom value detection type) of the timing control unit 120. Similar to FIG. 2 above, in order from the top, the input voltage Vi, the coil current IL, and the timing control signal ST are depicted. In the second operation example of this figure, the timing control signal ST is generated so as to sample the bottom value Ib (minimum value) of the coil current IL. Therefore, in the DC / DC converter 1, output feedback control is applied so as to maintain the bottom value Ib of the coil current IL constant.

[0045] Thus, a general current mode control method is classified into a peak detection type (Fig. 2) or a bottom detection type (Fig. 3) according to the sampling timing of the coil current IL. However, in these control methods, for example, when the ripple component of the coil current IL changes with the variation of the input voltage Vi, the average coil current Idc (corresponding to the DC component of the coil current Idc) changes when the error voltage signal COMP is maintained at a constant value. As a result, the thresholds for overcurrent protection operation and light load detection operation change according to the input / output conditions, making it difficult to design the application. The countermeasures will be described below.

[0046] FIG. 4 is a waveform diagram showing a third operation example (on-period center value detection type) of the timing control unit 120, in which the input voltage Vi, the coil current IL, the switch voltage Vsw, and the timing control signal ST are depicted in order from the top. In the third operation example of this figure, the timing control signal ST is generated so as to sample the center value Ic of the coil current IL at the center timing of the on-period ton of the switch output stage 10 (corresponding to the period when the output transistor 11 is on and the synchronous rectifier transistor 12 is off, i.e., the high-level period of the switch voltage Vsw). Therefore, in the DC / DC converter 1, output feedback control is applied to maintain the center value Ic of the coil current IL constant.

[0047] Here, the center value Ic of the coil current IL is equal to the aforementioned average coil current Idc (and thus the load current). Therefore, by limiting the error voltage signal COMP to below a predetermined upper limit value or above a predetermined lower limit value, it is possible to apply overcurrent protection or reverse current protection with a constant load current regardless of the input / output conditions. Also, by stopping the switching operation of the switch output stage 10 when the error voltage signal COMP falls below a predetermined threshold value, it is possible to shift to the sleep mode with a constant load current regardless of the input / output conditions.

[0048] FIG. 5 is a waveform diagram showing a fourth operation example (off period center value detection type) of the timing control unit 120. Similar to FIG. 4 above, the input voltage Vi, the coil current IL, the switch voltage Vsw, and the timing control signal ST are depicted in order from the top. In the fourth operation example of this figure, the timing control signal ST is generated so as to sample the center value Ic of the coil current IL at the center timing of the off period toff of the switch output stage 10 (i.e., the period during which the output transistor 11 is off and the synchronous rectifier transistor 12 is on, that is, the low level period of the switch voltage Vsw). Therefore, similar to the case of adopting the third operation example above, in the DC / DC converter 1, output feedback control is applied so as to keep the center value Ic of the coil current IL constant.

[0049] Note that when the on period ton is short, it becomes difficult to complete the sampling of the coil current IL during that period. Therefore, it is desirable to set the sampling timing to the off period Toff. Conversely, when the off period toff is short, the coil current IL may be sampled during the on period Ton.

[0050] <Second Embodiment> FIG. 6 is a circuit diagram showing a third embodiment of the DC / DC converter. The DC / DC converter 1 of this embodiment is based on the first embodiment (FIG. 1), and has an arithmetic unit 130 instead of the differential amplifier 60. It is characterized in that the current sense signal ISNS is fed back to the arithmetic unit 130 instead of the differential amplifier 60. Therefore, for the components similar to those in the first embodiment, the same reference numerals as those in FIG. 1 are given to avoid redundant explanations. Hereinafter, the characteristic parts of the second embodiment will be mainly described.

[0051] The arithmetic unit 130 performs an arithmetic process (for example, a subtraction process of subtracting the current sense signal ISNS from the error voltage signal COMP) between the error voltage signal COMP and the current sense signal ISNS to generate a first analog signal VC (=COMP - ISNS).

[0052] Thus, when performing output feedback control in the current mode control method, the current sense signal ISNS may be subtracted from the error voltage signal COMP input to the non-inverting input terminal (+) of the PWM comparator 80.

[0053] <Third Embodiment> FIG. 7 is a circuit diagram showing a third embodiment of the DC / DC converter. The DC / DC converter 1 of this embodiment is characterized in that an arithmetic unit 140 is used instead of the arithmetic unit 130 while based on the second embodiment (FIG. 6). Therefore, for the components similar to those in the second embodiment, the same reference numerals as in FIG. 6 are given and the overlapping explanations are omitted. Hereinafter, the characteristic parts of the third embodiment will be mainly described.

[0054] The arithmetic unit 140 performs arithmetic processing (for example, addition processing of the first ramp signal VR1 and the current sense signal ISNS) between the first ramp signal VR1 and the current sense signal ISNS to generate an offset first ramp signal VR1’ (=VR1 + ISNS).

[0055] The PWM comparator 80 compares the first analog signal VC1 input to the non-inverting input terminal (+) with the offset first ramp signal VR1’ input to the inverting input terminal (-) in accordance with the above change to generate a first comparison signal CMP1.

[0056] Thus, when performing output feedback control in the current mode control method, the current sense signal ISNS may be added to the first ramp signal VR1 input to the inverting input terminal (-) of the PWM comparator 80.

[0057] Regarding methods for implementing the current mode control method, there are various variations other than those described above. Due to space limitations, not all will be exemplified here. For example, by adding or subtracting a signal having error information of the current sense signal and the output voltage and inputting it to an amplifier or a comparator, output feedback control of the current mode control method can be performed. Alternatively, by inputting a current sense signal or a signal obtained by subjecting this to a predetermined arithmetic process (addition, subtraction, multiplication, or division) and a signal having error information of the output voltage to an amplifier or a comparator, output feedback control of the current mode control method may be performed.

[0058] In each of the above embodiments, the merits of adopting the center value detection type (FIGS. 4 and 5) current mode control method have been described. In the following embodiments, a timing control method for correctly detecting the center value Ic of the coil current IL will be described in detail with specific examples.

[0059] <Fourth Embodiment> FIG. 8 is a diagram showing a fourth embodiment of the DC / DC converter. The DC / DC converter 1 of this embodiment is characterized in that a timing control signal ST is generated using a first analog signal VC1 and a second ramp signal VR2 while being based on the first embodiment (FIG. 1). Therefore, for components similar to those in the first embodiment, the same reference numerals as in FIG. 1 are given and duplicate explanations are omitted. Hereinafter, the characteristic parts of the fourth embodiment will be mainly described.

[0060] In the DC / DC converter 1 of this embodiment, the oscillator 70 generates a first ramp signal VR1 and supplies it to the inverting input terminal (-) of the PWM comparator 80, and at the same time, generates a second ramp signal VR2 synchronized with the first ramp signal VR1 and supplies it to the timing control unit 120. Note that the second ramp signal VR2 is a sawtooth wave signal having a slew rate twice that of the first ramp signal VR1.

[0061] The timing control unit 120 generates a timing control signal ST so that sampling of the coil current IL is performed at the center timing of the on-period ton or the off-period toff of the switch output stage 10 by using both the first analog signal VC1 and the second lamp signal VR2. Hereinafter, a specific operation example of the timing control unit 120 will be described in detail.

[0062] FIG. 9 is a waveform diagram showing a first operation example of the timing control unit 120 in the fourth embodiment, and depicts, in order from the top, the first analog signal VC1 (dashed-dotted line), the first lamp signal VR1 (solid line), and the second lamp signal VR2 (dashed line), the coil current IL, and the timing control signal ST.

[0063] As shown in this figure, both the first lamp signal VR1 and the second lamp signal VR2 repeat rising and resetting at a common switching period T.

[0064] When the first analog signal VC1 is higher than the first lamp signal VR1, the switch output stage 10 is in the on-period ton and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the first lamp signal VR1, the switch output stage 10 is in the off-period toff and the coil current IL decreases.

[0065] That is, the higher the first analog signal VC1 is, the larger the on-duty Don (=ton / T) of the switch output stage 10 becomes, and conversely, the lower the first analog signal VC1 is, the smaller the on-duty Don of the switch output stage 10 becomes.

[0066] Here, the timing control unit 120 compares the first analog signal VC1 and the second lamp signal VR2 to generate the timing control signal ST. More specifically, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the timing when the second lamp signal VR2 rises and crosses the first analog signal VC1.

[0067] As shown in this figure, the timing at which the second lamp signal VR2 and the first analog signal VC1 cross each other coincides with the center timing of the on-period ton (= the timing when ton / 2 has elapsed since the coil current IL started to increase).

[0068] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL in the on-period ton by sampling the coil current IL triggered by the one-shot pulse of the timing control signal ST.

[0069] FIG. 10 is a waveform diagram showing a second operation example of the timing control unit 120 in the fourth embodiment. Similar to the previous FIG. 9, from top to bottom in order, the first analog signal VC1 (dashed-dotted line), the first lamp signal VR1 (solid line), and the second lamp signal VR2 (dashed line), the coil current IL, and the timing control signal ST are depicted.

[0070] Also in the second operation example of this figure, both the first lamp signal VR1 and the second lamp signal VR2 repeat rising and resetting at the common switching period T. However, the relationship between the first analog signal VC1 and the on-duty ratio Don is opposite to that in the first operation example (FIG. 9).

[0071] Specifically, when the first analog signal VC1 is higher than the first lamp signal VR1, the switch output stage 10 enters the off-period toff and the coil current IL decreases. On the other hand, when the first analog signal VC1 is lower than the first lamp signal VR1, the switch output stage 10 enters the on-period ton and the coil current IL increases.

[0072] That is, the higher the first analog signal VC1, the smaller the on-duty ratio Don (= ton / T) of the switch output stage 10, and conversely, the lower the first analog signal VC1, the larger the on-duty ratio Don of the switch output stage 10.

[0073] In order to realize such an operation, for example, the input polarities of the error amplifier 30 and the PWM comparator 80 may be inverted from those in FIG. 8, respectively.

[0074] Here, the timing control unit 120 compares the first analog signal VC1 and the second ramp signal VR2 and generates a timing control signal ST, similar to the previous first operation example (FIG. 9). More specifically, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the timing when the second ramp signal VR2 rises and crosses the first analog signal VC1.

[0075] As shown in this figure, the timing at which the second ramp signal VR2 and the first analog signal VC1 cross each other coincides with the center timing of the off period toff (= the timing when toff / 2 has elapsed since the coil current IL began to decrease).

[0076] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL in the off period toff by sampling the coil current IL using the one-shot pulse of the timing control signal ST as a trigger.

[0077] FIG. 11 is a waveform diagram showing a third operation example of the timing control unit 120 in the fourth embodiment. Similar to FIGS. 9 to 10 above, the first analog signal VC1 (dashed-dotted line), the first ramp signal VR1 (solid line), and the second ramp signal VR2 (dashed line), the coil current IL, and the timing control signal ST are depicted in order from the top.

[0078] In the third operation example of this figure, the polarities of the first ramp signal VR1 and the second ramp signal VR2 are inverted from those in the first operation example (FIG. 9). That is, both the first ramp signal VR1 and the second ramp signal VR2 repeatedly decrease and reset in a common switching period T.

[0079] When the first analog signal VC1 is higher than the first lamp signal VR1, the switch output stage 10 enters the on period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the first lamp signal VR1, the switch output stage 10 enters the off period toff, and the coil current IL decreases.

[0080] That is, the higher the first analog signal VC1, the larger the on-duty ratio Don (= ton / T) of the switch output stage 10. Conversely, the lower the first analog signal VC1, the smaller the on-duty ratio Don of the switch output stage 10. This is the same as the previous first operation example (Fig. 9).

[0081] Here, similar to the previous first operation example (Fig. 9), the timing control unit 120 compares the first analog signal VC1 with the second lamp signal VR2 to generate a timing control signal ST. More specifically, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the timing when the second lamp signal VR2 decreases and crosses the first analog signal VC1.

[0082] As shown in this figure, the timing at which the second lamp signal VR2 crosses the first analog signal VC1 coincides with the center timing of the off period toff (= the timing when toff / 2 has elapsed since the coil current IL began to decrease).

[0083] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL in the off period toff by sampling the coil current IL using the one-shot pulse of the timing control signal ST as a trigger.

[0084] Thus, in the third operation example of this figure, unlike the previous second operation example (Fig. 10), it is possible to sample the center value Ic of the coil current IL in the off period toff while maintaining the relationship between the first analog signal VC1 and the on-duty ratio Don as before.

[0085] FIG. 12 is a waveform diagram showing a fourth operation example of the timing control unit 120 in the fourth embodiment. Similar to FIGS. 9 to 11 above, in order from the top, the first analog signal VC1 (dashed-dotted line), the first lamp signal VR1 (solid line), and the second lamp signal VR2 (dashed line), the coil current IL, and the timing control signal ST are depicted.

[0086] Also in the fourth operation example of this figure, similar to the first operation example (FIG. 9) above, both the first lamp signal VR1 and the second lamp signal VR2 repeat rising and resetting at the common switching period T. However, the second lamp signal VR2 starts rising with a delay of 1 / 2 of the switching period T from the rising start point of the first lamp signal VR1.

[0087] Note that when the first analog signal VC1 is higher than the first lamp signal VR1, the switch output stage 10 is in the on period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the first lamp signal VR1, the switch output stage 10 is in the off period toff, and the coil current IL decreases.

[0088] That is, the higher the first analog signal VC1, the larger the on-duty ratio Don (=ton / T) of the switch output stage 10 becomes. Conversely, the lower the first analog signal VC1, the smaller the on-duty ratio Don of the switch output stage 10 becomes. This point is the same as the first operation example (FIG. 9) above.

[0089] Here, similar to the first operation example (FIG. 9) above, the timing control unit 120 compares the first analog signal VC1 and the second lamp signal VR2 to generate the timing control signal ST. More specifically, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the timing when the second lamp signal VR2 rises and crosses the first analog signal VC1.

[0090] As shown in this figure, the timing at which the second lamp signal VR2 and the first analog signal VC1 cross each other coincides with the center timing of the off period toff (= the timing when toff / 2 has elapsed since the coil current IL started to decrease).

[0091] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL in the off period toff by sampling the coil current IL using the one-shot pulse of the timing control signal ST as a trigger.

[0092] Thus, in the fourth operation example of this figure, unlike the previous third operation example (FIG. 11), without inverting the polarities of the first lamp signal VR1 and the second lamp signal VR2, while maintaining the relationship between the first analog signal VC1 and the on-duty Don as before, it becomes possible to sample the center value Ic of the coil current IL in the off period toff.

[0093] FIG. 13 is a waveform diagram showing a fifth operation example of the timing control unit 120 in the fourth embodiment. From top to bottom in order, the first analog signal VC1 (dashed-dotted line), the equivalent analog signal VC1' (double-dashed-dotted line), the first lamp signal VR1 (solid line), and the second lamp signal VR2 (dashed line), the coil current IL, and the timing control signal ST are depicted.

[0094] The fifth operation example of this figure is basically the same as the previous first operation example (FIG. 9). However, the timing control unit 120 is different in that, instead of the first analog signal VC1, it generates the timing control signal ST by comparing an equivalent analog signal VC1' having the same information as this with the second lamp signal VR2.

[0095] In a configuration where the first analog signal VC1 is compared with a plurality of ramp signals (= the first ramp signal VR1 and the second ramp signal VR2), the risk that the first analog signal VC1 fluctuates due to noise (= the risk that the PWM control becomes unstable) is higher than in a configuration where the first analog signal VC1 is compared with a single ramp signal (= only the first ramp signal VR1).

[0096] Therefore, in view of improving the stability of the PWM control, rather than comparing the first analog signal VC1 itself with the second ramp signal VR2, it is desirable to compare an equivalent analog signal VC1' having information equivalent to that of the first analog signal VC1 with the second ramp signal VR2.

[0097] As a method for generating the equivalent analog signal VC1', for example, a method of simply buffering the first analog signal VC1 is convenient.

[0098] Also, a method of calculating the theoretical value of the first analog signal VC1 (= α × (Vo / Vi) × T, where α is the slew rate of the first ramp signal VR1) from the actual value of the input voltage Vi and the target value of the output voltage Vo, and generating an equivalent analog signal VC1' having that value is also conceivable.

[0099] In the latter method, as shown in this figure, when the first analog signal VC1 transiently varies, the center value Ic of the coil current IL cannot be correctly sampled. However, the deviation of the sampling timing is only temporary, and there is no particular problem in the overcurrent protection operation or the light load detection operation.

[0100] In the fifth operation example of this figure, an example based on the previous first operation example (Figure 9) was given. However, in the second to fourth operation examples (Figures 10 to 12), it is of course also possible to perform the comparison process between the equivalent analog signal VC1' and the second ramp signal VR2.

[0101] <Fifth Embodiment> FIG. 14 is a diagram showing a fifth embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is characterized in that, based on the first embodiment (FIG. 1), a timing control signal ST is generated using a first lamp signal VR1 and a second analog signal VC2. Therefore, for the components similar to those in the first embodiment, the same reference numerals as those in FIG. 1 are used, and redundant descriptions are omitted. Hereinafter, the characteristic parts of the fifth embodiment will be mainly described.

[0102] The DC / DC converter 1 of the present embodiment has an average value generation unit 150 as a means for generating the second analog signal VC2. The average value generation unit 150 generates a second analog signal VC2 having a simple average value of the signal value of the first analog signal VC1 and the starting value or the ending value of the first lamp signal VR1.

[0103] The timing control unit 120 generates a timing control signal ST so that the coil current IL is sampled at the center timing of the on-period ton or the off-period toff of the switch output stage 10 by using both the first lamp signal VR1 and the second analog signal VC2. Hereinafter, a specific operation example of the timing control unit 120 will be described in detail.

[0104] FIG. 15 is a waveform diagram showing a first operation example of the timing control unit 120 in the fifth embodiment, in which, in order from the top, the first analog signal VC1 (dashed-dotted line), the second analog signal VC2 (two-dot chain line), the first lamp signal VR1 (solid line), the coil current IL, and the timing control signal ST are depicted.

[0105] As shown in this figure, the first lamp signal VR1 is a sawtooth wave signal that repeats rising and resetting at a predetermined switching period T.

[0106] When the first analog signal VC1 is higher than the first lamp signal VR1, the switch output stage 10 enters the on period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the first lamp signal VR1, the switch output stage 10 enters the off period toff, and the coil current IL decreases.

[0107] That is, the higher the first analog signal VC1, the larger the on-duty ratio Don (= ton / T) of the switch output stage 10. Conversely, the lower the first analog signal VC1, the smaller the on-duty ratio Don of the switch output stage 10.

[0108] Here, the average value generation unit 150 generates a second analog signal VC2 (= (VC1 + VR1L) / 2) having a simple average value of the signal value of the first analog signal VC1 and the starting value of the first lamp signal VR1 (= the bottom value VR1L of the first lamp signal VR1 in this figure).

[0109] Also, the timing control unit 120 compares the first lamp signal VR1 and the second analog signal VC2 to generate a timing control signal ST. More specifically, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the timing when the first lamp signal VR1 rises and intersects the second analog signal VC2.

[0110] As shown in this figure, the timing at which the first lamp signal VR1 and the second analog signal VC2 intersect coincides with the center timing of the on period ton (= the timing when ton / 2 has elapsed since the coil current IL began to increase).

[0111] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the on period ton by sampling the coil current IL triggered by the one-shot pulse of the timing control signal ST.

[0112] In the previous fourth embodiment (Figs. 8 to 13), it was necessary to generate a second ramp signal VR2 having a slew rate twice that of the first ramp signal VR1 that fluctuates in voltage value at high speed. However, in this embodiment, the second ramp signal VR2 is not required. Therefore, when it is difficult to generate the second ramp signal VR2, it is desirable to adopt this embodiment.

[0113] FIG. 16 is a waveform diagram showing a second operation example of the timing control unit 120 in the fifth embodiment. Similar to the previous FIG. 15, from top to bottom in order, the first analog signal VC1 (dashed line), the second analog signal VC2 (two-dot chain line), and the first ramp signal VR1 (solid line), the coil current IL, and the timing control signal ST are depicted.

[0114] The second operation example in this figure is basically the same as the previous first operation example (FIG. 15), but in the average value generation unit 150, a second analog signal VC2 having a simple average value of the signal value of the first analog signal VC1 and the end point value of the first ramp signal VR1 (= the peak value VR1H of the first ramp signal VR1 in this figure) is generated. There is a difference in that ((VC1 + VR1H) / 2).

[0115] In this case, the timing at which the first ramp signal VR1 and the second analog signal VC2 intersect coincides with the center timing of the off period toff (= the timing when toff / 2 has elapsed since the coil current IL started to decrease).

[0116] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL in the off period toff by sampling the coil current IL using the one-shot pulse of the timing control signal ST as a trigger.

[0117] FIG. 17 is a waveform diagram showing a third operation example of the timing control unit 120 in the fifth embodiment. From top to bottom in order, the first analog signal VC1 (dashed-dotted line), the second analog signal VC2 (two-dot chain line), the first lamp signal VR1 (solid line), and the second lamp signal VR2 (dashed line), the coil current IL, and the timing control signal ST are depicted.

[0118] The operation example in this figure is basically the same as the above-described first operation example (FIG. 15), but there is a difference in that the average value generation unit 150 generates a second analog signal VC2 having a weighted average value of the signal value of the first analog signal VC1 and the start value or end value of the first lamp signal VR1.

[0119] Also, along with the above changes, in the timing control unit 120, using the second lamp signal VR2 having a slew rate different from that of the first lamp signal VR1 and the second analog signal VC2, the timing control signal ST is generated so that sampling of the coil current IL is performed at the center timing of the on period ton or the off period toff of the switch output stage 10. Note that, unlike the previous fourth embodiment (FIGS. 8 to 13), the second lamp signal VR2 does not necessarily have a slew rate twice that of the first lamp signal VR1.

[0120] For example, specifically described with reference to this figure, the second analog signal VC2 has a weighted average value (= mVC1 + nVR1L) of the signal value (weight m) of the first analog signal VC1 and the bottom value VR1L (weight n) of the first lamp signal VR1. Also, the second lamp signal VR2 has a slew rate that is 2m / (m + n) times that of the first lamp signal VR1.

[0121] With such a configuration, the timing at which the second lamp signal VR2 and the second analog signal VC2 intersect coincides with the center timing of the on period ton (= the timing when ton / 2 has elapsed since the coil current IL started to increase).

[0122] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the on period ton by sampling the coil current IL using the one-shot pulse of the timing control signal ST as a trigger.

[0123] <Sixth Embodiment> FIG. 18 is a diagram showing a sixth embodiment of the DC / DC converter. The DC / DC converter 1 of the present embodiment is based on the first embodiment (FIG. 1), and performs PWM control using a triangular-wave third ramp signal VR3 instead of a sawtooth-wave first ramp signal VR1. Further, the DC / DC converter 1 is characterized in that it detects the timing at which the third ramp signal VR3 takes the peak value VR3H or the bottom value VR3L (= peak timing or bottom timing) and generates a timing control signal ST. Therefore, components similar to those in the first embodiment are denoted by the same reference numerals as in FIG. 1, and redundant descriptions are omitted. Hereinafter, the characteristic parts of the sixth embodiment will be mainly described.

[0124] In the DC / DC converter 1 of the present embodiment, the oscillator 70 generates a triangular-wave third ramp signal VR3 with an equal up / down slew rate and supplies it to the inverting input terminal (-) of the PWM comparator 80. Further, the oscillator 70 generates a first clock signal CLK1 whose logic level switches at the peak timing and the bottom timing of the third ramp signal VR3 and supplies it to the timing control unit 120.

[0125] FIG. 19 is a circuit diagram showing a configuration example of the oscillator 70 in the sixth embodiment. The oscillator 70 of this configuration example includes current sources 71a and 71b, switches 72a and 72b, a capacitor 73a, a comparator 74a, resistors 75a, 75b, and 75c, and a selector 76.

[0126] The first terminal of the current source 71a is connected to the terminal to which the power supply voltage VDD is applied. The second terminal of the current source 71a is connected to the first terminal of the switch 72a. The second terminal of the switch 72a, the first terminal of the switch 72b, the first terminal of the capacitor 73a, and the non-inverting input terminal (+) of the comparator 74a are all connected to the output terminal of the third lamp signal VR3. The second terminal of the switch 72b is connected to the first terminal of the current source 71b. The second terminal of the current source 71b and the second terminal of the capacitor 73a are connected to the ground terminal.

[0127] Resistors 75a, 75b, and 75c are connected in series in the illustrated order between the terminal to which the reference voltage VREF is applied and the ground terminal. The connection node between the resistor 75a and the resistor 75b is connected to the first input terminal of the selector 76 as the output terminal of the first divided voltage (corresponding to the peak value VR3H of the third lamp signal VR3). The connection node between the resistor 75b and the resistor 75c is connected to the second input terminal of the selector 76 as the output terminal of the second divided voltage lower than the first divided voltage (corresponding to the bottom value VR3L of the third lamp signal VR3). The output terminal of the selector 76 is connected to the inverting input terminal (-) of the comparator 74 as the output terminal of the threshold voltage VTH. Note that the control terminals of the switches 72a and 72b and the selector 76 are all connected to the output terminal of the comparator 74a (= the output terminal of the first clock signal CLK1).

[0128] In the oscillator 70 having the above configuration, the current source 71a generates a predetermined charging current I71a, and the current source 71b generates a discharging current I71b equal to the charging current I71a.

[0129] Also, the switches 72a and 72b are turned on / off according to the first clock signal CLK1 so as to switch whether to charge the capacitor 73a with the charging current I71a or discharge it with the discharging current I71b.

[0130] Specifically, when the first clock signal CLK1 is at a low level, switch 72a turns on and switch 72b turns off, causing capacitor 73a to be charged by charging current I71a. Therefore, the third lamp signal VR3 monotonically increases at a predetermined rising slew rate (see times t1 to t2 in FIG. 20).

[0131] On the other hand, when the first clock signal CLK1 is at a high level, switch 72a turns off and switch 72b turns on, causing capacitor 73a to be discharged by discharge current I71b. Therefore, the third lamp signal VR3 monotonically decreases at a falling slew rate equal to the rising slew rate (with the opposite polarity) (see times t2 to t3 in FIG. 20).

[0132] Comparator 74a compares the third lamp signal VR3 with the threshold voltage VTH (= peak value VR3H or bottom value VR3L) to generate the first clock signal CLK1. Note that selector 76 selects the peak value VR3H as the threshold voltage VTH when the first clock signal CLK1 is at a low level (see times t1 to t2 in FIG. 20), and conversely, selects the bottom value VR3L as the threshold voltage VTH when the first clock signal CLK1 is at a high level (see times t2 to t3 in FIG. 20).

[0133] Therefore, when the first clock signal CLK1 is at a low level, the first clock signal CLK1 is maintained at a low level until the third lamp signal VR3 exceeds the peak value VR3H. When the third lamp signal VR3 exceeds the peak value VR3H, the first clock signal CLK1 is raised from a low level to a high level (see times t1 to t2 in FIG. 20).

[0134] On the other hand, when the first clock signal CLK1 is at a high level, the first clock signal CLK1 is maintained at a high level until the third lamp signal VR3 falls below the bottom value VR3L. When the third lamp signal VR3 falls below the bottom value VR3L, the first clock signal CLK1 is lowered from a high level to a low level (see times t2 to t3 in FIG. 20).

[0135] Thus, the comparator 74a, the resistors 75a to 75c, and the selector 76 function as a clock signal generation unit that compares the third lamp signal VR3 with the peak value VR3H and the bottom value VR3L to generate the first clock signal CLK1.

[0136] The timing control unit 120 receives the input of the first clock signal CLK1 described above, and generates a timing control signal ST so that the sampling of the coil current IL is performed at the timing when the logic level switches (= the peak timing or the bottom timing of the third lamp signal VR3). Hereinafter, a specific operation example of the timing control unit 120 will be described in detail.

[0137] FIG. 21 is a waveform diagram showing a first operation example of the timing control unit 120 in the sixth embodiment, and depicts the first analog signal VC1 (dashed line) and the third lamp signal VR3 (solid line), the coil current IL, and the timing control signal ST in order from the top.

[0138] As shown in this figure, the third lamp signal VR3 has a predetermined switching period T, rises to the peak value VR3H and then turns down, and turns up when it drops to the bottom value VR3L, and repeats rising and falling between the peak value VR3H and the bottom value VR3L.

[0139] When the first analog signal VC1 is higher than the third lamp signal VR3, the switch output stage 10 is in the on period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the third lamp signal VR3, the switch output stage 10 is in the off period toff, and the coil current IL decreases.

[0140] That is, the higher the first analog signal VC1, the larger the on duty Don (= ton / T) of the switch output stage 10, and conversely, the lower the first analog signal VC1, the smaller the on duty Don of the switch output stage 10.

[0141] Here, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the bottom timing when the third lamp signal VR3 takes the bottom value VR3L (corresponding to the timing when the first clock signal CLK1 falls from the high level to the low level).

[0142] As shown in this figure, the bottom timing of the third lamp signal VR3 coincides with the center timing of the on-period ton (the timing when ton / 2 has elapsed since the coil current IL began to increase).

[0143] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL in the on-period ton by sampling the coil current IL using the one-shot pulse of the timing control signal ST as a trigger.

[0144] Thus, if a configuration is used in which PWM control is performed using the triangular-wave third lamp signal VR3 instead of the sawtooth-wave first lamp signal VR1, it is possible to easily sample the center value Ic of the coil current IL simply by detecting the peak timing or the bottom timing of the third lamp signal VR3.

[0145] FIG. 22 is a waveform diagram showing a second operation example of the timing control unit 120 in the sixth embodiment. Similar to the previous FIG. 21, the first analog signal VC1 (dashed line) and the third lamp signal VR3 (solid line), the coil current IL, and the timing control signal ST are depicted in order from the top.

[0146] The second operation example of this figure is basically the same as the previous first operation example (FIG. 21). However, the timing control unit 120 is different in that it generates a one-shot pulse in the timing control signal ST at the peak timing when the third lamp signal VR3 takes the peak value VR3H (corresponding to the timing when the first clock signal CLK1 rises from the low level to the high level).

[0147] Note that, as shown in this figure, the peak timing of the third lamp signal VR3 coincides with the center timing of the off period toff (= the timing when toff / 2 has elapsed since the coil current IL started to decrease).

[0148] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL in the off period toff by sampling the coil current IL using the one-shot pulse of the timing control signal ST as a trigger.

[0149] <Seventh Embodiment> FIG. 23 is a diagram showing a seventh embodiment of the DC / DC converter. The DC / DC converter 1 of this embodiment is based on the first embodiment (FIG. 1), and a PWM comparator 160 and an OR gate 170 are newly added separately. PWM control is performed using the first lamp signal VR1 and the inverted first lamp signal VR1B obtained by inverting its polarity, and it is characterized in that the respective reset timings are detected to generate a timing control signal ST. Therefore, for the components similar to those in the first embodiment, the same reference numerals as those in FIG. 1 are given, and redundant explanations are omitted. Hereinafter, the characteristic parts of the seventh embodiment will be mainly described.

[0150] In the DC / DC converter 1 of this embodiment, the oscillator 70 generates a sawtooth-wave first lamp signal VR1 and an inverted first lamp signal VR1B that have opposite polarities to each other and repeat rising or falling and resetting at a common switching period T, and supplies them to the inverting input terminals (-) of the PWM comparators 80 and 160, respectively. Further, the oscillator 70 generates a second clock signal CLK2 in which a one-shot pulse is generated at the reset timings of the first lamp signal VR1 and the inverted first lamp signal VR1B, and supplies it to the timing control unit 120.

[0151] As described above, the PWM comparator 80 compares the first analog signal VC1 input to the non-inverting input terminal (+) with the first ramp signal VR1 input to the inverting input terminal (-) to generate a first comparison signal CMP1. The first comparison signal CMP1 goes high when the first analog signal VC1 is higher than the first ramp signal VR1, and goes low when the first analog signal VC1 is lower than the first ramp signal VR1.

[0152] On the other hand, the PWM comparator 160 compares the first analog signal VC1 input to the non-inverting input terminal (+) with the inverted first ramp signal VR1B input to the inverting input terminal (-) to generate a second comparison signal CMP2. The second comparison signal CMP2 goes high when the first analog signal VC1 is higher than the inverted first ramp signal VR1B, and goes low when the first analog signal VC1 is lower than the inverted first ramp signal VR1B.

[0153] The OR gate 170 generates a logical sum signal SX (corresponding to the control signal of the switch output stage 10) of the first comparison signal CMP1 and the second comparison signal CMP2 and outputs it to the driver 90. The logical sum signal SX goes high when at least one of the first comparison signal CMP1 and the second comparison signal CMP2 is high, and goes low when both the first comparison signal CMP1 and the second comparison signal CMP2 are low.

[0154] FIG. 24 is a circuit diagram showing a configuration example of the oscillator 70 in the seventh embodiment. The oscillator 70 of this configuration example includes a current source 71c, switches 72c and 72d, capacitors 73b and 73c, a comparator 74b, and a delay unit 77.

[0155] The first terminal of the current source 71c is connected to the applied terminal of the power supply voltage VDD. The second terminal of the current source 71c, the first terminal of the switch 73b, the first terminal of the capacitor 73b, and the non-inverting input terminal (+) of the comparator 74b are all connected to the output terminal of the first ramp signal VR1. The second terminal of the switch 72c and the second terminal of the capacitor 73b are connected to the applied terminal (e.g., the ground terminal) of the first voltage VR1L (corresponding to the bottom value VR1L of each of the first ramp signal VR1 and the inverted first ramp signal VR1B). The inverting input terminal (-) of the comparator 74b is connected to the applied terminal of the second voltage VR1H (corresponding to the peak value VR1H of the first ramp signal VR1 and the inverted first ramp signal VR1B). The output terminal of the comparator 74b is connected to the input terminal of the delay unit 77.

[0156] The first terminal of the switch 72d and the first terminal of the capacitor 73c are both connected to the applied terminal of the second voltage VR1H. The second terminal of the switch 72d, the second terminal of the capacitor 73c, and the first terminal of the current source 71d are all connected to the output terminal of the inverted first ramp signal VR1B. The second terminal of the current source 71d is connected to the applied terminal of the first voltage VR1L. The control terminals of the switches 72c and 72d are both connected to the output terminal of the delay unit 77 (= the output terminal of the second clock signal CLK2).

[0157] In the oscillator 70 having the above configuration, the current source 71c generates a charging current I71c for charging the capacitor 73b, and the current source 71d generates a charging current I71d for charging the capacitor 73c. Note that the charging currents I71c and I71d are set to have equal current values.

[0158] Also, both switches 72c and 72d are turned on / off so as to discharge capacitors 73b and 73c in response to the second clock signal CLK2. More specifically, when the second clock signal CLK2 is at a low level, both switches 72c and 72d are turned off, and capacitors 73b and 73c are charged by charging currents I71c and I71d, respectively. Therefore, the first lamp signal VR1 monotonically increases from the bottom value VR1L toward the peak value VR1H at a predetermined rising slew rate, and the inverted first lamp signal VR1B monotonically decreases from the peak value VR1H toward the bottom value VR1L at a falling slew rate equal to the rising slew rate (with the opposite polarity) (see times t11 to t12 in FIG. 25).

[0159] On the other hand, when the second clock signal CLK2 is at a high level, both switches 72c and 72d are turned on, and capacitors 73b and 73c are discharged without delay (i.e., the state where both ends of each are short-circuited). As a result, the first lamp signal VR1 is reset to the bottom value VR1L, and the inverted first lamp signal VR1B is reset to the peak value VR1H (see times t12 to t13 in FIG. 25).

[0160] Comparator 74b compares the first lamp signal VR1 with the second voltage VR1H (corresponding to the peak value VR1H) and generates a comparison signal S74b. Note that the comparison signal S74b is at a low level when the first lamp signal VR1 is lower than the peak value VR1H, and at a high level when the first lamp signal VR1 is higher than the peak value VR1H.

[0161] The delay unit 77 performs a delay process on the comparison signal S74b to generate a second clock signal CLK2. More specifically, when the comparison signal S74b rises to the high level, the delay unit 77 immediately raises the second clock signal CLK2 to the high level (see time t12 in FIG. 25). On the other hand, when the comparison signal S74b falls to the low level, the delay unit 77 waits for a predetermined delay time to elapse and then lowers the second clock signal CLK2 to the low level (see times t12 to t13 in FIG. 25). With such a configuration, it becomes possible to reliably discharge the capacitors 73b and 73c.

[0162] In this way, the comparator 74b and the delay unit 77 function as a clock signal generation unit that compares the first lamp signal VR1 with the second voltage VR3H (corresponding to the peak value VR1H) to generate the second clock signal CLK2.

[0163] The timing control unit 120 receives the input of the second clock signal CLK2 described above and generates a timing control signal ST so that the coil current IL is sampled at the timing when the logic level thereof switches (= the reset timing of the first lamp signal VR1 and the inverted first lamp signal VR1B). Hereinafter, a specific operation example of the timing control unit 120 will be described in detail.

[0164] FIG. 26 is a waveform diagram showing an operation example of the timing control unit 120 in the seventh embodiment. From top to bottom, the first analog signal VC1 (dashed-dotted line), the first lamp signal VR1 (solid line), the inverted first lamp signal VR1B (dashed line), the coil current IL, and the timing control signal ST are depicted.

[0165] As also shown in FIG. 25 above, the first lamp signal VR1 and the inverted first lamp signal VR1B repeat rising or falling and resetting with a common switching period T while having opposite polarities to each other between the peak value VR1H and the bottom value VR1L. On the other hand, the first analog signal VC1 varies within a voltage range of VR1L < VC1 < (VR1H + VR1L) / 2.

[0166] When the first analog signal VC1 is higher than at least one of the first lamp signal VR1 and the inverted first lamp signal VR1B, the switch output stage 10 enters the on period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than both the first lamp signal VR1 and the inverted first lamp signal VR1B, the switch output stage 10 enters the off period toff, and the coil current IL decreases.

[0167] That is, the higher the first analog signal VC1, the larger the on-duty ratio Don (= ton / T) of the switch output stage 10. Conversely, the lower the first analog signal VC1, the smaller the on-duty ratio Don of the switch output stage 10.

[0168] Here, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the reset timing of the first lamp signal VR1 and the inverted first lamp signal VR1B (corresponding to the timing when the second clock signal CLK2 rises to the high level).

[0169] As shown in this figure, the reset timing of the first lamp signal VR1 and the inverted first lamp signal VR1B coincides with the center timing of the on period ton (the timing when ton / 2 has elapsed since the coil current IL began to increase).

[0170] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the on period ton by sampling the coil current IL triggered by the one-shot pulse of the timing control signal ST.

[0171] <Eighth Embodiment> FIG. 27 is a diagram showing an eighth embodiment of the DC / DC converter. The DC / DC converter 1 of this embodiment is characterized in that, while based on the seventh embodiment (FIG. 23), an AND gate 180 is used instead of the OR gate 170. Therefore, for the components similar to those in the seventh embodiment, the same reference numerals as in FIG. 23 are given, and redundant explanations are omitted. Hereinafter, the characteristic parts of the eighth embodiment will be mainly described.

[0172] In the DC / DC converter 1 of this embodiment, the AND gate 180 generates a logical product signal SY (= corresponding to the control signal of the switch output stage 10) of the first comparison signal CMP1 and the second comparison signal CMP2 and outputs it to the driver 90. The logical product signal SY becomes high level when both the first comparison signal CMP1 and the second comparison signal CMP2 are high level, and becomes low level when at least one of the first comparison signal CMP1 and the second comparison signal CMP2 is low level.

[0173] FIG. 28 is a waveform diagram showing an operation example of the timing control unit 120 in the eighth embodiment. Similar to FIG. 26 above, in order from the top, the first analog signal VC1 (dashed line), the first lamp signal VR1 (solid line), and the inverted first lamp signal VR1B (dotted line), the coil current IL, and the timing control signal ST are depicted.

[0174] Also in the operation example of this figure, the first lamp signal VR1 and the inverted first lamp signal VR1B repeat rising, falling, and resetting at a common switching period T while having opposite polarities to each other between the peak value VR1H and the bottom value VR1L. On the other hand, the first analog signal VC1 varies within a voltage range of (VR1H + VR1L) / 2 < VC1 < VR1H.

[0175] When the first analog signal VC1 is higher than both the first lamp signal VR1 and the inverted first lamp signal VR1B, the switch output stage 10 enters the on period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than at least one of the first lamp signal VR1 and the inverted first lamp signal VR1B, the switch output stage 10 enters the off period toff, and the coil current IL decreases.

[0176] That is, the higher the first analog signal VC1, the larger the on-duty ratio Don (= ton / T) of the switch output stage 10. Conversely, the lower the first analog signal VC1, the smaller the on-duty ratio Don of the switch output stage 10.

[0177] Here, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the reset timing of the first lamp signal VR1 and the inverted first lamp signal VR1B (corresponding to the timing when the second clock signal CLK2 rises to the high level).

[0178] As shown in this figure, the reset timing of the first lamp signal VR1 and the inverted first lamp signal VR1B coincides with the center timing of the off period toff (the timing when toff / 2 has elapsed since the coil current IL began to decrease).

[0179] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL in the off period toff by sampling the coil current IL using the one-shot pulse of the timing control signal ST as a trigger.

[0180] <Embodiment 9> FIG. 29 is a diagram showing a ninth embodiment of a DC / DC converter. The DC / DC converter 1 of this embodiment is based on the seventh embodiment (FIG. 23) and the eighth embodiment (FIG. 27), while changing the switch output stage 10 to a buck-boost type, reversing the input polarities of the PWM comparators 80 and 160 respectively, and using a logic operation unit 190 instead of the OR gate 170 and the AND gate 180. Therefore, for the components similar to those in the seventh and eighth embodiments, the same reference numerals as in FIGS. 23 and 27 are given to avoid redundant explanations, and the following will focus on the characteristic parts of the ninth embodiment.

[0181] In the DC / DC converter 1 of this embodiment, the switch output stage 10 includes, in addition to the step-down output transistor 11 and the synchronous rectification transistor 12, a step-up output transistor 15 (an NMOSFET in this figure) and a synchronous rectification transistor 16 (a PMOSFET in this figure), and steps down or steps up the input voltage Vin to generate a desired output voltage Vout.

[0182] The source of the output transistor 11 is connected to the applied end of the input voltage Vi. The drain of the output transistor 11 and the drain of the synchronous rectification transistor 12 are connected to the first end of the coil 13. The source of the synchronous rectification transistor 12 is connected to the ground terminal. The drain of the output transistor 15 and the drain of the synchronous rectification transistor 16 are connected to the second end of the coil 13. The source of the output transistor 15 is connected to the ground terminal. The source of the synchronous rectification transistor 16 is connected to the output end of the output voltage Vo and the first end of the capacitor 14. The second end of the capacitor 14 is connected to the ground terminal.

[0183] The output transistor 11 turns on when the step-down drive signal D1 is at a low level and turns off when the step-down drive signal D1 is at a high level. The synchronous rectification transistor 12 turns on when the step-down drive signal D2 is at a high level and turns off when the step-down drive signal D2 is at a low level. The output transistor 15 turns on when the boost drive signal U1 is at a high level and turns off when the boost drive signal U1 is at a low level. The synchronous rectification transistor 16 turns on when the boost drive signal U2 is at a low level and turns off when the boost drive signal U2 is at a high level.

[0184] Also, in the DC / DC converter 1 of this embodiment, the logic operation unit 190 includes a NAND gate 191 and an OR gate 192, receives the inputs of the first comparison signal CMP1 and the second comparison signal CMP2, and generates a step-down control signal D0 and a boost control signal U0.

[0185] The NAND gate 191 generates the step-down control signal D0 by performing a negative logical product operation on the first comparison signal CMP1 and the second comparison signal CMP2. Therefore, the step-down control signal D0 becomes a low level when both the first comparison signal CMP1 and the second comparison signal CMP2 are at a high level, and becomes a high level when at least one of the first comparison signal CMP1 and the second comparison signal CMP2 is at a low level.

[0186] The OR gate 192 generates the boost control signal U0 by performing a logical sum operation on the first comparison signal CMP1 and the second comparison signal CMP2. Therefore, the boost control signal U0 becomes a low level when both the first comparison signal CMP1 and the second comparison signal CMP2 are at a low level, and becomes a high level when at least one of the first comparison signal CMP1 and the second comparison signal CMP2 is at a high level.

[0187] That is, the logic operation unit 190 receives the inputs of the first comparison signal CMP1 and the second comparison signal CMP2, and extracts a state where the first analog signal VC1 is lower than both the first lamp signal VR1 and the inverted first lamp signal VR1B (CMP1 = CMP2 = H), and conversely, a state where the first analog signal VC1 is higher than both the first lamp signal VR1 and the inverted first lamp signal VR1B (CMP1 = CMP2 = L). Based on one of the extraction results, a buck control signal D0 is generated, and based on the other extraction result, a boost control signal U0 is generated.

[0188] Also, in the DC / DC converter 1 of the present embodiment, the driver 90 receives the inputs of the buck control signal D0 and the boost control signal U0, generates buck drive signals D1 and D2, and boost drive signals U1 and U2, and drives the switch output stage 10 using these signals.

[0189] FIG. 30 is a timing chart showing the generation operation of the buck drive signals D1 and D2, depicting the buck control signal D0, and the buck drive signals D1 and D2.

[0190] The buck drive signal D1 becomes low level with a delay of delay time d from the rising edge of the buck control signal D0, and becomes high level simultaneously with the falling edge of the buck control signal D0. On the other hand, the buck drive signal D2 becomes low level simultaneously with the rising edge of the buck control signal D0, and becomes high level with a delay of delay time d from the falling edge of the buck control signal D0.

[0191] In this way, the buck drive signals D1 and D2 basically become logical inversion signals of the buck control signal D0. Therefore, the output transistor 11 and the synchronous rectifier transistor 12 are turned on / off complementarily. However, a period (so-called dead time) during which both the output transistor 11 and the synchronous rectifier transistor 12 are turned off is provided in the buck drive signals D1 and D2 over the delay time d. Therefore, it is possible to prevent the occurrence of through current caused by the simultaneous on of the output transistor element 11 and the synchronous rectifier transistor 12.

[0192] FIG. 31 is a timing chart showing the generation operations of the boost drive signals U1 and U2, in which a boost control signal U0 and the boost drive signals U1 and U2 are depicted.

[0193] The boost drive signal U1 becomes low level simultaneously with the rising edge of the boost control signal U0, and becomes high level with a delay of a delay time d from the falling edge of the boost control signal U0. On the other hand, the boost drive signal U2 becomes low level with a delay of the delay time d from the rising edge of the boost control signal U0, and becomes high level simultaneously with the falling edge of the boost control signal U0.

[0194] Thus, the boost drive signals U1 and U2 basically become logical inversion signals of the boost control signal U0. Therefore, the output transistor 15 and the synchronous rectification transistor 16 are turned on / off complementarily. However, a period (so-called dead time) during which both the output transistor 15 and the synchronous rectification transistor 16 are turned off is provided in the boost drive signals U1 and U2 over the delay time d. Therefore, it is possible to prevent the generation of a through current caused by the simultaneous on of the output transistor 15 and the synchronous rectification transistor 16.

[0195] FIG. 32 is a waveform diagram showing a first operation example (during step-down) of the timing control unit 120 in the ninth embodiment, in which, in order from the top, a first analog signal VC1 (dashed-dotted line), a first lamp signal VR1 (solid line) and an inverted first lamp signal VR1B (dashed line), a first comparison signal CMP1 and a second comparison signal CMP2, a step-down control signal D0 and a boost control signal U0, a coil current IL, and a timing control signal ST are depicted.

[0196] As also shown in the previous FIG. 25, the first lamp signal VR1 and the inverted first lamp signal VR1B repeat rising or falling and reset at a common switching period T while having opposite polarities to each other between a peak value VR1H and a bottom value VR1L.

[0197] Here, when VR1L < VC1 < (VR1H + VR1L) / 2, the boost control signal U0 is always at a high level, so the output transistor 15 is always off and the synchronous rectifier transistor 16 is always on. On the other hand, the buck control signal D0 is in a state of being pulse-driven with an on-duty ratio Don (= the ratio of the on-period ton to the switching period T) corresponding to the first analog signal VC1, so the output transistor 11 and the synchronous rectifier transistor 12 are complementarily turned on / off.

[0198] When the output transistor 11 is on and the synchronous rectifier transistor 12 is off, energy is stored in the coil 13. On the other hand, when the output transistor 11 is off and the synchronous rectifier transistor 12 is on, the energy stored in the coil 13 is released. By repeating such energy storage and release, an output voltage Vo obtained by stepping down the input voltage Vi is generated.

[0199] Note that when the first analog signal VC1 is higher than at least one of the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 is in the on-period ton and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than both the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 is in the off-period toff and the coil current IL decreases.

[0200] That is, during the buck operation of this figure, the higher the first analog signal VC1, the larger the on-duty ratio Don (= ton / T) of the switch output stage 10. Conversely, the lower the first analog signal VC1, the smaller the on-duty ratio Don of the switch output stage 10.

[0201] Here, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B (corresponding to the timing when the second clock signal CLK2 rises to a high level).

[0202] Note that, as shown in this figure, the reset timings of the first lamp signal VR1 and the inverted first lamp signal VR1B coincide with the center timing of the on period ton (= the timing when ton / 2 has elapsed since the coil current IL started to increase).

[0203] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL in the on period ton by sampling the coil current IL triggered by the one-shot pulse of the timing control signal ST. In this way, the sampling timing during the buck operation is the same as that in FIG. 26 described above.

[0204] FIG. 33 is a waveform diagram showing a second operation example (during boost) of the timing control unit 120 in the ninth embodiment. In order from the top, the first analog signal VC1 (dashed-dotted line), the first lamp signal VR1 (solid line) and the inverted first lamp signal VR1B (dashed line), the first comparison signal CMP1 and the second comparison signal CMP2, the buck control signal D0 and the boost control signal U0, the coil current IL, and the timing control signal ST are depicted.

[0205] Also in the operation example of this figure, the first lamp signal VR1 and the inverted first lamp signal VR1B repeat rising, falling, and resetting at a common switching period T while having opposite polarities to each other between the peak value VR1H and the bottom value VR1L.

[0206] Here, when (VR1H + VR1L) / 2 < VC1 < VR1H, the buck control signal D0 is always at a high level, so the output transistor 11 is always on and the synchronous rectification transistor 12 is always off. On the other hand, the boost control signal U0 is in a state of being pulse-driven with an on duty ratio Don (= the ratio of the on period ton in the switching period T) corresponding to the first analog signal VC1, so the output transistor 15 and the synchronous rectification transistor 16 are complementarily turned on / off.

[0207] When the output transistor 15 is turned on and the synchronous rectifier transistor 16 is turned off, energy is stored in the coil 13. On the other hand, when the output transistor 15 is turned off and the synchronous rectifier transistor 16 is turned on, the energy stored in the coil 13 is released. By repeating such energy storage and release, an output voltage Vo obtained by boosting the input voltage Vi is generated.

[0208] Note that when the first analog signal VC1 is higher than both the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 enters the on period ton, and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than at least one of the first ramp signal VR1 and the inverted first ramp signal VR1B, the switch output stage 10 enters the off period toff, and the coil current IL decreases.

[0209] That is, during the boosting operation of this figure, the higher the first analog signal VC1, the larger the on duty Don (= ton / T) of the switch output stage 10. Conversely, the lower the first analog signal VC1, the smaller the on duty Don of the switch output stage 10.

[0210] Here, the timing control unit 120 generates a one-shot pulse in the timing control signal ST at the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B (which corresponds to the timing when the second clock signal CLK2 rises to the high level).

[0211] As shown in this figure, the reset timing of the first ramp signal VR1 and the inverted first ramp signal VR1B coincides with the center timing of the off period toff (the timing when toff / 2 has elapsed since the coil current IL started to decrease).

[0212] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL in the off period toff by sampling the coil current IL using the one-shot pulse of the timing control signal ST as a trigger. In this way, the sampling timing during the boost operation is the same as that in FIG. 28 described above.

[0213] <Embodiment 10> The DC / DC converter 1 of this embodiment basically has the same configuration as that of the first embodiment (FIG. 1), and is characterized by the circuit configuration of the timing control unit 120. Therefore, the description of the overall configuration of the DC / DC converter 1 will be omitted, and the following will focus on the characteristic parts of the tenth embodiment.

[0214] First, prior to explaining the configuration and operation of the timing control unit 120, the configuration and operation of the oscillator 70 will be supplementarily explained with reference to FIG. 34.

[0215] FIG. 34 is a circuit diagram showing a configuration example of the oscillator 70 in the tenth embodiment. In the oscillator 70 of this configuration example, components related to the generation of the inverted first ramp signal VR1B (current source 71d, switch 72d, and capacitor 73c) are omitted while based on the seventh embodiment (FIG. 24).

[0216] Also, in the oscillator 70 of this configuration example, for ease of understanding the description, it is assumed that a first ramp signal VR1 with the reference voltage Vref as the peak value and the ground voltage GND as the bottom value is generated. More specifically, the reference voltage Vref is input to the inverting input terminal (-) of the comparator 74b, and the ground voltage GND is applied to the second terminal of the capacitor 73b.

[0217] Furthermore, in the oscillator 70 of this configuration example, as circuit elements forming the current source 71c, a P-channel type MOS field effect transistor P1 and P2, an N-channel type MOS field effect transistor N1, an operational amplifier AMP1, and a resistor R1 are specifically depicted.

[0218] The sources of transistors P1 and P2 are both connected to the applied terminal of the power supply voltage VDD. The gates of transistors P1 and P2 are both connected to the drain of transistor P1. The drain of transistor P1 is connected to the drain of transistor N1. The drain of transistor P2 is connected to the first terminal of capacitor 73b as the output terminal of the charging current I71c.

[0219] The non-inverting input terminal (+) of operational amplifier AMP1 is connected to the applied terminal of the constant voltage V1. The inverting input terminal (-) of operational amplifier AMP1 is connected to the source of transistor N1 and the first terminal of resistor R1. The output terminal of operational amplifier AMP1 is connected to the gate of transistor N1. The second terminal of resistor R1 is connected to the ground terminal.

[0220] In the current source 71c having the above configuration, operational amplifier AMP1 controls the gate of transistor N1 so that the non-inverting input terminal (+) and the inverting input terminal (-) are in an imaginary short circuit state. Therefore, since the constant voltage V1 is applied to the first terminal of resistor R1, a predetermined drain current (V1 / R1) flows through transistor N1.

[0221] Transistors P1 and P2 form a current mirror, and by mirroring the above drain current (V1 / R1) with a mirror ratio α, a charging current I71c (=α×(V1 / R1)) of capacitor 73b is generated.

[0222] Note that when the current value of the charging current I71c is I0 and the capacitance value of capacitor 73b is C0, in order to generate the first lamp signal VR1 and the second clock signal CLK2 with a desired switching period T, the mirror ratio α, the voltage value of the constant voltage V1, and the resistance value of resistor R1 may be appropriately set so that I0 = Vref×C0×(1 / T) is satisfied.

[0223] FIG. 35 is a circuit diagram showing a configuration example of the timing control unit 120 in the tenth embodiment. The timing control unit 120 of this configuration example includes a first internal signal generation unit 121, a second internal signal generation unit 122, and a comparator 123.

[0224] The first internal signal generation unit 121 is a circuit unit that generates a first internal signal V11 by charging and discharging the capacitor C1 in synchronization with the on signal ON, and includes a capacitor C1, current sources CS1 to CS3, switches SW1 and SW2, a pnp bipolar transistor Qp, an npn bipolar transistor Qn, and resistors R11 and R12.

[0225] The first ends of the current sources CS1 to CS3 are all connected to the power supply terminal. The second end of the current source CS1 is connected to the base of the transistor Qp and the first end of the switch SW1. The second end of the switch SW1 is connected to the first end of the capacitor C1 and the first end of the switch SW2. The second end of the current source CS2 is connected to the base of the transistor Qn and the emitter of the transistor Qp. The second end of the current source CS3 is connected to the non-inverting input terminal (+) of the comparator 123, the collector of the transistor Qn, and the first end of the resistor R12. The emitter of the transistor Qn is connected to the first end of the resistor R11. The second end of the capacitor C1, the second end of the switch SW2, the collector of the transistor Qp, and the second ends of the resistors R11 and R12 are all connected to the ground terminal. The control terminal of the switch SW1 is connected to the application terminal of the on signal ON. The control terminal of the switch SW2 is connected to the application terminal of the reset signal RST.

[0226] The switch SW1 turns on when the switch output stage 10 is in the on period ton (for example, ON = H) and turns off when the switch output stage 10 is in the off period toff (for example, ON = L). Note that the on signal ON is a logic signal synchronized with the on / off control of the switch output stage 10, and for example, the first comparison signal CMP1 can be diverted and used.

[0227] Switch SW2 turns on when, for example, the reset signal RST is at a high level, and turns off when the reset signal RST is at a low level. The reset signal RST is a signal for discharging the capacitor C1 prior to the on period ton, and for example, the above-described second clock signal CLK2 (see FIG. 34) can be diverted for use.

[0228] The second internal signal generation unit 122 is a circuit unit that generates a second internal signal V12 by charging and discharging the capacitor C2 in synchronization with the off signal OFF, and includes a capacitor C2, a current source CS4, and a switch SW3.

[0229] The first terminal of the current source CS4 is connected to the power supply terminal. The second terminal of the current source CS4 is connected to the inverting input terminal (−) of the comparator 123, the first terminal of the capacitor C2, and the first terminal of the switch SW3. The second terminal of the capacitor C2 and the second terminal of the switch SW3 are connected to the ground terminal. The control terminal of the switch SW3 is connected to the application terminal of the off signal OFF.

[0230] Switch SW3 turns on when the switch output stage 10 is in the on period ton (e.g., OFF = H), and turns off when the switch output stage 10 is in the off period toff (e.g., OFF = L). Note that the off signal OFF is a logic signal synchronized with the on / off control of the switch output stage 10, and for example, the first comparison signal CMP1 can be diverted for use.

[0231] The comparator 123 compares the first internal signal V11 input to the non-inverting input terminal (+) with the second internal signal V12 input to the inverting input terminal (−) to generate a timing control signal ST. The timing control signal ST becomes high when the first internal signal V11 is higher than the second internal signal V12, and conversely, becomes low when the first internal signal V11 is lower than the second internal signal V12.

[0232] As described above, different from the previous fourth to ninth embodiments (Figs. 8 to 33), the timing control unit 120 in this embodiment uses the first internal signal V11 and the second internal signal V12 generated by itself in synchronization with the on / off control of the switch output stage 10 to generate a timing control signal ST so that sampling of the coil current IL is performed at the center timing of the off period toff of the switch output stage 10. Hereinafter, a specific operation example of the timing control unit 120 will be described in detail with reference to Fig. 36 together with this figure.

[0233] Fig. 36 is a waveform diagram showing an operation example of the timing control unit 120 in the tenth embodiment. From the top in order, the first lamp signal VR1 (solid line) and the first analog signal VC1 (dashed-dotted line), the first comparison signal CMP1 (= on signal ON and off signal OFF), the coil current IL, the reset signal RST, the charging voltage V10 of the capacitor C1, the first internal signal V11 (solid line) and the second internal signal V12 (dashed line), and the timing control signal ST are depicted.

[0234] First, while referring to the upper three stages (VR1 / VC1, CMP1, and IL) of this figure, the overall operation of the DC / DC converter 1 will be reconfirmed.

[0235] When the first analog signal VC1 is higher than the first lamp signal VR1, the switch output stage 10 enters the on period ton (= time t21 to t22), and the coil current IL increases. On the other hand, when the first analog signal VC1 is lower than the first lamp signal VR1, the switch output stage 10 enters the off period toff (= time t22 to t24), and the coil current IL decreases. That is, the higher the first analog signal VC1, the larger the on duty Don (= ton / T) of the switch output stage 10. Conversely, the lower the first analog signal VC1, the smaller the on duty Don of the switch output stage 10.

[0236] Thus, the overall operation of the DC / DC converter 1 is not different from that in the first embodiment (Fig. 1) in any way.

[0237] Next, while referring to the lower four stages (RST, V10, V11 / V12, and ST) of this figure, the operation of the timing control unit 120 will be described in detail.

[0238] First, focusing on the first internal signal generation unit 121, at time t21, prior to the on period ton of the switch output stage 10, a one-shot pulse is generated in the reset signal RST. As a result, the switch SW2 turns on and the capacitor C1 is discharged, so the charging voltage V10 is reset to a zero value (= GND).

[0239] Thereafter, during the on period ton (= time t21 to t22) of the switch output stage 10, the switch SW1 turns on and conduction is established between the current source CS1 and the capacitor C1. As a result, the capacitor C1 is charged using the charging current I1 supplied from the current source CS1, so the charging voltage V10 rises with the passage of time t with a predetermined slope (= I1 / C1). Therefore, if set to I1 = Vref×C1×(1 / T), the charging voltage V10[t] after time t has elapsed from time t21 can be expressed as V10[t] = Vref×(t / T). That is, at time t21 (t = 0), V10 = GND, and at time t22 (t = ton), V10 = Vref×(ton / T).

[0240] Note that the charging voltage V10 is applied to the first end of the resistor R11 via the transistors Qp and Qn that receive the driving current I2 from the current source CS2. Accordingly, a lower current I11 (= V10 / R11) corresponding to the charging voltage V10 flows through the resistor R11. In this way, the current source CS2, the transistors Qp and Qn, and the resistor R11 function as a voltage / current conversion unit that converts the charging voltage V10 of the capacitor C1 into the lower current I11.

[0241] Also, a differential current I12 (= I3 - I11), which is obtained by subtracting the aforementioned lower current I11 from the upper current I3 generated by the current source CS3, flows through the resistor R12. Therefore, the first internal signal V11 drawn from the first end of the resistor R12 can be expressed as V11 = I12 × R12. In this way, the resistor R12 functions as a current / voltage conversion unit that converts the differential current I12 between the upper current I3 and the lower current I11 into the first internal signal V11.

[0242] Here, if I3 = Vref / R11 and R11 = 2×R12 are set, the first internal signal V11[t] after a time t has elapsed from the time t21 can be expressed as V11[t] = (1 / 2)×Vref×{1 - (t / T)}. That is, at the time t21 (t = 0), V11 = (1 / 2)×Vref, and at the time t22 (t = ton), V11 = (1 / 2)×Vref×(toff / T).

[0243] On the other hand, during the off period toff (= time t22 to t24) of the switch output stage 10, the switch SW1 is turned off. Therefore, the increase in the charging voltage V10 stops, and the first internal signal V11 is maintained at the voltage value just before the off state (= (1 / 2)×Vref×(toff / T)).

[0244] In this way, the first internal signal V11 changes from half of the reference voltage Vref (= (1 / 2)×Vref) to a value obtained by multiplying this by the off duty of the switch output stage 10 (= toff / T, that is, the ratio of the off period toff to the switching period T) during the on period ton of the switch output stage 10, and then is held at that value during the off period toff of the switch output stage 10.

[0245] Next, focusing on the second internal signal generation unit 122, during the on period ton (= time t21 to t22) of the switch output stage 10, the switch SW3 is turned on and the both ends of the capacitor C2 are short-circuited, so the second internal signal V12 is maintained at the zero value (= GND). Therefore, during the on period ton of the switch output stage 10, since the first internal signal V11 is always higher than the second internal signal V12, the timing control signal ST is maintained at the low level.

[0246] On the other hand, during the off period toff (= time t22 to t24) of the switch output stage 10, the switch SW3 is turned off. As a result, the capacitor C2 is charged using the charging current I4 supplied from the current source CS4, so the second internal signal V12 rises with a predetermined slope (= I4 / C2) as time t elapses. Therefore, if I4 = Vref × C2 × (1 / T) is set, the second internal signal V12[t] after time t has elapsed from time t22 can be expressed as V12[t] = Vref × (t / T). That is, at time t22 (t = 0), V12 = GND, and at time t24 (t = toff), V12 = Vref × (toff / T).

[0247] In this way, the second internal signal V12 is held at the zero value (= GND) during the on period ton of the switch output stage 10, and then changes from the zero value to the value obtained by multiplying the reference voltage Vref by the off-duty ratio (= toff / T) (= Vref × (toff / T)) during the off period toff of the switch output stage 10.

[0248] Here, the timing (= time t23) at which the first internal signal V11 and the second internal signal V12 cross each other coincides with the center timing of the off period toff (= the timing at which toff / 2 has elapsed since the coil current IL started to decrease). That is, the timing control signal ST rises from the low level to the high level at time t23.

[0249] Therefore, the current detection unit 50 can generate a current sense signal ISNS corresponding to the center value Ic of the coil current IL during the off period toff by sampling the coil current IL triggered by the rising edge of the timing control signal ST.

[0250] <Summary> Hereinafter, the various embodiments described so far will be summarized.

[0251] The DC / DC converter disclosed in this specification has a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, and the first internal signal and the second internal signal generated by itself in synchronization with the on / off control of the switch output stage. It has a timing control unit that generates the timing control signal so that the coil current is sampled at the center timing of the off period of the switch output stage, and generates a desired output voltage from the input voltage by performing output feedback control of the current mode control method using the current sense signal. It is configured as (the first configuration).

[0252] In the DC / DC converter having the first configuration, the timing control unit includes a first internal signal generation unit that generates the first internal signal in synchronization with the on period, a second internal signal generation unit that generates the second internal signal in synchronization with the off period, and a comparator that compares the first internal signal and the second internal signal and generates the timing control signal. It is preferably configured as (the second configuration).

[0253] Further, in the DC / DC converter having the second configuration, the first internal signal changes from half of the reference voltage to a value obtained by multiplying the off duty of the switch output stage during the on period, and then is held at that value during the off period. The second internal signal is held at a zero value during the on period, and then changes from the zero value to a value obtained by multiplying the off duty by the reference voltage during the off period. It is preferably configured as (the third configuration).

[0254] Also, in the DC / DC converter having the above-described third configuration, the first internal signal generation unit preferably has a configuration (a fourth configuration) including a first capacitor, a first current source that generates a charging current for the first capacitor, a first switch that charges the first capacitor during the on period, a second switch that discharges the first capacitor prior to the on period, a second current source that generates a predetermined upper current, a voltage / current conversion unit that converts the charging voltage of the first capacitor into a lower current, and a current / voltage conversion unit that converts the differential current between the upper current and the lower current into the first internal signal.

[0255] Also, in the DC / DC converter having the above-described third or fourth configuration, the second internal signal generation unit preferably has a configuration (a fifth configuration) including a second capacitor, a current source that generates a charging current for the second capacitor, and a switch that charges the second capacitor during the off period.

[0256] Also, the DC / DC converter having any one of the above-described first to fifth configurations preferably has a configuration (a sixth configuration) including an error amplifier that generates an error signal according to the difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage, an oscillator that generates a ramp signal at a predetermined switching period, a differential amplifier that generates an analog signal according to the difference between the error signal and the current sense signal, a comparator that compares the analog signal and the ramp signal to generate a comparison signal, and a driver that generates a drive signal for the switch output stage according to the comparison signal.

[0257] Also, the DC / DC converter having the above-described sixth configuration preferably further has a configuration (a seventh configuration) including a clamper that limits the error signal to be equal to or less than a predetermined upper limit value or equal to or greater than a predetermined lower limit value.

[0258] Further, the DC / DC converter having the above-described sixth or seventh configuration may be configured to further include a light load detection comparator that compares the error signal with a predetermined threshold value to control the operability of the switch output stage (eighth configuration).

[0259] Also, the DC / DC converter disclosed in this specification includes a comparator that compares a first analog signal and a ramp signal to generate a control signal for the switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing corresponding to a timing control signal, an average value generation unit that generates a second analog signal having a simple average value of the signal value of the first analog signal and the start value or end value of the ramp signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the center timing of the on period or off period of the switch output stage using the ramp signal and the second analog signal. By performing output feedback control of the current mode control method using the current sense signal, it is configured to generate a desired output voltage from the input voltage (ninth configuration).

[0260] Also, the DC / DC converter disclosed in this specification includes a comparator that compares a first analog signal and a first ramp signal to generate a control signal for the switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing corresponding to a timing control signal, an average value generation unit that generates a second analog signal having a weighted average value of the signal value of the first analog signal and the start value or end value of the first ramp signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the center timing of the on period or off period of the switch output stage using a second ramp signal having a slew rate different from that of the first ramp signal and the second analog signal. By performing output feedback control of the current mode control method using the current sense signal, it is configured to generate a desired output voltage from the input voltage (tenth configuration).

[0261] Also, in the DC / DC converter having the tenth configuration described above, the second analog signal has a weighted average value of the signal value (weight m) of the first analog signal and the starting value (weight n) of the first ramp signal (where m + n = 1, 0 < m < 1, 0 < n < 1, m ≠ n), and the second ramp signal may have a slew rate that is 2m / (m + n) times that of the first ramp signal (eleventh configuration).

[0262] Also, in the DC / DC converter having any of the ninth to eleventh configurations described above, both the first ramp signal and the second ramp signal may have a sawtooth waveform that repeats rising or falling and resetting in a common switching period (twelfth configuration).

[0263] Also, the DC / DC converter having any of the ninth to twelfth configurations described above may further have an error amplifier that generates an error signal according to the difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage, and a differential amplifier that generates the first analog signal according to the difference between the error signal and the current sense signal (thirteenth configuration).

[0264] Also, the DC / DC converter having the thirteenth configuration described above may further have a clamper that limits the error signal to be equal to or less than a predetermined upper limit value or equal to or greater than a predetermined lower limit value (fourteenth configuration).

[0265] Also, the DC / DC converter having the thirteenth or fourteenth configuration described above may further have a light load detection comparator that compares the error signal with a predetermined threshold value and controls the operability of the switch output stage (fifteenth configuration).

[0266] In addition, the DC / DC converter disclosed in this specification includes an oscillator that generates a triangular-wave lamp signal with equal up / down slew rates, a comparator that compares an analog signal with the lamp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing corresponding to a timing control signal, and a timing control unit that generates the timing control signal so that the sampling of the coil current is performed at a timing when the lamp signal reaches a peak value or a bottom value. By performing output feedback control in a current mode control method using the current sense signal, a configuration (16th configuration) is adopted to generate a desired output voltage from an input voltage.

[0267] In the DC / DC converter having the 16th configuration described above, it is preferable that the oscillator includes a capacitor connected between an output terminal and a fixed potential terminal of the lamp signal, a first current source that generates a predetermined charging current, a second current source that generates a discharging current equal to the charging current, a switch that switches whether to charge the capacitor with the charging current or discharge it with the discharging current according to a clock signal, and a clock signal generation unit that compares the lamp signal with the peak value and the bottom value to generate the clock signal (17th configuration).

[0268] In addition, in the DC / DC converter having the 17th configuration described above, it is preferable that the timing control unit generates the timing control signal using the clock signal (18th configuration).

[0269] In addition, the DC / DC converter disclosed in this specification includes an oscillator that generates a sawtooth-shaped ramp signal and an inverted ramp signal that have opposite polarities to each other and repeat rising, falling, and resetting in a common switching period, a first comparator and a second comparator that respectively compare an analog signal with the ramp signal and the inverted ramp signal to generate a first comparison signal and a second comparison signal, a logic operation unit that generates a control signal for a switch output stage by performing a logic operation using the first comparison signal and the second comparison signal, a current detection unit that generates a current sense signal by sampling a coil current of the switch output stage at a timing according to a timing control signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the reset timing of the ramp signal and the inverted ramp signal. By performing output feedback control in a current mode control method using the current sense signal, a configuration (19th configuration) is adopted to generate a desired output voltage from an input voltage.

[0270] In the DC / DC converter having the 19th configuration described above, it is preferable that the oscillator includes a first capacitor connected between an output terminal of the ramp signal and an application terminal of a first voltage, a second capacitor connected between an application terminal of a second voltage different from the first voltage and an output terminal of the inverted ramp signal, a first current source and a second current source that respectively generate charging currents for the first capacitor and the second capacitor, a first switch and a second switch that respectively discharge the first capacitor and the second capacitor according to a clock signal, and a clock signal generation unit that compares the ramp signal with the second voltage to generate the clock signal (20th configuration).

[0271] In the DC / DC converter having the 20th configuration described above, it is preferable that the timing control unit has a configuration (21st configuration) that generates the timing control signal using the clock signal.

[0272] Further, in the DC / DC converter having any one of the configurations of the above-described 19th to 21st, it is preferable that the switch output stage has a configuration (22nd configuration) in which an on period is set when the analog signal is higher than at least one of the ramp signal and the inverted ramp signal, and an off period is set when the analog signal is lower than both the ramp signal and the inverted ramp signal.

[0273] Further, in the DC / DC converter having any one of the configurations of the above-described 19th to 21st, it is also possible to have a configuration (23rd configuration) in which the switch output stage has an on period when the analog signal is higher than both the ramp signal and the inverted ramp signal, and an off period when the analog signal is lower than at least one of the ramp signal and the inverted ramp signal.

[0274] Further, the DC / DC converter having any one of the configurations of the above-described 16th to 23rd preferably has a configuration (24th configuration) further including an error amplifier that generates an error signal corresponding to a difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage, and a differential amplifier that generates the analog signal according to a difference between the error signal and the current sense signal.

[0275] Further, the DC / DC converter having the 24th configuration preferably has a configuration (25th configuration) further including a clamper that limits the error signal to be equal to or lower than a predetermined upper limit value or equal to or higher than a predetermined lower limit value.

[0276] Further, the DC / DC converter having the 24th or 25th configuration preferably has a configuration (26th configuration) further including a light load detection comparator that compares the error signal with a predetermined threshold value and controls whether the switch output stage operates or not.

[0277] In addition, the DC / DC converter disclosed in this specification samples the coil current of the switch output stage at the center timing of the on-period or off-period of the switch output stage, and performs output feedback control in a current mode control method using a current sense signal corresponding to the sampled value, thereby generating a desired output voltage from the input voltage (Configuration 27).

[0278] Note that the DC / DC converter having the above Configuration 27 may be configured to perform output feedback control in a current mode control method by inputting the current sense signal or a signal obtained by performing a predetermined arithmetic process on the current sense signal and a signal having error information of the output voltage to an amplifier or a comparator (Configuration 28).

[0279] In addition, the DC / DC converter having the above Configuration 27 may be configured to perform output feedback control in a current mode control method by adding or subtracting the current sense signal and a signal having error information of the output voltage and inputting the result to an amplifier or a comparator (Configuration 29).

[0280] In addition, the DC / DC converter having the above Configuration 27 may be configured to monitor the current sense signal and control the operability of the switch output stage according to the comparison result between the current sense signal and a predetermined threshold value (Configuration 30).

[0281] In addition, the DC / DC converter having the above Configuration 28 or 29 may be configured to perform overcurrent protection or reverse current protection of the coil current by clamping a signal added or subtracted from the current sense signal, or a signal differentiated or compared with the current sense signal by the amplifier or the comparator (Configuration 31).

[0282] Further, the DC / DC converter having the above-described 28th or 29th configuration may be configured to monitor a signal that is added to or subtracted from the current sense signal, or a signal that is differentiated or compared with the current sense signal by the amplifier or the comparator, and control the operability of the switch output stage according to the comparison result with a predetermined threshold value (32nd configuration).

[0283] Further, the DC / DC converter having any one of the above-described 27th to 32nd configurations may be configured to include a current detection unit that generates the current sense signal by sampling the coil current at a timing according to a timing control signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the center timing of the on period or the off period of the switch output stage (33rd configuration).

[0284] Further, the DC / DC converter having the above-described 33rd configuration may be configured to include an error amplifier that generates an error signal according to the difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage, an oscillator that generates a ramp signal at a predetermined switching period, a differential amplifier that generates an analog signal according to the difference between the error signal and the current sense signal, a comparator that compares the analog signal and the ramp signal to generate a comparison signal, and a driver that generates a drive signal for the switch output stage according to the comparison signal (34th configuration).

[0285] Further, the DC / DC converter having the above-described 34th configuration may be configured to further include a clamper that limits the error signal to be equal to or less than a predetermined upper limit value or equal to or greater than a predetermined lower limit value (35th configuration).

[0286] Further, the DC / DC converter having the above-described 34th or 35th configuration may be configured to further include a light load detection comparator that compares the error signal with a predetermined threshold value and controls the operability of the switch output stage (36th configuration).

[0287] In addition, the DC / DC converter disclosed in this specification includes a comparator that compares an analog signal with a first ramp signal to generate a control signal for a switch output stage, a current detection unit that generates a current sense signal by sampling the coil current of the switch output stage at a timing according to a timing control signal, and a timing control unit that generates the timing control signal so that the coil current is sampled at the center timing of the on period or the off period of the switch output stage using a second ramp signal having a slew rate twice that of the first ramp signal. By performing output feedback control in a current mode control method using the current sense signal, a configuration (37th configuration) is adopted to generate a desired output voltage from an input voltage.

[0288] In the DC / DC converter having the 37th configuration, it is preferable that the timing control unit has a configuration (38th configuration) that compares the analog signal with the second ramp signal to generate the timing control signal.

[0289] In addition, in the DC / DC converter having the 38th configuration, both the first ramp signal and the second ramp signal repeat rising and resetting in a common switching period, and the switch output stage has a configuration (39th configuration) in which it is in an on period when the analog signal is higher than the first ramp signal and in an off period when the analog signal is lower than the first ramp signal.

[0290] In addition, in the DC / DC converter having the 38th configuration, both the first ramp signal and the second ramp signal repeat rising and resetting in a common switching period, and the switch output stage may have a configuration (40th configuration) in which it is in an off period when the analog signal is higher than the first ramp signal and in an on period when the analog signal is lower than the first ramp signal.

[0291] Also, in the DC / DC converter having the above-described 38th configuration, both the first lamp signal and the second lamp signal repeat decrease and reset in a common switching period, and the switch output stage has an on period when the analog signal is higher than the first lamp signal and an off period when the analog signal is lower than the first lamp signal (41st configuration).

[0292] Also, in the DC / DC converter having the above-described 38th configuration, the second lamp signal may have a configuration (42nd configuration) in which it starts to change with a delay of 1 / 2 of the switching period from the start point of change of the first lamp signal.

[0293] Also, in the DC / DC converter having any one of the above-described 38th to 42nd configurations, the timing control unit may have a configuration (43rd configuration) in which it compares an equivalent analog signal having information equivalent to the analog signal with the second lamp signal instead of the analog signal.

[0294] Also, the DC / DC converter having any one of the above-described 37th to 43rd configurations preferably has an error amplifier that generates an error signal according to the difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage, and a differential amplifier that generates the analog signal according to the difference between the error signal and the current sense signal (44th configuration).

[0295] Also, the DC / DC converter having the above-described 44th configuration preferably has a clamper that limits the error signal to be equal to or less than a predetermined upper limit value or equal to or greater than a predetermined lower limit value (45th configuration).

[0296] Also, the DC / DC converter having the above-described 44th or 45th configuration preferably has a light load detection comparator that compares the error signal with a predetermined threshold value to control the operation availability of the switch output stage (46th configuration).

[0297] <Other Modification Examples> In the above-described embodiment, a buck or buck-boost DC / DC converter has been described as an example. However, the configuration of the present invention is not limited to this, and it can also be applied to DC / DC converters adopting other output formats (boost type, inversion type).

[0298] Moreover, various technical features disclosed in this specification can be variously modified within the scope not departing from the gist of the technical creation in addition to the above-described embodiment. For example, the mutual substitution between bipolar transistors and MOS field effect transistors and the logical level inversion of various signals are arbitrary. That is, the above-described embodiment should be considered as illustrative in all respects and not restrictive, and the technical scope of the present invention is not limited to the above-described embodiment, but should be understood to include all modifications belonging to the meaning and scope equivalent to the claims.

Industrial Applicability

[0299] The DC / DC converter disclosed in this specification can be used as a power supply means for various applications.

Explanation of Signs

[0300] 1 DC / DC converter 10 Switch output stage 11 Output transistor (for buck) 12 Synchronous rectifier transistor (for buck) 13 Coil 14 Capacitor 15 Output transistor (for boost) 16 Synchronous rectifier transistor (for boost) 20 Feedback voltage generation unit 21, 22 Resistors 30 Error amplifier 40 Phase compensation unit 41 Resistor 42 Capacitor 50 Current detection unit 60 Differential amplifier 70 Oscillator Current sources 71a, 71b, 71c Switches 72a, 72b, 72c, 72d Capacitors 73a, 73b, 73c Comparators 74a, 74b Resistors 75a, 75b, 75c Selector 76 Delay unit 77 PWM comparator 80 Driver 90 NAND gate 91 AND gate 92 Clamper 100 Light load detection comparator 110 Timing control unit 120 First internal signal generation unit 121 Second internal signal generation unit 122 Comparator 123 Arithmetic units 130, 140 Average value generation unit 150 PWM comparator 160 OR gate 170 AND gate 180 Logic operation unit 190 NAND gate 191 OR gate 192 P-channel MOS field effect transistors P1, P2 N-channel MOS field effect transistor N1 Operational amplifier AMP1 Resistors R1, R11, R12 Capacitors C0, C1, C2 Current sources CS1, CS2, CS3, CS4 Switches SW1, SW2, SW3 Pnp bipolar transistor Qp Npn bipolar transistor Qn

Claims

1. an oscillator for generating a ramp signal and an inverted ramp signal of a sawtooth waveform that have opposite polarities and repeat rising or falling and resetting in a common switching period; a first comparator and a second comparator for comparing an analog signal with the ramp signal and the inverted ramp signal, respectively, to generate a first comparison signal and a second comparison signal; a logic operation unit that generates a step-down control signal and a step-up control signal for a step-up / step-down type switch output stage by performing a logic operation using the first comparison signal and the second comparison signal; a current detection unit that generates a current sense signal by sampling a coil current of the switch output stage at a timing corresponding to a timing control signal; a timing control unit that generates the timing control signal so that sampling of the coil current is performed at reset timings of the ramp signal and the inverted ramp signal; having the step-down control signal is used for on / off control of a first output transistor and a first synchronous rectifier transistor for step-down included in the switch output stage, the boost control signal is used for on / off control of a second boost output transistor and a second synchronous rectification transistor included in the switch output stage, A DC / DC converter that generates a desired output voltage from an input voltage by performing output feedback control of a current mode control system using the current sense signal.

2. The switch output stage comprises: During a step-down operation, the second output transistor is always off, the second synchronous rectifier transistor is always on, and the first output transistor and the first synchronous rectifier transistor are complementarily turned on / off; During a boost operation, the first output transistor is always on, the first synchronous rectifier transistor is always off, and the second output transistor and the second synchronous rectifier transistor are complementarily turned on / off.

2. The DC / DC converter according to claim 1.

3. 3. The DC / DC converter according to claim 1, wherein the logic operation unit extracts a state in which the analog signal is lower than both of the ramp signal and the inverted ramp signal, and a state in which the analog signal is higher than both of the ramp signal and the inverted ramp signal, and generates the step-down control signal based on one extraction result, and generates the step-up control signal based on the other extraction result.

4. The switch output stage comprises: During a step-down operation, an on-period occurs when the analog signal is higher than at least one of the ramp signal and the inverted ramp signal, and an off-period occurs when the analog signal is lower than both the ramp signal and the inverted ramp signal; During a boost operation, an on-period occurs when the analog signal is higher than both the ramp signal and the inverted ramp signal, and an off-period occurs when the analog signal is lower than at least one of the ramp signal and the inverted ramp signal.

4. The DC / DC converter according to claim 1.

5. The reset timing of the ramp signal and the inverted ramp signal is During the step-down operation, the timing coincides with the center timing of the on-period, During boost operation, the timing coincides with the center timing of the off period.

5. The DC / DC converter according to claim 4.

6. 6. The DC / DC converter according to claim 1, further comprising: an error amplifier that generates an error signal according to a difference between the output voltage or a feedback voltage corresponding thereto, and a predetermined reference voltage; and a differential amplifier that generates the analog signal according to a difference between the error signal and the current sense signal.

7. 7. The DC / DC converter according to claim 6, further comprising a clamper for limiting the error signal to a value equal to or lower than a predetermined upper limit value or equal to or higher than a predetermined lower limit value.

8. 8. The DC / DC converter according to claim 6, further comprising a light load detection comparator for comparing the error signal with a predetermined threshold value to control whether or not the switch output stage is operable.

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