Stack structure and manufacturing method thereof, capacitor using the same, transistor using the same, dye-sensitized solar cell using the same and architectural film for window glass coating using the same

Abstract

To provide a manufacturing method of a stack structure which improves interface characteristics between a channel layer and a dielectric layer, a stack structure and a transistor.SOLUTION: A manufacturing method of a stack structure includes the steps of: preparing a substrate; forming a two-dimensional semiconductor material on the substrate; and oxidizing the two-dimensional semiconductor material using oxygen plasma to form a dielectric layer including a high dielectric (high-k) material containing any one of Bi2SeO5, a hafnium oxide (HfOx, x>0) and a zirconium oxide (ZrOx, x>0). The stack structure may be easily applied to a MOS capacitor, a field effect transistor (FET), an impact ionization super-tilt switching device, a dye-sensitized solar cell, an architectural film (particularly, a film used for window coating), and the like.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a stack structure and a method for manufacturing the same, and more specifically, to a stack structure having a structure in which a plurality of thin films are stacked and a method for manufacturing the same.

[0002] The stack structure and the method for manufacturing the same according to the present invention are applied to MOS capacitors, ultra-low power switching elements, dye-sensitized solar cells, and architectural films for window glass coats.

Background Art

[0003] Since the development of field effect transistors (FETs), semiconductor / dielectric gate stack structures have served as basic building blocks for controlling the overall current flow along the surface of conductive channels for efficient information processing and computing applications. However, as the geometric scaling of silicon (Si)-based semiconductor devices continues, problems have arisen in that the controllability of the gate stack is lost and the electrical performance generally deteriorates.

[0004] Two-dimensional (2D) van der Waals (vdW) semiconductor materials have unique low dielectric constants, thin thicknesses, and high charge mobilities, and thus can effectively suppress the specific problems of silicon (Si)-based semiconductor devices. They are attracting attention as promising material candidates to replace silicon (Si). In particular, for two-dimensional van der Waals semiconductor materials, the technology of integrating high-k dielectrics can improve the controllability of the gate stack through a thin equivalent oxide thickness and efficient capacitive coupling. Therefore, the development of high-quality high-k gate stacks based on two-dimensional van der Waals semiconductor materials is one of the core challenges for the hyper-connected society of the fourth industrial revolution. As a result, various studies on high-k gate stacks based on two-dimensional semiconductor materials have been conducted for several years.

[0005] The most commonly used approach to form a gate stack having a two-dimensional semiconductor / dielectric structure is the atomic layer deposition (ALD) method of directly depositing a dielectric on a two-dimensional semiconductor layer. However, unlike existing silicon (Si)-based technologies, the atomic layer deposition method (ALD) has a problem that current leakage easily occurs when the equivalent oxide thickness (EOT) is low by causing non-uniform nucleation and island formation in two-dimensional semiconductors (Kim, H. G. & Lee, H. B. R., “Atomic layer deposition on 2D materials”, April 25, 2017, Chem. Mater. 29, 3809-3826).

[0006] To overcome the problems of such an atomic layer deposition method, the introduction of a buffer layer such as perylene tetracarboxylic dianhydride has been proposed (Zhang, X. et al., “Van der Waals‐Interface‐Dominated All‐2D Electronics”, November 10, 2022, Adv. Mater. 2207966), but there is a problem that effective EOT scaling is not achieved by the buffer layer.

[0007] Therefore, in order to manufacture an electronic device having higher electrical characteristics and reliability and being drivable with low power, an approach of a method different from the above-described method is required.

Prior Art Documents

Non-Patent Documents

[0008]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0009] An object of the present invention is to provide a stack structure in which a channel layer containing a two-dimensional semiconductor material and a dielectric layer containing a high-k (high dielectric constant) material are laminated, and a method for manufacturing the same.

[0010] Another object of the present invention is to provide a stack structure in which the interface characteristics between the channel layer and the dielectric layer are improved, and a method for manufacturing the same.

[0011] Still another object of the present invention is to provide a stack structure having a subthreshold swing (SS) value close to the Boltzmann limit at room temperature, and a method for manufacturing the same.

[0012] Still another object of the present invention is to provide a stack structure in which it is easy to embody a low-power device, and a method for manufacturing the same.

[0013] Still another object of the present invention is to provide a capacitor to which the stack structure is applied.

[0014] Still another object of the present invention is to provide a transistor to which the stack structure is applied.

[0015] Still another object of the present invention is to provide a solar cell to which the stack structure is applied.

[0016] Still another object of the present invention is to provide a building film to which the stack structure is applied.

[0017] The object of the present invention is not limited to the above.

Means for Solving the Problems

[0018] To achieve the above object, the present invention provides a method for manufacturing a stack structure.

[0019] The method for manufacturing the stack structure includes a step of preparing a substrate, a step of forming a two-dimensional (2D) semiconductor material layer containing Bi2O2Se on the substrate, and a step of oxidizing the two-dimensional semiconductor material layer to form a high-k material layer containing Bi2SeO5.

[0020] By the oxidation method of the two-dimensional semiconductor material layer, the crystal structure of Bi2SeO5 contained in the high-k material layer is controlled.

[0021] When the two-dimensional semiconductor material layer is oxidized by oxygen plasma (O2 plasma), the high-k material layer containing amorphous Bi2SeO5 is formed.

[0022] When the two-dimensional semiconductor material layer is naturally oxidized, the high-k material layer containing crystalline Bi2SeO5 is formed.

[0023] When the two-dimensional semiconductor material layer is oxidized by an oxidation method using ultraviolet (UV) rays, the high-k material layer containing single crystalline β-Bi2SeO5 is formed.

[0024] The manufacturing method of the stack structure includes the steps of preparing a substrate, forming a channel layer containing a two-dimensional (2D) semiconductor material on the substrate, and oxidizing the channel layer to form a dielectric layer containing a high-k material.

[0025] When the channel layer is oxidized, one region of the channel layer is converted into the dielectric layer containing the high-k material, and the other region of the channel layer remains as the channel layer containing the 2D semiconductor material.

[0026] The high-k material is formed by oxidizing the 2D semiconductor material.

[0027] The dielectric layer is formed by oxidizing the channel layer with oxygen plasma.

[0028] The thickness of the dielectric layer is controlled by the time the channel layer is exposed to the oxygen plasma.

[0029] To achieve the above object, the present invention provides a stack structure.

[0030] The stack structure includes a channel layer containing a two-dimensional (2D) semiconductor material and a dielectric layer disposed on the channel layer, and the dielectric layer contains a high-k material formed by oxidizing the 2D semiconductor material.

[0031] The 2D semiconductor material includes any one of Bi2O2Se, hafnium diselenide (HfSe2), hafnium disulfide (HfS2), and zirconium diselenide (ZrSe2).

[0032] The high-k material includes any one of Bi2SeO5, hafnium oxide (HfO x , x>0), and zirconium oxide (ZrO x , x>0).

[0033] An interface is formed between the channel layer and the dielectric layer.

[0034] To achieve the above object, the present invention provides a transistor.

[0035] The transistor includes a source electrode and a drain electrode which are spaced apart from each other, and a channel layer which is disposed on the source electrode and the drain electrode such that one side thereof is in contact with the source electrode and the other side is in contact with the drain electrode, and includes a two-dimensional (2D) semiconductor material, and a dielectric layer which is disposed on the channel layer and includes a high-k material in which the two-dimensional semiconductor material is oxidized, and a gate electrode which is disposed on the dielectric layer.

[0036] The dielectric layer is formed by oxidizing a part of the channel layer with oxygen plasma, and the electrical characteristics are controlled by the power of the oxygen plasma provided to the channel layer.

Advantages of the Invention

[0037] The method for manufacturing a stack structure according to the present invention includes a step of preparing a substrate, a step of forming a channel layer including a two-dimensional semiconductor material on the substrate, and a step of oxidizing the channel layer with oxygen plasma to form a dielectric layer having a high-k material. Thereby, the interface characteristics between the channel layer and the dielectric layer are improved.

[0038] Thereby, an electronic device (for example, a field effect transistor or the like) to which the stack structure is applied can have a subthreshold swing (SS) value close to the Boltzmann limit at room temperature, so that low-power driving can be easily performed.

Brief Description of the Drawings

[0039]

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Embodiments for Carrying Out the Invention

[0040] Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail. However, the technical idea of the present invention is not limited to the embodiments described herein and can be embodied in other forms. The embodiments introduced here are provided so that the disclosed content is thorough and complete, and that the idea of the present invention is sufficiently conveyed to those skilled in the art.

[0041] In this specification, when it is stated that a certain component is on another component, it means that it can be directly formed on the other component or a third component can be sandwiched between them. Also, in the drawings, shapes and sizes are exaggerated for an effective explanation of the technical content.

[0042] Also, in various embodiments of this specification, terms such as first, second, third, etc. are used to describe various components, but these components should not be limited by such terms. These terms are merely used to distinguish one component from another. Thus, what is referred to as the first component in one embodiment can also be referred to as the second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiments. Also, in this specification, "and / or" is used to mean including at least one of the components listed before and after.

[0043] In the specification, singular expressions also include plural expressions unless the context clearly indicates otherwise. Also, terms such as "including" or "having" are intended to specify the presence of the features, numbers, steps, components, or combinations thereof described in the specification, and should not be understood as excluding the presence or possibility of addition of one or more other features, numbers, steps, components, or combinations thereof. Also, in this specification, "connected" is used to mean including both indirectly connecting a plurality of components and directly connecting them.

[0044] Also, when explaining the present invention, if it is determined that a detailed explanation of related known functions or configurations makes the gist of the present invention unnecessarily unclear, that detailed explanation will be omitted.

[0045] (Stack structure and method for manufacturing the same) FIG. 1 is a flowchart for explaining a method of manufacturing a stack structure according to an embodiment of the present invention, and FIGS. 2 and 3 are schematic diagrams for explaining a manufacturing process of the stack structure according to an embodiment of the present invention.

[0046] As shown in FIGS. 1 to 3, a substrate (SB) is prepared (S110). According to one embodiment, the substrate (SB) is a silicon semiconductor substrate. According to another embodiment, the substrate (SB) is a compound semiconductor substrate. According to another embodiment, the substrate (SB) is a glass substrate. Also, according to another embodiment, the substrate (SB) is a plastic substrate. The type of the substrate (SB) is not limited.

[0047] A channel layer 100 containing a two-dimensional semiconductor material is formed on the substrate (SB) (S120). According to one embodiment, the two-dimensional semiconductor material includes any one of Bi2O2Se, hafnium diselenide (HfSe2), hafnium disulfide (HfS2), and zirconium diselenide (ZrSe2). According to one embodiment, the channel layer 100 is formed using various growth methods such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) using a precursor. According to another embodiment, the channel layer 100 can also be formed by transferring a two-dimensional semiconductor material peeled from a bulk onto the substrate (SB). The formation method of the channel layer 100 is not limited.

[0048] Oxidize the channel layer 100 to form a dielectric layer 200 containing a high-k material (130). According to one embodiment, as the channel layer 100 oxidizes, one region of the channel layer 100 is converted into the dielectric layer 200 containing the high-k material, and the other region of the channel layer 100 remains as the channel layer 100 containing the two-dimensional semiconductor material. That is, when the channel layer 100 oxidizes, the oxidized region in the channel layer 100 is converted into the high-k material in which the two-dimensional semiconductor material is oxidized, and the non-oxidized region remains as the two-dimensional semiconductor material. Thereby, the high-k material can be defined as the material in which the two-dimensional semiconductor material is oxidized.

[0049] According to one embodiment, the high-k material includes any one of Bi2SeO5, hafnium oxide (HfO x , x>0), and zirconium oxide (ZrO x , x>0). More specifically, when the two-dimensional semiconductor material includes Bi2O2Se, as the two-dimensional semiconductor material oxidizes, Bi2O2Se is converted into the Bi2SeO5 high-k material. In contrast, when the two-dimensional semiconductor material includes hafnium diselenide (HfSe2) or hafnium disulfide (HfS2), as the two-dimensional semiconductor material oxidizes, hafnium diselenide (HfSe2) or hafnium disulfide (HfS2) is converted into the hafnium oxide (HfO x , x>0) high-k material. In contrast, when the two-dimensional semiconductor material includes zirconium diselenide (ZrSe2), as the two-dimensional semiconductor material oxidizes, zirconium diselenide (ZrSe2) is converted into the zirconium oxide (ZrO x , x>0) high-k material.

[0050] According to one embodiment, the channel layer 100 is oxidized by any one of plasma oxidation, native oxidation, and oxidation methods using ultraviolet (UV) light. Further, the channel layer 100 can be applied with different oxidation methods depending on the type of the two-dimensional semiconductor material.

[0051] Specifically, when the two-dimensional semiconductor material contains Bi2O2Se, the channel layer 100 is oxidized by any one of plasma oxidation, native oxidation, and oxidation methods using ultraviolet (UV) light. Further, when the two-dimensional semiconductor material contains Bi2O2Se, the crystal structure of the Bi2SeO5 high-dielectric substance formed by the oxidation of Bi2O2Se is controlled by the oxidation method of the channel layer 100. For example, when the channel layer 100 containing Bi2O2Se is oxidized by oxygen plasma (O2 plasma), an amorphous Bi2SeO5 high-dielectric substance is formed. In contrast, when the channel layer 100 containing Bi2O2Se is oxidized by native oxidation, a crystalline Bi2SeO5 high-dielectric substance is formed. In contrast, when the channel layer 100 containing Bi2O2Se is oxidized by an oxidation method using ultraviolet light (for example, UV-assisted intercalative oxidation), a single crystalline β-Bi2SeO5 high-dielectric substance is formed.

[0052] When the two-dimensional semiconductor material contains zirconium diselenide (ZrSe2), the channel layer 100 is oxidized by native oxidation to form a zirconium oxide (ZrO x , x>0) high-dielectric substance.

[0053] When the two-dimensional semiconductor material contains hafnium diselenide (HfSe2) or hafnium disulfide (HfS2), the channel layer 100 is oxidized by native oxidation or oxygen plasma (O2 plasma) to form hafnium oxide (HfO x , x>0).

[0054] As described above, various oxidation methods can be applied depending on the type of the two-dimensional semiconductor material to form the high dielectric constant material. However, except for the case where hafnium diselenide (HfSe2) is oxidized with oxygen plasma to form hafnium oxide (HfO2), the interface characteristics between the channel layer 100 and the dielectric layer 200 are low, and the subthreshold swing (SS) value increases, resulting in a problem that it is difficult to implement a low-power device.

[0055] That is, the Bi2SeO5 / Bi2O2Se stack structure formed by plasma oxidation, natural oxidation, and an oxidation method using ultraviolet light, the ZrO x / ZrSe2 stack structure formed by an oxidation method using natural oxidation, the HfO x / HfSe2 stack structure formed by an oxidation method using natural oxidation, and the HfO x / HfS2 stack structure formed by oxidation methods using natural oxidation and plasma oxidation have low interface characteristics between the channel layer 100 and the dielectric layer 200, and the subthreshold swing (SS) value increases, resulting in a problem that it is difficult to implement a low-power device.

[0056] On the other hand, the HfO2 / HfSe2 stack structure formed by a plasma oxidation (for example, O2 plasma oxidation) method has high interface characteristics between the channel layer 100 and the dielectric layer 200, so that it can have a subthreshold swing (SS) value close to the Boltzmann limit at room temperature, and it is easy to implement a low-power device. Hereinafter, the HfO2 / HfSe2 stack structure formed by a plasma oxidation (for example, O2 plasma oxidation) method will be described in more detail.

[0057] FIG. 4 to FIG. 6 are schematic diagrams for explaining the manufacturing process of the HfO2 / HfSe2 stack structure, FIG. 7 is a schematic diagram for more specifically explaining the manufacturing mechanism of the HfO2 / HfSe2 stack structure, FIG. 8 is a schematic diagram for explaining the HfSe2 oxidation process at an appropriate oxygen concentration, and FIG. 9 is a schematic diagram for explaining the HfSe2 oxidation process at an excessive oxygen concentration.

[0058] As shown in FIGS. 4 to 7, when an oxidation process by oxygen plasma is performed on the channel layer 100 containing hafnium diselenide (HfSe2), layer-by-layer oxidation, that is, layer-by-layer oxidation, is performed.

[0059] More specifically, when an oxidation process by oxygen plasma is performed on the channel layer 100, oxygen atoms (O) penetrate into the channel layer 100, and one of the oxygen atoms (O) that penetrate into the channel layer 100 can replace the selenium atom (Se) of the hafnium diselenide (HfSe2) without a further substitution energy barrier. In addition, the oxygen atom (O) that has replaced the selenium atom (Se) can form a covalent bond with three hafnium atoms (Hf). As a result, hafnium oxide (HfO2) formed by oxidizing hafnium diselenide (HfSe2) can be formed. That is, a region of the channel layer 100 containing hafnium diselenide (HfSe2) is converted into a dielectric layer 200 containing the hafnium oxide (HfO2). Thereafter, as shown in FIGS. 5 and 7(a), the region of the dielectric layer 200 sequentially increases due to the continuously penetrated oxygen atoms (O). That is, due to the continuously penetrated oxygen atoms (O), the thickness of the dielectric layer 200 sequentially increases, and the thickness of the channel layer 100 sequentially decreases.

[0060] On the one hand, as shown in FIGS. 5 and 7(b), the substituted selenium atoms (Se) generated by the substituted oxygen atoms (O) replacing the selenium atoms (Se) of hafnium diselenide (HfSe2) diffuse into the oxygen vacancies (Vo) in the dielectric layer 200 and are then discharged outside the dielectric layer 200 through the oxygen vacancies in the dielectric layer 200. Further, the substituted selenium atoms (Se) form an interface between the channel layer 100 and the dielectric layer 200 before diffusing into the oxygen vacancies in the dielectric layer 200. Thereby, the channel layer 100 and the dielectric layer 200 are prevented from merging by the interface formed by the substituted selenium atoms (Se). Thereby, layer-by-layer oxidation by continuously infiltrated oxygen atoms (O) can be easily performed.

[0061] However, the formation of the interface by the substituted selenium atoms (Se) is performed under the condition of an appropriate oxygen concentration as shown in FIG. 8. That is, when hafnium diselenide (HfSe2) is oxidized with oxygen plasma, layer-by-layer oxidation can be easily performed by maintaining appropriate oxygen concentration conditions, and a HfO2 / HfSe2 stack structure in which hafnium diselenide (HfSe2) and hafnium oxide (HfO2) are clearly distinguished can be manufactured. In contrast, when hafnium diselenide (HfSe2) is oxidized under excessive oxygen concentration conditions, as shown in FIG. 9, since the interface formation by the substituted selenium atoms (Se) does not occur, a problem occurs in that the channel layer 100 and the dielectric layer 200 merge. That is, when hafnium diselenide (HfSe2) is oxidized under excessive oxygen concentration conditions, hafnium diselenide (HfSe2) and hafnium oxide (HfO2) are not clearly distinguished, and a problem occurs in that hafnium diselenide (HfSe2) and hafnium oxide (HfO2) are mixed.

[0062] According to one embodiment, the oxygen concentration condition is controlled by the power of the oxygen plasma provided to hafnium diselenide (HfSe2). More specifically, the power of the oxygen plasma provided to hafnium diselenide (HfSe2) is controlled to be more than 7W and less than 20W. Different from this, when the power of the oxygen plasma is controlled to be 20W or more, due to the excessive oxygen concentration, hafnium diselenide (HfSe2) and hafnium oxide (HfO2) cannot be clearly distinguished, and there is a problem that hafnium diselenide (HfSe2) and hafnium oxide (HfO2) are mixed. Also, when the power of the oxygen plasma is controlled to be 7W or less, the minimum penetration of oxygen atoms (O) for forming hafnium oxide (HfO2) does not occur, so the oxidation of hafnium diselenide (HfSe2) does not occur, and there is a problem that hafnium oxide (HfO2) is not formed.

[0063] As a result, the HfO2 / HfSe2 stack structure according to the embodiment of the present invention is manufactured by oxidizing hafnium diselenide (HfSe2) with oxygen plasma, and during the oxidation process, an interface is formed by the substituted selenium atoms (Se) between the channel layer 100 (HfSe2) and the dielectric layer 200 (HfO2), thereby improving the interface characteristics between the channel layer 100 (HfSe2) and the dielectric layer 200 (HfO2). Accordingly, an electronic device using the HfO2 / HfSe2 stack structure according to the embodiment can have a subthreshold swing value close to the Boltzmann limit at room temperature, so that a low-power device can be easily realized.

[0064] The stack structure and its manufacturing method according to the embodiment of the present invention have been described above. Hereinafter, various application examples of the stack structure according to the embodiment of the present invention will be described.

[0065] (Capacitor applying the HfO2 / HfSe2 stack structure) FIG. 10 is a flowchart for explaining a method of manufacturing a capacitor to which an HfO2 / HfSe2 stack structure according to an embodiment of the present invention is applied, and FIG. 11 is a schematic diagram for explaining a capacitor to which an HfO2 / HfSe2 stack structure according to an embodiment of the present invention is applied.

[0066] As shown in FIGS. 10 and 11, after preparing a substrate (SB) (S210), a lower electrode (BE) is formed on the substrate (SB) (S220). According to one embodiment, the substrate (SB) is a silicon semiconductor substrate. According to another embodiment, the substrate (SB) is a compound semiconductor substrate. According to still another embodiment, the substrate (SB) is a glass substrate. According to still another embodiment, the substrate (SB) is a plastic substrate. The type of the substrate (SB) is not limited.

[0067] A channel layer 100 containing a two-dimensional semiconductor material is formed on the lower electrode (BE) (S230). The two-dimensional semiconductor material includes hafnium diselenide (HfSe2). According to one embodiment, the channel layer 100 is formed by dry-transferring hafnium diselenide (HfSe2) flakes mechanically exfoliated from a bulk crystal using PDMS (polydimethylsiloxane).

[0068] The channel layer 100 is oxidized to form a dielectric layer 200 containing a high-k material (S240). More specifically, the channel layer 100 containing hafnium diselenide (HfSe2) is oxidized with oxygen plasma to convert a partial region of the channel layer 100 into hafnium oxide (HfO2). That is, a region where hafnium diselenide (HfSe2) is oxidized and converted into hafnium oxide (HfO2) is defined as the dielectric layer 200.

[0069] Finally, an upper electrode (TE) is formed on the dielectric layer 200 (S250). Thereby, a MOS capacitor to which an HfO2 / HfSe2 stack structure is applied can be manufactured.

[0070] In the MOS capacitor according to the above embodiment, hafnium diselenide (HfSe2) included in the channel layer 100 exhibits N-type semiconductor characteristics, shows behaviors that do not vary significantly between the depletion region and the accumulation region over various frequency ranges (1 kHz to 1 MHz), and can have low-level interface traps (interface traps between the channel layer and the dielectric layer). Also, the MOS capacitor according to the above embodiment has a constant dielectric constant (k) of 23 over various frequency ranges (1 kHz to 1 MHz). That is, the MOS capacitor according to the above embodiment can be easily applied to low-power and high-frequency electronic devices by virtue of having stable high-dielectric-constant dielectric properties.

[0071] (Field-Effect Transistor Applying HfO2 / HfSe2 Stack Structure) FIG. 12 is a flowchart for explaining a method of manufacturing a field-effect transistor applying an HfO2 / HfSe2 stack structure according to an embodiment of the present invention, and FIG. 13 is a schematic diagram for explaining a field-effect transistor applying an HfO2 / HfSe2 stack structure according to an embodiment of the present invention.

[0072] As shown in FIGS. 12 and 13, a source electrode (S) and a drain electrode (D) spaced apart from each other are prepared (S310). Thereafter, a channel layer 100 containing a two-dimensional semiconductor material is formed on the source electrode (S) and the drain electrode (D) (S320). More specifically, the channel layer 100 is formed such that one side contacts the source electrode (S) and the other side contacts the drain electrode (D). Also, the two-dimensional semiconductor material includes hafnium diselenide (HfSe2). According to one embodiment, the channel layer 100 is formed by a method of dry-transferring hafnium diselenide (HfSe2) flakes mechanically exfoliated from a bulk crystal using PDMS.

[0073] The channel layer 100 is oxidized to form a dielectric layer 200 containing a high-k material (S330). More specifically, the channel layer 100 containing hafnium diselenide (HfSe2) is oxidized with oxygen plasma to convert a partial region of the channel layer 100 into hafnium oxide (HfO2). That is, the region where hafnium diselenide (HfSe2) is oxidized and converted into hafnium oxide (HfO2) is defined as the dielectric layer 200.

[0074] Finally, a gate electrode (GE) is formed on the dielectric layer 200 so as to entirely cover the upper part of the dielectric layer 200 (S250). Thereby, a field effect transistor (FET) to which an HfO2 / HfSe2 stack structure is applied can be manufactured.

[0075] The field effect transistor according to the embodiment has excellent electrical characteristics due to the excellent interface characteristics of the HfO2 / HfSe2 stack structure. More specifically, the field effect transistor according to the embodiment has an ideal subthreshold swing value of 61 mV / dec close to the Boltzmann limit at room temperature, a high on-off ratio of about 10 8 and a low gate leakage current value of 10 -6 A / cm 2 .

[0076] (Impact ionization super-steep switching element applying an HfO2 / HfSe2 stack structure) FIG. 14 is a flowchart for explaining a method of manufacturing an impact ionization super-steep switching element applying an HfO2 / HfSe2 stack structure according to an embodiment of the present invention, and FIG. 15 is a schematic diagram for explaining an impact ionization super-steep switching element applying an HfO2 / HfSe2 stack structure according to an embodiment of the present invention.

[0077] As shown in FIGS. 14 and 15, a source electrode (S) and a drain electrode (D) spaced apart from each other are provided (S410). Thereafter, a channel layer 100 containing a two-dimensional semiconductor material is formed on the source electrode (S) and the drain electrode (D) (S420). More specifically, the channel layer 100 is formed such that one side contacts the source electrode (S) and the other side contacts the drain electrode (D). Further, the two-dimensional semiconductor material includes hafnium diselenide (HfSe2). According to one embodiment, the channel layer 100 is formed by a method of dry-transferring hafnium diselenide (HfSe2) flakes mechanically exfoliated from a bulk crystal using PDMS.

[0078] The channel layer 100 is oxidized to form a dielectric layer 200 containing a high-k material (S430). More specifically, the channel layer 100 containing hafnium diselenide (HfSe2) is oxidized with oxygen plasma to convert a partial region of the channel layer 100 into hafnium oxide (HfO2). That is, a region where hafnium diselenide (HfSe2) is oxidized and converted into hafnium oxide (HfO2) is defined as the dielectric layer 200.

[0079] Finally, a gate electrode (GE) is formed on the dielectric layer 200 such that one region above the dielectric layer 200 is covered and the other region is exposed (S440). Thereby, an impact ionization super-steep switching element to which an HfO2 / HfSe2 stack structure is applied can be manufactured. The impact ionization super-steep switching element has n-type characteristics by applying an HfO2 / HfSe2 stack structure.

[0080] According to an embodiment, the gate electrode (GE) is formed to cover an area on top of the dielectric layer 200, and is formed to be disposed adjacent to the source electrode (S) among the source electrode (S) and the drain electrode (D). That is, the upper surface of the dielectric layer 200 is divided into a first region (A1) where the gate electrode (GE) overlaps and a second region (A2) where the gate electrode (GE) does not overlap and the upper surface of the dielectric layer 200 is exposed to the outside.

[0081] According to an embodiment, a voltage for generating an electric field greater than the minimum electric field strength (hereinafter defined as the "critical electric field") for avalanche multiplication to occur in the second region (A2) is applied to the drain electrode (D).

[0082] Also, a voltage is applied to the drain electrode (D), and a voltage is also applied to the gate electrode (GE), and the voltages are applied so that the sequential voltages increase. As a result, an avalanche carrier amplification phenomenon occurs in the second region (A2). That is, while applying an electric field stronger than the critical electric field to the first region (A1) through the voltage of the drain electrode (D), the gate voltage is gradually increased to generate an avalanche carrier amplification phenomenon, thereby realizing an ultra-steep switching phenomenon at room temperature.

[0083] When an electric field is applied to the first region (A1), charge carriers are accelerated within the second region (A2). Generally, the charge carrier velocity does not increase without limit and saturates at a certain velocity due to collisions with the lattice. However, when a sufficiently high electric field, i.e., an electric field greater than the critical electric field, is applied, the charge carriers sufficiently accelerated by the electric field collide with the lattice, raising electrons in the valence band to the conduction band and generating new electron-hole pairs. Such secondary electron-hole pairs acquire high energy again and continuously generate further electron-hole pairs, thus greatly increasing the carrier density. The avalanche amplification described above means that carriers are amplified by such impact ionization, and the critical electric field means the electric field strength of the minimum size at which the avalanche amplification occurs.

[0084] The impact ionization super-steep switching element according to the embodiment has excellent electrical characteristics due to the excellent interface characteristics of the HfO2 / HfSe2 stack structure. More specifically, the impact ionization super-steep switching element according to the embodiment can overcome the thermionic limit (60 mV / dec) of CMOS elements and have a very low threshold swing (SS) value of 3.43 mV / dec. Thereby, while maintaining a high on-off ratio, the supply voltage can be decreased, so that power consumption and device reliability can be easily improved.

[0085] In the case of the impact ionization super-steep switching element according to the above embodiment, the gate electrode (GE) overlaps only a part of the channel layer 100 and the dielectric layer 200 having impact ionization characteristics, thereby adjusting the gate region. While applying an electric field stronger than the critical electric field to the channel layer 100, the gate voltage is gradually increased to increase the probability of occurrence of the avalanche carrier amplification phenomenon. As a result, the number of charge carriers generated in the channel layer 100 can be significantly increased. As a result, a super-steep switching element having a very low SS (Subthreshold Swing) value even at room temperature can be realized.

[0086] Further, according to the present invention, by configuring a simple series connection circuit of a transistor that can operate complementarily with the super-steep switching element, an inverter element having a high inverter gain and an ideal noise margin based on the super-steep switching phenomenon can be realized.

[0087] Further, according to the present invention, the upper surface of the dielectric layer 200 includes a first region (A1) where the gate electrode (GE) overlaps and a second region (A2) where the gate electrode (GE) does not overlap. The first region (A1) and the second region (A2) have a length ratio of 1:0.1 to 0.4. As a result, the probability of occurrence of the avalanche carrier amplification phenomenon occurring in the first region (A1) can be increased, and the number of charge carriers generated in the channel layer 100 can be significantly increased. As a result, a super-steep switching element having a very low (5 mv / dec or less) SS value and an optimized On / Off ratio even at room temperature can be realized. On the contrary, when the length ratio of the second region (A2) to the length of the first region (A1) is less than 0.1, the off current increases while the On / Off ratio decreases, thereby increasing the SS value and reducing the probability of occurrence of impact ionization. On the other hand, when the length ratio of the second region (A2) to the length of the first region (A1) exceeds 0.4, there is a problem that the steep-switching phenomenon does not occur.

[0088] (Architectural film applying HfO2 / HfSe2 stack structure) FIG. 16 is a schematic diagram for explaining an architectural film applying an HfO2 / HfSe2 stack structure according to an embodiment of the present invention.

[0089] Passive cooling is a building design approach that focuses on heat acquisition control and heat dissipation of a building in order to improve indoor thermal comfort with little or no energy consumption. It is a technology that adjusts only the convection direction without a special temperature control device to adjust the temperature inside the building. Among the technologies related to such passive cooling technology, as a conventional architectural film (especially a film used for window coating), as shown in the upper part of FIG. 16, a film in which silicon carbide (SiC) and hafnium oxide (HfO2) are alternately and repeatedly laminated (HfO2 / SiC) film has been used.

[0090] However, instead of silicon carbide (SiC), hafnium diselenide (HfSe2) can also be used. When hafnium diselenide (HfSe2) is used, as described in the present invention, an HfO2 / HfSe2 laminated structure can be manufactured by a simple method of oxidizing hafnium diselenide (HfSe2). Therefore, compared with the conventional method, not only the convenience of the process is improved, but also large-area manufacturing can be easily performed.

[0091] (Solar cell applying HfO2 / HfSe2 stack structure) FIG. 17 is a schematic diagram for explaining a solar cell applying an HfO2 / HfSe2 stack structure according to an embodiment of the present invention.

[0092] As shown in FIG. 17, the HfO2 / HfSe2 stack structure according to the embodiment is used as a blocking layer for preventing electron back reaction between the TCO (Transparent Conductive Oxide) and the electrolyte of a DSSC (Dye-Sensitized Solar Cell). When electron back reaction occurs between the TCO and the electrolyte, there is a problem that the efficiency of the DSSC significantly decreases. Thus, conventionally, titanium oxide (TiO2) has been used as the blocking layer. However, when using hafnium oxide (HfO2) which has a larger energy band gap compared to titanium dioxide (TiO2), electron back reaction between the TCO and the electrolyte can be prevented more efficiently, so the problem of efficiency reduction of the DSSC can be solved more easily.

[0093] As described above, various application examples of the HfO2 / HfSe2 stack structure according to the embodiment of the present invention have been explained. Hereinafter, various modification examples of the HfO2 / HfSe2 stack structure according to the embodiment of the present invention will be described.

[0094] (First Modification Example: Crystallization of HfO2) FIG. 18 is a schematic diagram for explaining a first modification example of the HfO2 / HfSe2 stack structure according to the embodiment of the present invention.

[0095] As shown in FIG. 18, after forming a stack structure in which the channel layer 100 and the dielectric layer 200 are stacked on a substrate (SB), that is, a HfO2 / HfSe2 stack structure, the dielectric layer 200 is post-processed to change hafnium oxide (HfO2) from an amorphous state to a crystalline state. That is, in the case of hafnium oxide (HfO2) formed by oxidizing hafnium diselenide (HfSe2), by having an amorphous state, it can be post-processed to change to a crystalline state. According to one embodiment, an amorphous hafnium oxide (HfO2) can be changed to a crystalline state by performing post-processing steps such as thermal annealing, laser exposure, and electron beam exposure.

[0096] In the case of crystalline hafnium oxide (HfO2), since the insulation characteristics are relatively improved compared to amorphous hafnium oxide (HfO2), it can be easily applied to locations where high insulation characteristics are required using the method described above.

[0097] Also, according to one embodiment, amorphous hafnium oxide (HfO2) is changed to crystalline hafnium oxide (HfO2), one region is changed to crystalline hafnium oxide (HfO2), and the remaining region remains as amorphous hafnium oxide (HfO2). For example, by post-processing only the upper surface of amorphous hafnium oxide (HfO2), the upper region of the dielectric layer 200 can be changed to crystalline hafnium oxide (HfO2), while the lower region, that is, the region where the dielectric layer 200 is adjacent to the channel layer 100, can remain as amorphous hafnium oxide (HfO2). In this case, while maintaining the excellent interface characteristics between the channel layer 100 and the dielectric layer 200, the reduction characteristics of the gate leakage current of crystalline hafnium oxide (HfO2) can be exhibited together, and it can be easily applied to various fields.

[0098] (Second Modification Example: Formation of HfZrO2 by Zr Doping) FIG. 19 and FIG. 20 are schematic diagrams for explaining a second modification example of the HfO2 / HfSe2 stack structure according to an embodiment of the present invention.

[0099] As shown in FIG. 19, after sequentially laminating hafnium diselenide (HfSe2) and zirconium diselenide (ZrSe2) on a substrate, oxygen plasma (O2 plasma) is provided to the zirconium diselenide (ZrSe2). In this case, the zirconium diselenide (ZrSe2) is decomposed to generate zirconium atoms (Zr atoms), and at this time, HfZrO2 can be formed using the generated zirconium atoms (Zr atoms). More specifically, when oxygen plasma is continuously provided to the zirconium diselenide (ZrSe2), the zirconium atoms (Zr atoms) decomposed from the zirconium diselenide (ZrSe2) are bonded to oxygen atoms (O atoms), and the zirconium-oxygen bond (Zr-O) penetrates into the hafnium diselenide (HfSe2). Thereafter, the penetrated zirconium-oxygen bond (Zr-O) replaces the selenium atoms (Se) of the hafnium diselenide (HfSe2), and HfZrO2 is formed. Further, by thermally annealing the formed HfZrO2, the HfZrO2 can be crystallized.

[0100] As shown in FIG. 20, after sequentially laminating hafnium diselenide (HfSe2) and zirconium diselenide (ZrSe2) on a substrate, oxygen plasma is continuously provided to zirconium diselenide (ZrSe2). In this case, zirconium atoms (Zr atoms) decomposed from zirconium diselenide (ZrSe2) are bonded to oxygen atoms (O atoms), and zirconium-oxygen bonds (Zr-O) penetrate into hafnium diselenide (HfSe2). Thereafter, the penetrated zirconium-oxygen bonds (Zr-O) will replace the selenium atoms (Se) of hafnium diselenide (HfSe2), and all hafnium diselenide (HfSe2) will be converted to HfZrO2. Also, by heat-treating the formed HfZrO2, HfZrO2 can be crystallized, and various transition metal dichalcogenides (TMDCs) are inserted between HfZrO2 and the substrate.

[0101] (Third modification example: Oxidize all HfSe2 to convert it to HfO2) FIG. 21 is a schematic diagram for explaining a third modification example of the HfO2 / HfSe2 stack structure according to an embodiment of the present invention.

[0102] As shown in FIG. 21, after forming the channel layer 100 on a substrate (SB), by providing continuous oxygen plasma, all of the channel layer 100 is converted into the dielectric layer 200. That is, all hafnium diselenide (HfSe2) is converted into hafnium oxide (HfO2).

[0103] According to one embodiment, the third modification described above is used as a method for integrating a gate dielectric on various two-dimensional semiconductors. For example, after laminating hafnium diselenide (HfSe2) on molybdenum disulfide (MoS2), hafnium diselenide (HfSe2) is continuously provided with oxygen plasma to convert hafnium diselenide (HfSe2) into hafnium oxide (HfO2). As a result, a structure in which a gate dielectric (HfO2) is integrated on a two-dimensional semiconductor (MoS2) is formed. More specifically, the method described above is performed by laminating hafnium diselenide (HfSe2) on a two-dimensional semiconductor (MoS2) and utilizing the van der Waals gap (vdW gap) formed between the two-dimensional semiconductor (MoS2) and hafnium diselenide (HfSe2) as a defect free vdW interface.

[0104] As described above, various modifications of the stack structure according to the embodiments of the present invention have been explained. Hereinafter, specific experimental examples and characteristic evaluation results of the HfO2 / HfSe2 stack structure according to the embodiments of the present invention will be described.

[0105] (Experimental Example 1: Confirmation of Characteristics of HfO2 / HfSe2 Stack Structure) After forming hafnium diselenide (HfSe2) on a substrate, hafnium diselenide (HfSe2) was plasma oxidized to convert a region of hafnium diselenide (HfSe2) into hafnium oxide (HfO2). In addition, a 5-nm-thick protection layer was formed on the hafnium oxide (HfO2). More specifically, the plasma oxidation of hafnium diselenide (HfSe2) was performed by providing oxygen plasma under the conditions of a flow rate of 5 sccm and a pressure of 470 mTorr.

[0106] FIG. 22 is a TEM image of HfSe2 oxidized with oxygen plasma having a power of 7 W.

[0107] Figure 22 shows a TEM (Transmission Electron Microscopy) image of HfSe2 oxidized with an oxygen plasma having a power of 7W. From Figure 22, it can be confirmed that oxidation of HfSe2 does not occur with a low plasma power.

[0108] Figure 23 is a TEM image of HfSe2 oxidized with an oxygen plasma having a power of 8W.

[0109] Figure 23 shows a TEM image of HfSe2 oxidized with an oxygen plasma having a power of 8W. From Figure 23, it can be confirmed that one region of HfSe2 has been converted to HfO2.

[0110] Figure 24 is a TEM image of HfSe2 oxidized with an oxygen plasma having a power of 10W.

[0111] Figure 24 shows a TEM image of HfSe2 oxidized with an oxygen plasma having a power of 10W. From Figure 24, it can be confirmed that one region of HfSe2 has been converted to HfO2 and that HfSe2 and HfO2 are clearly separated by an interface.

[0112] Figure 25 is a TEM image of HfSe2 oxidized with an oxygen plasma having a power of 20W.

[0113] Figure 25 shows a TEM image of HfSe2 oxidized with an oxygen plasma having a power of 20W. From Figure 25, it can be confirmed that one region of HfSe2 has been converted to HfO2, but that collapse of the interface occurs.

[0114] Figure 26 is a TEM image of HfSe2 oxidized with an oxygen plasma having a power of 30W.

[0115] Figure 26 shows a TEM image of HfSe2 oxidized with an oxygen plasma having a power of 30 W. From Figure 26, it can be confirmed that although a region of HfSe2 was converted to HfO2, the collapse of the interface occurred more clearly.

[0116] As a result, it can be seen from Figures 22 to 26 that when manufacturing an HfO2 / HfSe2 stack structure, the power of the oxygen plasma must be controlled during the plasma oxidation process of HfSe2. Specifically, it can be seen that a plasma power of more than 7 W is required to convert HfSe2 to HfO2, and a plasma power of less than 20 W is required to prevent the collapse of the interface between HfSe2 and HfO2.

[0117]

Table 1

[0118] Figure 27 is a diagram for explaining an OM image and a thickness change profile of HfSe2 in the state before being oxidized with an oxygen plasma.

[0119] Figure 27 shows an OM (Optical Microscopy) image and a thickness change profile of HfSe2 in the state before being oxidized with an oxygen plasma (0 min oxidation). From Figure 27, it can be confirmed that only HfSe2 is observed in the state before being oxidized with an oxygen plasma.

[0120] Figure 28 is a diagram for explaining an OM image and a thickness change profile of HfSe2 in the state oxidized with an oxygen plasma for 3 minutes.

[0121] Figure 28 shows an OM (Optical Microscopy) image and a thickness change profile of HfSe2 in the state oxidized with an oxygen plasma for 3 minutes (3 min oxidation). From Figure 28, it can be confirmed that HfSe2 was partially converted to HfO2.

[0122] FIG. 29 is a diagram for explaining an OM image and a thickness change profile of HfSe2 in a state oxidized by oxygen plasma for 5 minutes.

[0123] FIG. 29 shows an OM (Optical Microscopy) image and a thickness change profile of HfSe2 in a state (5min oxidation) oxidized by oxygen plasma for 5 minutes. It can be confirmed from FIG. 29 that all of the HfSe2 has been converted to HfO2 (Fully converted).

[0124] Also, from the measurements of FIGS. 27 to 29, considering the molecular weights (336.41 / 210.5) and densities (6.54 / 9.68 g / cm 3 ) of HfO2 / HfSe2, it can be seen that the volume of HfO2 converted from HfSe2 is estimated to be 1:2.3.

[0125] FIG. 30 is a diagram for explaining the Raman analysis results for the plasma oxidation process of HfSe2.

[0126] FIG. 30 shows Raman spectra for HfO2 and HfO2 / HfSe2 formed by plasma oxidation of HfSe2 and the remaining HfSe2. From FIG. 30, the decreased A 1g Raman peak (red curve) also seen after 3 minutes of plasma treatment indicates that there is a single-crystalline HfSe2 layer that has not been converted under the converted HfO2 after plasma treatment. However, the disappeared A 1g Raman peak after 5 minutes of plasma treatment indicates that HfSe2 has been converted to completely amorphous HfO2 (blue curve).

[0127] FIG. 31 is a diagram for explaining the thickness change due to plasma oxidation of HfSe2 and the thickness change of HfO2 converted from HfSe2.

[0128] Figure 31 shows the change in thickness (Total thickness) of HfSe2 with plasma oxidation time and the change in thickness (Converted HfO2 thickness) of HfO2 converted from HfSe2. From Figure 31, it can be confirmed that as the plasma oxidation time increases, the thickness of HfSe2 decreases, and the thickness of HfO2 changed from HfSe2 increases.

[0129] Figure 32 is a diagram for explaining the conversion rate of HfO2 by plasma oxidation of HfSe2.

[0130] In Figure 32, the change in thickness (HfO2 thickness, nm) of HfO2 with the plasma oxidation time (Plasma time, min) of HfSe2 is measured, and from this, the conversion rate of HfO2, that is, the oxidation rate, is derived and shown. More specifically, HfSe2 was plasma oxidized by oxygen plasma under the conditions of a power of 10 W, a flow rate of 5 sccm, and a pressure of 470 mTorr. From Figure 32, it can be seen that the conversion rate of HfO2, that is, the oxidation rate, is derived to be approximately 2.1 nm / min.

[0131] Figure 33 is a schematic diagram for the definition of various intermediate variables required for the thickness calculation of HfO2 converted from HfSe2.

[0132] At the thicknesses measured in Figures 27 to 31, since both the thickness of unconverted HfSe2 and the thickness of converted HfO2 are included, the thickness of HfO2 cannot be directly known by AFM (Atomic Force Microscope). Therefore, an indirect approach for grasping the thickness of converted HfO2 is applied, and as shown by the black arrow in Figure 33, the related elements are defined as follows.

[0133] [Table 2]

[0134] The quantitative relationships between the above-described intermediate variables are shown as follows. The difference between the thickness (t0) of the initial HfSe2 and the total thickness (t3) of the HfO2 / HfSe2 stack structure is the same as the difference between the thickness (t2) of the HfSe2 converted to HfO2 and the thickness (t1) of the HfO2 converted from HfSe2, and can be summarized as in Equation (1) below.

[0135]

Equation

[0136] Also, as described above, since the thickness (t2) of the HfSe2 converted to HfO2 is 2.3 times thicker than the thickness (t1) of the HfO2 converted from HfSe2, it can be summarized as in Equation (2) below.

[0137]

Equation

[0138] Considering Equation (1) and Equation (2) above, Equation (3) below is derived. Since the thickness (t0) of the initial HfSe2 and the total thickness (t3) of the HfO2 / HfSe2 stack structure can be confirmed using AFM, the thickness (t1) of the HfO2 converted from HfSe2 is derived from Equation (3). Also, from the thickness (t1) of the HfO2 converted from HfSe2, as shown in FIG. 32, an oxidation rate of 2.1 nm / min is derived, and a constant oxidation rate is also confirmed from various HfSe2 flakes. Thereby, the high controllability of the plasma oxidation process can be confirmed.

[0139]

Equation

[0140] FIG. 34 is a diagram for explaining the XPS analysis results of the HfO2 / HfSe2 stack structure.

[0141] Figure 34 shows the XPS (X-ray Photoelectron Spectroscopy) depth profile obtained by analyzing the HfO2 / HfSe2 stack structure after manufacturing it, with the thickness reduced by 2.5 nm each time through sputtering at a rate of 0.5 nm / min. From Figure 34, when the thickness is reduced by 10 nm each time, a distinct Se 3d peak and a disappearing O 1s peak (Hf-O) can be confirmed. Thus, through the above-mentioned thickness control conditions, the thickness reduction is achieved, and the accuracy of the oxidation rate can be confirmed again.

[0142] Figure 35 is a diagram showing the STEM image and FFT pattern for the HfO2 / HfSe2 stack structure.

[0143] Figure 35 shows the STEM (Scanning Transmission Electron Microscopy) image for the HfO2 / HfSe2 stack structure on the right side, and the FFT (Fast Fourier Transform) patterns for HfO2 and HfSe2 in the HfO2 / HfSe2 stack structure on the left side.

[0144] From the STEM image in Figure 35, an extremely clean interface can be confirmed where no prominent defects are visible even in a wide range. Also, from the FFT pattern in Figure 35, the amorphous structure of HfO2 and the crystal structure of HfSe2 can be confirmed. More specifically, the non-transformed HfSe2 interplanar distance of (001) is estimated to be approximately 0.614 nm, indicating that the unchanged HfSe2 maintains its original crystal structure.

[0145] Figure 36 is a diagram showing the STEM image and EDS mapping results for the HfO2 / HfSe2 stack structure.

[0146] Figure 36 shows the STEM (Scanning Transmission Electron Microscopy) image of the HfO2 / HfSe2 stack structure on the left side and the EDS mapping (Energy Dispersive Spectrometer mapping) results on the right side. From the EDS mapping results in Figure 36, it can be seen that hafnium (Hf) is confirmed in HfO2 and HfSe2, selenium (Se) is only confirmed in HfSe2, and oxygen (O) is only confirmed in HfO2 and the substrate.

[0147] Figure 37 is a diagram showing a high-resolution STEM image of the HfO2 / HfSe2 stack structure.

[0148] From Figure 37, an atomically clean interface between HfO2 and HfSe2 can be confirmed again, indicating that the formation of HfO2 restricted the merger of unconverted HfSe2 and HfO2 converted from HfSe2. Also, it can be seen that the HfO2 formation process is carried out by layer-by-layer oxidation.

[0149] Figure 38 is a diagram for explaining the XPS analysis results for each of HfO2 and HfSe2 in the HfO2 / HfSe2 stack structure.

[0150] Figure 38 shows the XPS (X-ray Photoelectron Spectroscopy) analysis results for each of HfO2 and HfSe2 in the HfO2 / HfSe2 stack structure confirmed from Figure 37. From Figure 38, it can be confirmed that the Hf 4f peak observed at 16.01 eV and the O 1s peak at 532.4 eV represent the same results as those of a general HfO2 dielectric.

[0151] (Experimental Example 2: Confirmation of MOS capacitor characteristics with the HfO2 / HfSe2 stack structure applied) After forming a lower electrode with a thickness of 10 nm on a substrate, hafnium diselenide (HfSe2) mechanically exfoliated from a bulk crystal was dry-transferred using PDMS. Subsequently, hafnium diselenide (HfSe2) was plasma oxidized to convert a region of hafnium diselenide (HfSe2) into hafnium oxide (HfO2), and an upper electrode with a thickness of 30 nm was formed on the hafnium oxide (HfO2) to fabricate a MOS capacitor to which an HfO2 / HfSe2 stack structure was applied. More specifically, hafnium diselenide (HfSe2) was formed with a thickness of 15 nm, and hafnium oxide (HfO2) was formed with a thickness of 10 nm.

[0152] Figure 39 is a diagram showing the capacitance-voltage characteristics and a schematic diagram of the MOS capacitor according to Experimental Example 2.

[0153] In Figure 39, the capacitance (capacitance, nF / cm G ) measured by the gate voltage (V 2 ) of the MOS capacitor is shown. From Figure 39, it can be seen that as the gate voltage increases, through the accumulated capacitance, HfSe2 is a typical N-type semiconductor. Also, it can be seen that there are low-level interface traps through the behavior that does not change significantly in both the depletion region and the accumulation region depending on the frequency (1 kHz to 1 MHz).

[0154] Figure 40 is a diagram showing the conductance-voltage characteristics of the MOS capacitor according to Experimental Example 2.

[0155] In Figure 40, the conductance (G G / w, nF / cm P ) measured by the gate voltage (V 2 ) of the MOS capacitor is shown. From Figure 40, it can be confirmed that a substantially constant change is represented at various frequencies (1 kHz to 1 MHz).

[0156] FIG. 41 is a diagram for explaining the result of extracting the interface trap density of the MOS capacitor according to Experimental Example 2 using the conductance measured by FIG. 40.

[0157] In FIG. 41, to evaluate the interface charge trap density (D it ) that determines the performance of the stack structure based on HfO2 / HfSe2, the conduction method using the conductivity of FIG. 40 is used, and from FIG. 41, a very low interface charge trap density (D it ) ~ 5.7×10 10 cm -2 eV -1 is confirmed to be present. More specifically, the interface charge trap density (D it ) is derived by Equation 4 below, and Samples 1 to 3 (Sample #1, Sample #2, Sample #3) in FIG. 41 each show MOS capacitors manufactured in the same process.

[0158]

Equation

[0159] FIG. 42 is a diagram for explaining the equivalent oxide thickness and dielectric constant of the MOS capacitor according to Experimental Example 2.

[0160] FIG. 42 shows the thickness of the equivalent oxide thickness (EOT) and the dielectric constant (k) according to the frequency calculated from the conductance-voltage curve of the MOS capacitor. From FIG. 42, the MOS capacitor exhibits a constant dielectric constant (k) of 23 over all frequency ranges, which confirms that the HfO2 chemically converted through the oxidation process is a stable high-k dielectric for low-power and high-frequency electronic devices. Also, the thickness of the equivalent oxide (EOT~1.6 nm) was derived from the dielectric constant (k) value.

[0161] (Experimental Example 3: Confirmation of Field-Effect Transistor Characteristics with HfO2 / HfSe2 Stack Structure) Hafnium diselenide (HfSe2) mechanically exfoliated from a bulk crystal was dry-transferred onto the source and drain electrodes using PDMS. Subsequently, hafnium diselenide (HfSe2) was plasma oxidized to convert a region of hafnium diselenide (HfSe2) into hafnium oxide (HfO2), and a 50-nm-thick gate electrode was formed on the hafnium oxide (HfO2) to fabricate a field-effect transistor (FET) with an HfO2 / HfSe2 stack structure. More specifically, the gate electrode was formed to entirely cover the upper surface of the hafnium oxide (HfO2).

[0162] FIG. 43 is a schematic diagram of the field-effect transistor according to Experimental Example 3.

[0163] FIG. 43 shows the field-effect transistor according to Experimental Example 3 with an HfO2 / HfSe2 stack structure applied. From FIG. 43, it can be confirmed that HfSe2 was formed such that one side was in contact with the source electrode and the other side was in contact with the drain electrode, and the gate electrode was formed to entirely cover the upper surface of HfO2.

[0164] FIG. 44 is a diagram showing the ID-VG curve of the field-effect transistor according to Experimental Example 3.

[0165] Figure 44 shows the measurement of I GS (A) with respect to V DS (V) of the field effect transistor according to Experimental Example 3. From Figure 44, it can be confirmed that the field effect transistor has an ideal subthreshold swing value of 61 mV / dec close to the Boltzmann limit at room temperature, a high on-off ratio (Ion / off) of ~10 8 , and a low gate leakage current value of 10 -6 A / cm 2 . Thus, it can be seen that the HfO2 / HfSe2 stack structure of the field effect transistor has excellent interface characteristics.

[0166] Figure 45 is a diagram showing the ID-VG curve by the gate voltage sweep of the field effect transistor according to Experimental Example 3.

[0167] Figure 45 shows the hysteresis observed during the gate voltage sweep (forward / reverse sweep). From Figure 45, it can be confirmed that the field effect transistor exhibits a small hysteresis of ~11 mV during the gate voltage sweep. Thus, it can be seen that the HfO2 / HfSe2 stack structure of the field effect transistor contains a low trap concentration at the interface and inside HfO2.

[0168] Figure 46 is a diagram showing the ID-VG curve of the field effect transistor according to Experimental Example 3 with respect to temperature.

[0169] Figure 46 shows the change in the subthreshold swing (SS) value of the field effect transistor according to Experimental Example 3 with respect to temperature (100K - 300K). From Figure 46, it can be confirmed that as the temperature decreases from 300K to 100K, the subthreshold swing (SS) value also decreases from 61 mV / dec to 26 mV / dec.

[0170] Figure 47 is a diagram showing the change in the subthreshold swing value of the field effect transistor according to Experimental Example 3 with respect to temperature.

[0171] Figure 47 shows the change in the subthreshold swing value (SS, mV / dec) due to the change in the temperature of the ferroelectric transistor from 50K to 300K. From Figure 47, it can be confirmed that as the temperature increases, the subthreshold swing value also increases, which is substantially consistent with the experimental data.

[0172] Figure 48 is a diagram for explaining the simulation results of the RC Delay characteristics according to the interface charge trap concentration of the field effect transistor according to Experimental Example 3.

[0173] Figure 48 shows the simulation results of the RC Delay characteristics according to the HfO2 / HfSe2 interface charge trap concentration (D it ) of the field effect transistor according to Experimental Example 3. From Figure 48, it can be seen from the simulation evaluation of the RC Delay that appears in the circuit due to the increase in the interface charge trap concentration (D it ) that the importance of a low interface charge trap concentration (D it ) is understood.

[0174] Figure 49 is a diagram showing the electrical characteristics of the field effect transistor according to Experimental Example 3 in which the thickness ratio of HfO2:HfSe2 is 1:1.

[0175] Figure 49 shows the measurement of the subthreshold swing value (SS), the on-current value, and the threshold voltage (Threshold Voltage, VTH) of the field effect transistor according to Experimental Example 3 in which the thickness ratio of HfO2:HfSe2 is 1:1. More specifically, the thickness of HfO2 and the thickness of HfSe2 are each 10 nm.

[0176] From Figure 49, the subthreshold swing value (SS) is measured to be ~61.5 mV / dec, the on-current value is measured to be ~10 -5 A, and the threshold voltage (V TH) can be confirmed to have been measured at ~ - 0.75V.

[0177] Figure 50 is a diagram showing the electrical characteristics of a field - effect transistor according to Experimental Example 3 in which the thickness ratio of HfO2:HfSe2 is 1:2.

[0178] In Figure 50, the sub - threshold swing value (SS), the on - current value, and the threshold voltage (Threshold Voltage, VTH) of the field - effect transistor according to Experimental Example 3 in which the thickness ratio of HfO2:HfSe2 is 1:2 are measured and shown. More specifically, the thickness of HfO2 and the thickness of HfSe2 are 10 nm and 20 nm, respectively.

[0179] From Figure 50, the sub - threshold swing value (SS) is measured to be ~ 80.7 mV / dec, the on - current value is ~ 10 -7 A, and the threshold voltage (V TH ) can be confirmed to have been measured at ~ - 1.1V.

[0180] Figure 51 is a diagram showing the electrical characteristics of a field - effect transistor according to Experimental Example 3 in which the thickness ratio of HfO2:HfSe2 is 1:3.

[0181] In Figure 51, the sub - threshold swing value (SS), the on - current value, and the threshold voltage (Threshold Voltage, VTH) of the field - effect transistor according to Experimental Example 3 in which the thickness ratio of HfO2:HfSe2 is 1:3 are measured and shown. More specifically, the thickness of HfO2 and the thickness of HfSe2 are 10 nm and 30 nm, respectively.

[0182] From Figure 51, the sub - threshold swing value (SS) is measured to be ~ 103.2 mV / dec, the on - current value is ~ 10 -8 A, and the threshold voltage (V TH ) can be confirmed to have been measured at ~ - 1.6V.

[0183]

Table 3

[0184] As a result, as can be seen from FIGS. 49 to 51, when the HfSe2 thickness increases compared to the HfO2 thickness, the subthreshold swing value (SS) increases, and the operating current value (On current) and the threshold voltage (V TH ) decrease, confirming that the electrical characteristics deteriorate. Also, even when the ratio of the HfSe2 thickness to the HfO2 thickness decreases, the electrical characteristics were measured. When the ratio of the HfSe2 thickness to the HfO2 thickness decreases below 1, it was confirmed that no substantial change occurred compared to the case where the ratio of the HfSe2 thickness to the HfO2 thickness is 1. Thus, it can be seen that when manufacturing a field-effect transistor applying an HfO2 / HfSe2 stack structure, the ratio of the HfSe2 thickness to the HfO2 thickness must be controlled to 1 or less.

[0185] FIG. 52 is a diagram for explaining the result of measuring the subthreshold swing value of a field-effect transistor according to Experimental Example 3 to which an HfO2 / HfSe2 stack structure oxidized by oxygen plasma having a power of 10 W was applied.

[0186] In FIG. 52, for the field-effect transistor according to Experimental Example 3 to which an HfO2 / HfSe2 stack structure oxidized by oxygen plasma having a power of 10 W was applied, V GS (V) was used to measure I DS (A), and the subthreshold swing value (SS) was derived. From FIG. 52, it can be seen that when a power of 10 W was applied, it has a subthreshold swing value (SS) of ~65 mV / dec.

[0187] FIG. 53 is a diagram for explaining the result of measuring the subthreshold swing value of a field-effect transistor according to Experimental Example 3 to which an HfO2 / HfSe2 stack structure oxidized by oxygen plasma having a power of 15 W was applied.

[0188] For the field-effect transistor according to Experimental Example 3 to which a HfO2 / HfSe2 stack structure oxidized with an oxygen plasma having a power of 15 W was applied, V GS (V) was used to measure I DS (A), and the subthreshold swing value (SS) was derived. From FIG. 53, it can be seen that when a power of 15 W is applied, it has a subthreshold swing value (SS) of ~98 mV / dec.

[0189] FIG. 54 is a diagram for explaining the result of measuring the subthreshold swing value of the field-effect transistor according to Experimental Example 3 to which a HfO2 / HfSe2 stack structure oxidized with an oxygen plasma having a power of 20 W was applied.

[0190] For the field-effect transistor according to Experimental Example 3 to which a HfO2 / HfSe2 stack structure oxidized with an oxygen plasma having a power of 20 W was applied, V GS (V) was used to measure I DS (A), and the subthreshold swing value (SS) was derived. From FIG. 54, it can be seen that when a power of 20 W is applied, it has a subthreshold swing value (SS) of ~130 mV / dec.

[0191] FIG. 55 is a diagram for explaining the result of measuring the subthreshold swing value of the field-effect transistor according to Experimental Example 3 to which a HfO2 / HfSe2 stack structure oxidized with an oxygen plasma having a power of 25 W was applied.

[0192] For the field-effect transistor according to Experimental Example 3 to which a HfO2 / HfSe2 stack structure oxidized with an oxygen plasma having a power of 25 W was applied, V GS (V) was used to measure I DS (A), and the subthreshold swing value (SS) was derived. From FIG. 55, it can be seen that when a power of 25 W is applied, it has a subthreshold swing value (SS) of ~192 mV / dec.

[0193] FIG. 56 is a diagram for explaining the result of measuring the subthreshold swing value of a field effect transistor according to Experimental Example 3 to which a HfO2 / HfSe2 stack structure oxidized with an oxygen plasma having a power of 30 W is applied.

[0194] In FIG. 56, for the field effect transistor according to Experimental Example 3 to which a HfO2 / HfSe2 stack structure oxidized with an oxygen plasma having a power of 30 W is applied, V GS (V) is used to measure I DS (A), and the subthreshold swing value (SS) is derived. From FIG. 56, it can be seen that when a power of 30 W is applied, the subthreshold swing value (SS) is ~250 mV / dec.

[0195] [Table 4]

[0196] From FIGS. 52 to 56, it was confirmed that as the oxygen plasma power increased from 10 W to 30 W, the subthreshold swing value increased from ~65 mV / dec to ~250 mV / dec. Also, based on the results measured in FIGS. 52 to 56, an equation for calculating the subthreshold swing value (SS) according to the oxygen plasma power (W) was derived, and the derived equation is summarized through Equation 5 below.

[0197] [Equation] (x: the number obtained by dividing the oxygen plasma power by W with W as the reference, y: the subthreshold swing value, y0: -25.79881, A1: 50.00735, t1: -16.5733)

[0198] As described above, the field-effect transistor to which the HfO2 / HfSe2 stack structure is applied can derive the subthreshold swing value only through the oxygen plasma power for the oxidation of HfSe2. Therefore, from the prediction of the subthreshold swing value, it can be easily applied to various fields.

[0199] FIG. 57 is a diagram for explaining the result of measuring the leakage current value of the field-effect transistor according to Experimental Example 3 to which the HfO2 / HfSe2 stack structure oxidized by oxygen plasmas having different powers is applied.

[0200] In FIG. 57, for the field-effect transistor according to Experimental Example 3 to which the HfO2 / HfSe2 stack structure oxidized by oxygen plasmas having different powers (10 W, 15 W, 20 W, 25 W, 30 W) is applied, V GS (V) is used to measure and show the leakage current value (Gate leakage current density, A / cm 2 ). It can be confirmed from FIG. 57 that as the oxygen plasma power increases from 10 W to 30 W, the leakage current value also increases.

[0201] (Experimental Example 4: Confirmation of characteristics of impact ionization super-steep switching element to which HfO2 / HfSe2 stack structure is applied) Hafnium diselenide (HfSe2) mechanically exfoliated from a bulk crystal was dry-transferred onto the source electrode and the drain electrode using PDMS. Thereafter, hafnium diselenide (HfSe2) was plasma oxidized to convert a region of hafnium diselenide (HfSe2) into hafnium oxide (HfO2), and a gate electrode with a thickness of 50 nm was formed on the hafnium oxide (HfO2) to manufacture a field-effect transistor (FET) with an HfO2 / HfSe2 stack structure. More specifically, the gate electrode was formed so as to cover a part of the upper surface of the hafnium oxide (HfO2) and the rest was exposed to the outside.

[0202] Figure 58 is a schematic diagram of the impact ionization super-steep switching element according to Experimental Example 4.

[0203] Figure 58 shows the impact ionization super-steep switching element according to Experimental Example 4 to which an HfO2 / HfSe2 stack structure is applied. Also shown is a drawing representing the band structure degree and the impact ionization phenomenon by the gate voltage and the drain voltage.

[0204] From Figure 58, it can be confirmed that HfSe2 is formed such that one side is in contact with the source electrode and the other side is in contact with the drain electrode, and the region (L gated ) where the gate electrode overlaps with HfO2, and the region (L ungated ) where the gate electrode does not overlap with HfO2 and the upper surface of HfO2 is exposed to the outside are separated.

[0205] Also, when a sufficiently high drain voltage (V BR ) and a gate voltage are applied, it can be confirmed that the impact ionization phenomenon occurs in the region (L ungated ) where the gate electrode does not overlap with HfO2.

[0206] Figure 59 is a diagram showing the ID-VG curve of the impact ionization super-steep switching element according to Experimental Example 4.

[0207] Figure 59 shows the transmission characteristics representing the rapid current increase due to the impact ionization phenomenon occurring in the impact ionization super-steep switching element according to Experimental Example 4. Also, in the inserted part of Figure 59, the part where super-steep switching occurs is enlarged and shown. From Figure 59, it can be confirmed that the impact ionization super-steep switching element according to Experimental Example 4 overcomes the thermionic limit (60 mV / dec) of the CMOS element and has a very low threshold swing (SS) value of 3.43 mV / dec.

[0208] Figure 60 is a diagram showing the ID-VD curve of the impact ionization super-steep switching element according to Experimental Example 4.

[0209] From FIG. 60, it can be confirmed that the output characteristics showing a rapid current increase due to the impact ionization phenomenon occurring in the impact ionization super-steep switching element according to Experimental Example 4 are obtained.

[0210] FIG. 61 is a diagram showing electron-hole pairs generated in the ungated region of the impact ionization super-steep switching element according to Experimental Example 4.

[0211] FIG. 61 shows the simulation results of the impact ionization rate and the generated electron-hole density in the region where the gate electrode of the super-steep switching element according to Experimental Example 4 does not overlap with HfO2 (ungated region). From FIG. 61, it can be confirmed that a sufficient number of electron-hole pairs are generated by impact ionization in the region where the gate electrode does not overlap with HfO2 (ungated region).

[0212] FIG. 62 is a diagram showing the critical voltage according to changes in the HfO2 thickness and the ungated region length of the impact ionization super-steep switching element according to Experimental Example 4.

[0213] FIG. 62 shows the change in the critical voltage (V) according to the adjustment of the HfO2 thickness (HfO2 thickness, nm) and the length of the region where the gate electrode does not overlap with HfO2 (L, nm) of the impact ionization super-steep switching element according to Experimental Example 4. From FIG. 62, it can be confirmed that super-steep switching is realized under a lower driving voltage. ungated 、nm) of the impact ionization super-steep switching element according to Experimental Example 4. From FIG. 62, it can be confirmed that super-steep switching is realized under a lower driving voltage. BR 、V) of the impact ionization super-steep switching element according to Experimental Example 4. From FIG. 62, it can be confirmed that super-steep switching is realized under a lower driving voltage.

[0214] FIG. 63 shows the channel current (I) according to various drain voltages (V) and gate voltages (V) of the impact ionization super-steep switching element according to Experimental Example 4. DS ) and the gate voltage (V GS ) of the impact ionization super-steep switching element according to Experimental Example 4. DS ) of the impact ionization super-steep switching element according to Experimental Example 4.

[0215] From FIG. 63, the interrelated prerequisite conditions of the gate voltage and the drain voltage for super-steep switching in the impact ionization super-steep switching element according to Experimental Example 4 can be confirmed.

[0216] FIG. 64 is a diagram for explaining changes in electrical characteristics due to changes in the length of the gate non-overlap region of the impact ionization super-steep switching element according to Experimental Example 4.

[0217] FIG. 64 shows the simulation results of the threshold voltage (V ungated ), critical voltage (V TH ), and on-off ratio with respect to the change in the length (L BR , nm) of the region where the gate electrode of the impact ionization super-steep switching element according to Experimental Example 4 does not overlap with HfO2.

[0218] From FIG. 64, it can be seen that when the length (L ungated , nm) of the region where the gate electrode does not overlap with HfO2 is reduced, the threshold voltage (V TH ) and the critical voltage (V BR ) are further reduced. Thus, it can be understood that while maintaining a high on-off ratio, the supply voltage can be reduced to improve power consumption and device reliability.

[0219] (Experimental Example 5: Characteristics Confirmation of a Transistor with a Gate Dielectric Integrated on a MoS2 Two-Dimensional Semiconductor) FIG. 65 is a schematic diagram for explaining the manufacturing process of the transistor according to Experimental Example 5.

[0220] In FIG. 65, MoS2 was formed as a two-dimensional semiconductor on a substrate, and a source electrode (S) and a drain electrode (D) were formed on one side and the other side of MoS2, respectively. Subsequently, HfSe2 was formed on MoS2, and continuous oxygen plasma was provided to HfSe2 to convert both HfSe2 to HfO2. Finally, a gate electrode was formed on HfO2 to manufacture the transistor according to Experimental Example 5.

[0221] FIG. 66 is a diagram for explaining the MoS2 semiconductor characteristics of the transistor according to Experimental Example 5.

[0222] From FIG. 66, the I BG / TG (V) of the transistor according to Experimental Example 5 with respect to V DSBy measuring (A), the semiconductor characteristics of MoS2 were confirmed. From FIG. 66, it can be confirmed that MoS2 has n-type semiconductor characteristics. Also, it can be confirmed that the transistor according to Experimental Example 5 exhibits a small hysteresis.

[0223] FIG. 67 is a diagram for explaining the subthreshold swing value of the transistor according to Experimental Example 5.

[0224] In FIG. 67, the V of the transistor according to Experimental Example 5 TG (V) by measuring I DS (A), the subthreshold swing value (SS) was derived. From FIG. 67, it can be confirmed that the transistor according to Experimental Example 5 has a low subthreshold swing value of ~60.5 mV / dec.

[0225] That is, from FIGS. 66 and 67, since the transistor according to Experimental Example 5 has a very low subthreshold swing value and a small hysteresis, it can be seen that there are excellent interface characteristics between MoS2 and HfO2, which can be predicted to be manifested by a high-quality van der Waals interface (vdW interface).

[0226] (Experimental Example 6: Confirmation of characteristics of a transistor with a gate dielectric integrated on a WSe2 two-dimensional semiconductor) On a substrate, WSe2 was formed as a two-dimensional semiconductor, and a source electrode (S) and a drain electrode (D) were formed on one side and the other side of WSe2, respectively. Thereafter, HfSe2 was formed on WSe2, and oxygen plasma was continuously provided to HfSe2 to convert both HfSe2 into HfO2. Finally, a gate electrode was formed on HfO2 to fabricate the transistor according to Experimental Example 6.

[0227] FIG. 68 is a diagram for explaining the WSe2 semiconductor characteristics of the transistor according to Experimental Example 6.

[0228] From FIG. 68, the V of the transistor according to Experimental Example 6 BG / TGI by (V) DS By measuring (A), the semiconductor characteristics of WSe2 were confirmed. From FIG. 68, it can be confirmed that WSe2 has p-type semiconductor characteristics. Further, it can be confirmed that the transistor according to Experimental Example 6 exhibits a small hysteresis.

[0229] FIG. 69 is a diagram for explaining the subthreshold swing value of the transistor according to Experimental Example 6.

[0230] As shown in FIG. 69, the V of the transistor according to Experimental Example 6 TG I by (V) DS By measuring (A), the subthreshold swing value (SS) was derived. From FIG. 69, it can be confirmed that the transistor according to Experimental Example 6 has a low subthreshold swing value of ~61.3 mV / dec.

[0231] That is, from FIGS. 68 and 69, it can be seen that the transistor according to Experimental Example 6 has very low subthreshold swing value and small hysteresis, and thus it can be predicted that it has excellent interface characteristics between WSe2 and HfO2, which is manifested by a high-quality van der Waals interface (vdW interface).

[0232] As described above, the present invention has been described in detail using preferred embodiments. However, the scope of the present invention is not limited to specific embodiments and should be analyzed according to the appended claims. Also, those having ordinary knowledge in the relevant technical field will understand that many modifications and variations are possible without departing from the scope of the present invention.

Explanation of Reference Numerals

[0233] 100 Channel layer 200 Dielectric layer SB Substrate GT Stack structure BE Bottom electrode TE Top electrode S, D Source electrode, Drain electrode GE Gate electrode

Claims

1. providing a substrate; On the substrate, ２ O ２ forming a layer of two-dimensional (2D) semiconductor material comprising Se; The two-dimensional semiconductor material layer is oxidized to form a Bi ２ SeO ５ and forming a high-k material layer comprising the material.

2. The two-dimensional semiconductor material layer is oxidized to form a high dielectric material layer having a Bi content. ２ SeO ５ 2. The method for manufacturing a stack structure according to claim 1, wherein the crystal structure of said first layer is controlled.

3. The two-dimensional semiconductor material layer is oxidized by oxygen plasma to form amorphous Bi. ２ SeO ５ 3. The method for manufacturing a stack structure according to claim 2, wherein the high-k material layer is formed to include a material selected from the group consisting of tungsten, ... and zinc.

4. The two-dimensional semiconductor material layer is naturally oxidized to form crystalline Bi. ２ SeO ５ 3. The method for manufacturing a stack structure according to claim 2, wherein the high-k material layer is formed to include a material selected from the group consisting of tungsten, ... and zinc.

5. The two-dimensional semiconductor material layer is oxidized by an ultraviolet (UV) oxidation method to form a single crystal β-Bi. ２ SeO ５ 3. The method for manufacturing a stack structure according to claim 2, wherein the high-k material layer is formed to include a material selected from the group consisting of tungsten, ... and zinc.

6. providing a substrate; forming a channel layer on the substrate, the channel layer comprising a two-dimensional (2D) semiconductor material; and oxidizing the channel layer to form a dielectric layer including a high-k material.

7. The channel layer is oxidized to convert a region of the channel layer into the dielectric layer including the high dielectric material; 7. The method of claim 6, wherein the other region of the channel layer is left as the channel layer including the two-dimensional semiconductor material.

8. 7. The method of claim 6, wherein the high dielectric material is formed by oxidizing the two-dimensional semiconductor material.

9. The method for manufacturing a stack structure according to claim 6, wherein the dielectric layer is formed by oxidizing the channel layer with oxygen plasma.

10. The method for manufacturing a stack structure according to claim 9, wherein the thickness of the dielectric layer is controlled by the time during which the channel layer is exposed to the oxygen plasma.

11. a channel layer comprising a two-dimensional (2D) semiconductor material; a dielectric layer disposed on the channel layer; The stack structure, wherein the dielectric layer comprises a high-k material in which the two-dimensional semiconductor material is oxidized.

12. The two-dimensional semiconductor material is Bi ２ O ２ Se, hafnium diselenide (HfSe 2 ), hafnium disulfide (HfS 2 ), and zirconium diselenide (ZrSe 2 12. The stack structure according to claim 11, further comprising any one of the following:

13. The high dielectric material is Bi ２ SeO ５ , hafnium oxide (HfO x , x>0), and zirconium oxide (ZrO x 12. The stack structure according to claim 11, further comprising any one of the following: x>0.

14. The stack structure of claim 11 , wherein an interface is formed between the channel layer and the dielectric layer.

15. A source electrode and a drain electrode spaced apart from each other; a channel layer including a two-dimensional (2D) semiconductor material disposed on the source electrode and the drain electrode such that one side of the channel layer contacts the source electrode and the other side of the channel layer contacts the drain electrode; a dielectric layer disposed on the channel layer, the dielectric layer including a high-k material in which the two-dimensional semiconductor material is oxidized; and a gate electrode disposed on the dielectric layer.

16. the dielectric layer is formed by oxidizing a portion of the channel layer with oxygen plasma; 16. The transistor of claim 15, wherein electrical characteristics are controlled by the power of the oxygen plasma provided to the channel layer.

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