Semiconductor device

Abstract

To provide a semiconductor device with large on-state current and excellent reliability.SOLUTION: In a semiconductor device, a transistor 200 includes a first insulator 214, a first oxide 230a thereon, a second oxide 230b thereon, third and fourth oxides 243a and 243b thereon, first and second conductors 242a and 242b on the third and fourth oxides, a fifth oxide 230c on the second oxide, a second insulator 250 thereon, and a third conductor 260 thereon. The fifth oxide is in contact with each of an upper surface of the second oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the third oxide, and a side surface of the fourth oxide. The second oxide contains In, an element M (Al, Ga, Y, or Sn is particularly preferable), and Zn. Each of the first and fifth oxides contains at least one of the constituent elements in the second oxide. Each of the third and fourth oxides contains the element M. The third and fourth oxides include a region in which the concentration of the element M is higher than that in the second oxide.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Alternatively, one aspect of the present invention relates to a semiconductor wafer, a module, and an electronic device. In the present specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices are one aspect of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, and electronic devices may be said to have semiconductor devices in some cases.

[0002] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in the present specification and the like relates to an article, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003]

[0004]

Background Art

[0004] As a semiconductor thin film applicable to transistors, silicon-based semiconductor materials are widely known, but oxide semiconductors are attracting attention as other materials. Examples of oxide semiconductors include not only oxides of monovalent metals such as indium oxide and zinc oxide but also oxides of multivalent metals. Among the oxides of multivalent metals, in particular, research on indium-gallium-zinc oxide (hereinafter also referred to as IGZO) has been actively conducted.

[0005] ​​​​Research on IGZO has revealed that in oxide semiconductors, there are structures called C that are neither single crystals nor amorphous AAC (c-axis aligned crystalline) structure and nc (n anocrystalline) structure (see Non-Patent Documents 1 to 3). . In Non-Patent Documents 1 and 2, techniques for fabricating transistors using oxide semiconductors having a CAAC structure are also disclosed. Furthermore, it has been shown in Non-Patent Documents 4 and 5 that even oxide semiconductors with lower crystallinity than the CAAC structure and nc structure have minute crystals.

[0006] Furthermore, transistors using IGZO as an active layer have an extremely low off-current (see Non-Patent Document 6), and LSIs and displays utilizing such characteristics have been reported (see Non-Patent Documents 7 and 8).

Prior Art Documents

Non-Patent Documents

[0007]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Non-Patent Document 4

Non-Patent Document 5

Non-Patent Document 6

Non-Patent Document 7

Non-Patent Document 8

Summary of the Invention

Problems to be Solved by the Invention

[0008] One aspect of the present invention is to provide a semiconductor device having a large on-current as one of the problems. Alternatively, one aspect of the present invention is to provide a semiconductor device having high frequency characteristics as one of the problems. Alternatively, one aspect of the present invention is to provide a semiconductor device having good reliability as one of the problems. Alternatively, one aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration as one of the problems. Alternatively, one aspect of the present invention is to have good electrical characteristics One of the problems is to provide a semiconductor device. Or, one aspect of the present invention is to provide a semiconductor device with high productivity. One of the problems is to provide a semiconductor device with high productivity.

[0009] One of the problems of one aspect of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. One of the problems of one aspect of the present invention is to provide a semiconductor device with a high information writing speed. One of the problems of one aspect of the present invention is to provide a semiconductor device with a high information writing speed. One of the problems of one aspect of the present invention is to provide a semiconductor device with a high degree of design freedom. One of the problems of one aspect of the present invention is to provide a semiconductor device with a high degree of design freedom. One of the problems of one aspect of the present invention is to provide a semiconductor device capable of suppressing power consumption. One of the problems of one aspect of the present invention is to provide a semiconductor device capable of suppressing power consumption. One of the problems of one aspect of the present invention is to provide a novel semiconductor device. One of the problems of one aspect of the present invention is to provide a novel semiconductor device. One of the problems is to provide a novel semiconductor device.

[0010] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily have to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that one aspect of the present invention does not necessarily have to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention includes a first insulator, a first oxide on the first insulator, a second oxide on the first oxide, a third oxide and a fourth oxide on the second oxide, a first conductor on the third oxide, a second conductor on the fourth oxide, a fifth oxide on the second oxide, a second insulator on the fifth oxide, and a third conductor on the second insulator. The fifth oxide covers the upper surface of the second oxide, the side surfaces of the first conductor, the side surfaces of the second conductor, and the third oxide. oxide, the side surfaces of the first conductor, the side surfaces of the second conductor, and the third oxide, the side surfaces of the first conductor, the side surfaces of the second conductor, and the third oxide, the side surfaces of the first conductor, the side surfaces of the second conductor, and the third The side of the oxide and the side of the fourth oxide are in contact with each other, respectively. The second oxide contains In, an element M (where M is Al, Ga, Y, or Sn), and Zn. The first oxide and the fifth oxide each have at least one of the constituent elements of the second oxide. The third oxide and the fourth oxide each have the element M, and the third oxide and the fourth oxide have a region where the concentration of the element M is higher than that of the second oxide. This is a semiconductor device. element M (where M is Al, Ga, Y, or Sn), and Zn. The first oxide and the fifth oxide each have at least one of the constituent elements of the second oxide. The third oxide and the fourth oxide each have the element M, and the third oxide and the fourth oxide have a region where the concentration of the element M is higher than that of the second oxide.

[0012] Also, in the above, it is preferable that the third oxide and the fourth oxide each have a region where the film thickness is 0.5 nm or more and 5 nm or less.

[0013] Also, in the above, it is preferable that the third oxide and the fourth oxide each have a region where the film thickness is 1 nm or more and 3 nm or less.

[0014] Also, in the above, it is preferable that the third oxide and the fourth oxide each contain gallium.

[0015] Also, in the above, the third oxide and the fourth oxide may each have crystallinity.

[0016] Also, in the above, the second oxide may have crystallinity.

[0017] Also, in the above, the first oxide, the third oxide, the fourth oxide, and the fifth oxide may have substantially the same composition.

Advantages of the Invention

[0018] According to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Or ​​​​​, according to one aspect of the present invention, a semiconductor device having high frequency characteristics can be provided. Or, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Also or, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided . Or, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided . Or, according to one aspect of the present invention, a highly productive semiconductor device can be provided .

[0019] Or, a semiconductor device capable of retaining data over a long period can be provided. Also or, a semiconductor device with a high data writing speed can be provided. Or, a semiconductor device with a high design freedom can be provided. Or, a semiconductor device capable of suppressing power consumption can be provided . Or, a novel semiconductor device can be provided .

[0020] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims , etc.

Brief Description of the Drawings

[0021]

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Best Mode for Carrying Out the Invention

[0022] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

[0023] Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Note that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, etc. may unintentionally decrease due to processes such as etching, but may not be reflected in the figures for ease of understanding. Also, in the drawings, the same reference numerals are commonly used for the same part or parts having the same function among different drawings, and the repeated description may be omitted. Also, in cases where the same function is indicated, the hatching patterns may be the same and may not be particularly labeled.

[0024] Also, particularly in top views (also referred to as "plan views") and perspective views, etc., for ease of understanding the invention, the description of some components may be omitted. Also, the description of some hidden lines, etc. may be omitted.

[0025] Also, in this specification, etc., ordinal numbers such as first, second, etc. are used for convenience and do not indicate the process order or stacking order. Therefore, for example, "the first" can be "the second" It can be described by appropriately replacing it with, for example, "first", "second", or "third". Also, in this specification and the like, the ordinal numbers described in the present specification and the ordinal numbers used to specify an aspect of the present invention may not match.

[0026] In addition, in this specification and the like, terms indicating arrangements such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0027] For example, in this specification and the like, when it is explicitly described that X and Y are connected, it is disclosed in this specification and the like that the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are all included. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also considered to be disclosed in the figure or the text. Here, it is assumed that X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films,

[0028] layers, etc.). layers, etc.).

[0029] Also, the functions of the source and drain may be interchanged when transistors of different polarities are employed or when the direction of the current changes during circuit operation. For this reason, in this specification and the like, the terms source and drain may be used interchangeably in some cases.

[0030] ​In the present specification and the like, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter also referred to as "effective channel width") and the channel width shown in the top view of the transistor (hereinafter also referred to as "apparent channel width") may be different. For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may become larger than the apparent channel width, and there may be a case where the influence cannot be ignored. For example, in a fine transistor where the gate electrode covers the side surface of the semiconductor, the ratio of the channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width. In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. In the present specification, when simply described as "channel width", it may refer to the apparent channel width. Or, in the present specification, when simply described as "channel width", it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like. Note that the semiconductor impurities refer to, for example, components other than the main components constituting the semiconductor. For example, the concentration

[0031]

[0032]

[0033] Elements with a degree of less than 0.1 atomic % can be regarded as impurities. When impurities are included, for example, the DOS (Density of States) of the semiconductor increases, or the crystallinity becomes low and the like may occur. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component of the oxide semiconductor. For example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, water may also function as an impurity. Also, in the case of an oxide semiconductor, for example oxygen vacancies may be formed due to the incorporation of impurities. Also, when the semiconductor is silicon impurities that change the characteristics of the semiconductor include, for example, Group 1 elements excluding oxygen and hydrogen , Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0034] In addition, in this specification and the like, silicon oxynitride means that, in terms of its composition, the oxygen content is higher than the nitrogen content. Also, silicon nitride oxide means that, in terms of its composition, the nitrogen content is higher than the oxygen content.

[0035] In addition, in this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer . Also, the term "conductor" can be replaced with a conductive film or a conductive layer . Also, the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer .

[0036] In addition, in this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less degrees. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also In addition, "substantially parallel" means a state where two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" means a state where two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. "Substantially perpendicular" means a state where two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0037] In addition, in this specification, a barrier film is a film having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. When the barrier film has conductivity, it may be called a conductive barrier film.

[0038] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS). For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when described as an OS FET or an OS transistor, it can be paraphrased as a transistor having an oxide or an oxide semiconductor.

[0039] In addition, in this specification and the like, normally-off means that when no potential is applied to the gate or the gate is given a ground potential, the current per 1 μm of the channel width flowing through the transistor is 1 × 10 A or less at room temperature, 1 × 10 -20 A or less at 85 °C, or -18 1 × 10 -16 A or less at 125 °C. ​​​​​​​​

[0040] (Embodiment 1) Hereinafter, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention will be described.

[0041] <Configuration Example of Semiconductor Device> FIGS. 1(A), 1(B), and 1(C) are top views and cross-sectional views of a transistor 2 00 and the periphery of the transistor 200 according to one aspect of the present invention.

[0042] FIG. 1(A) is a top view of a semiconductor device having a transistor 200. Also, FIG. 1( B) and FIG. 1(C) are cross-sectional views of the semiconductor device. Here, FIG. 1(B) is a cross-sectional view of the part indicated by the dashed line A1 - A2 in FIG. 1(A), and is also a cross-sectional view in the channel length direction of the transistor 200. Further, FIG. 1(C) is a cross-sectional view of the part indicated by the dashed line A3 - A4 in FIG. 1(A) and is also a cross-sectional view in the channel width direction of the transistor 200. Note that, in the top view of FIG. 1(A), some elements are omitted for clarity of the drawing.

[0043] A semiconductor device according to one aspect of the present invention includes an insulator 214 on a substrate (not shown), a transistor 200 on the insulator 21 4, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 274 on the insulator 282, and an insulator 281 on the insulator 274 . The insulator 214, the insulator 280, the insulator 282, the insulator 274, and the insulator 281 function as interlayer films. It also has a conductor 240 (conductor 240a and conductor 240b) that is electrically connected to the transistor 200 and functions as a plug. Note that an insulator 241 (insulator 241a and ) is in contact with the side surface of the conductor 240 that functions as a plug. A calling insulator 241b) is provided. Also, on the insulator 281 and on the conductor 240, a conductor 246 (conductor 246a, and conductor 246b) that is electrically connected to the conductor 240 and functions as wiring is provided.

[0044] Also, an insulator 241a is provided in contact with the inner walls of the openings of the insulators 272, insulator 273, insulator 280, insulator 282, insulator 274, and insulator 281, and a first conductor of the conductor 240a is provided in contact with its side surface, and a second conductor of the conductor 240a is further provided inside. Also, an insulator 241b is provided in contact with the inner walls of the openings of the insulators 272, insulator 273, insulator 280, insulator 282, insulator 274, and insulator 281, and a first conductor of the conductor 240b is provided in contact with its side surface, and a second conductor of the conductor 240b is further provided inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be made approximately the same. In the transistor 200, a configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are laminated is shown, but the present invention is not limited to this. For example, the conductor 240 may be provided in a single-layer or laminated structure of three or more layers. When the structure has a laminated structure, ordinal numbers may be assigned in the order of formation to distinguish them. In the transistor 200, a configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are laminated is shown, but the present invention is not limited to this. For example, the conductor 240 may be provided in a single-layer or laminated structure of three or more layers. When the structure has a laminated structure, ordinal numbers may be assigned in the order of formation to distinguish them. For example, the conductor 240 may be provided in a single-layer or laminated structure of three or more layers. When the structure has a laminated structure, ordinal numbers may be assigned in the order of formation to distinguish them.

[0045] [Transistor 200] As shown in FIG. 1, the transistor 200 includes an insulator 216 on the insulator 214, and a conductor 205 (conductor 205a and conductor 2 05b) arranged to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, and an insulator 222 on the insulator 222 Insulator 224, oxide 230a on insulator 224, and oxide 23 0b, oxide 243a and oxide 243b on oxide 230b, and on oxide 243a Conductor 242a, conductor 242b on oxide 243b, and oxide on oxide 230b 230c, insulator 250 on oxide 230c, located on insulator 250, and oxide 23 0c overlapping conductor 260 (conductor 260a and conductor 260b), and insulator 224 Part of the upper surface of, side surface of oxide 230a, side surface of oxide 230b, side surface of oxide 243a, Side surface of oxide 243b, side surface of conductor 242a, upper surface of conductor 242a, conductor 242b Side surface of, and upper surface of, and insulator 272 in contact with the upper surface of conductor 242b Insulator 273 on insulator 272, and having. Also, oxide 230c is in contact with the side surfaces of oxide 243a, oxide 243b Side surfaces of, side surface of conductor 242a, and side surface of conductor 242b respectively. Conductor 2 60 has conductor 260a and conductor 260b, and conductor 260a is arranged so as to wrap the bottom surface and side surface Of conductor 260b. Here, as shown in FIG. 1(B), the upper surface of conductor 2 60 is arranged substantially flush with the upper surface of insulator 250 and the upper surface of oxide 230c And insulator 282 is in contact with the upper surfaces of conductor 260, oxide 230c, insulator 250, and insulator 280 respectively.

[0046] Also, insulators 222, 272, 273, and 282 preferably have a function of suppressing the diffusion of hydrogen (for example, At least one of a hydrogen atom, a hydrogen molecule, etc.). Also, insulators 222, 272, 273, and 282 have a function of suppressing the diffusion of acid For example, at least one of an oxygen atom, an oxygen molecule, etc.) Function to suppress diffusion. is preferable. For example, insulator 222, insulator 272, insulator 273, and insulator 28 2 each preferably have lower permeability to one or both of oxygen and hydrogen than insulator 224 . Insulator 222, insulator 272, insulator 273, and insulator 282 each preferably have lower permeability to one or both of oxygen and hydrogen than insulator 250 . Insulator 222, insulator 272, insulator 273, and insulator 282 each preferably have lower permeability to one or both of oxygen and hydrogen than insulator 280 . As shown in FIG. 1(B), insulator 272 preferably contacts the upper and side surfaces of conductor 242a, the upper and side surfaces of conductor 24 2b, the side surface of oxide 243a, the side surface of oxide 243b, the side surface of oxide 230a, the side surface of oxide 230b, and the upper surface of insulator 224. Further,

[0047] it is preferable that insulator 273 is provided in contact with insulator 272. Thereby, insulator 280 is separated from insulator 224 and oxide 230 by insulator 272 and insulator 273. Also, oxide 230 preferably includes oxide 230a on insulator 224, oxide 230b on oxide 230a, and oxide 230c disposed on oxide 230b and at least partially in contact with the upper surface of oxide 230b.

[0048] Note that in transistor 200, a region where a channel is formed (hereinafter also referred to as a channel formation region .) and in the vicinity thereof, a configuration in which three layers of oxide 230a, oxide 230b, and oxide 2 30c are laminated is shown, but the present invention is not limited thereto

[0049] . For example, a single layer of oxide 230b, a two-layer structure of oxide 230b and oxide 230a, The structure may be a two-layer structure of the substrate 230b and the oxide 230c, or a laminate structure of four or more layers. In addition, in the transistor 200, the conductor 260 is shown as having a two-layer structure. However, the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure. Alternatively, it may have a laminated structure of three or more layers.

[0050] Here, the conductor 260 functions as a gate electrode of the transistor, and the conductors 242a and and the conductor 242b function as a source electrode and a drain electrode, respectively. The transistor 200 has a conductor 260 that functions as a gate electrode formed on an insulator 280 or the like. The conductor 260 is formed in a self-aligned manner so as to fill the opening. Thus, the conductor 260 is aligned in the region between the conductors 242a and 242b. The arrangement can be ensured without any distortion.

[0051] The transistor 200 also includes an oxide 230 (oxide 230a) including a channel formation region. , oxide 230b, and oxide 230c) are metal oxides that function as oxide semiconductors. It is preferable to use an oxide semiconductor (hereinafter also referred to as an oxide semiconductor).

[0052] The transistor 200 having an oxide semiconductor in a channel formation region is in a non-conducting state. Since the leakage current (off-state current) is extremely small, a semiconductor device with low power consumption can be provided. In addition, oxide semiconductors can be formed into films by sputtering or the like, and therefore are suitable for use as highly integrated semiconductors. It can be used for the transistor 200 that constitutes the device.

[0053] For example, as the oxide 230, an In-M-Zn oxide (element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) and other metal oxides may be used. In particular, element M is preferably aluminum, gallium, yttrium, or tin. Also, as the oxide 230, an In-Ga oxide or an In-Zn oxide may be used. The oxide 230 has an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. By having the oxide 230a under the oxide 230b, the diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed. Also, by having the oxide 230c on the oxide 230b, the diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed. It should be noted that the oxide 230 preferably has a laminated structure with oxides having different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 230b. Also, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Also, for the oxide 230b, ) etc. Furthermore, the oxide 230 may have an In-Ga oxide or an In-Zn oxide.

[0054] In this way, the diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed. Also, by having the oxide 230c on the oxide 230b, the diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.

[0055] In addition, the oxide 230 preferably has a laminated structure with oxides having different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 230b. Also, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Also, for the oxide 230b, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 230b. Also, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Also, for the oxide 230b, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Also, for the oxide 230b, ​​​​​​​​In the metal oxide to be used, the atomic ratio of In to element M is preferably higher than the atomic ratio of In to element M in the metal oxide used for the oxide 230a. Also, in the metal oxide, it is preferably higher than the atomic ratio of In to element M. Also, the oxide 230c can be the metal oxide that can be used for the oxide 230a or the oxide 230b.

[0056] Also, the oxide 230b preferably has crystallinity. For example, it is preferable to use CAAC -OS (c-axis aligned crystalline oxide sem iconductor). Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen deficiencies) and have a dense structure with high crystallinity. Therefore, oxygen extraction from the oxide 230b by the source electrode or the drain electrode can be suppressed. As a result, even when heat treatment is performed, oxygen extraction from the oxide 230b can be reduced, so the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0057] Also, the energy of the lower end of the conduction band of the oxide 230a and the oxide 230c is preferably higher than the energy of the lower end of the conduction band of the oxide 230b. In other words, the electron affinity of the oxide 230a and the oxide 230c is preferably smaller than the electron affinity of the oxide 230b.

[0058] Here, at the junction of the oxide 230a, the oxide 230b, and the oxide 230c, the energy level of the lower end of the conduction band changes smoothly. In other words, the energy level of the lower end of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c is continuous. ​​​​​​​​​ It can also be said to change continuously or be continuously joined. To do this, the defect level density of the mixed layer formed at the interface between oxide 230a and oxide 230b and at the interface between oxide 230b and oxide 230c

[0059] should be lowered. Specifically, as oxide 230a, a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio] or 1:1:0.5 [atomic ratio] may be used. Also, as oxide 230b, a metal oxide with In:Ga:Zn = 4:2:3 [atomic ratio] or 1:1:1 [atomic ratio] may be used. Further, as oxide 230c, a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio], Ga:Zn = 2:1 [atomic ratio], or Ga:Zn = 2:5 [atomic ratio] may be used. Also, specific examples when oxide 230c has a laminated structure include a laminated structure of In:Ga:Zn = 1:3:4 [atomic ratio] and In:Ga:Zn = 4:2:3 [atomic ratio], a laminated structure of Ga:Zn = 2:1 [atomic ratio] and In:Ga:Zn = 4 :2:3 [atomic ratio], a laminated structure of Ga:Zn = 2:5 [atomic ratio] and In:Ga:Zn = 4:2:3 [atomic ratio], a laminated structure of gallium

[0060] oxide and In:Ga:Zn = 4:2:3 [atomic ratio], etc. At this time, the main path of carriers is oxide 230b. By configuring oxide 230a and oxide 230c as described above, the defect level density at the interface between oxide 230a and oxide 230b and at the interface between oxide 230b and oxide 230c It is possible to obtain an ion current and high frequency characteristics.

[0061] The oxide 230 preferably uses a metal oxide that functions as an oxide semiconductor. For example, those having an energy gap of 2 eV or more, preferably 2.5 eV or more are preferably used. By using a metal oxide with a large energy gap in this way, the off-current of the transistor can be reduced. By using such a transistor, a low-power semiconductor device can be provided.

[0062] The electron affinity or the energy level Ec at the lower end of the conduction band is, as shown in Fig. 12, the ionization potential Ip which is the difference between the vacuum level Evac and the energy Ev at the upper end of the valence band, and can be obtained from the energy gap Eg. The ionization potential Ip can be measured, for example, using an ultraviolet photoelectron spectroscopy (UPS) device. The energy gap Eg can be measured, for example, using a spectroscopic ellipsometer.

[0063] In addition, in a transistor using an oxide semiconductor, if impurities and oxygen deficiencies exist in the region where the channel in the oxide semiconductor is formed, the electrical characteristics tend to fluctuate and the reliability may deteriorate. Also, if the region where the channel in the oxide semiconductor is formed contains oxygen deficiencies, the transistor tends to have normally-on characteristics. Therefore, it is preferable that the oxygen deficiencies in the region where the channel is formed are reduced as much as possible. For example, oxygen can be supplied to the oxide 230 through an insulator 250 or the like to It is possible to provide a transistor that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

[0064] In addition, when the conductor disposed near the oxide semiconductor is made of a metal or an alloy, the conductor may be oxidized by oxygen atoms constituting the oxide semiconductor. When the conductivity of the conductor decreases due to oxidation, there is a high probability of causing variations in the electrical characteristics of the semiconductor device and a decrease in reliability.

[0065] Here, with reference to FIGS. 13 to 15, the oxidation reaction of a structure made of a metal or an alloy in contact with an oxide semiconductor by oxygen atoms of the oxide semiconductor will be described. Hereinafter, specifically, the oxidation reaction in the case of using indium-gallium-zinc oxide as the oxide semiconductor and tantalum nitride as the conductor will be described.

[0066] FIG. 13(A) shows a region near the interface in a cross-section of a laminate of an oxide semiconductor 10 made of indium-gallium-zinc oxide and a conductor 20 made of tantalum nitride. In the figure, black circles shown in each structure indicate oxygen atoms. Also, white circles shown in the oxide semiconductor 10 indicate oxygen vacancies generated in the oxide semiconductor.

[0067] FIG. 13(B) shows an initial process of the oxidation reaction of the conductor 20. In the conductor 20, a region where oxygen is dissolved at a low concentration is shown as an oxygen solid solution region 22. Also, FIG. 13(C) shows a growth process of the oxide 30 generated by the oxidation reaction of the conductor 20.

[0068] First, with reference to FIG. 14, the initial process of the oxidation reaction of the conductor 20 will be described. In the figure, the arrow ​​​​​​​​​​​​indicates the moving direction of oxygen atoms. In the initial process of the oxidation reaction of the conductor 20, it is speculated that the metal atom tantalum at the interface of the conductor 20 interacts with the oxygen ions at the interface of the oxide semiconductor 10. As shown in FIG. 14(A), when the oxygen ions indicated by the black circles in the figure reach the interface between the oxide semiconductor 10 and the conductor 20, they adsorb to the metal atom tantalum at the interface of the conductor 20.

[0069] As shown in FIG. 14(B), when heat treatment is performed with the oxygen ions adsorbed to the metal atom tantalum, the oxygen ions diffuse into the interior of the conductor 20, and an oxygen solid solution region 22 is formed inside the tantalum nitride (see FIG. 14(B)). At the time when the oxygen solid solution region 22 is formed, the oxidation reaction has not yet occurred, and the oxygen ions are in a state of being solid-solved as impurities in the interior of the conductor 20. Further, when the oxygen ions diffuse into the conductor 20, oxygen deficiency may temporarily occur at the interface of the oxide semiconductor 10.

[0070] It is presumed that the capacity of the conductor 20 to solid-solve oxygen depends on the crystallinity or density of the conductor 20. Also, when the oxygen ions at the interface of the oxide semiconductor 10 are solid-solved in the conductor 20, the oxygen atoms in the interior of the oxide semiconductor 10 fill the oxygen deficiency generated at the interface of the oxide semiconductor 10 (see FIG. 14(C)). As shown in FIG. 14(A) to FIG. 14(C) are repeated, the oxygen concentration in the oxygen solid solution region 22 increases. Here, when the solid solution of oxygen in the oxygen solid solution region 22 reaches saturation, the oxidation of the metal atom tantalum in the oxygen solid solution region 22 starts. Therefore, as shown in FIG. 14(D), When the oxygen solid solution region 22 is formed, the oxidation reaction has not yet occurred, and the oxygen ions are in a state of being solid-solved as impurities in the interior of the conductor 20. Also, when the oxygen ions diffuse into the conductor 20, oxygen deficiency may temporarily occur at the interface of the oxide semiconductor 10. It is presumed that the capacity of the conductor 20 to solid-solve oxygen depends on the crystallinity or density of the conductor 20. Also, when the oxygen ions at the interface of the oxide semiconductor 10 are solid-solved in the conductor 20, the oxygen atoms in the interior of the oxide semiconductor 10 fill the oxygen deficiency generated at the interface of the oxide semiconductor 10 (see FIG. 14(C)). As shown in FIG. 14(A) to FIG. 14(C) are repeated, the oxygen concentration in the oxygen solid solution region 22 increases. Here, when the solid solution of oxygen in the oxygen solid solution region 22 reaches saturation, the oxidation of the metal atom tantalum in the oxygen solid solution region 22 starts. Therefore, as shown in FIG. 14(D), It is presumed that the capacity of the conductor 20 to solid-solve oxygen depends on the crystallinity or density of the conductor 20. Also, when the oxygen ions at the interface of the oxide semiconductor 10 are solid-solved in the conductor 20, the oxygen atoms in the interior of the oxide semiconductor 10 fill the oxygen deficiency generated at the interface of the oxide semiconductor 10 (see FIG. 14(C)).

[0071] It is presumed that the capacity of the conductor 20 to solid-solve oxygen depends on the crystallinity or density of the conductor 20. Also, when the oxygen ions at the interface of the oxide semiconductor 10 are solid-solved in the conductor 20, the oxygen atoms in the interior of the oxide semiconductor 10 fill the oxygen deficiency generated at the interface of the oxide semiconductor 10 (see FIG. 14(C)). As shown in FIG. 14(A) to FIG. 14(C) are repeated, the oxygen concentration in the oxygen solid solution region 22 increases. Here, when the solid solution of oxygen in the oxygen solid solution region 22 reaches saturation, the oxidation of the metal atom tantalum in the oxygen solid solution region 22 starts. Therefore, as shown in FIG. 14(D), It is presumed that the capacity of the conductor 20 to solid-solve oxygen depends on the crystallinity or density of the conductor 20. Also, when the oxygen ions at the interface of the oxide semiconductor 10 are solid-solved in the conductor 20, the oxygen atoms in the interior of the oxide semiconductor 10 fill the oxygen deficiency generated at the interface of the oxide semiconductor 10 (see FIG. 14(C)). As shown in FIG. 14(A) to FIG. 14(C) are repeated, the oxygen concentration in the oxygen solid solution region 22 increases. Here, when the solid solution of oxygen in the oxygen solid solution region 22 reaches saturation, the oxidation of the metal atom tantalum in the oxygen solid solution region 22 starts. Therefore, as shown in FIG. 14(D),

[0072] By repeating the processes shown in FIGS. 14(A) to 14(C), the oxygen concentration in the oxygen solid solution region 22 increases. Here, when the solid solution of oxygen in the oxygen solid solution region 22 reaches saturation, the oxidation of the metal atom tantalum in the oxygen solid solution region 22 starts. Therefore, as shown in FIG. 14(D), When the solid solution of oxygen in the oxygen solid solution region 22 reaches saturation, the oxidation of the metal atom tantalum in the oxygen solid solution region 22 starts. Therefore, as shown in FIG. 14(D), When the solid solution of oxygen in the oxygen solid solution region 22 reaches saturation, the oxidation of the metal atom tantalum in the oxygen solid solution region 22 starts. Therefore, as shown in FIG. 14(D), An oxide 30 containing tantalum oxide is formed between the oxide semiconductor 10 and the conductor 20. .

[0073] In the initial process of the oxidation reaction of a metal, generally, nucleation of an oxide occurs. On the other hand, since the heat in the manufacturing process of a semiconductor device using an oxide semiconductor is relatively low temperature, it is presumed that an amorphous oxide thin film is formed at the interface between the oxide semiconductor 10 and the conductor 20.

[0074] Subsequently, with reference to FIG. 15, the growth process of the oxide 30 generated between the oxide semiconductor 10 and the conductor 20 will be described. When the oxide 30 is generated, the interface between the oxide 30 and the oxide semiconductor 10 becomes a state where oxygen is deficient and the concentration of oxygen vacancies is high. That is, it is considered that a concentration gradient of oxygen vacancies is generated in the oxide semiconductor 10.

[0075] Therefore, as shown in FIGS. 15(A) to 15(C), in the oxide semiconductor 10, in order to equalize the concentration of oxygen vacancies, oxygen ions inside the oxide semiconductor 10 diffuse. It is considered that the oxygen ions reach the interface with the oxide 30 (see FIG. 15(A)). Furthermore, the reached oxygen ions are used for the growth reaction of tantalum oxide that the oxide 30 has, and the oxide 30 grows in thickness (see FIGS. 15(B) and 15(C)).

[0076] In the oxide 30 having tantalum oxide, when the influence of defects at the interface is not considered, generally, the oxidation reaction depends on the diffusion rates of metal and oxygen ions in the thin film of the oxide 30.

[0077] Therefore, due to the diffusion of oxygen ions, inside the oxide semiconductor 10 and the oxide 30, ​​​​​​​​​​A gradient in oxygen concentration occurs. In that case, it can be inferred that the diffusion rate of oxygen ions in the oxide 30 becomes a factor determining the growth rate of tantalum oxide in the oxide 30. In the case of oxygen ions, they diffuse within the tantalum oxide of the oxide 30 and reach the interface between the oxide 30 and the conductor 20, whereupon new tantalum oxide is generated, and it is considered that film growth of the oxide 30 occurs. Also, in the growth process of this oxidation reaction, it is considered that the oxygen solid solution region 22 of the conductor 20 expands into the interior of the conductor 20. In order to suppress the oxidation reaction of the conductor as described above, the transistor 20 0 according to one aspect of the present invention, as shown in FIG. 1(B), between the oxide 230b and the conductor 242 (conductor 242a and conductor 242b) functioning as a source electrode or a drain electrode, an oxide 24

[0078] 3 (oxide 243a and oxide 243b) is disposed. Since the conductor 242 and the oxide 230 are not in contact, it is possible to suppress the conductor 242 from absorbing the oxygen of the oxide 230. That is, by preventing the oxidation of the conductor 242, it is possible to suppress a decrease in the conductivity of the conductor 242. Therefore, the oxide 243 preferably has a function of suppressing the oxidation of the conductor 242. That is, by preventing the oxidation of the conductor 242, it is possible to suppress a decrease in the conductivity of the conductor 242. Therefore, the oxide 243 preferably has a function of suppressing the oxidation of the conductor 242. Since the conductor 242 and the oxide 230 are not in contact, it is possible to suppress the conductor 242 from absorbing the oxygen of the oxide 230. That is, by preventing the oxidation of the conductor 242, it is possible to suppress a decrease in the conductivity of the conductor 242. Therefore, it is preferable that the oxide 243 has a function of suppressing the oxidation of the conductor 242. Therefore, it is preferable that the oxide 243 has a function of suppressing the oxidation of the conductor 242.

[0079] Therefore, it is preferable that the oxide 243 has a function of suppressing oxygen permeation. By disposing an oxide 243 having a function of suppressing oxygen permeation between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b is reduced, which is preferable. By adopting such a configuration, the electrical characteristics of the transistor 200 and the reliability of the transistor 200 can be improved. Therefore, it is preferable that the oxide 243 has a function of suppressing oxygen permeation. By disposing an oxide 243 having a function of suppressing oxygen permeation between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b is reduced, which is preferable. By adopting such a configuration, the electrical characteristics of the transistor 200 and the reliability of the transistor 200 can be improved. Therefore, it is preferable that the oxide 243 has a function of suppressing oxygen permeation. By disposing an oxide 243 having a function of suppressing oxygen permeation between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b is reduced, which is preferable. By adopting such a configuration, the electrical characteristics of the transistor 200 and the reliability of the transistor 200 can be improved.

[0080] As the oxide 243, a metal oxide containing the element M may be used. In particular, as the element M, aluminum, gallium, yttrium, or tin may be used. It is preferable that the concentration of the element M in the oxide 243 is higher than that in the oxide 230b. Further, as the oxide 243, gallium oxide may be used. Further, as the oxide 243, a metal oxide such as an In-M-Zn oxide may be used. Specifically, in the metal oxide used for the oxide 243, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Further, the film thickness of the oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less. Further, the oxide 243 preferably has crystallinity. When the oxide 243 has crystallinity, the release of oxygen in the oxide 230 can be suitably suppressed. For example, if the oxide 243 has a crystal structure such as a hexagonal crystal, the release of oxygen in the oxide 230 may be suppressed. In one aspect of the present invention, the transistor 200 has a structure in which the insulator 282 and the insulator 250 are in direct contact as shown in FIGS. 1(B) and 1(C). By adopting such a structure, it becomes difficult for oxygen contained in the insulator 280 to be absorbed by the conductor 260. Therefore, the oxygen contained in the insulator 280 can be efficiently injected into the oxide 230a and the oxide 230b via the oxide 230c, so that the oxygen deficiency in the oxide 230a and the oxide 230b can be reduced, and the electrical characteristics and reliability of the transistor 200 can be improved. Further, impurities such as hydrogen contained in the insulator 280 are prevented from mixing into the insulator 250.

[0081] ​ Since it is possible to suppress this, adverse effects on the electrical characteristics and reliability of the transistor 200 can be suppressed. As the insulator 282, silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide can be used.

[0082] The insulator 272 and the insulator 273 preferably have a function of suppressing the permeation of impurities such as hydrogen and water and oxygen.

[0083] FIG. 3(A) is an enlarged view of a cross section of a portion indicated by a one-dot chain line of A5 - A6 in FIG. 1(A), and is also a cross-sectional view in the channel width direction of the source region or the drain region of the transistor 200. As shown in FIG. 3(A), the upper surface of the conductor 242b, the side surface of the conductor 242b, the side surface of the oxide 230a, and the side surface of the oxide 230b are covered with the insulator 272 and the insulator 273, so that diffusion of impurities such as hydrogen and water and oxygen into the conductor 242b from the side surface direction of the conductor 242b and the upper surface direction of the conductor 242b can be suppressed. Also, the lower surface of the conductor 242b has a structure in contact with the oxide 243b, and oxygen in the oxide 230b is blocked by the oxide 243b and thus diffusion into the conductor 242b is suppressed. Therefore, diffusion of oxygen into the conductor 242b from around the conductor 242b can be suppressed, so that oxidation of the conductor 242b can be suppressed. Note that the conductor 242 a has the same effect. Also, diffusion of impurities such as hydrogen and water into the oxide 230a and the oxide 230b from the side surface direction of the oxide 230a and the side surface direction of the oxide 230b can be suppressed. As the insulator 272, for example, aluminum oxide, hafnium oxide Umm, gallium oxide, indium gallium zinc oxide, silicon oxide film, silicon nitride film , or a silicon oxynitride film can be used. Further, as the insulator 273, for example , aluminum oxide or hafnium oxide can be used.

[0084] FIG. 3(B) is an enlarged view of the right half of the transistor 200 in FIG. 1(B). The conductor The left side surface of 240b (the portion surrounded by the dotted line in FIG. 3(B).) is in contact with the oxide 230c, and diffusion of impurities such as hydrogen and water and oxygen from the insulator 250 into the conductor 240b can be suppressed. Further, the right side surface of the conductor 240b is in contact with the insulator 272, and diffusion of impurities such as hydrogen and water and oxygen from the insulator 280 into the conductor 240b can be suppressed. Note that the conductor 240a also has the same effect. By configuring the insulator 272, the oxide 230c, and the oxide 243b to have a function of suppressing the permeation of impurities such as hydrogen and water and oxygen around the conductor 242b as described above, oxidation of the conductor 240 can be suppressed, and the electrical characteristics of the transistor 200 and the reliability of the transistor 200 can be improved.

[0085] Further, as shown in FIG. 1(C), with respect to the bottom surface of the insulator 224, the bottom surface of the conductor 260 in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 is preferably lower than the height of the bottom surface of the oxide 230b. Also, the height of the bottom surface of the conductor 260 in the region where the oxide 230b does not overlap with the conductor 260 and the oxide 2 By forming a structure surrounded by the insulator 272, the oxide 230c, and the oxide 243b that has a function of suppressing the permeation of impurities such as hydrogen and water and oxygen around the conductor 240, oxidation of the conductor 240 can be suppressed, and the electrical characteristics and reliability of the transistor 200 can be improved.

[0086] Further, as shown in FIG. 1(C), with reference to the bottom surface of the insulator 224, the bottom surface of the conductor 260 in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 is preferably lower than the height of the bottom surface of the oxide 230b. Also, the height of the bottom surface of the conductor 260 in the region where the oxide 230b does not overlap with the conductor 260 and the oxide 2 The height of the bottom surface of the conductor 260 in the region where the oxide 230b and the conductor 260 do not overlap, and the oxide 2 The height of the bottom surface of the conductor 260 in the region where the oxide 230b and the conductor 260 do not overlap, and the oxide 2 The difference between the height of the bottom surface of 30b and is 0 nm or more and 100 nm or less, preferably 3 nm or more and 5 0 nm or less, more preferably 5 nm or more and 20 nm or less.

[0087] In this way, the conductor 260 that functions as a gate electrode covers the side surface and the upper surface of 30b via the oxide 230c and the insulator 250, resulting in a configuration that makes it easier for the electric field of the conductor 260 to act on the entire oxide 230b in the channel formation region. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.

[0088] As described above, a semiconductor device having a transistor with a large on-current can be provided. Or, a semiconductor device having a transistor with high frequency characteristics can be provided. Or, a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability can be provided. Or, a semiconductor device having a transistor with a small off-current can be provided.

[0089] Hereinafter, the detailed configuration of the semiconductor device having the transistor 200 according to one aspect of the present invention will be described.

[0090] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably provided embedded in the insulator 214 and the insulator 216.

[0091] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. In addition, the conductor 205 functions as a second gate (also referred to as a bottom gate) electrode. ​​​​​It may function in this way. In that case, by changing the potential applied to the conductor 205 independently without linking it to the potential applied to the conductor 260, the Vth of the transistor 200 can be controlled. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be made greater than 0 V, making it possible to reduce the off-current. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be made smaller than when no potential is applied.

[0092] Note that, as shown in Fig. 1(A), the conductor 205 is preferably provided to be larger than the size of the region that does not overlap with the conductors 242a and 242b of the oxides 230a and 230 b. In particular, as shown in Fig. 1(C), the conductor 205 preferably extends also in the region outside the end portion intersecting with the channel width direction of the oxides 230a and the oxide 230b. That is, outside the sides in the channel width direction of the oxides 230a and 230b, it is preferable that the conductor 205 and the conductor 260 overlap with each other via an insulator. Alternatively, by providing the conductor 205 to be large, in the process using plasma in the manufacturing process after the formation of the conductor 205, local charging (also called charge accumulation ) may be alleviated. However, one aspect of the present invention is not limited to this. The conductor 205 only needs to overlap with the oxides 230a and 230b located at least between the conductor 242a and the conductor 242b.

[0093] By having the above configuration, the electric field of the conductor 260 having the function as the first gate electrode ​​​​​​​​and, by the electric field of the conductor 205 having a function as a second gate electrode, the channel formation region can be electrically surrounded. In this specification, the structure of a transistor that electrically surrounds the channel formation region by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0094] Further, the conductor 205a is preferably a conductor that suppresses the permeation of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. Also, the conductor 205b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 205 is illustrated as a two-layer structure, it may be a multilayer structure of three or more layers.

[0095] An example in which the conductor 205 is a five-layer structure is shown in FIG. 2. The conductor 205c is formed in contact with the inner wall of the opening of the insulator 216, and the conductor 205d is further formed inside. Also, the conductor 205e is formed inside the conductor 205d. Further, the conductor 205f is formed in contact with the inner wall of the conductor 205d and in contact with the upper surface of the conductor 205e, and the conductor 205g is formed inside the conductor 205f. Here, the heights of the upper surfaces of the conductors 205c, 205d, 205f, and 205g can be made approximately the same as the height of the upper surface of the insulator 216. Also, the conductor 205c is preferably made of the same material as the conductor 205a, and the conductors 205e and 205g are preferably made of the same material as the conductor 205b.

[0096] ​​​​​​​​​​​​​​Here, by continuously forming different film species of an oxide semiconductor, an insulator or a conductor located under the oxide semiconductor, and an insulator or a conductor located above the oxide semiconductor without exposing them to the atmosphere, it is preferable because an oxide semiconductor film with a substantially high degree of purity and a reduced concentration of impurities (particularly, hydrogen and water) can be formed. For example, using a film forming apparatus having six processing chambers, an insulating film such as insulator 222 and insulator 224 disposed on insulator 216 and conductor 205, an oxide film such as oxide 230a, an oxide film such as oxide 230b, an oxide film such as oxide 243, and a conductive film such as conductor 242 may be continuously formed in order. Insulator 214, insulator 272, and insulator 281 preferably function as barrier insulating films that suppress the mixing of impurities such as water or hydrogen into transistor 200 from the substrate side or from above. Therefore, insulator 214, insulator 272, and insulator 281 preferably use an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (the above impurities are difficult to permeate). Or, it preferably uses an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). For example, it is preferable to use silicon nitride or the like as insulator 214, insulator 272, and insulator 281. Thereby, impurities such as water or hydrogen are less likely to enter the transistor 200 from the insulator 214 than from the substrate side or from above.

[0097] For example, using a film forming apparatus having six processing chambers, an insulating film such as insulator 222 and insulator 224 disposed on insulator 216 and conductor 205, an oxide film such as oxide 230a, an oxide film such as oxide 230b, an oxide film such as oxide 243, and a conductive film such as conductor 242 may be continuously formed in order. Insulator 214, insulator 272, and insulator 281 preferably function as barrier insulating films that suppress the mixing of impurities such as water or hydrogen into transistor 200 from the substrate side or from above. Therefore, insulator 214, insulator 272, and insulator 281 preferably use an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (the above impurities are difficult to permeate). Or, it preferably uses an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). For example, it is preferable to use silicon nitride or the like as insulator 214, insulator 272, and insulator 281. Thereby, impurities such as water or hydrogen are less likely to enter the transistor 200 from the insulator 214 than from the substrate side or from above. For example, using a film forming apparatus having six processing chambers, an insulating film such as insulator 222 and insulator 224 disposed on insulator 216 and conductor 205, an oxide film such as oxide 230a, an oxide film such as oxide 230b, an oxide film such as oxide 243, and a conductive film such as conductor 242 may be continuously formed in order.

[0098] Insulator 214, insulator 272, and insulator 281 preferably function as barrier insulating films that suppress the mixing of impurities such as water or hydrogen into transistor 200 from the substrate side or from above. Therefore, insulator 214, insulator 272, and insulator 281 preferably use an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (the above impurities are difficult to permeate). Or, it preferably uses an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). For example, it is preferable to use silicon nitride or the like as insulator 214, insulator 272, and insulator 281. Thereby, impurities such as water or hydrogen are less likely to enter the transistor 200 from the insulator 214 than from the substrate side or from above. Insulator 214, insulator 272, and insulator 281 preferably function as barrier insulating films that suppress the mixing of impurities such as water or hydrogen into transistor 200 from the substrate side or from above. Therefore, insulator 214, insulator 272, and insulator 281 preferably use an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (the above impurities are difficult to permeate). Or, it preferably uses an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). For example, it is preferable to use silicon nitride or the like as insulator 214, insulator 272, and insulator 281. Thereby, impurities such as water or hydrogen are less likely to enter the transistor 200 from the insulator 214 than from the substrate side or from above. Insulator 214, insulator 272, and insulator 281 preferably function as barrier insulating films that suppress the mixing of impurities such as water or hydrogen into transistor 200 from the substrate side or from above. Therefore, insulator 214, insulator 272, and insulator 281 preferably use an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (the above impurities are difficult to permeate). Or, it preferably uses an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). For example, it is preferable to use silicon nitride or the like as insulator 214, insulator 272, and insulator 281. Thereby, impurities such as water or hydrogen are less likely to enter the transistor 200 from the insulator 214 than from the substrate side or from above. Insulator 214, insulator 272, and insulator 281 preferably function as barrier insulating films that suppress the mixing of impurities such as water or hydrogen into transistor 200 from the substrate side or from above. Therefore, insulator 214, insulator 272, and insulator 281 preferably use an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (the above impurities are difficult to permeate). Or, it preferably uses an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). For example, it is preferable to use silicon nitride or the like as insulator 214, insulator 272, and insulator 281. Thereby, impurities such as water or hydrogen are less likely to enter the transistor 200 from the insulator 214 than from the substrate side or from above.

[0099] For example, it is preferable to use silicon nitride or the like as insulator 214, insulator 272, and insulator 281. Thereby, impurities such as water or hydrogen are less likely to enter the transistor 200 from the insulator 214 than from the substrate side or from above. For example, it is preferable to use silicon nitride or the like as insulator 214, insulator 272, and insulator 281. Thereby, impurities such as water or hydrogen are less likely to enter the transistor 200 from the insulator 214 than from the substrate side or from above. Diffusion from the board side to the transistor 200 side can be suppressed. Or, oxygen contained in the insulator 2 24 etc. can be suppressed from diffusing to the board side rather than the insulator 214. Also, impurities such as water or hydrogen are arranged above the insulator 272, and the insulator 280, and / or diffusion from the conductor 246 etc. to the transistor 200 side can be suppressed.

[0100] Also, it may be preferable to lower the resistivity of the insulator 214, the insulator 272, and the insulator 281. For example, by setting the resistivity of the insulator 214, the insulator 272, and the insulator 281 to approximately 1×10 Ωcm, in the process using plasma etc. in the semiconductor device manufacturing process, the insulator 214, the insulator 272, and the insulator 281 may be able to relax the charge-up of the conductor 205, the conductor 242 or the conductor 260. The resistivity of the insulator 13 214, the insulator 272, and the insulator 281 is preferably 1×10 Ωc m or more and 1×10 Ωcm or less. 10 Ωc m or more and 1×10 15 Ωcm or less.

[0101] Also, the insulator 214 may have a laminated structure. For example, it is suitable to use a laminated structure of an aluminum oxide film and a silicon nitride film for the insulator 214. By the aluminum oxide film, oxygen can be supplied below the insulator 214. Also, by the silicon nitride film, diffusion of impurities such as hydrogen and water diffusing from the board side to the transistor 200 side can be suppressed. Also, the insulator 216, the insulator 280, and the insulator 274 have a higher dielectric constant than the insulator 214. suppressed. can be.

[0102] Also, the insulator 216, the insulator 280, and the insulator 274 have a higher dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic For example, the capacitance of the insulator 216, the insulator 280, and the insulator 27 can be reduced. 4. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine silicon oxide doped with , silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen Silicon or silicon oxide having voids may be used appropriately.

[0103] The insulator 222 and the insulator 224 function as gate insulators.

[0104] Here, it is preferable that the insulator 224 in contact with the oxide 230 is heated to release oxygen. In this specification, the oxygen released by heating may be referred to as excess oxygen. The insulator 224 may be made of silicon oxide or silicon oxynitride as appropriate. By providing an insulator containing the oxide 230 in contact with the oxide 230, oxygen vacancies in the oxide 230 are reduced. Therefore, the reliability of the transistor 200 can be improved.

[0105] Specifically, the insulator 224 is made of an oxide material from which some oxygen is released when heated. The oxide that releases oxygen by heating is called TDS (Thermal Dynamics) oxide. The amount of oxygen molecules released was 1.0 ×10 18 molecules / cm 3 More than 1.0×10 19 molecu les / cm 3 More preferably, 2.0×10 19 molecules / cm 3 Below Above, or 3.0×10 20molecules / cm 3 It is the oxide film described above. Also, as the surface temperature of the film during the above TDS analysis, a range of 100°C or higher and 700°C or lower, or a range of 100°C or higher and 400°C or lower is preferable.

[0106] The insulator 222 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side. For example, the insulator 222 preferably has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the oxide 230, etc. with the insulator 222 and the insulator 27 2, it is possible to suppress the intrusion of impurities such as water or hydrogen from the outside into the transistor 200. Furthermore, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). (The above oxygen is difficult to permeate.) For example, the insulator 222 preferably has lower oxygen permeability than the insulator 224. Since the insulator 222 has a function of suppressing the diffusion of oxygen and impurities, it is possible to reduce the diffusion of the oxygen contained in the oxide 230 to the lower side of the insulator 222, which is preferable. Also, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the oxide 230.

[0107] The insulator 222 may be an insulator containing one or both of the oxides of aluminum and hafnium, which are insulating materials. As the insulator containing one or both of the oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. It is preferable that the insulator 222 has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). (The above oxygen is difficult to permeate.) For example, the insulator 222 preferably has lower oxygen permeability than the insulator 224. Since the insulator 222 has a function of suppressing the diffusion of oxygen and impurities, it is possible to reduce the diffusion of the oxygen contained in the oxide 230 to the lower side of the insulator 222, which is preferable. Also, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the oxide 230. Since the insulator 222 has a function of suppressing the diffusion of oxygen and impurities, it is possible to reduce the diffusion of the oxygen contained in the oxide 230 to the lower side of the insulator 222, which is preferable. Also, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the oxide 230. Furthermore, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the oxide 230. It is preferable that the insulator 222 has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). (The above oxygen is difficult to permeate.) For example, the insulator 222

[0108] The insulator 222 may be an insulator containing one or both of the oxides of aluminum and hafnium, which are insulating materials. As the insulator containing one or both of the oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. As the insulator containing one or both of the oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. As the insulator containing one or both of the oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. In this way, When the insulator 222 is formed using a certain material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 and the incorporation of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230.

[0109] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulators. Or these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the above insulators and used.

[0110] In addition, the insulator 222 may be a single layer or a laminate of an insulator containing a so-called high-k material such as, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As the transistor is miniaturized and highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0111] Note that the insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials is also acceptable.

[0112] On the oxide 230b, an oxide 243 is provided, and on the oxide 243, a source electrode, and a conductor 242 (conductor 242a and conductor 242 b) that functions as a drain electrode is provided. The film thickness of the conductor 242 is, for example, 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0113] As the conductor 242, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel lum, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium ium, lanthanum, or an alloy containing the above-described metal element as a component or an alloy combining the above-described metal elements is preferably used. For example, tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and al uminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium an oxide containing lanthanum and nickel, etc. are preferably used. Further, tantalum nitride titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum a nitride, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium an oxide, an oxide containing lanthanum and nickel are preferred because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when they absorb oxygen.

[0114] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230c. The insulator 250 is silicon oxide, silicon oxynitride nitrided silicon oxide, silicon nitride, silicon oxide with fluorine added, acid with carbon added Silicon oxide added with silicon, carbon and nitrogen, and silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0115] Similar to the insulator 224, the insulator 250 is preferably formed using an insulator that releases oxygen upon heating. By providing an insulator that releases oxygen upon heating as the insulator 250 in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b. Also, similar to the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0116] Also, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Also, oxidation of the conductor 260 by oxygen in the insulator 250 can be suppressed.

[0117] Also, the metal oxide may function as part of the gate insulator. Therefore, when using silicon oxide or silicon oxynitride for the insulator 250, it is preferable to use a metal oxide which is a high-k material having a high relative permittivity as the metal oxide. By forming the gate insulator into a laminated structure of the insulator 250 and the metal oxide, it is stable against heat. ​​​​​​​​​​​​It is possible to form a laminated structure with a high and constant relative dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to thin the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. This can be achieved.

[0118] Specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tantalum, tungsten, titanium, nickel, germanium, or magnesium can be used. In particular, it is preferable to use an insulator containing one or both oxides of aluminum or hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). One or more of the above elements can be used. Preferably, an insulator containing one or both oxides of aluminum or hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Preferably, an insulator containing one or both oxides of aluminum or hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Preferably, an insulator containing one or both oxides of aluminum or hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Preferably, an insulator containing one or both oxides of aluminum or hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0119] Alternatively, the metal oxide may function as part of the gate electrode. In this case, it is preferable to provide a conductive material containing oxygen on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material can be easily supplied to the channel formation region. This makes it easier for oxygen released from the conductive material to be supplied to the channel formation region.

[0120] In particular, as the conductor that functions as the gate electrode, it is preferable to use a conductive material containing the metal element and oxygen contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the above-mentioned metal element and nitrogen may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide containing titanium oxide, etc. In particular, as the conductor that functions as the gate electrode, it is preferable to use a conductive material containing the metal element and oxygen contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the above-mentioned metal element and nitrogen may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide containing titanium oxide, etc. In particular, as the conductor that functions as the gate electrode, it is preferable to use a conductive material containing the metal element and oxygen contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the above-mentioned metal element and nitrogen may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide containing titanium oxide, etc. In particular, as the conductor that functions as the gate electrode, it is preferable to use a conductive material containing the metal element and oxygen contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the above-mentioned metal element and nitrogen may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide containing titanium oxide, etc. In particular, as the conductor that functions as the gate electrode, it is preferable to use a conductive material containing the metal element and oxygen contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the above-mentioned metal element and nitrogen may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide containing titanium oxide, etc. Lead oxide or indium tin oxide added with silicon may be used. Also, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Or, it may be possible to capture hydrogen mixed in from an external insulator or the like. Although the conductor 260 is shown as a two-layer structure in FIG. 1, it may be a single-layer structure or a laminated structure of three or more layers. Or, it may be possible to capture hydrogen mixed in from an external insulator or the like. Although the conductor 260 is shown as a two-layer structure in FIG. 1, it may be a single-layer structure or a laminated structure of three or more layers.

[0121] Although the conductor 260 is shown as a two-layer structure in FIG. 1, it may be a single-layer structure or a laminated structure of three or more layers. Although the conductor 260 is shown as a two-layer structure in FIG. 1, it may be a single-layer structure or a laminated structure of three or more layers.

[0122] The conductor 260a preferably uses a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). The conductor 260a preferably uses a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). The conductor 260a preferably uses a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). The conductor 260a preferably uses a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0123] Also, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and the conductivity from decreasing. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Also, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and the conductivity from decreasing. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Also, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and the conductivity from decreasing. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Also, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and the conductivity from decreasing. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0124] Also, the conductor 260b preferably uses a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductor 260 functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 260b has a laminated structure Also, since the conductor 260 functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 260b has a laminated structure Also, since the conductor 260 functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 260b has a laminated structure Also, the conductor 260b has a laminated structure It may also be, for example, a laminated structure of titanium, titanium nitride and the above conductive material. .

[0125] The insulator 280 preferably includes, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having pores. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because a region containing fluorine that desorbs by heating can be easily formed.

[0126] It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. Also, the upper surface of the insulator 280 may be planarized.

[0127] The insulator 282 preferably functions as a barrier insulating film that suppresses the mixing of impurities such as water or hydrogen into the insulator 280 from above. As the insulator 282, for example, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used. .

[0128] Also, it is preferable to provide an insulator 274 that functions as an interlayer film on the insulator 282. Similar to the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 274 is reduced.

[0129] For the conductors 240a and 240b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Also, for the conductors 240a and 240 ​​​​​​​​​​​ 0b may have a laminated structure.

[0130] When the conductor 240 has a laminated structure, for the insulators 281, 274, 28 2, 280, 273, and the conductor in contact with the insulator 272, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. In addition, the conductive material having a function of suppressing the permeation of impurities such as water or hydrogen may be used in a single layer or in a laminate. By using such a conductive material, it is possible to prevent oxygen added to the insulator 280 from being absorbed by the conductors 240a and 240b. Also, it is possible to suppress impurities such as water or hydrogen from the upper layer of the insulator 281 from mixing into the oxide 230 through the conductors 240a and 240b.

[0131] As the insulators 241a and 241b, for example, insulators such as aluminum oxide, silicon nitride, or silicon oxynitride may be used. Since the insulators 241a and 241b are provided in contact with the insulators 272 and 273, it is possible to suppress impurities such as water or hydrogen from the insulator 28 0 from mixing into the oxide 230 through the conductors 240a and 240b.

[0132] In addition, conductors 246 (conductors 246a and 246b) that function as wiring may be arranged in contact with the upper surfaces of the conductor 240a and the conductor 240b. The conductor 2 46 may be made of a conductive material mainly composed of tungsten, copper, or aluminum. ​ is preferable. Further, the conductor may have a laminated structure, for example, titanium, titanium nitride and the above conductive material may be laminated. Note that the conductor may be formed so as to be embedded in an opening provided in an insulator .

[0133] <Constituent Materials of Semiconductor Device> Hereinafter, constituent materials that can be used in a semiconductor device will be described.

[0134] <Substrate> As the substrate on which the transistor 200 is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a s apphire substrate, a stabilized zirconia substrate (such as yttria-stabilized zirconia substrate), a resin bas plate, and the like. Examples of the semiconductor substrate include a semiconductor substrate made of, for example, silicon, germanium, etc., or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, for example, an SOI (Silico n On Insulator) substrate and the like. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, and the like. Or, a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there is a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Or, those with elements provided on these substrates may be used. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like. an insulator is provided on a conductor substrate, and the like. Or, those with elements provided on these substrates may be used. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0135] <Insulator> Examples of insulators include oxides, nitrides, oxynitrides, nitroxides, metal oxides, metal oxynitrides, metal nitroxides, etc.

[0136] For example, as the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as a gate insulator, it is possible to reduce the operating voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low relative permittivity for the insulator that functions as an interlayer film, the parasitic capacitance

[0137] generated between the wirings can be reduced. Therefore, the material may be selected according to the function of the insulator. Examples of insulators with a high relative permittivity include gallium oxide,

[0138] hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium, etc.

[0139] In addition, a transistor using an oxide semiconductor is surrounded by an insulator having a function of suppressing the permeation of impurities such as hydrogen and It is possible. As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, , for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon , phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lan thanum, neodymium, hafnium, or tantalum may be used singly or in a laminate. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or metal oxides such as tantalum oxide, aluminum nitride, aluminum titanium nitride, nitr ides such as titanium nitride, silicon oxynitride or silicon nitride can be used. .

[0140] Further, the insulator functioning as a gate insulator preferably has a region containing oxygen that desorbs by heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that desorbs by heating is in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated. .

[0141] <Conductor> As the conductor, metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, ti tanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnes ium, zirconium, beryllium, indium, ruthenium, iridium, stronti um, lanthanum, etc., or an alloy containing the above-described metal elements as components , it is preferable to use an alloy or the like combining the above-described metal elements. For example, tantalum nitride , titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum , ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium , an oxide containing lanthanum and nickel, etc. are preferably used. Also, tantalum nitride , titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum , ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium , an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Also, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, a silicide such as nickel silicide may be used.

[0142] Further, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure combining a material containing the above-described metal element and a conductive material containing oxygen may be used . Also, a laminated structure combining a material containing the above-described metal element and a conductive material containing nitrogen may be used . Also, a laminated structure combining a material containing the above-described metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used . Also, a laminated structure combining a material containing the above-described metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used .

[0143] In addition, when an oxide is used in the channel formation region of the transistor, for the conductor that functions as the gate electrode , it is preferable to use a laminated structure combining a material containing the above-described metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is used as the channel It is preferably provided on the channel formation region side. A conductive material containing oxygen is provided on the channel formation region side. By doing so, oxygen detached from the conductive material is likely to be supplied to the channel formation region.

[0144] In particular, as the conductor functioning as the gate electrode, it is preferable to use a conductive material containing a metal element and oxygen contained in the metal oxide in which the channel is formed. Further, a conductive material containing the above-mentioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten, indium zinc oxide containing tungsten, indium oxide containing titanium, indium tin oxide containing titanium, indium zinc oxide, indium tin oxide added with silicon may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Or, it may be possible to capture hydrogen mixed from an outer insulator or the like.

[0145] <Metal Oxide> As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Hereinafter, metal oxides applicable to the oxide 230 according to the present invention will be described.

[0146] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. Further, in addition to them, it is preferable that aluminum, gallium, yttrium or tin is contained. Further, boron, titanium, iron , nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , one or more selected from hafnium, tantalum, tungsten, magnesium, etc. may be included.

[0147] Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M and zinc. Note that element M is aluminum, gallium, yttrium, or tin, etc. Elements applicable to other element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. However, as element M, there may be cases where a plurality of the above-mentioned elements are combined.

[0148] Note that in this specification, etc., a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Also, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0149] [Structure of Metal Oxide] An oxide semiconductor (metal oxide) is divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0150] CAAC-OS has c-axis orientation and a plurality of nanocrystals are connected in the a-b plane direction. It is bonded and has a crystal structure with strain. The strain refers to the connection of a plurality of nanocrystals in a region where the lattice arrangement changes between a region with an aligned lattice arrangement and another region with an aligned lattice arrangement at a location where the direction of the lattice arrangement changes.

[0151] The nanocrystals are based on a hexagon, but are not necessarily regular hexagons and may be non-regular hexagons in some cases. Also, in the strain, there may be cases where there are lattice arrangements such as pentagons and heptagons . In CAAC-OS, it is difficult to confirm a clear grain boundary (also called a grain boundary) even near the strain. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This is because CAAC-OS allows strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the change in the bond distance between atoms due to the substitution of metal elements . Also, CAAC-OS tends to have a layered crystal structure (also called a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing element M, zinc, and oxygen (hereinafter, (M,Zn) layer) are stacked. Note that indium and element M are mutually substitutable. When element M in the (M,Zn) layer is substituted with indium, it can also be represented as an (In,M,Zn

[0152] ) layer. Also, when indium in the In layer is substituted with element M, it can also be represented as an (In, M) layer. ) layer. Also, when indium in the In layer is substituted with element M, it can also be represented as an (In, M) layer.

[0153] CAAC-OS is a highly crystalline metal oxide. On the other hand, since it is difficult to confirm a clear grain boundary in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur . It can be said that. In addition, the crystallinity of the metal oxide may decrease due to the incorporation of impurities or the generation of defects, etc. Therefore, CAAC-OS can also be said to be a metal oxide with few impurities and defects (such as oxygen vacancies (also referred to as V O :oxygen v acancy).). Therefore, the physical properties of the metal oxide having CAAC -OS are stable. Therefore, the metal oxide having CAAC-OS is heat-resistant and highly reliable.

[0154] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, nc-OS has no regularity in the crystal orientation between different nano crystals. Therefore, no orientation is observed in the entire film. Thus , depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor in some cases.

[0155] Note that indium-gallium-zinc oxide (hereinafter referred to as IGZO), which is a kind of metal oxide having indium , gallium, and zinc, may have a stable structure by forming the above-described nano crystals. In particular, since IGZO has a tendency that crystal growth is difficult in the air , in some cases, a smaller crystal (for example, the above-described nano crystal) is more structurally stable than a large crystal (here, a crystal of several mm or a crystal of several cm ).

[0156] a-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor . a-like OS has a loose or low-density region. That is, a-li ke OS has lower crystallinity compared to nc-OS and CAAC-OS.

[0157] Oxide semiconductors (metal oxides) have various structures, each with different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-li ke OS, nc-OS, and CAAC-OS.

[0158] In the semiconductor device according to one aspect of the present invention, although there is no particular limitation on the structure of the oxide semiconductor (metal oxide), it preferably has crystallinity. For example, the oxide 230 can have a CA AC-OS structure, and the oxide 243 can have a hexagonal crystal structure. By setting the oxide 23 0 and the oxide 243 to the above crystal structures, a semiconductor device with high reliability can be obtained. Also, the oxide 230a, the oxide 230c, and the oxide 243 can have substantially the same composition.

[0159] [Impurities] Here, the influence of each impurity in the metal oxide will be described.

[0160] In addition, when an alkali metal or an alkaline earth metal is contained in the metal oxide, defect levels may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal in the channel formation region tends to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or the alkaline earth metal in the metal oxide obtained by SIMS (the concentration obtained by secondary ion mass spectrometry (SIMS: Secon dary Ion Mass Spectrometry)) is 1 ×10 atoms / cm ×10 18 atoms / cm 3 ​​​Hereinafter, preferably 2×10 16 atoms / cm 3 or less is done.

[0161] In addition, since hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to form water , oxygen deficiency may be formed. When hydrogen enters the oxygen deficiency, carriers, electrons may be generated. Also, a part of hydrogen may bond with oxygen bonded to the metal atom to generate carriers, electrons . Therefore, a transistor using a metal oxide containing hydrogen tends to have normally-on characteristics.

[0162] For this reason, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically , in the metal oxide, the hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 less than, preferably 1×10 19 atoms / cm 3 less than, more preferably 5×1 0 18 atoms / cm 3 less than, still more preferably 1×10 18 atoms / cm 3 less than is set. By using a metal oxide with sufficiently reduced impurities in the channel formation region of the transistor , stable electrical characteristics can be imparted.

[0163] As the metal oxide used for the semiconductor of the transistor, it is preferable to use a highly crystalline thin film . By using the thin film, the stability or reliability of the transistor can be improved . Examples of the thin film include a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide . However, a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide To form it on a substrate, a high-temperature or laser heating process is required. Therefore, the cost of the manufacturing process increases, and furthermore, the throughput also decreases. In 2009, the discovery of In-Ga-Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was reported in Non-Patent Document 1 and Non-Patent Document 2. Here, it is reported that CAAC-IGZO has c-axis orientation, no clearly confirmed grain boundaries, and can be formed on a substrate at low temperature. Furthermore, it is reported that a transistor using CAAC-IGZO has excellent electrical characteristics and reliability.

[0164] In 2009, the discovery of In-Ga-Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was reported in Non-Patent Document 1 and Non-Patent Document 2. Here, it is reported that CAAC-IGZO has c-axis orientation, no clearly confirmed grain boundaries, and can be formed on a substrate at low temperature. Furthermore, it is reported that a transistor using CAAC-IGZO has excellent electrical characteristics and reliability. In 2009, the discovery of In-Ga-Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was reported in Non-Patent Document 1 and Non-Patent Document 2. Here, it is reported that CAAC-IGZO has c-axis orientation, no clearly confirmed grain boundaries, and can be formed on a substrate at low temperature. Furthermore, it is reported that a transistor using CAAC-IGZO has excellent electrical characteristics and reliability. Here, it is reported that CAAC-IGZO has c-axis orientation, no clearly confirmed grain boundaries, and can be formed on a substrate at low temperature. Furthermore, it is reported that a transistor using CAAC-IGZO has excellent electrical characteristics and reliability. Here, it is reported that CAAC-IGZO has c-axis orientation, no clearly confirmed grain boundaries, and can be formed on a substrate at low temperature. Furthermore, it is reported that a transistor using CAAC-IGZO has excellent electrical characteristics and reliability. Here, it is reported that CAAC-IGZO has c-axis orientation, no clearly confirmed grain boundaries, and can be formed on a substrate at low temperature. Furthermore, it is reported that a transistor using CAAC-IGZO has excellent electrical characteristics and reliability.

[0165] Also, in 2013, In-Ga-Zn oxide having an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Document 3). Here, it is reported that nc-IGZO has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and no regularity is seen in the crystal orientation between different regions. Also, in 2013, In-Ga-Zn oxide having an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Document 3). Here, it is reported that nc-IGZO has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and no regularity is seen in the crystal orientation between different regions. Also, in 2013, In-Ga-Zn oxide having an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Document 3). Here, it is reported that nc-IGZO has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and no regularity is seen in the crystal orientation between different regions. Also, in 2013, In-Ga-Zn oxide having an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Document 3). Here, it is reported that nc-IGZO has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and no regularity is seen in the crystal orientation between different regions.

[0166] In Non-Patent Document 4 and Non-Patent Document 5, the transition of the average crystal size due to electron beam irradiation of each of the above-mentioned CAAC-IGZO, nc-IGZO, and IGZO with low crystallinity thin films is shown. In the thin film of IGZO with low crystallinity, even before electron beam irradiation, crystalline IGZO of about 1 nm has been observed. Therefore, here, it is reported that the existence of a completely amorphous structure could not be confirmed in IGZO. Furthermore, IGZO with low crystallinity In Non-Patent Document 4 and Non-Patent Document 5, the transition of the average crystal size due to electron beam irradiation of each of the above-mentioned CAAC-IGZO, nc-IGZO, and IGZO with low crystallinity thin films is shown. In the thin film of IGZO with low crystallinity, even before electron beam irradiation, crystalline IGZO of about 1 nm has been observed. Therefore, here, it is reported that the existence of a completely amorphous structure could not be confirmed in IGZO. Furthermore, IGZO with low crystallinity In Non-Patent Document 4 and Non-Patent Document 5, the transition of the average crystal size due to electron beam irradiation of each of the above-mentioned CAAC-IGZO, nc-IGZO, and IGZO with low crystallinity thin films is shown. In the thin film of IGZO with low crystallinity, even before electron beam irradiation, crystalline IGZO of about 1 nm has been observed. Therefore, here, it is reported that the existence of a completely amorphous structure could not be confirmed in IGZO. Furthermore, IGZO with low crystallinity In Non-Patent Document 4 and Non-Patent Document 5, the transition of the average crystal size due to electron beam irradiation of each of the above-mentioned CAAC-IGZO, nc-IGZO, and IGZO with low crystallinity thin films is shown. In the thin film of IGZO with low crystallinity, even before electron beam irradiation, crystalline IGZO of about 1 nm has been observed. Therefore, here, it is reported that the existence of a completely amorphous structure could not be confirmed in IGZO. Furthermore, IGZO with low crystallinity In Non-Patent Document 4 and Non-Patent Document 5, the transition of the average crystal size due to electron beam irradiation of each of the above-mentioned CAAC-IGZO, nc-IGZO, and IGZO with low crystallinity thin films is shown. In the thin film of IGZO with low crystallinity, even before electron beam irradiation, crystalline IGZO of about 1 nm has been observed. Therefore, here, it is reported that the existence of a completely amorphous structure could not be confirmed in IGZO. Furthermore, IGZO with low crystallinity In Non-Patent Document 4 and Non-Patent Document 5, the transition of the average crystal size due to electron beam irradiation of each of the above-mentioned CAAC-IGZO, nc-IGZO, and IGZO with low crystallinity thin films is shown. In the thin film of IGZO with low crystallinity, even before electron beam irradiation, crystalline IGZO of about 1 nm has been observed. Therefore, here, it is reported that the existence of a completely amorphous structure could not be confirmed in IGZO. Furthermore, IGZO with low crystallinity Compared with the thin film of , the thin films of CAAC-IGZO and nc-IGZO have been shown to have high stability against electron beam irradiation. Therefore, as the semiconductor of the transistor, it is preferable to use the thin film of CAAC C-IGZO or the thin film of nc-IGZO.

[0167] A transistor using a metal oxide has an extremely small leakage current in the non-conducting state. Specifically, it is shown in Non-Patent Document 6 that the off-current per 1 μm of the channel width of the transistor is on the order of yA / μm (10 -2 4 A / μm). For example, a low-power CPU that applies the characteristic of low leakage current of a transistor using a metal oxide has been disclosed (see Non-Patent Document 7). (See Non-Patent Document 7.)

[0168] In addition, the application of the transistor using a metal oxide to a display device by utilizing the characteristic of low leakage current has been reported (see Non-Patent Document 8). In a display device , the displayed image is switched dozens of times per second. The number of times the image is switched per second is called the refresh rate. Also, the refresh rate is sometimes called the driving frequency . Such a high-speed screen switching that is difficult for the human eye to perceive is considered to be the cause of eye fatigue. Therefore, it has been proposed to reduce the refresh rate of the display device to reduce the number of times the image is rewritten. Also, by driving with a reduced refresh rate , it is possible to reduce the power consumption of the display device. Such a driving method is called idling stop driving.

[0169]

[0169] The discovery of the CAAC structure and the nc structure is that a metal oxide having the CAAC structure or the nc structure Improvement in electrical characteristics and reliability of transistors using the substance, and contribution to cost reduction and throughput improvement in the manufacturing process. Also, application research on the display device and LSI of the transistor utilizing the characteristic of low leakage current of the transistor is being advanced. It is contributing to cost reduction and throughput improvement in the manufacturing process. Also, application research on the display device and LSI of the transistor utilizing the characteristic of low leakage current of the transistor is being advanced. And research on the application of the transistor to a display device and an LSI is being carried out using the characteristic that the leakage current of the transistor is low. is being carried out.

[0170] <Method of manufacturing a semiconductor device> Next, a method of manufacturing a semiconductor device having the transistor 200 according to the present invention shown in FIG. 1 will be described with reference to FIGS. 4 to 11. Also, in FIGS. 4 to 11, (A) in each figure shows a top view. Also, (B) in each figure is a cross-sectional view corresponding to the position indicated by the one-dot chain line A1 - A2 shown in (A), and is also a cross-sectional view in the channel length direction of the transistor 200. Further, (C) in each figure is a cross-sectional view corresponding to the portion indicated by the one-dot chain line A3 - A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of (A) in each figure, some elements are omitted for clarity of the figure. First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The formation of the insulator 214 can be performed using a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD (Atomic Layer Deposition) method, etc. First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The formation of the insulator 214 can be performed using a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD (Atomic Layer Deposition) method, etc. First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The formation of the insulator 214 can be performed using a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD (Atomic Layer Deposition) method, etc. First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The formation of the insulator 214 can be performed using a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD (Atomic Layer Deposition) method, etc. First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The formation of the insulator 214 can be performed using a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD (Atomic Layer Deposition) method, etc. First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The formation of the insulator 214 can be performed using a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD (Atomic Layer Deposition) method, etc.

[0171] First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The formation of the insulator 214 can be performed using a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD (Atomic Layer Deposition) method, etc. First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The formation of the insulator 214 can be performed using a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD (Atomic Layer Deposition) method, etc. First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The formation of the insulator 214 can be performed using a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD (Atomic Layer Deposition) method, etc. First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The formation of the insulator 214 can be performed using a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD (Atomic Layer Deposition) method, etc. First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The formation of the insulator 214 can be performed using a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD (Atomic Layer Deposition) method, etc. First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The formation of the insulator 214 can be performed using a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an ALD (Atomic Layer Deposition) method, etc.

[0172] Note that the CVD method can be a plasma CVD (PECVD: Plasma Enhanced CVD), thermal CVD (TCVD: Thermal C VD), photo CVD (Photo CVD) using light, etc. Furthermore, depending on the raw material gas used, it can be classified into metal CVD (MCVD: Metal CVD) and metal organic CVD (MOCVD: Metal Organic CVD).

[0173] In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Also, since the thermal CVD method does not use plasma, it is a film-forming method that can reduce plasma damage to the object to be processed. For example, wirings, electrodes, and elements (such as transistors and capacitor elements) included in semiconductor devices may be charged up by receiving charges from plasma. At this time , the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged by the accumulated charges. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur. Therefore, the yield of semiconductor devices can be increased. Also, in the thermal CVD method, since plasma damage does not occur in the deposited film, a film with few defects can be obtained.

[0174] Also, the ALD method utilizes the self-limiting property of atoms and can deposit atoms one by one. Therefore, it is possible to form an extremely thin film, form a film on a structure with a high aspect ratio, form a film with few defects such as pinholes, form a film with excellent coverage, and form a film at a low temperature. In addition, the ALD method includes a film-forming method using plasma, PEALD ( Plasma Enhanced ALD). By using plasma, it may be possible to form a film at a lower temperature, which is preferable. Note that the precursors used in the ALD method Some of them contain impurities such as carbon. Therefore, the film formed by the ALD method may contain more impurities such as carbon than the film formed by other film formation methods. Incidentally, the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0175] The CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of an object to be processed. Therefore, it is a film formation method that is less affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method is suitable for coating the surface of an opening with a high aspect ratio because it has excellent step coverage and excellent thickness uniformity. However, since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as the CVD method with a high film formation rate.

[0176] The CVD method and the ALD method can control the composition of the obtained film by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film with an arbitrary composition can be formed by the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened because the time required for transfer and pressure adjustment is not required compared to the case of forming a film using a plurality of film formation chambers. Therefore, it may be possible to improve the productivity of semiconductor devices.

[0177] In this embodiment, silicon nitride is deposited as the insulator 214 by the CVD method. Thus, as the insulator 214, an insulator through which copper hardly permeates, such as silicon nitride, is used. As a result, even if a metal that easily diffuses, such as copper, is used for the conductor in the layer below the insulator 214 (not shown), diffusion of the metal into the layer above the insulator 214 can be suppressed.

[0178] Next, an insulator 216 is deposited on the insulator 214. The deposition of the insulator 216 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0179] Next, an opening reaching the insulator 214 is formed in the insulator 216. The opening includes, for example, a groove or a slit. In some cases, the region where the opening is formed may be referred to as an opening portion. The opening may be formed using wet etching, but dry etching is more preferable for microfabrication. Further, it is preferable to select the insulator 214 as an insulator that functions as an etching stopper film when forming a groove in the insulator 216. For example, when a silicon oxide film is used for the insulator 216 for forming the groove, the insulator 214 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.

[0180] After the formation of the opening, a conductive film that becomes the conductor 205 is deposited. The conductive film desirably includes a conductor having a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, it can be a laminated film with tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy.​​​​​​​​​The conductive film that becomes the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be carried out using a PLD method, an ALD method, or the like.

[0181] In this embodiment, the conductive film that becomes the conductor 205 has a multi-layer structure. A tantalum nitride film is formed by a deposition method, and titanium nitride is laminated on the tantalum nitride. By using such a metal nitride as the lower layer of the conductive film that becomes the conductor 205, Even if a metal that easily diffuses, such as copper, is used as the conductive film on the conductive film that becomes the conductor 205, The metal can be prevented from diffusing out of the conductor 205 .

[0182] Next, a conductive film is formed on the conductive film that will become the conductor 205. The conductive film is formed by plating. The method is performed using the deposition method, sputtering method, CVD method, MBE method, PLD method, or ALD method. In this embodiment, the conductive film on the conductive film that becomes the conductor 205 is A film of a low resistance conductive material such as copper is deposited.

[0183] Next, CMP (Chemical Mechanical Polishing) By carrying out the above, the upper layer of the conductive film which becomes the conductor 205 and the A portion of the lower layer is removed to expose the insulator 216. As a result, the conductor 205 is only present in the opening. As a result, a conductive film that becomes a flat conductive body 205 is formed. Note that the CMP process may remove a part of the insulator 216 (see FIG. 4). reference.).

[0184] Hereinafter, a method for forming the conductor 205 that differs from the above will be described.

[0185] A conductive film that becomes the conductor 205 is formed on the insulator 214. The conductive film that becomes the conductor 205 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the conductive film that becomes the conductor 205 can be a multilayer film. In this embodiment, tungsten is formed as the conductive film that becomes the conductor 205.

[0186] Next, the conductive film that becomes the conductor 205 is processed using a lithography method to form the conductor 205.

[0187] In the lithography method, first, a resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, by performing an etching process through the resist mask, conductors, semiconductors, insulators, etc. can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique in which a liquid (for example, water) is filled between the substrate and the projection lens and exposure is performed may be used. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when using an electron beam or an ion beam, a mask is not required. For removing the resist mask, ashing, dry etching, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching can be performed.

[0188] Alternatively, a hard mask made of an insulator or a conductor may be used instead of the resist mask. . When using a hard mask, an insulating film or a conductive film serving as the hard mask material is formed on the conductive film that will become the conductor 205, and a resist mask is formed thereon. By etching the hard mask material, a hard mask having a desired shape can be formed. The etching of the conductive film that will become the conductor 205 may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during the etching. After etching the conductive film that will become the conductor 205, the hard mask may be removed by etching. On the other hand, if the material of the hard mask has no influence on the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.

[0189] As the dry etching apparatus, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency power source to one of the parallel plate electrodes. Alternatively, a plurality of different high-frequency power sources may be applied to one of the parallel plate electrodes. Alternatively, high-frequency power sources having the same frequency may be applied to each of the parallel plate electrodes. Alternatively, high-frequency power sources having different frequencies may be applied to each of the parallel plate electrodes. Or a dry etching apparatus having a high-density plasma source can be used. The dry etching apparatus having a high-density plasma source can use, for example, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching apparatus or the like. ​​​​​​​​​​​​​​​

[0190] Next, an insulating film that becomes the insulator 216 is formed on the insulator 214 and on the conductor 205. The formation of the insulator that becomes the insulator 216 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, etc. In this embodiment, silicon oxide is formed as the insulating film that becomes the insulator 216 by the CVD method. Here, the film thickness of the insulating film that becomes the insulator 216 is preferably equal to or greater than the film thickness of the conductor 205. For example, if the film thickness of the conductor 205 is 1, the film thickness of the insulating film that becomes the insulator 216 is set to be 1 or more and 3 or less. In this embodiment, the film thickness of the conductor 205 is 150 nm, and the film thickness of the insulating film that becomes the insulator 216 is 350 nm. Next, by performing CMP processing on the insulating film that becomes the insulator 216, a part of the insulating film that becomes the insulator 216 is removed to expose the surface of the conductor 205. Thereby, the conductor 205 with a flat upper surface and the insulator 216 can be formed. The above is the different formation method of the conductor 205. Next, an insulator 222 is formed on the insulator 216 and on the conductor 205. As the insulator 222, an insulator containing one or both of aluminum oxide and hafnium oxide is preferably formed. As the insulator containing one or both of aluminum oxide and hafnium oxide, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. The insulator containing one or both of aluminum oxide and hafnium oxide has barrier properties against oxygen, hydrogen, and water.

[0191]

[0192]

[0193]

[0193] ​​​​​​It has. Since the insulator 222 has barrier properties against hydrogen and water, hydrogen and water contained in the structure provided around the transistor 200 are suppressed from diffusing into the transistor 200 through the insulator 222, and the generation of oxygen vacancies in the oxide 230 can be suppressed. Hydrogen and water contained in the structure provided around the transistor 200 are suppressed from diffusing into the inside of the transistor 200 through the insulator 222, and the generation of oxygen vacancies in the oxide 230 can be suppressed.

[0194] The insulator 222 can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0195] Next, an insulating film 224A is formed on the insulator 222. The insulating film 224A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0196] Subsequently, it is preferable to perform a heat treatment. The heat treatment can be performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may be performed under reduced pressure. Or, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to supplement the desorbed oxygen after heat treatment in a nitrogen or inert gas atmosphere.

[0197] In this embodiment, after performing a treatment at a temperature of 400°C for 1 hour in a nitrogen atmosphere, a treatment at a temperature of 400°C for 1 hour is continuously performed in an oxygen atmosphere. By this heat treatment, impurities such as water and hydrogen contained in the insulating film 224A can be removed.

[0198] ​​​​​​​​​​​​ Further, the heat treatment may be performed after the formation of the insulator 222. The heat treatment may use the above-described heat treatment conditions.

[0199] Here, in order to form an excess oxygen region in the insulating film 224A, plasma treatment containing oxygen may be performed in a reduced pressure state. The plasma treatment containing oxygen is preferably performed using, for example, a device having a power source for generating high-density plasma using microwaves. Alternatively, it may have a power source for applying RF (Radio Frequency) to the substrate side. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulating film 224A. Or, after performing plasma treatment containing an inert gas using this device, plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. Note that by appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulating film 224A can be removed. In that case, the heat treatment may not be performed. (Radio Frequency) to the substrate side. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulating film 224A. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulating film 224A. By applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulating film 224A. Or, after performing plasma treatment containing an inert gas using this device, plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. Note that by appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulating film 224A can be removed. In that case, the heat treatment may not be performed. Or, after performing plasma treatment containing an inert gas using this device, plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. Note that by appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulating film 224A can be removed. In that case, the heat treatment may not be performed. By appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulating film 224A can be removed. In that case, the heat treatment may not be performed. By appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulating film 224A can be removed. In that case, the heat treatment may not be performed.

[0200] Here, on the insulating film 224A, for example, aluminum oxide may be formed by sputtering, and CMP may be performed until the aluminum oxide reaches the insulating film 224A. By performing the CMP, planarization of the surface of the insulating film 224A and smoothing of the surface of the insulating film 224A can be performed. By arranging the aluminum oxide on the insulating film 224A and performing CMP, it becomes easy to detect the end point of CMP. Also, by CMP, a part of the insulating film 224A may be polished and the film thickness of the insulating film 224A may become thinner, but at the time of forming the insulating film 224A By performing the CMP, planarization of the surface of the insulating film 224A and smoothing of the surface of the insulating film 224A can be performed. By arranging the aluminum oxide on the insulating film 224A and performing CMP, it becomes easy to detect the end point of CMP. Also, by CMP, a part of the insulating film 224A may be polished and the film thickness of the insulating film 224A may become thinner, but at the time of forming the insulating film 224A By arranging the aluminum oxide on the insulating film 224A and performing CMP, it becomes easy to detect the end point of CMP. Also, by CMP, a part of the insulating film 224A may be polished and the film thickness of the insulating film 224A may become thinner, but at the time of forming the insulating film 224A By arranging the aluminum oxide on the insulating film 224A and performing CMP, it becomes easy to detect the end point of CMP. Also, by CMP, a part of the insulating film 224A may be polished and the film thickness of the insulating film 224A may become thinner, but at the time of forming the insulating film 224A By arranging the aluminum oxide on the insulating film 224A and performing CMP, it becomes easy to detect the end point of CMP. Also, by CMP, a part of the insulating film 224A may be polished and the film thickness of the insulating film 224A may become thinner, but at the time of forming the insulating film 224A By flattening and smoothing the surface of the insulating film 224A, It is possible to prevent the deterioration of the coverage of the oxide film to be formed and to prevent a decrease in the yield of the semiconductor device. In addition, aluminum oxide may be deposited on the insulating film 224A by sputtering. This is preferable because oxygen can be added to the insulating film 224A by forming the insulating film 224A.

[0201] Next, an oxide film 230A and an oxide film 230B are formed in this order on the insulating film 224A (see FIG. 4). It is preferable that the oxide film is formed continuously without exposing it to the air environment. By forming the film without exposing it to the atmosphere, the oxide film 230A and the oxide film 230B are not exposed to the atmosphere. The oxide film 230A and the oxide film 230B can be prevented from being adhered to the oxide film 230. The area near the interface with B can be kept clean.

[0202] The oxide film 230A and the oxide film 230B are formed by sputtering, CVD, MBE, etc. The deposition can be performed by using a deposition method, a PLD method, an ALD method, or the like.

[0203] For example, the oxide film 230A and the oxide film 230B are formed by a sputtering method. In this case, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the oxide film to be formed is reduced. In addition, when the oxide film is formed by sputtering, In this case, the above-mentioned In-M-Zn oxide target can be used.

[0204] In particular, when the oxide film 230A is formed, a part of the oxygen contained in the sputtering gas is mixed with the insulating film. Therefore, the sputtering gas for the oxide film 230A may be The proportion of oxygen contained is 70% or more, preferably 80% or more, more preferably 100%. That's all right.

[0205] Also, when forming the oxide film 230B by sputtering, the proportion of oxygen contained in the sputtering gas is set to 1% or more and 30% or less, preferably 5% or more and 20% or less for film formation, and an oxygen-deficient oxide semiconductor is formed. A transistor using the oxygen-deficient oxide semiconductor in the channel formation region can obtain a relatively high field-effect mobility. In this embodiment, as the oxide film 230A, by sputtering, In:Ga: Zn = 1:1:0.5 [atomic ratio] (2:2:1 [atomic ratio]), or 1:3:4

[0206] atomic ratio], a film is formed using a target. Also, as the oxide film 230B, by sputtering, In:Ga:Zn = 4:2:4.1 [atomic ratio], or 1:1:1 atomic ratio], a film is formed using a target. Note that each oxide film may be formed according to the characteristics required for the oxide 230 by appropriately selecting the film formation conditions and the atomic ratio. Next, heat treatment may be performed. The heat treatment conditions described above can be used. By heat treatment, impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed. In this embodiment, after performing a treatment at a temperature of 400°C for 1 hour in a nitrogen atmosphere, a treatment at a temperature of 400°C for 1 hour is continuously performed in an oxygen atmosphere. That's all right. Next, an oxide film 243A is formed on the oxide film 230B. The formation of the oxide film 243A is sputtered.

[0207] Next, heat treatment may be performed. The heat treatment conditions described above can be used. By heat treatment, impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed. In this embodiment, after performing a treatment at a temperature of 400°C for 1 hour in a nitrogen atmosphere, a treatment at a temperature of 400°C for 1 hour is continuously performed in an oxygen atmosphere. Next, an oxide film 243A is formed on the oxide film 230B. The formation of the oxide film 243A is sputtered. Next, heat treatment may be performed. The heat treatment conditions described above can be used. By heat treatment, impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed. In this embodiment, after performing a treatment at a temperature of 400°C for 1 hour in a nitrogen atmosphere, a treatment at a temperature of 400°C for 1 hour is continuously performed in an oxygen atmosphere. Next, an oxide film 243A is formed on the oxide film 230B. The formation of the oxide film 243A is sputtered. That's all right.

[0208] Next, an oxide film 243A is formed on the oxide film 230B. The formation of the oxide film 243A is sputtered. This can be done using deposition, CVD, MBE, PLD, or ALD methods. The oxide film 243A has an atomic ratio of Ga to In that is equal to that of the oxide film 230B. In the present embodiment, the oxide film 243A is preferably made of By sputtering, a target of In:Ga:Zn=1:3:4 [atomic ratio] was Next, a conductive film 242A is formed on the oxide film 243A. The deposition of A is performed using the sputtering method, CVD method, MBE method, PLD method, or ALD method. This can be done by using the following method (see Figure 4).

[0209] Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A are formed into an island. The oxide layer 230a, the oxide layer 230b, the oxide layer 243B, and the conductive layer 2 42B is formed (see FIG. 5). Although not shown, in this process, the insulating film 22 The thickness of the film in the area not overlapping with the oxide 230a of 4A may be thin.

[0210] Here, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242 B is formed so that at least a portion of it overlaps with the conductor 205. The sides of the oxide 230b, the oxide layer 243B, and the conductive layer 242B are It is preferable that the oxide 230a, the oxide 230b, and the oxide 230c are approximately perpendicular to the upper surface. The side surfaces of the layer 243B and the conductive layer 242B are approximately perpendicular to the upper surface of the insulator 222. This allows a reduction in area and a high density when providing multiple transistors 200. Alternatively, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242 It is also possible to adopt a configuration in which the angle formed by B and the upper surface of the insulator 222 is a low angle. In that case, the oxides 230a, oxide 230b, oxide layer 243B, and the side surface of the conductor layer 242B and the upper surface of the insulator 222 preferably form an angle of 60° or more and less than 70°. By adopting such a shape, in subsequent processes, the coating property of the insulator 272 and the like is improved, and defects such as looseness can be reduced.

[0211] Also, a curved surface is provided between the side surface of the conductor layer 242B and the upper surface of the conductor layer 242B. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as round). The curved surface has, for example, a curvature radius of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, at the end of the conductor layer 242B. By not having a corner at the end, the coating property of the film in subsequent film-forming processes is improved.

[0212] Note that the processing of the oxide film and the conductive film may be performed using a lithography method. Also, this processing can use a dry etching method or a wet etching method. Processing by the dry etching method is suitable for microfabrication.

[0213] Next, an insulating film 272A is formed on the insulator 224, the oxides 230a, 230b, the oxide layer 243B, and the conductor layer 242B (see FIG. 6).

[0214] The insulating film 272A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method or the like. It is preferable to use an insulating film having a function of suppressing oxygen permeation for the insulating film 272A. For example, by the sputtering method or the ALD method, ​​​Then, aluminum oxide, silicon nitride, silicon oxide, or gallium oxide is deposited. Good too.

[0215] Next, the insulating film 273A is formed on the insulating film 272A. This can be done using the sputtering method, CVD method, MBE method, PLD method, or ALD method. For example, it is preferable to form an aluminum oxide film by the ALD method. In this embodiment, an aluminum oxide film is formed by the ALD method (see FIG. 6). Alternatively, the insulating film 273A may not be formed.

[0216] Next, an insulating film that will become the insulator 280 is formed on the insulating film 273A. The insulating film is formed by a method such as sputtering, CVD, MBE, PLD, or ALD. Next, a CMP process is performed on the insulating film that will become the insulator 280. A flat surfaced insulator 280 is formed (see FIG. 7).

[0217] Next, a part of the insulator 280, a part of the insulating film 273A, a part of the insulating film 272A, and the oxide layer A part of 243B, a part of the conductive layer 242B, and a part of the insulating film 224A are processed to remove the oxide. An opening is formed so as to reach the conductor 230b. The opening is formed so as to overlap the conductor 205. By forming the opening, the oxide 243a, the oxide 243b, the conductor 24 2a, conductor 242b, insulator 224, insulator 272, and insulator 273 are formed ( See Figure 7.

[0218] In addition, a part of the insulator 280, a part of the insulating film 273A, a part of the insulating film 272A, and the oxide layer A part of the insulating layer 224A, a part of the conductive layer 243B, a part of the conductive layer 242B, and a part of the insulating layer 224A are processed. They may be processed under different conditions respectively. For example, a part of the insulator 280 may be processed by dry etching method, a part of the insulating film 273A may be processed by wet etching method, and a part of the insulating film 272A a part of the oxide layer 243B, a part of the conductor layer 242B, and a part of the insulating film 224A may be processed by dry etching method.

[0219] By performing the previous processes such as dry etching, impurities caused by etching gas or the like may adhere or diffuse on the surface or inside of the oxides 230a and 230b. Examples of the impurities include fluorine or chlorine.

[0220] In order to remove the above impurities and the like, cleaning is performed. Examples of the cleaning method include wet cleaning using a cleaning solution or the like, plasma treatment using plasma, or cleaning by heat treatment. These cleaning methods may be appropriately combined.

[0221] As the wet cleaning, a cleaning process may be performed using an aqueous solution diluted with oxalic acid, phosphoric acid, aqueous ammonia, hydrofluoric acid, carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed.

[0222] Next, heat treatment may be performed. The heat treatment is performed under reduced pressure without exposing to the atmosphere, and the oxide film 230C may be continuously formed. By performing such a process, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and further, the moisture concentration and hydrogen concentration in the oxides 230a and 230b can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is 20 Set it to 0°C (see Fig. 8).

[0223] Here, the oxide film 230C is in contact with at least a part of the side surface of the oxide 230a, a part of the side surface and a part of the upper surface of the oxide 230b , a part of the side surface of the oxide 243, a part of the side surface of the conductor 242 , the side surface of the insulator 272, the side surface of the insulator 273, and the side surface of the insulator 280, and is preferably provided. The conductor 242 is surrounded by the oxide 243, the insulator 272, and the oxide film 23 0C, so that a decrease in conductivity due to oxidation of the conductor 242 in subsequent processes can be suppressed.

[0224] The formation of the oxide film 230C can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, or an A LD method or the like. As the oxide film 230C, it is preferable that the atomic number ratio of Ga to In is larger than the atomic number ratio of Ga to In in the oxide film 230B. In this embodiment , as the oxide film 230C, by a sputtering method, In:Ga:Zn = 1:3:4 [atomic number ratio] target is used for film formation.

[0225] Note that the oxide film 230C may be a laminate. For example, by a sputtering method, In :Ga:Zn = 1:3:4 [atomic number ratio] target is used for film formation, and then continuously In: Ga:Zn = 4:2:4.1 [atomic number ratio] target may be used for film formation.

[0226] In particular, when forming the oxide film 230C, a part of the oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Therefore, the ratio of oxygen contained in the sputtering gas of the oxide film 230C is 70% or more, preferably 80% or more, more preferably 100%. ​​

[0227] Next, a heat treatment may be performed. The heat treatment is performed under reduced pressure without exposure to the atmosphere. The insulating film 250A may be formed continuously. By performing such a process, the oxide film The moisture and hydrogen adsorbed on the surface of 230C are removed, and the oxide 230a and the acid The moisture concentration and hydrogen concentration in the oxide film 230b and the oxide film 230C can be reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower (see FIG. 9).

[0228] The insulating film 250A is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulating film 250A can be formed by a CVD method. It is preferable to form a film of silicon hydride by using a silicon nitride film. The temperature is preferably 350° C. or higher and lower than 450° C., and more preferably about 400° C. By forming the film at 400°C, an insulator with few impurities can be formed.

[0229] Next, the conductive film 260Aa and the conductive film 260Ab are formed. The conductive film 260Ab is formed by sputtering, CVD, MBE, PLD or A This can be done by using the LD method or the like. For example, it is preferable to use the CVD method. In this embodiment, the conductive film 260Aa is formed by the ALD method, and the conductive film 260B is formed by the CVD method. A film of 260Ab is formed (see Figure 10).

[0230] Next, the oxide film 230C, the insulating film 250A, the conductive film 260Aa, and The oxide 230 is removed by polishing the conductive film 260Ab until the insulator 280 is exposed. c. Form the insulator 250 and the conductor 260 (conductor 260a and conductor 260b). (See Fig. 11.)

[0231] Here, since the conductor 242 is surrounded by the oxide 243, the insulator 272, and the oxide 230c, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 242.

[0232] Next, heat treatment may be performed. In this embodiment, the treatment is carried out at a temperature of 400 °C for 1 hour in a nitrogen atmosphere. By this heat treatment, it is possible to reduce the moisture concentration and the hydrogen concentration in the insulator 250 and the insulator 280.

[0233] Next, an insulating film that becomes the insulator 282 may be formed on the conductor 260, on the oxide 230c, on the insulator 250, and on the insulator 280. The formation of the insulating film that becomes the insulator 282 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film that becomes the insulator 282, for example, it is preferable to form aluminum oxide by a sputtering method. In this way, by forming the insulator 282 in contact with the upper surface of the conductor 260, it is preferable because it is possible to suppress the absorption of oxygen in the insulator 280 by the conductor 260 in the subsequent heat treatment (see Fig. 11).

[0234] Next, heat treatment may be performed. In this embodiment, the treatment is carried out at a temperature of 400 °C for 1 hour in a nitrogen atmosphere. By this heat treatment, it is possible to inject oxygen added by the formation of the insulator 282 into the insulator 280. Also, the oxygen can be passed through the oxide 230c to the acid ​​​​​It can be implanted into the oxide 230a and the oxide 230b.

[0235] Next, an insulator that will become the insulator 274 may be formed on the insulator 282. The insulator 274 The formation of the insulating film that will become the insulating film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. (see Fig. 11).

[0236] Next, an insulating film that will become the insulator 281 may be formed on the insulator 274. The insulator 281 The formation of the insulating film that will become the insulating film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, etc. As the insulating film that will become the insulator 281, for example, it is preferable to form silicon nitride by the sputtering method. (see Fig. 11).

[0237] Next, openings reaching the conductors 242a and 242b are formed in the insulators 272, 273, 280, 282, 274, and also the insulator 281. The formation of the openings may be performed using a lithography method.

[0238] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241. The formation of the insulating film can be performed using a sputtering method, a CVD method, an MBE method, a PL D method, or an ALD method, etc. As the insulating film that will become the insulator 241 It is preferable to use an insulating film having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. For example, it is preferable to form aluminum oxide or silicon nitride by the ALD method. Also, the anisotropic etching may be performed, for example, by a dry etching method . By configuring the side wall portion of the opening in this way, the permeation of oxygen from the outside is suppressed, and next, the shape . Oxidation of the conductors 240a and 240b can be prevented. Also, impurities such as water and hydrogen can be prevented from diffusing to the outside from the conductors 240a and 240b.

[0239] Next, a conductive film that will become the conductors 240a and 240b is formed. The conductive film that will become the conductors 240a and 240b preferably has a laminated structure including a conductor having a function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. The formation of the conductive film that will become the conductor 240 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0240] Next, by performing a CMP process, a part of the conductive film that will become the conductors 240a and 240b is removed to expose the insulator 281. As a result, the conductive film remains only in the above opening, and conductors 240a and 240b having a flat upper surface can be formed (see FIG. 1). Note that a part of the insulator 281 may be removed by the CMP process.

[0241] Next, a conductive film that will become the conductor 246 is formed. The formation of the conductive film that will become the conductor 246 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0242] Next, the conductive film that will become the conductor 246 is processed by a lithography method to form a conductor 246a that contacts the upper surface of the conductor 240a and a conductor 246b that contacts the upper surface of the conductor 240b (see FIG. 1). ​​​​​​​​​​​​​​​

[0243] As described above, a semiconductor device having the transistor 200 shown in FIG. 1 can be fabricated. As shown in FIGS. 4 to 11, the transistor 200 can be fabricated by using the method for fabricating a semiconductor device according to the present embodiment.

[0244] According to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Or According to one aspect of the present invention, a semiconductor device having high frequency characteristics can be provided. Or, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Also Or, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Or, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Or, according to one aspect of the present invention, a semiconductor device with a small off-current can be provided. Or, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Or, according to one aspect of the present invention, a highly productive semiconductor device can be provided.

[0245] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments and other examples.

[0246] (Embodiment 2) In the present embodiment, one form of the semiconductor device will be described with reference to FIGS. 16 and 17.

[0247] [Storage device 1] An example of a storage device using the semiconductor device according to one aspect of the present invention is shown in FIG. 16. FIG. 16 The memory device shown has a transistor 200, a transistor 300, and a capacitive element 100. The transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 300 and the transistor 200. Note that as the transistor 200, the transistor 200 described in the previous embodiment or the like can be used.

[0248] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200 has a small off-current, by using it in a memory device, it is possible to hold the stored content for a long time. That is, since a refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.

[0249] In the semiconductor device shown in FIG. 16, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Also, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1 006 is electrically connected to the second gate of the transistor 200. And the gate of the transistor 300, and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitive element 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitive element 100.

[0250] Also, the memory device shown in FIG. 16 can form a memory cell array by being arranged in a matrix. ​​It can be configured.

[0251] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 that functions as a gate electrode, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or a drain region. The transistor 300 can be either p-channel or n-channel. 16, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or a drain region. The transistor 300 can be either p-channel or n-channel. 313, and low-resistance regions 314a and 314b that function as a source region or a drain region. The transistor 300 can be either p-channel or n-channel. and low-resistance regions 314b. The transistor 300 can be either p-channel or n-channel. nel type.

[0252] Here, in the transistor 300 shown in FIG. 16, the semiconductor region 313 (a part of the substrate 311) where the channel is formed has a convex shape. Also, the side and upper surfaces of the semiconductor region 313 are provided so as to be covered by the conductor 316 via the insulator 315. Note that the conductor 316 may use a material for adjusting the work function. Such a transistor 300 is also called a FIN type transistor because it utilizes the convex portion of the semiconductor substrate. Note that it may have an insulator that functions as a mask for forming the convex portion and is in contact with the upper portion of the convex portion. Also, although the case of forming a convex portion by processing a part of the semiconductor substrate is shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate. a part of the substrate 311) has a convex shape. Also, the side and upper surfaces of the semiconductor region 313 are provided so as to be covered by the conductor 316 via the insulator 315. Note that the conductor 316 may use a material for adjusting the work function. Such a transistor 300 is also called a FIN type transistor because it utilizes the convex portion of the semiconductor substrate. Note that it may have an insulator that functions as a mask for forming the convex portion and is in contact with the upper portion of the convex portion. Also, although the case of forming a convex portion by processing a part of the semiconductor substrate is shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate. an insulator 315. Note that the conductor 316 may use a material for adjusting the work function. Such a transistor 300 is also called a FIN type transistor because it utilizes the convex portion of the semiconductor substrate. Note that it may have an insulator that functions as a mask for forming the convex portion and is in contact with the upper portion of the convex portion. Also, although the case of forming a convex portion by processing a part of the semiconductor substrate is shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate. A material for adjusting the work function may be used. Such a transistor 300 is also called a FIN type transistor because it utilizes the convex portion of the semiconductor substrate. Note that it may have an insulator that functions as a mask for forming the convex portion and is in contact with the upper portion of the convex portion. Also, although the case of forming a convex portion by processing a part of the semiconductor substrate is shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate. A material for adjusting the work function may be used. Such a transistor 300 is also called a FIN type transistor because it utilizes the convex portion of the semiconductor substrate. Note that it may have an insulator that functions as a mask for forming the convex portion and is in contact with the upper portion of the convex portion. Also, although the case of forming a convex portion by processing a part of the semiconductor substrate is shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate. A material for adjusting the work function may be used. Such a transistor 300 is also called a FIN type transistor because it utilizes the convex portion of the semiconductor substrate. Note that it may have an insulator that functions as a mask for forming the convex portion and is in contact with the upper portion of the convex portion. Also, although the case of forming a convex portion by processing a part of the semiconductor substrate is shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate. Here, although the case of forming a convex portion by processing a part of the semiconductor substrate is shown, a semiconductor film having a convex shape may be formed by processing an SOI substrate. Here, although the case of forming a convex portion by processing a part of the semiconductor substrate is shown, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0253] Note that the transistor 300 shown in FIG. 16 is an example and is not limited to its structure. An appropriate transistor may be used according to the circuit configuration and driving method. Note that the transistor 300 shown in FIG. 16 is an example and is not limited to its structure. An appropriate transistor may be used according to the circuit configuration and driving method.

[0254] <Capacitor element 100> The capacitor element 100 is provided above the transistor 200. The capacitor element 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and and an insulator 130 that functions as a dielectric.

[0255] Also, for example, the conductor 112 provided on the conductor 246 and the conductor 110 are formed at the same time. Note that the conductor 112 can be used for the capacitor 100, the transistor 200, and has a function as a plug or wiring that is electrically connected to the transistor 300 .

[0256] In FIG. 16, the conductor 112 and the conductor 110 are shown to have a single-layer structure. However, the present invention is not limited to this, and may be a laminated structure of two or more layers. For example, Conductors that have barrier properties between weak conductors and those with high electrical conductivity have good adhesion to conductors with high electrical conductivity. may form a highly conductive material.

[0257] The insulator 130 may be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, nitrogen Aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium The conductive layer may be formed as a laminate or a single layer.

[0258] For example, the insulator 130 may be made of a material with high dielectric strength, such as silicon oxynitride, or a material with high dielectric strength. It is preferable to use a laminated structure with a high-k material. The element 100 has a high dielectric constant (high-k) insulator, so that it can ensure sufficient capacitance. By using an insulator having a large dielectric strength, the dielectric strength is improved, and the electrostatic breakdown of the capacitance element 100 is prevented. This can suppress the destruction.

[0259] In addition, oxide is an insulator for high dielectric constant (high-k) materials (materials with a high relative dielectric constant). having gallium, hafnium oxide, zirconium oxide, aluminum and hafnium oxide having aluminum and hafnium, oxynitride having aluminum and hafnium, silicon and hafnium oxide having silicon and hafnium, oxynitride having silicon and hafnium, or nitride having silicon and haf nium, etc. are available.

[0260] On the other hand, as materials with high breakdown voltage (materials with low relative dielectric constant), there are silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or resin, etc. silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or resin, etc. silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or resin, etc. silicon oxide having pores, or resin, etc.

[0261] <Wiring layer> A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers can be provided according to the design. Here, conductors having the function of plugs or wiring may be given the same reference numeral for a plurality of structures. Also, in this specification, etc., the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug. A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers can be provided according to the design. Here, conductors having the function of plugs or wiring may be given the same reference numeral for a plurality of structures. Also, in this specification, etc., the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug. A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers can be provided according to the design. Here, conductors having the function of plugs or wiring may be given the same reference numeral for a plurality of structures. Also, in this specification, etc., the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug. A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers can be provided according to the design. Here, conductors having the function of plugs or wiring may be given the same reference numeral for a plurality of structures. Also, in this specification, etc., the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug. A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers can be provided according to the design. Here, conductors having the function of plugs or wiring may be given the same reference numeral for a plurality of structures. Also, in this specification, etc., the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug. A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers can be provided according to the design. Here, conductors having the function of plugs or wiring may be given the same reference numeral for a plurality of structures. Also, in this specification, etc., the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0262] For example, on the transistor 300, as the interlayer film, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked and provided. Also, a capacitor element 100, or conductors 328 and 330, etc. electrically connected to the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. For example, on the transistor 300, as the interlayer film, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked and provided. Also, a capacitor element 100, or conductors 328 and 330, etc. electrically connected to the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. For example, on the transistor 300, as the interlayer film, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked and provided. Also, a capacitor element 100, or conductors 328 and 330, etc. electrically connected to the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. For example, on the transistor 300, as the interlayer film, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked and provided. Also, a capacitor element 100, or conductors 328 and 330, etc. electrically connected to the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Note that the conductors 328 and 330 function as plugs or wirings.

[0263] In addition, the insulator that functions as an interlayer film may function as a planarization film that covers the uneven shape below it. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing ( CMP) method or the like to enhance flatness.

[0264] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 16, the insulators 350, 352, and 354 are sequentially stacked and provided. In addition, a conductor 356 is formed in the insulators 350, 352, and 354. The conductor 356 functions as a plug or a wiring.

[0265] Similarly, conductors 218 and the conductors constituting the transistor 200 are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 has a function as a plug or a wiring that is electrically connected to the capacitor element 100 or the transistor 300. Further, an insulator 150 is provided on the conductor 120 and the insulator 130.

[0266] Examples of insulators that can be used as interlayer films include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, and the like.

[0267] For example, by using a material with a low relative permittivity for the insulator that functions as an interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, the material may be selected according to the function of the insulator.

[0268] For example, for the insulator 150, the insulator 212, the insulator 352, the insulator 354, etc., it is preferable to use an insulator with a low relative permittivity. For example, the insulator preferably has silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with pores or resin, etc. Alternatively, the insulator preferably has a laminated structure of silicon oxide , silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine , silicon oxide with added carbon, silicon oxide with added carbon and nitrogen or silicon oxide with pores and resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure with low relative permittivity and thermal stability can be obtained by combining them with resin. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate or acrylic, etc.

[0269] In addition, a transistor using an oxide semiconductor can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, for the insulator 210, the insulator 350, etc., an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen can be used. Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine,

[0270] etc. Elements, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum An insulator containing hafnium or tantalum may be used in a single layer or in a laminate. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide, metal oxides such as, silicon oxynitride or silicon nitride can be used. .

[0271] As a conductor that can be used for wiring and plugs, materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used. Also, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, silicides such as nickel silicide may be used.

[0272] For example, as the conductors 328, 330, 356, 218, and 112, etc., conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed of the above materials can be used in a single layer or in a laminate. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is preferable to use tungsten. Or, it is preferable to form with a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be lowered. ​​​can be achieved.

[0273] <Wiring or plug of the layer provided with the oxide semiconductor> In addition, when an oxide semiconductor is used for the transistor 200, an insulator having an excessive oxygen region may be provided in the vicinity of the oxide semiconductor. In that case, it is preferable to provide an insulator having a barrier property between the insulator having the excessive oxygen region and a conductor provided in the insulator having the excessive oxygen region. It is preferable to provide.

[0274] For example, in FIG. 16, it is preferable to provide an insulator 276 between the insulator 224 having excessive oxygen and the conductor 245. By providing the insulator 276 in contact with the insulator 222, the insulator 272, and the insulator 273, the insulator 224 and the transistor 200 can be structured to be sealed with an insulator having a barrier property. Further, it is preferable that the insulator 276 is in contact with the insulator 280. With such a configuration, diffusion of oxygen and impurities can be further suppressed. That is, by providing the insulator 276, it is possible to suppress the absorption of the excessive oxygen of the insulator 224 by the conductor 245. Further, by having the insulator 276, it is possible to suppress the diffusion of hydrogen, which is an impurity, to the transistor 200 through the conductor 245.

[0275] That is, by providing the insulator 276, it is possible to suppress the absorption of the excessive oxygen of the insulator 224 by the conductor 245. It is possible to do.

[0276] In addition, as the insulator 276, an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen may be used. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, for example, magnesium oxide, gallium oxide, etc. ​​​​​​​​​Umm, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide Metal oxides such as osmium or tantalum oxide, silicon oxynitride or silicon nitride, etc. can be used.

[0277] The above is the description of the configuration example. By using this configuration, in a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and the reliability can be improved. Or, a transistor having an oxide semiconductor with a large on-current can be provided. Or, a transistor having an oxide semiconductor with a small off-current can be provided. Or, a semiconductor device with reduced power consumption can be provided. In a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and the reliability can be improved. Or, a transistor having an oxide semiconductor with a large on-current can be provided. Or, a transistor having an oxide semiconductor with a small off-current can be provided. Or, a semiconductor device with reduced power consumption can be provided.

[0278] [Memory device 2] An example of a memory device using the semiconductor device according to one aspect of the present invention is shown in FIG. 17. The memory device shown in FIG. 17 has a transistor 400 in addition to the semiconductor device having the transistor 200, the transistor 300, and the capacitive element 100 shown in FIG. 16. The memory device shown in FIG. 17 has a transistor 400 in addition to the semiconductor device having the transistor 200, the transistor 300, and the capacitive element 100 shown in FIG. 16. The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200. When the negative potential of the second gate of the transistor 200 is held in this configuration, the voltage between the first gate and the source and the voltage between the second gate and the source of the transistor 400 become 0V. In the transistor 400, the second gate voltage and the first gate voltage

[0279] The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200. When the negative potential of the second gate of the transistor 200 is held in this configuration, the voltage between the first gate and the source and the voltage between the second gate and the source of the transistor 400 become 0V. When the negative potential of the second gate of the transistor 200 is held in this configuration, the voltage between the first gate and the source and the voltage between the second gate and the source of the transistor 400 become 0V. The voltage between the first gate and the source and the voltage between the second gate and the source of the transistor 400 become 0V. pressure become 0V. In the transistor 400, the second gate voltage and the first gate voltage ​Since the drain current when the voltage is 0V is extremely small, even without supplying power to transistor 200 and transistor 400, the negative potential of the second gate of transistor 200 can be maintained for a long time. Thus, a memory device having transistor 200 and transistor 400 can retain the stored content over a long period of time.

[0280] Therefore, in FIG. 17, wiring 1001 is electrically connected to the source of transistor 300 and wiring 1002 is electrically connected to the drain of transistor 300. Also, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Then, the gate of transistor 3 00, and the other of the source and drain of transistor 200 are electrically connected to one of the electrodes of capacitor element 1 00, and wiring 1005 is electrically connected to the other electrode of capacitor element 100. Wiring 1007 is electrically connected to the source of transistor 400 and wiring 1008 is electrically connected to the first gate of transistor 400, wiring 1009 is electrically connected to the second gate of transistor 400, and wiring 1010 is electrically connected to the drain of transistor 400. Here, wiring 1006, wiring 1007, wiring 1008, and wiring 1009 are electrically connected.

[0281] Also, the memory device shown in FIG. 17 can form a memory cell array by being arranged in a matrix in the same manner as the memory device shown in FIG. 16. Note that one transistor 40 0 can control the second gate voltages of the plurality of transistors 200. It is preferable to provide fewer transistors 400 than transistors 200.

[0282] <Transistor 400> Transistor 400 is formed in the same layer as transistor 200 and is fabricated in parallel. The transistor 400 has a first gate electrode and a second gate electrode. A conductor 460 (conductor 460a and conductor 460b) that functions as a gate electrode and a second gate electrode The conductor 405 functions as a gate electrode, the insulator 222 functions as a gate insulating layer, and the insulator 2 24, and an insulator 450, an oxide 430c having an area in which a channel is to be formed, and The conductor 442a, which functions as either the source or drain, the oxide 443a, and the oxide 43 2a, and oxide 432b, and conductor 44 serving as the other of the source or drain. 2b, oxide 443b, oxide 431a, and oxide 431b, and conductor 440 (conductive 440a, and conductor 440b).

[0283] In the transistor 400, the conductor 405 is the same layer as the conductor 205. The oxide 431a and oxide 432a are the same layer as the oxide 230a. The conductors 442a and 442b are the same layer as the oxide 230b. The conductor 442b is the same layer as the conductor 242. b is the same layer as oxide 243. Oxide 430c is the same layer as oxide 230c. The insulator 450 is the same layer as the insulator 250. The conductor 460 is the same layer as the conductor 260. It is the same layer.

[0284] Note that structures formed in the same layer can be formed simultaneously. For example, oxide 4 30c can be formed by processing the oxide film 230C.

[0285] The oxide 430c that functions as the active layer of the transistor 400 has reduced oxygen deficiency and reduced impurities such as hydrogen or water, similar to the oxide 230 and the like. As a result, the threshold voltage of the transistor 400 can be made greater than 0 V, the off-current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be made very small.

[0286] <Dicing line> Hereinafter, a dicing line (sometimes referred to as a scribe line, a dividing line, or a cutting line) provided when a large-area substrate is divided into individual semiconductor elements to take out a plurality of semiconductor devices in chip form will be described. As a dividing method, for example, first, a groove (dicing line) for dividing the semiconductor elements is formed in the substrate, and then cutting is performed at the dicing line to divide (split) the substrate into a plurality of semiconductor devices.

[0287] Here, for example, as shown in FIG. 17, it is preferable to design the region where the insulator 272 and the insulator 222 are in contact to be the dicing line. That is, openings are provided in the insulator 224 in the vicinity of the region that becomes the dicing line provided at the outer edge of the memory cell having a plurality of transistors 200 and the transistor 400. Further, an insulator 272 is provided so as to cover the side surface of the insulator 224.

[0288] That is, in the opening provided in the insulator 224, the insulator 222 and the insulator 272 are​​​​​​​​​​​ They are in contact. For example, at this time, the insulator 222 and the insulator 272 may be formed using the same material and the same method. By providing the insulator 222 and the insulator 272 using the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use aluminum oxide.

[0289] With this structure, the insulator 222 and the insulator 272 can wrap the insulator 224, the transistor 200, and the transistor 400. Since the insulator 222 and the insulator 272 have a function of suppressing the diffusion of oxygen, hydrogen, and water, by dividing the substrate for each circuit region where the semiconductor element shown in this embodiment is formed, even if it is processed into a plurality of chips, impurities such as hydrogen or water can be prevented from mixing in from the side surface direction of the divided substrate and diffusing into the transistor 200 and the transistor 400.

[0290] In addition, with this structure, it is possible to prevent the excess oxygen of the insulator 224 from diffusing to the outside of the insulator 272 and the insulator 222. Therefore, the excess oxygen of the insulator 224 is efficiently supplied to the oxide in which the channel is formed in the transistor 200 or the transistor 400. By this oxygen, the oxygen deficiency of the oxide in which the channel is formed in the transistor 200 or the transistor 400 can be reduced. As a result, the oxide in which the channel is formed in the transistor 200 or the transistor 400 can be made into an oxide semiconductor having stable characteristics with a low defect level density. That is, the variation in the electrical characteristics of the transistor 200 or the transistor 400 can be suppressed, and the reliability can be improved.

[0291] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments and other examples.

[0292] (Embodiment 3) In this embodiment, with reference to FIGS. 18 and 19, a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) and a memory device to which a capacitive element is applied (hereinafter sometimes referred to as an OS memory device) according to one aspect of the present invention will be described. The OS memory device is a memory device having at least a capacitive element and an OS transistor that controls the charge and discharge of the capacitive element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a non-volatile memory. .

[0293] <Configuration Example of Memory Device> FIG. 18(A) shows an example of the configuration of an OS memory device. The memory device 1400 has a peripheral circuit 1 411 and a memory cell array 1470. The peripheral circuit 1411 has a row circuit 142 0, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0294] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. Note that the above wiring is the wiring connected to the memory cells included in the memory cell array 1470 and will be described in detail later. The amplified data signal is output as a data signal via the output circuit 1440. It is output to the outside of the memory device 1400 as RDATA. Also, the row circuit 1420 has, for example, a row decoder, a word line driver circuit, etc., and can select the row to be accessed.

[0295] The memory device 1400 is supplied with a low power supply voltage (VSS) as a power supply voltage from the outside, a high power supply voltage (VDD) for the peripheral circuit 14 11, and a high power supply voltage (VIL) for the memory cell array 1470. Also, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the memory device 1400 from the outside. The address signal ADDR is input to the row decoder and the column decoder, and WDATA is input to the write circuit.

[0296] The control logic circuit 1460 processes input signals (CE, WE, RE) from the outside and generates control signals for the row decoder and the column decoder. CE is a chip enable signal , WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and if necessary, other input signals may be processed to generate control signals for the row decoder or the column decoder.

[0297] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wires. Note that the number of wires connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cells MC in a column, etc. . Also, the number of wires connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cells MC in a row, etc.​​​​​​

[0298] In FIG. 18(A), an example is shown in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane. However, the present embodiment is not limited to this. For example, as shown in FIG. 18(B), the memory cell array 14 70 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap under the memory cell array 1470.

[0299] A configuration example of a memory cell applicable to the above-described memory cell MC will be described with reference to FIG. 19.

[0300] [DOSRAM] Circuit configuration examples of DRAM memory cells are shown in FIGS. 19(A) to (C). In this specification and the like, a DRAM using a 1OS transistor 1 capacitor element type memory cell may be referred to as DOSRA M (Dynamic Oxide Semiconductor Random Acc ess Memory). The memory cell 1471 shown in FIG. 19(A) has a transistor M1 and a capacitor element CA. The transistor M1 has a gate (which may be referred to as a front gate in some cases), and a back gate.

[0301] The first terminal of the transistor M1 is connected to the first terminal of the capacitor element CA, the second terminal of the transistor M 1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 is connected to the wiring BGL. The second terminal of the capacitor element C A is connected to the wiring CAL.

[0302] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. During data writing and reading, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

[0303] Also, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC can be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 19(B). Further, for example, the memory cell MC can be a memory cell composed of a transistor M1 having a single gate structure, that is, a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 19(C).

[0304] When the semiconductor device shown in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitive element 100 can be used as the capacitive element CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very low. That is, since the written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Moreover, the refreshing operation of the memory cell can be made unnecessary. Also, since the leakage current is very low, the memory cells 1471, 1472, The memory cell 1473 can store multi-level data or analog data.

[0305] In addition, in the DOSRAM, as described above, By providing a sense amplifier as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0306] [NOSRAM] FIG. 19(D) to (H) show a gain cell type memory cell having two transistors and one capacitor. A memory cell 1474 shown in FIG. The transistor M2 is a front-side transistor M3 and a capacitance element CB. The gate (sometimes simply referred to as the gate) and the back gate. The transistor M2 has a gain cell type memory cell. The storage device is NOSRAM (Nonvolatile Oxide Semiconductor It is sometimes called vector RAM.

[0307] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, and the transistor M The second terminal of the transistor M2 is connected to the wiring WBL, and the gate of the transistor M3 is connected to the wiring WOL. The back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the transistor M1 is connected to the wiring CAL. The first terminal of the transistor M2 is connected to the wiring R BL, the second terminal of the transistor M3 is connected to the line SL, and the second terminal of the transistor M The gate of 3 is connected to a first terminal of the capacitance element CB.

[0308] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor element CB. When writing data, during data retention, and when reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased. Also, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be appropriately changed. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 19(E). Also, for example, the memory cell MC may be a memory cell configured with a transistor M2 having a single gate structure, that is, a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 19(F). Also, for example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 19(G). When using the semiconductor device shown in the above embodiment for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor element 100 can be used as the capacitor element CB. When writing data, during data retention, and when reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased. Also, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be appropriately changed. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 19(E). Also, for example, the memory cell MC may be a memory cell configured with a transistor M2 having a single gate structure, that is, a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 19(F). Also, for example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 19(G). When using the semiconductor device shown in the above embodiment for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor element 100 can be used as the capacitor element CB. Also, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be appropriately changed. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 19(E). Also, for example, the memory cell MC may be a memory cell configured with a transistor M2 having a single gate structure, that is, a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 19(F). Also, for example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 19(G).

[0309] Also, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be appropriately changed. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 19(E). Also, for example, the memory cell MC may be a memory cell configured with a transistor M2 having a single gate structure, that is, a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 19(F). Also, for example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 19(G). When using the semiconductor device shown in the above embodiment for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor element 100 can be used as the capacitor element CB. Also, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be appropriately changed. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 19(E). Also, for example, the memory cell MC may be a memory cell configured with a transistor M2 having a single gate structure, that is, a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 19(F). Also, for example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 19(G). When using the semiconductor device shown in the above embodiment for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor element 100 can be used as the capacitor element CB. Also, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be appropriately changed. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 19(E). Also, for example, the memory cell MC may be a memory cell configured with a transistor M2 having a single gate structure, that is, a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 19(F). Also, for example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 19(G). When using the semiconductor device shown in the above embodiment for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor element 100 can be used as the capacitor element CB. Also, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be appropriately changed. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 19(E). Also, for example, the memory cell MC may be a memory cell configured with a transistor M2 having a single gate structure, that is, a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 19(F). Also, for example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 19(G). When using the semiconductor device shown in the above embodiment for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor element 100 can be used as the capacitor element CB.

[0310] When using the semiconductor device shown in the above embodiment for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor element 100 can be used as the capacitor element CB. When using the semiconductor device shown in the above embodiment for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor element 100 can be used as the capacitor element CB. When using the semiconductor device shown in the above embodiment for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor element 100 can be used as the capacitor element CB. By using an OS transistor, the leakage current of transistor M2 can be made very low. As a result, the written data can be held by transistor M2 for a long time, so that the frequency of refreshing the memory cell can be reduced. Moreover, the refresh operation of the memory cell can be made unnecessary. In addition, since the leakage current is very low, multi-valued data or analog data can be held in memory cell 1474. The same applies to memory cells 1475 to 1477. Note that transistor M3 may be a transistor having silicon in the channel formation region (hereinafter sometimes referred to as an Si transistor).

[0311] The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have a higher field-effect mobility than the OS transistor. Therefore, an Si transistor may be used as transistor M3 that functions as a read transistor. In addition, by using an Si transistor for transistor M3, transistor M2 can be stacked on transistor M3, so that the occupied area of the memory cell can be reduced and the high integration of the storage device can be achieved.

[0312] Moreover, transistor M3 may be an OS transistor.

[0313] When OS transistors are used for transistors M2 and M3, the memory cell array 1470 can be configured with only n-type transistors.

[0313] In addition, FIG. 19(H) shows an example of a gain cell type memory cell of a three-transistor one-capacitor element. is shown. The memory cell 1478 shown in FIG. 19(H) includes transistors M4 to M6 and a capacitance element CC. The capacitance element CC is provided as appropriate. The memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. The wiring GNDL is a wiring that provides a low-level potential. Note that the memory cell 1478 may be electrically connected to wirings RBL and WBL instead of the wiring BIL.

[0314] Transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of transistor M4 may be electrically connected to each other. Alternatively, transistor M4 may not have a back gate.

[0315] Note that transistors M5 and M6 may each be an n-channel type Si transistor or a p-channel type Si transistor. Alternatively, transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured with only n-type transistors.

[0316] When the semiconductor device shown in the above embodiment is used for the memory cell 1478, transistor 200 can be used as transistor M4, transistor 300 can be used as transistors M5 and M6, and capacitance element 100 can be used as the capacitance element CC. By using an OS transistor as transistor M4, the leakage current of transistor M4 can be made extremely low.

[0317] Note that, in the present embodiment, the peripheral circuit 1411, the memory cell array 1470, etc. The configuration is not limited to the above. The arrangement or function of these circuits, and the wires, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary. The arrangement or function of these circuits, and the wires, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.

[0318] As described above, the configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments and other examples.

[0319] (Embodiment 4) In this embodiment, an example of a chip 1200 on which a semiconductor device of the present invention is mounted will be described with reference to FIG. 20. A plurality of circuits (systems) are mounted on the chip 1200. The technology of integrating a plurality of circuits (systems) on one chip is sometimes referred to as a system on chip (SoC). As shown in FIG. 20(A), the chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like. As shown in FIG. 20(A), the chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like. Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like. The chip 1200 is provided with bumps (not shown), and is connected to the first surface of a printed circuit board (PCB) 1201 as shown in FIG. 20(B). Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201, and are connected to a motherboard 1203.

[0320] As shown in FIG. 20(A), the chip 1200 includes a CPU (Central Processing ssing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like. As shown in FIG. 20(A), the chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like. The chip 1200 is provided with bumps (not shown), and is connected to the first surface of a printed circuit board (PCB) 1201 as shown in FIG. 20(B). Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201, and are connected to a motherboard 1203.

[0321] The chip 1200 is provided with bumps (not shown), and is connected to the first surface of a printed circuit board (PCB) 1201 as shown in FIG. 20(B). Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201, and are connected to a motherboard 1203. As shown in FIG. 20(B), the chip 1200 is provided with bumps (not shown), and is connected to the first surface of a printed circuit board (PCB) 1201. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201, and are connected to a motherboard 1203. As shown in FIG. 20(B), the chip 1200 is provided with bumps (not shown), and is connected to the first surface of a printed circuit board (PCB) 1201. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201, and are connected to a motherboard 1203. As shown in FIG. 20(B), the chip 1200 is provided with bumps (not shown), and is connected to the first surface of a printed circuit board (PCB) 1201. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201, and are connected to a motherboard 1203.

[0322] ​​The motherboard 1203 is provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be provided with a DOSR as shown in the previous embodiment. For example, the flash memory 1222 may be The NOSRAM shown in FIG.

[0323] The CPU 1211 preferably has multiple CPU cores. It is preferable that the CPU 1211 and the GPU 1 have multiple GPU cores. Each of the CP 212 may have a memory for temporarily storing data. A memory common to U1211 and GPU1212 is provided on chip 1200. The memory may be the above-mentioned NOSRAM or DOSRAM. In addition, the GPU1212 is suitable for parallel calculation of large amounts of data, and is ideal for image processing and multiply-and-accumulate operations. The GPU 1212 can be used as an image processing circuit or the like using the oxide semiconductor of the present invention. By providing a multiply-and-accumulate circuit, image processing and multiply-and-accumulate operations can be performed with low power consumption. This will be possible.

[0324] In addition, the CPU 1211 and GPU 1212 are integrated on the same chip, The wiring between the CPU1211 and the GPU1212 can be shortened, and the Data transfer from the CPU 1211 to the GPU 1212, memory of the CPU 1211 and the GPU 1212 After data transfer between GPU1212 and calculation in GPU1212, the data is transferred from GPU1212 to CPU12. The calculation results can be transferred to 11 at high speed.

[0325] The analog calculation unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital has one or both of digital / analog conversion circuits. Also, the analog arithmetic unit 1213 may be provided with the above-mentioned sum-of-products arithmetic circuit.

[0326] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221 and has a circuit that functions as an interface for the flash memory 1222.

[0327] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As such an interface it is possible to use USB (Universal Serial Bus), HDMI (registered trademark) (H igh-Definition Multimedia Interface), etc. and so on. igh-Definition Multimedia Interface) and the like. It can be used.

[0328] The network circuit 1216 has a network circuit such as a LAN (Local Area Network). Also, it may have a circuit for network security. and so on. It may have.

[0329] It is possible to form the above circuit (system) on the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost. and so on. and the chip 1200 can be manufactured at low cost.

[0330] A PCB 1201 provided with a chip 1200 having a GPU 1212, a DRAM 122 1, and a motherboard 1203 provided with a flash memory 1222 are GPU modules It can be called the Yule 1204.

[0331] Since the GPU module 1204 has the chip 1200 using the SoC technology, its size can be reduced. Also, since it is excellent in image processing, smart phones, tablet terminals, laptop PCs, portable (portable) game machines, etc. are preferably used for portable electronic devices. Also, the multiplication-accumulation circuit using the GPU 1212 can execute operations such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), deep belief networks (DBN), etc. Therefore, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0332] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments and other examples.

[0333] (Embodiment 5) In this embodiment, an application example of a storage device using the semiconductor device shown in the previous embodiment will be described. The semiconductor device shown in the previous embodiment can be applied to storage devices of various electronic devices (for example, information terminals, computers, smartphones, e-book terminals, digital cameras (including video cameras), video recording / playback devices, navigation systems, etc.). Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers, but also large-scale computers such as server systems. is useless. Or, the semiconductor device shown in the previous embodiment is a memory card (e.g., S D card), USB memory, SSD (Solid State Drive), etc. of various removable It is applied to bubble storage devices. Some configuration examples of the removable storage device are schematically shown in FIG. 21 For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0334] FIG. 21(A) is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101 , a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 110 4 is housed in the housing 1101. For example, a memory chip 110 5 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1 105 etc. on the substrate 1104.

[0335] FIG. 21(B) is a schematic diagram of the appearance of an SD card, and FIG. 21(C) is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a base plate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 11 13. By providing a memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Also, a wireless chip having a wireless communication function may be provided on the substrate 1113 . Thereby, data of the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. The memory on the substrate 1113 chip 1114 A semiconductor device shown in the previous embodiment can be incorporated into the chip 1114 or the like.

[0336] FIG. 21(D) is a schematic diagram of the appearance of the SSD, and FIG. 21(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, memory chips 1154, memory chips 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a working memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. A semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1154 or the like on the substrate 1153.

[0337] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments and other examples.

[0338] (Embodiment 6) In the present embodiment, a specific example of an electronic device to which a semiconductor device according to an aspect of the present invention is applicable will be described with reference to FIG. 22.

[0339] More specifically, a semiconductor device according to an aspect of the present invention can be used for a processor such as a CPU or a GPU, or for a chip. FIG. 22 shows a specific example of an electronic device including a processor such as a CPU or a GPU according to an aspect of the present invention, or a chip.

[0340] <Electronic device / system> ​​​​​​​​A GPU or chip according to an embodiment of the present invention can be installed in various electronic devices. Examples of electronic devices include television sets, desktop or notebook computers, etc. Personal computers, computer monitors, digital signage tal Signage, large game machines such as pachinko machines, etc. In addition to electronic devices with large screens, digital cameras, digital video cameras, digital photos, Examples of the optical fiber include frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Furthermore, by providing an integrated circuit or chip according to one embodiment of the present invention in an electronic device, It is possible to equip child devices with artificial intelligence.

[0341] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images and information on the display unit. And if a secondary battery is included, the antenna may be used for contactless power transmission.

[0342] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation Numbers, distance, light, liquids, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared rays) It may have.

[0343] The electronic device according to one embodiment of the present invention can have various functions. Functions for displaying still images, videos, text images, etc. on the display, touch panel function, calendar Functions such as displaying date or time, running various software (programs) A function, a wireless communication function, and the ability to read a program or data recorded on a recording medium It can have functions and the like. FIG. 22 shows an example of an electronic device.

[0344] [Mobile phone] FIG. 22(A) shows a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided in the display unit 5511, and buttons are provided in the housing 551 0.

[0345] By applying the chip of one aspect of the present invention, the information terminal 5500 can execute an application using artificial intelligence. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5511, an application that recognizes characters, graphics, etc. input by the user on the touch panel provided in the display unit 5511 and displays them on the display unit 5511, and an application that performs biometric authentication such as fingerprint and voiceprint.

[0346] [Information terminal 1] FIG. 22(B) shows a desktop information terminal 5300. The desktop type information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0347] Similar to the information terminal 5500 described above, the desktop information terminal 5300 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention. Examples of applications using artificial intelligence include, for example, design support software , examples include article editing software, menu automatic generation software, etc. Also, by using the desktop type information terminal 5300, new artificial intelligence can be developed.

[0348] In the above description, smartphones and desktop information terminals are used as examples of electronic devices and are illustrated in FIGS. 22(A) and (B) respectively. However, one aspect of the present invention can also be applied to information terminals other than smartphones and desktop information terminals. Examples of information terminals other than smartphones and desktop information terminals include, for example, PDAs (Personal Digital Assistant), notebook type information terminals, workstations and the like.

[0349] [Household Appliance] FIG. 22(C) shows an electric refrigerator-freezer 5800, which is an example of a household appliance. The electric refrigerator-freezer 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, etc.

[0350] By applying a chip of one aspect of the present invention to the electric refrigerator-freezer 5800, an electric refrigerator-freezer 5800 having artificial intelligence can be realized. By using artificial intelligence, the electric refrigerator-freezer 5800 can have functions such as automatically generating a menu based on the ingredients stored in the electric refrigerator-freezer 5800 and the expiration date of those ingredients, and automatically adjusting the temperature according to the ingredients stored in the electric refrigerator-freezer 5800.

[0351] In this example, an electric refrigerator-freezer has been described as a household appliance. However, for other household appliances such as, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers , heating and cooling appliances including a water server and an air conditioner, washing machines, dryers, audio-visual equipment, etc. Examples include.

[0352] [Game console] Figure 22(D) shows a portable game console 5200, which is an example of a game console. The portable game console 5200 has a housing 5201, a display unit 5202, buttons 5203, etc.

[0353] By applying the GPU or chip of one aspect of the present invention to the portable game console 5200, a portable game console 5200 with low power consumption can be realized. Also, due to the low power consumption, heat generation from the circuit can be reduced, so the influence on the circuit itself, peripheral circuits, and modules caused by heat generation can be minimized.

[0354] Furthermore, by applying the GPU or chip of one aspect of the present invention to the portable game console 5200, a portable game console 5200 with artificial intelligence can be realized.

[0355] Originally, the progress of the game, the speech and actions of the creatures appearing in the game, the phenomena occurring in the game, etc. are defined by the program of that game, but by applying artificial intelligence to the portable game console 520 0, expressions not limited to the game program become possible. For example, expressions such as the content asked by the player, the progress of the game, the time, and the speech and actions of the characters appearing in the game changing become possible.

[0356] Also, when playing a game that requires multiple players on the portable game console 5200, artificial intelligence can be used to anthropomorphically configure game players, so the opponent can be an artificial intelligence. By setting it as a game player, a game can be played even by one person.

[0357] In FIG. 22(D), a portable game machine is illustrated as an example of a game machine, but the game machine to which the GPU or chip of one aspect of the present invention is applied is not limited to this. Examples of the game machine to which the GPU or chip of one aspect of the present invention is applied include, for example, a home stationary game machine, an arcade game machine installed in an entertainment facility (such as a game center or an amusement park), and a pitching machine for batting practice installed in a sports facility.

[0358] [Mobile object] The GPU or chip of one aspect of the present invention can be applied to a mobile object, an automobile, and the periphery of the driver's seat of the automobile.

[0359] FIG. 22(E1) shows an automobile 5700 which is an example of a mobile object, and FIG. 22(E2) is a view showing the periphery of the windshield inside the automobile. In FIG. 22(E2), in addition to the display panels 5701, 5702, and 5703 attached to the dashboard, the display panel 5704 attached to the pillar is illustrated.

[0360] The display panels 5701 to 5703 can provide various other information by displaying a speedometer, a tachometer, the travel distance, the fuel gauge, the gear state, the air conditioning settings, etc. Also, the display items and layout displayed on the display panel can be appropriately changed according to the user's preference, and it is possible to enhance the design. The display panels 5701 to 5703 can also be used as lighting devices.

[0361] The display panel 5704 can complement the field of view (blind spot) blocked by a pillar by displaying the video from an imaging device (not shown) provided in the vehicle 5700. That is, by displaying the image from the imaging device provided outside the vehicle 5700, the blind spot can be compensated for and the safety can be enhanced. Also, by displaying the video that complements the invisible part, a safety check can be performed more naturally and without a sense of incongruity. The display panel 57 04 can also be used as a lighting device.

[0362] Since the GPU or chip according to one aspect of the present invention can be applied as a component of artificial intelligence, for example, the chip can be used in the automatic driving system of the vehicle 5700. Also, the chip can be used in a system that performs road guidance, danger prediction, etc. The display panels 57 01 to 5704 may be configured to display information such as road guidance and danger prediction.

[0363] In the above description, the vehicle has been described as an example of the moving body, but the moving body is not limited to the vehicle. For example, examples of the moving body include trains, monorails, ships, aircraft (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc. The chip according to one aspect of the present invention can be applied to these moving bodies to provide a system that utilizes artificial intelligence.

[0364] [Broadcast system] The GPU or chip according to one aspect of the present invention can be applied to a broadcast system.

[0365] FIG. 22(F) schematically shows data transmission in the broadcast system. Specifically, ​​​, Figure 22(F) shows the path of the radio wave (broadcast signal) transmitted from the broadcasting station 5680 until it reaches the television reception device (TV) 5600 of each household. The TV 5600 is equipped with a reception device (not shown). The broadcast signal received by the antenna 5650 is transmitted to the TV 5600 via the reception device.

[0366] In Figure 22(F), the antenna 5650 is shown as a UHF (Ultra High Frequency) antenna. However, as the antenna 5650, a BS·110°CS antenna, a CS antenna, etc. can also be applied.

[0367] The radio waves 5675A and 5675B are broadcast signals for terrestrial digital television. The radio tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B. In each household, by receiving the radio wave 5675B with the antenna 5650, terrestrial digital television broadcasts can be viewed on the TV 5600 . Note that the broadcast system is not limited to the terrestrial digital television broadcast shown in Figure 22(F), and it may also be a satellite broadcast using an artificial satellite, a data broadcast using an optical fiber, etc. The above-described broadcast system may be a broadcast system using artificial intelligence by applying a chip of one aspect of the present invention. When transmitting broadcast data from the broadcasting station 5680 to the TV 5600 of each household, the broadcast data is compressed by an encoder, and when the antenna 5650 receives the broadcast data, the decoder of the reception device included in the TV 5600 restores the broadcast data. By using artificial intelligence, for example, in motion compensation prediction, which is one of the compression methods of the encoder, the recognition of the display pattern included in the display image is performed .

[0368] The above-described broadcast system may be a broadcast system using artificial intelligence by applying a chip of one aspect of the present invention. When transmitting broadcast data from the broadcasting station 5680 to the TV 5600 of each household, the broadcast data is compressed by an encoder, and when the antenna 5650 receives the broadcast data, the decoder of the reception device included in the TV 5600 restores the broadcast data. By using artificial intelligence, for example, in motion compensation prediction, which is one of the compression methods of the encoder, the recognition of the display pattern included in the display image is performed . When transmitting broadcast data from the broadcasting station 5680 to the TV 5600 of each household, the broadcast data is compressed by an encoder, and when the antenna 5650 receives the broadcast data, the decoder of the reception device included in the TV 5600 restores the broadcast data. By using artificial intelligence, for example, in motion compensation prediction, which is one of the compression methods of the encoder, the recognition of the display pattern included in the display image is performed . When transmitting broadcast data from the broadcasting station 5680 to the TV 5600 of each household, the broadcast data is compressed by an encoder, and when the antenna 5650 receives the broadcast data, the decoder of the reception device included in the TV 5600 restores the broadcast data. By using artificial intelligence, for example, in motion compensation prediction, which is one of the compression methods of the encoder, the recognition of the display pattern included in the display image is performed . When the antenna 5650 receives the broadcast data, the decoder of the reception device included in the TV 5600 restores the broadcast data. By using artificial intelligence, for example, in motion compensation prediction, which is one of the compression methods of the encoder, the recognition of the display pattern included in the display image is performed . By using artificial intelligence, for example, in motion compensation prediction, which is one of the compression methods of the encoder, the recognition of the display pattern included in the display image is performed . In motion compensation prediction, which is one of the compression methods of the encoder, the recognition of the display pattern included in the display image is performed This is achievable. Additionally, it is also possible to perform in-frame prediction using artificial intelligence. Also, for example, when receiving broadcast data with low resolution and displaying the broadcast data on a high-resolution TV 5600, in the restoration of broadcast data by a decoder, interpolation processing of images such as up-conversion can be performed.

[0369] The broadcast system using artificial intelligence described above is suitable for ultra-high-definition television (UHDTV: 4K, 8K) broadcasts with an increasing amount of broadcast data.

[0370] Also, as an application of artificial intelligence on the TV 5600 side, for example, a recording device with artificial intelligence may be provided in the TV 5600. By adopting such a configuration, the recording device can automatically record programs according to the user's preferences by having the artificial intelligence learn the user's preferences.

[0371] The electronic devices, the functions of the electronic devices, application examples of artificial intelligence, and the effects described in this embodiment can be appropriately combined with the descriptions of other electronic devices.

[0372] As described above, the configurations, methods, etc. shown in this embodiment can be appropriately combined and used with the configurations, methods, etc. shown in other embodiments and other examples.

Example

[0373] In this example, in a laminate with a conductor provided on an oxide, the sheet resistance of the laminate was measured. As the conductor on the oxide, tantalum nitride was used, and the sheet resistance of tantalum nitride was measured. The samples used for the measurement will be described.

[0374] ​First, the method for preparing Sample A will be described. The surface of a substrate containing silicon was heat-treated in an atmosphere of hydrogen chloride (HCl), and a silicon oxide film with a thickness of 100 nm was formed on the substrate. Next, a silicon oxynitride film with a thickness of 300 nm was formed on the silicon oxide film using the CVD method. In addition, oxygen was implanted into the silicon oxynitride film using the ion implantation method so that the silicon oxynitride film functions as an oxygen supply film. Next, on the silicon oxynitride film, a first oxide with a thickness of 5 nm was formed using a sputtering method with a target of In:Ga:Zn = 4:2:4.1 [atomic ratio]. Next, on the first oxide, a tantalum nitride film with a thickness of 5 nm was formed using the sputtering method. The tantalum nitride film was formed at room temperature in an atmosphere containing argon and nitrogen using a target containing Ta.

[0375] Next, Sample B will be described. Sample B uses the same first oxide as Sample A described above. On the first oxide, a second oxide with a thickness of 1 nm was formed using a sputtering method with a target of In:Ga:Zn = 1:3:4 [atomic ratio]. Next, a tantalum nitride film was formed on the second oxide in the same manner as in Sample A.

[0376] Next, Sample C will be described. Sample C uses the same first oxide as Samples A and B described above. On the first oxide, a second oxide with a thickness of 5 nm was formed using a sputtering method with a target of In:Ga:Zn = 1:3:4 [atomic ratio]. Next, a tantalum nitride film was formed on the second oxide in the same manner as in Samples A and B.

[0377] ​​​​​​​​​​​Sample A is sample A1 to sample A8, and sample B is sample B1 to sample B8. Sample B8 and sample C were divided into eight parts, sample C1 to sample C8. The samples were heated in a nitrogen atmosphere at two temperatures: 150°C and 175°C. The treatment was carried out under four conditions: none, 1 hour, 10 hours, and 100 hours, for a total of eight conditions. The processing conditions for all samples are summarized in Table 1.

[0378] [Table 1]

[0379] FIG. 23 shows a graph of the heat treatment time dependence of the sheet resistance of tantalum nitride. 23(B) is a graph showing the results when the heat treatment temperature is 175° C. In all samples, the tantalum nitride crystallinity increased with increasing heat treatment time. Although an increase in the gate resistance is observed, by inserting a second oxide between the first oxide and tantalum nitride, In the implanted samples B and C, the increase in the sheet resistance of tantalum nitride was observed after the second The increase in sheet resistance of the tantalum nitride sample A without the oxide was suppressed. In addition, at a heating temperature of 150° C., as shown in FIG. 23(A), the second oxide Sample B has a thickness of 1 nm, and Sample C has a thickness of 5 nm. No difference in the increase in the sheet resistance of tantalum nitride was observed. At a temperature of 175°C, the thickness of the second oxide is smaller than that of sample B, which has a thickness of 1 nm. The increase in the sheet resistance of tantalum nitride is suppressed in sample C, which has a film thickness of 5 nm. It became.

[0380] This embodiment can be appropriately combined with the configurations, methods, etc. shown in other embodiments and other examples and used accordingly.

Example

[0381] In this embodiment, in a laminate in which a conductor is provided on an oxide, the sheet resistance in the depth direction of the oxide was measured. The sample used for the measurement will be described.

[0382] First, the method for manufacturing sample D will be described. A quartz substrate was prepared, and on the quartz substrate, , by sputtering, a first oxide with a film thickness of 500 nm was formed using a target of In:Ga:Zn = 4:2:4.1 [atomic ratio]. Next, heat treatment was carried out in a nitrogen atmosphere at 400 °C for 1 hour, and then heat treatment was carried out in an oxygen atmosphere at 400 °C for 1 hour.

[0383] Next, a tantalum nitride film with a film thickness of 20 nm was formed on the first oxide by sputtering. The tantalum nitride film was formed at room temperature in an atmosphere containing argon and nitrogen using a target containing Ta.

[0384] Next, sample E will be described. Sample E uses the same first oxide as sample D described above. On the first oxide, a second oxide with a film thickness of 1 nm was formed by sputtering using a target of In:Ga:Zn = 1:3:4 [atomic ratio]. Next, heat treatment was carried out in a nitrogen atmosphere at 400 °C for 1 hour, and then heat treatment was carried out in an oxygen atmosphere at 400 °C for 1 hour.

[0385] Next, a tantalum nitride film with a film thickness of 20 nm was formed on the first oxide by sputtering. It was formed. The tantalum nitride film was formed at room temperature in an atmosphere containing argon and nitrogen using a target containing Ta. It was formed at room temperature in an atmosphere containing argon and nitrogen using a target containing Ta.

[0386] Next, Sample F will be described. Sample F uses the one formed with the first oxide in the same manner as Sample D and Sample E described above. On the first oxide, by sputtering method, a second oxide with a film thickness of 5 nm was formed using a target of In:Ga:Zn = 1:3:4 [atomic ratio]. Next, heat treatment was continued at 400 °C for 1 hour in a nitrogen atmosphere, and then heat treatment was performed at 400 °C for 1 hour in an oxygen atmosphere. Next, on the first oxide, a tantalum nitride film with a film thickness of 20 nm was formed by sputtering method. The tantalum nitride film was formed at room temperature in an atmosphere containing argon and nitrogen using a target containing Ta.

[0387] Next, on the first oxide, a tantalum nitride film with a film thickness of 20 nm was formed by sputtering method. The tantalum nitride film was formed at room temperature in an atmosphere containing argon and nitrogen using a target containing Ta. It was formed at room temperature in an atmosphere containing argon and nitrogen using a target containing Ta.

[0388] Sample D was divided into 8 parts, namely Sample D1 to Sample D8, Sample E was divided into 8 parts, namely Sample E1 to Sample E8, and Sample F was divided into 8 parts, namely Sample F1 to Sample F8. Each sample was subjected to a total of 8 conditions of treatment, including 2 conditions of heat treatment temperatures of 150 °C and 175 °C in a nitrogen atmosphere, and 4 conditions of heat treatment times of 0 hour, 1 hour, 10 hours, and 100 hours. Table 2 shows a summary of the treatment conditions for all samples.

Table 2

[0389]

Table 2

[0390] Next, for each sample, the tantalum nitride was removed using the dry etching method. Next, for each sample, a step of measuring the sheet resistance of the first oxide (step 1) was performed. Next, a step of etching the first oxide by about 3 nm (step 2) was performed. Next, a step of measuring the remaining film thickness of the first oxide (step 3) was performed. Subsequently, steps 1 to 3 were repeated until the sheet resistance was over range at 6×10 Ω / □. Note that for the samples of E1 to E8 and F1 to F8, in the first step 1, the sheet resistance of the second oxide may be measured, but the influence on the results of this example is small. FIGS. 24 and 25 show the change in the sheet resistance of the first oxide in the depth direction. FIG. 24 is a graph at a heat treatment temperature of 150° C. FIG. 24(A) is a graph of a configuration without the second oxide, FIG. 24(B) is a graph of a configuration with a film thickness of 1 nm of the second oxide, and FIG. 24(C) is a graph of a configuration with a film thickness of 5 nm of the second oxide. FIG. 25 is a graph at a heat treatment temperature of 175° C. FIG. 25(A) is a graph of a configuration without the second oxide, FIG. 25(B) is a graph of a configuration with a film thickness of 1 nm of the second oxide, and FIG. 25(C) is a graph of a configuration with a film thickness of 5 nm of the second oxide. From FIGS. 24 and 25, it was found that by disposing 5 nm of the second oxide between the first oxide and the conductor, the progress of the low-resistance region of the first oxide in the depth direction is suppressed compared to the configuration without the second oxide even when heat treatment is performed at 150° C. and 175° C. for 1 hour, 10 hours, and 100 hours. 6

[0391]

[0392]

[0393] ​​​​​​​​​​​​​​​ This example can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments and other examples. It can be used in combination as appropriate with the configurations, methods, etc. shown in other embodiments and other examples.

Example

[0394] In this example, using the method described in <Method for manufacturing semiconductor device>, a sample fabricated up to the insulating film 250A was used to perform cross-sectional observation of the site shown in Fig. 3(A) and analysis by energy-dispersive X-ray spectroscopy (EDX) using a scanning transmission electron microscope (HD-2700 manufactured by Hitachi High-Technologies Corporation). Using the fabricated sample, cross-sectional observation of the site shown in Fig. 3(A) and analysis by energy-dispersive X-ray spectroscopy (EDX) were performed using a scanning transmission electron microscope (HD-2700 manufactured by Hitachi High-Technologies Corporation). Using the fabricated sample, cross-sectional observation of the site shown in Fig. 3(A) and analysis by energy-dispersive X-ray spectroscopy (EDX) were performed using a scanning transmission electron microscope (HD-2700 manufactured by Hitachi High-Technologies Corporation). was used.

[0395] The configuration of the fabricated sample will be described. Samples G1 and G2 have a configuration in which there is no oxide 243 between the oxide 230b and the conductor 242. Samples H1 and H2 have a configuration in which an oxide 243 is disposed between the oxide 230b and the conductor 242, and the film thickness of the oxide 243 is 1 nm. Samples I1 and I2 have a configuration in which an oxide 243 is disposed between the oxide 230b and the conductor 242, and the film thickness of the oxide 243 is 2 nm. Samples J1 and J2 have a configuration in which an oxide 243 is disposed between the oxide 230b and the conductor 242, and the film thickness of the oxide 243 is 3 nm. In all samples, the other configurations are the same. Samples G1 and G2 have a configuration in which there is no oxide 243 between the oxide 230b and the conductor 242. Samples H1 and H2 have a configuration in which an oxide 243 is disposed between the oxide 230b and the conductor 242, and the film thickness of the oxide 243 is 1 nm. Samples I1 and I2 have a configuration in which an oxide 243 is disposed between the oxide 230b and the conductor 242, and the film thickness of the oxide 243 is 2 nm. Samples J1 and J2 have a configuration in which an oxide 243 is disposed between the oxide 230b and the conductor 242, and the film thickness of the oxide 243 is 3 nm. In all samples, the other configurations are the same. Samples H1 and H2 have a configuration in which an oxide 243 is disposed between the oxide 230b and the conductor 242, and the film thickness of the oxide 243 is 1 nm. Samples I1 and I2 have a configuration in which an oxide 243 is disposed between the oxide 230b and the conductor 242, and the film thickness of the oxide 243 is 2 nm. Samples J1 and J2 have a configuration in which an oxide 243 is disposed between the oxide 230b and the conductor 242, and the film thickness of the oxide 243 is 3 nm. In all samples, the other configurations are the same. Samples I1 and I2 have a configuration in which an oxide 243 is disposed between the oxide 230b and the conductor 242, and the film thickness of the oxide 243 is 2 nm. Samples J1 and J2 have a configuration in which an oxide 243 is disposed between the oxide 230b and the conductor 242, and the film thickness of the oxide 243 is 3 nm. In all samples, the other configurations are the same. Samples J1 and J2 have a configuration in which an oxide 243 is disposed between the oxide 230b and the conductor 242, and the film thickness of the oxide 243 is 3 nm. In all samples, the other configurations are the same. Samples J1 and J2 have a configuration in which an oxide 243 is disposed between the oxide 230b and the conductor 242, and the film thickness of the oxide 243 is 3 nm. In all samples, the other configurations are the same. and the film thickness of the oxide 243 is 3 nm. In all samples, the other configurations are the same. are the same.

[0396] In this example, as the oxide 230b, a film formed using a target of In:Ga:Zn = 4:2:4.1 [atomic ratio] by sputtering was used, and as the oxide 243, a film formed using a target of In:Ga:Zn = 1:3:4 [atomic ratio] was used. Also, as the conductor 242, a film formed by sputtering tantalum nitride was used. using a target of In:Ga:Zn = 4:2:4.1 [atomic ratio] by sputtering was used, and as the oxide 243, a film formed using a target of In:Ga:Zn = 1:3:4 [atomic ratio] was used. Also, as the conductor 242, a film formed by sputtering tantalum nitride was used. using a target of In:Ga:Zn = 1:3:4 [atomic ratio] was used. Also, as the conductor 242, a film formed by sputtering tantalum nitride was used. using a target of In:Ga:Zn = 1:3:4 [atomic ratio] was used. Also, as the conductor 242, a film formed by sputtering tantalum nitride was used. was used.

[0397] Samples G1, H1, I1, and J1 were subjected to heat treatment in a nitrogen atmosphere at a heating temperature of 400°C for 4 hours. Samples G2, H2, I2, and J2 were subjected to heat treatment in a nitrogen atmosphere at a heating temperature of 400°C for 8 hours. After the above heat treatment, cross-sectional observations of each sample were performed. As an example, Fig. 26 shows a cross-sectional image of sample J1. It was confirmed that a laminate of oxide 230a, oxide 230b, oxide 243, and conductor 242 was formed on insulator 224. Next, EDX line analysis of each sample was performed. The outline of the analyzed location is indicated by an arrow in Fig. 26.

[0398] The results of summarizing the EDX line analysis for oxygen and gallium are shown in Figs. 27 and 28. Also, the distance between the conductor and the interface of the oxide was determined from the line analysis profile of gallium. In Fig. 27, it is around 29.1 nm, and in Fig. 28, it is around 28.7 nm that is the interface between the conductor and the oxide. Fig. 27 shows the EDX line analysis results of oxygen and gallium for samples G1, H1, I1, and J1 that were heat-treated for 4 hours, and Fig. 28 shows the EDX line analysis results of oxygen and gallium for samples G2, H2, I2, and J2 that were heat-treated for 8 hours. On insulator 224, it was confirmed that a laminate of oxide 230a, oxide 230b, oxide 243, and conductor 242 was formed.

[0399] In Fig. 27, the profile of oxygen of each sample intersects with the quantitative value = 20 atomic% at the position where sample G1, which does not have oxide 243, has the smallest distance, followed by sample H1 with a film thickness of 1 nm of oxide 243, and then

[0400]

[0401] ​ Sample I1 with the oxide 243 having a film thickness of 2 nm, and then sample J1 with the oxide 243 having a film thickness of 3 nm is obtained. That is, it was confirmed that the thicker the film thickness of the oxide 243, the more the diffusion of oxygen into the conductor 242 tends to be suppressed. Also, in FIG. 28, it was found that it generally shows a similar tendency . .

[0402] From the above results, the oxide 243 has a function of suppressing the diffusion of oxygen into the conductor 242, and it was found that the thicker the film thickness of the oxide 243, the more the diffusion of oxygen into the conductor 242 tends to be suppressed . .

[0403] This example can be appropriately combined with the configurations, methods, etc. shown in other embodiments and other examples and used .

Example

[0404] In this example, a sample having the transistor 200 was fabricated by the method described in <Method for fabricating a semiconductor device>, and the reliability of the transistor 200 was evaluated. The fabricated samples were two types, sample K and sample L. In sample K and sample L, the substrate temperature during the formation of the oxide 243 is different . Sample K was formed with a film thickness of 2 nm at a substrate temperature of 200 °C using a target of In:Ga:Zn = 1 :3:4 [atomic ratio] as the oxide 243 by sputtering. Also, sample L was formed with a film thickness of 2

[0405] nm at a substrate temperature of 250 °C using a target of In:Ga :Zn = 1:3:4 [atomic ratio] as the oxide 243 by sputtering. Note that both sample J and sample K were annealed at 400 °C for 8 hours in a nitrogen atmosphere . . nm. Also, both sample J and sample K were annealed at 400 °C for 8 hours in a nitrogen atmosphere Heat treatment was performed for a certain period of time.

[0406] Next, the reliability of Sample K and Sample L was evaluated. The reliability evaluation was performed by a +G BT (Gate Bias Temperature) stress test. In the BT stress test, while heating the substrate, the conductor 242a that functions as the source electrode of the transistor, the conductor 242b that functions as the drain electrode, and the conductor 205 that functions as the second gate (bottom gate) electrode are set to the same potential, and a potential higher than the potential applied to the conductor 242a, the conductor 242b, and the conductor 205 is applied to the conductor 260 that functions as the first gate (top gate electrode) for a certain period of time. In the +GBT stress test according to this embodiment, the set temperature was 150 °C, the drain potential V d, the source potential V

[0407] s, and the bottom gate potential V b were set to 0 V, and the top gate potential V S t was set to +3.63 V. Note that for Sample K and Sample L, stress tests were performed on two elements each. BG The size of the element was evaluated with a channel length of 60 nm and a channel width of 60 G nm as the design values. During the +GBT stress test, I -V measurements were performed at regular intervals. The I D -V

[0408] measurement was performed by setting the drain potential Vd of the transistor to +1.2 V, the source potential V G s to 0 V, the bottom D gate potential V G b to 0 V, and sweeping the gate potential V g from -3.3 V to +3.3 V. Note that the I S -V measurement was performed by setting the drain potential Vd of the transistor to +1.2 V, the source potential V BG s to 0 V, the bottom G gate potential V b to 0 V, and sweeping the gate potential V D g from -3.3 V to +3.3 V.G For the measurement, a semiconductor parameter analyzer manufactured by Keysight Technologies was used. Also, in the +GBT stress test, as an index of the amount of change in the electrical characteristics of the transistor, ΔVsh representing the amount of change in the shift voltage Vsh from the start of measurement was used. The shift voltage Vsh is defined as the value of Vg where the tangent line of the maximum slope of the I-V curve intersects with Id = 1.0×10(A). The results of the +GBT stress test of sample K are shown in Fig. 29(A). Also, the results of the +GBT stress test of sample L are shown in Fig. 29(B). In Fig. 29, the horizontal axis represents the stress time (hr), and the vertical axis represents ΔVsh (mV). As shown in Fig. 29(A), for both elements of sample K, even after 550 hours passed in the state where the above stress was applied, the amount of change in the shift voltage ΔVsh was 100 mV or less. Specifically, for the first element indicated by the white circle in the figure, ΔVsh after 550 hours was 28 mV, and for the second element indicated by the white square, ΔVsh after 550 hours was 23 mV. D -V G The tangent line of the maximum slope of the I-V curve intersects with Id = 1.0×10(A). -1 2 at the value of Vg where the tangent line of the maximum slope of the I-V curve intersects with Id = 1.0×10(A).

[0409] As shown in Fig. 29(B), also for sample L, for both elements, even after 550 hours passed in the state where the above stress was applied, the amount of change in the shift voltage ΔVsh was 100 mV or less. Specifically, for the first element indicated by the white circle in the figure, ΔVsh after 550 hours was 53 mV, and for the second element indicated by the white square, ΔVsh after 550 hours was 92 mV. In Fig. 29, the horizontal axis represents the stress time (hr), and the vertical axis represents ΔVsh (mV). The horizontal axis represents the stress time (hr), and the vertical axis represents ΔVsh (mV).

[0410] As shown in Fig. 29(A), for both elements of sample K, even after 550 hours passed in the state where the above stress was applied, the amount of change in the shift voltage ΔVsh was 100 mV or less. Specifically, for the first element indicated by the white circle in the figure, ΔVsh after 550 hours was 28 mV, and for the second element indicated by the white square, ΔVsh after 550 hours was 23 mV. Specifically, for the first element indicated by the white circle in the figure, ΔVsh after 550 hours was 28 mV, and for the second element indicated by the white square, ΔVsh after 550 hours was 23 mV. For the second element indicated by the white square, ΔVsh after 550 hours was 23 mV. was.

[0411] Also, as shown in Fig. 29(B), for sample L, for both elements, even after 550 hours passed in the state where the above stress was applied, the amount of change in the shift voltage ΔVsh was 100 mV or less. Specifically, for the first element indicated by the white circle in the figure, ΔVsh after 550 hours was 53 mV, and for the second element indicated by the white square, ΔVsh after 550 hours was 92 mV. Specifically, for the first element indicated by the white circle in the figure, ΔVsh after 550 hours was 53 mV, and for the second element indicated by the white square, ΔVsh after 550 hours was 92 mV. h was 53 mV, and for the second element indicated by the white square, ΔVsh after 550 hours was 92 mV.

[0412] From the above results, it was found that placing the oxide 243 between the oxide 230 and the conductor 242 can suppress ΔVsh in the +GBT stress to 1 00 mV or less after 550 hours of stress time. Also, for sample K with a substrate temperature of 2 00 °C during the formation of the oxide 243, ΔVsh in the +GBT stress was smaller than that of sample L with a substrate temperature of 250 °C. This was confirmed.

[0413] This example can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments and other examples.

Example

[0414] In this example, the reliability evaluation described in Example 4 was continued, and the results exceeding 1000 hours of stress time will be described. The sample for which the reliability evaluation was continued was the oxide 2 43, and sample K was formed with a film thickness of 2 nm at a substrate temperature of 200 °C using a sputtering method with a target of In:Ga:Zn = 1:3:4 [atomic ratio]. The reliability evaluation was performed by a +GBT stress test at a stress temperature of 150 °C in the same manner as in Example 4. In the same stress test, the stress time when ΔVsh exceeds 100 mV is defined as the life of the transistor. Also, the variations of Ion, S value, and μFE with stress time were evaluated.

[0415] Note that Ion (A) is the value of Id when Vd = 1.2 V and Vg = 3.3 V. The S value (mV / dec) is the value of Vg required for Id to change by one digit in the subthreshold region with Vd set to 1.2 V. μFE (cm / Vs) is the gradual 2 ... It is a value calculated from the equation in the linear region of channel approximation.

[0416] Figure 30 shows the results of the +GBT stress test. In Figure 30, the horizontal axis indicates the stress time ( hr), and the vertical axis indicates ΔVsh (mV). As shown in Figure 30, even after 1000 hours have elapsed with stress applied to sample K, the change amount ΔVsh of the shift voltage remained at 97 mV, maintaining below 100 mV.

[0417] The set temperature of 150°C for the +GBT stress test evaluated in this example is estimated to accelerate degradation by about 24 times compared to the set temperature of 125°C for the +GBT stress test . Therefore, it can be estimated that the lifetime in the case of a stress temperature of 125°C is 20,000 hours or more.

[0418] Figure 31(A) shows the variation of Ion with stress time. Figure 31(B) shows the variation of the S value with stress time. Figure 31(C) shows the variation of μFE with stress time. As shown in Figures 31(A), (B), and (C), it was confirmed that the variations of Ion, the S value, and μFE with stress time are small.

[0419] From the above results, it was confirmed that the transistor 200, which is one aspect of the present invention, has high reliability.

[0420] This example can be appropriately combined with the configurations, methods, etc. shown in other embodiments and other examples and used.

Example

[0421] In this example, a reliability evaluation was performed, and the results up to a stress time of 2000 hours will be described. ​​​​​​​​Samples for reliability evaluation were prepared as oxide 243 by sputtering method using a target with an atomic ratio of In:Ga:Zn = 1:3:4, at a substrate temperature of 200 °C to form a film with a thickness of 2 nm. Sample L was used. Note that Sample L was heat-treated in a nitrogen atmosphere at 400 °C for 8 hours, similar to Sample K. The reliability evaluation was performed by the +GBT stress test at a stress temperature of 150 °C, similar to Example 5. In the same stress test, the stress time when ΔVsh exceeded 100 mV was defined as the lifetime of the transistor. Also, the variations of Ion, S value, and μFE with stress time were evaluated as well.

[0422] The results of the +GBT stress test are shown in Fig. 32. In Fig. 32, the horizontal axis represents the stress time (hr), and the vertical axis represents ΔVsh (mV). As shown in Fig. 32, for Sample L, at the time when 1790 hours had passed under stress, ΔVsh = -92 mV, and the change amount of the shift voltage ΔVsh remained within ±100 mV. However, at the time when 1800 hours had passed, the change amount ΔVsh of the shift voltage exceeded ±100 mV. Therefore, in the +GBT stress test at a stress temperature of 150 °C, the lifetime of the transistor in Sample L was 1790 hours .

[0423] The set temperature of 150 °C for the +GBT stress test evaluated in this example is estimated to accelerate degradation by about 24 times compared to the set temperature of 125 °C for the +GBT stress test. Therefore, it can be estimated that the lifetime at a stress temperature of 125 °C is 40000 hours or more.

[0424] Figure 33(A) shows the change in Ion with stress time. Figure 33(B) shows the change in S value with stress time. Figure 33(C) shows the variation of μFE with stress time. As shown in 3(A), (B), and (C), Ion, S value, and μFE all change with stress time. It was confirmed that the fluctuation due to the

[0425] The above results show that the transistor 200 of one embodiment of the present invention has high reliability. I confirmed that.

[0426] This embodiment may be appropriately combined with the structures and methods shown in other embodiment modes and other embodiments. It can be used. EXAMPLES

[0427] In this embodiment, the transistor 200 is manufactured by the method described in <Method for manufacturing a semiconductor device>. A sample M having a transistor 200 is fabricated. D -V G Measure the electrical characteristics The variability was evaluated.

[0428] Sample M is a ZnO oxide 243 formed by sputtering. A 2 nm thick film was formed at a substrate temperature of 200°C using a target with an atomic ratio of 3:4. Sample M was subjected to a heat treatment at 400° C. for 4 hours in a nitrogen atmosphere.

[0429] Next, sample M's I D -V G The design values ​​were a channel length of 60 nm and a channel width of 60 nm. 27 elements of 60 nm and 9 elements with a channel length of 350 nm and a channel width of 350 nm as designed Each child was measured.

[0430] I D-V G The measurement was performed by setting the drain potential Vd of the transistor to +1.2 V, the source potential V S to 0 V, the bottom gate potential V BG to 0 V, and sweeping the gate potential V G from -3.3 V to + 3.3 V.

[0431] Figure 34 shows the normal probability plot of Vsh obtained from the I D -V G measurement. The variation in Vsh with a channel length of 60 nm and a channel width of 60 nm in the design value was 71 mV in standard deviation value and that. Also, the variation in Vsh with a channel length of 350 nm and a channel width of 350 nm in the design value was 38 mV in standard deviation value, and small variation results were obtained for both a channel length of 60 nm and a channel width of 60 nm in the design value and a channel length of 350 nm and a channel width of 350 nm in the design value.

[0432] Figure 35 shows the normal probability plot of I G when the gate potential V D (Ion1) is set to +3.3 V. The variation in Ion1 with a channel length of 60 nm and a channel width of 60 nm in the design value was 0.8 μA in standard deviation value and that. Also, the variation in Ion1 with a channel length of 350 nm and a channel width of 35 0 nm in the design value was 0.2 μA in standard deviation value.

[0433] Figure 36 shows the normal probability plot of I G when the gate potential V D (Ion2) is set to Vsh + 2.5 V. The variation in Ion2 with a channel length of 60 nm and a channel width of 60 nm in the design value was 0.6 μA in standard deviation value. Also, the variation in Ion2 with a channel length of 350 nm and a channel The variation of Ion2 at 350 nm was 0.1 μA in terms of the standard deviation value.

[0434] This example can be appropriately combined with the configurations, methods, etc. shown in other embodiments and other examples. and used.

Example

[0435] In this example, attention was paid to the fact that defects existing in the crystal of the oxide semiconductor contribute to the leakage current, and an estimate was made by device calculation about the influence of defects in CAAC-IGZO on the off-current, including the temperature dependence.

[0436] The model of the transistor used for the evaluation had the configuration of the transistor 200 shown in FIG. 1, and the gate insulating film had a thickness of 6 nm in terms of EOT, a gate length of 60 nm, and a channel width of 60 nm. Also, the defect level was set to be a level derived from oxygen deficiency located near the mid-gap of the energy gap of CAAC-IGZO from the analysis results such as hard X-ray photoelectron spectroscopy (HX-PES). As a result of the device calculation, the I-V characteristics at V = 1.2 V D = 1.2 V D -V G showed that the gradient of I was gentler in the region where V was lower than the I-V characteristics without setting the defect level. That is, for the negative direction variation of V, the change amount of I was smaller than that of the I-V characteristics without setting the defect level. D -V G This was confirmed. That is, for the negative direction variation of V, the change amount of I was smaller than that of the I-V characteristics without setting the defect level. G I D was found to be smaller. That is, it was found that the change amount of I was smaller than that of the I-V characteristics without setting the defect level for the negative direction variation of V. G This was confirmed. That is, for the negative direction variation of V, the change amount of I was smaller than that of the I-V characteristics without setting the defect level. I D -V G characteristics. D This was found.

[0437] Furthermore, when the temperature of the transistor was increased, the I-V characteristics at V = 1.2 V D = 1.2 V D -V​G Impact on characteristics Calculations were made regarding the impact. The temperatures of the transistors were set at 85°C, 125°C, and 192°C . As a result of the calculations, V G = -2V, and the off-current at a temperature of 85°C was 6.5×10 -2 0 A / μm, V G = -2V, and the off-current at a temperature of 125°C was 3.6×10 -1 8 A / μm, V G = -2V, and the off-current at a temperature of 192°C was 7.0×10 -1 6 A / μm.

[0438] Next, based on the off-currents at each temperature obtained from the above device calculations, calculations were performed on the temperature dependence of the potential fluctuation of the capacitive part connected to the transistor . The circuit configuration for which the calculations were made is shown in Fig. 37(A). One electrode of the drain of the transistor M20 and the capacitive element CD is connected . Also, the source of the transistor M20 is grounded to GND. Also, the other electrode of the capacitive element CD is grounded to GND. In this calculation, the capacitance of the capacitive element CD was set to 1 n F.

[0439] Also, the capacitive element CD is in a charged state, the transistor M20 is set to V G = -2 to be in the off state, and the potential of the drain of the transistor M20 and one electrode of the capacitive element CD was set with V

[0440] = 1.2V as the initial state. D The calculation results are shown in Fig. 37(B). As shown in Fig. 37(B), it was found that the higher the temperature, the greater the decrease in the potential V D over time.

Example

[0441] In this embodiment, it was noted that defects present in the crystal of the oxide semiconductor contribute to the leakage current, and the influence of the defects in CAAC-IGZO on the off-current was estimated by device calculation, including temperature dependence. Also, a simple holding circuit was constructed to verify by calculation how much influence this leakage current has on the holding characteristics of the circuit. Further, a TEG (Test Element Group) device for verifying the holding characteristics was fabricated, and the correspondence with the measured results was investigated. The model of the transistor used for evaluation had the configuration of the transistor 200 shown in FIG. 1, with the gate insulating film thickness of 6 nm in terms of EOT, a gate length of 60 nm, and a channel width of 60 nm. Also, for the setting of the defect level, based on the analysis results such as hard X-ray photoelectron spectroscopy (HX-PES), the level derived from oxygen deficiency located near the mid-gap of the energy gap of CAAC-IGZO was used. The distribution of the defect levels is shown in FIG. 38(A). E is the energy gap of the oxide semiconductor, which is 2.9 eV, N is the peak density of the defect levels, which is 1×10 / cm·eV, W is the standard deviation of the defect levels, which is set to 0.25 eV. E is the energy at the intermediate position of the defect levels, which is 1.4 eV and 1.5 eV. Also, the temperature was set to 27°C. The I-V characteristics at V = 1.2 V obtained from the device calculation results are shown in FIG. 38(A). As a result of this

[0442] g D 21 3 D D

[0443] D D G DThe off-current set to 1.4 eV is larger than the off-current set to E D = 1.5 eV was confirmed. That is, it was confirmed that the off-current increases when the energy at the intermediate position of the defect level approaches the lower end Ec of the conduction band. The off-current set to 1.4 eV is larger than the off-current set to E = 1.5 eV was confirmed. That is, it was confirmed that the off-current increases when the energy at the intermediate position of the defect level approaches the lower end Ec of the conduction band.

[0444] Next, E g , N D and W D were set to the same settings as above, and E D was fixed at 1.5 eV, and the temperatures were set to 27 °C, 85 °C, 125 °C, and 192 °C. The I-V characteristics at V = 1.2 V obtained from the device calculation are shown in Fig. 39(A). Also, a graph showing the relationship between the off-current at V D = 1.2 V and the reciprocal of the temperature is shown in Fig. 39(B). D -V G The I-V characteristics at V G = -2 V show that the gradient of I is gentler in the region where V is lower than the I-V characteristics without defect level setting. That is, the change amou...

Claims

[Claim 1] A first insulator; a first oxide on the first insulator; a second oxide on the first oxide; and a third oxide and a fourth oxide on the second oxide; a first conductor on the third oxide; and a second conductor on the fourth oxide; and a fifth oxide on the second oxide; and a second insulator on the fifth oxide; and a third conductor on the second insulator; and a third insulator on the first conductor and the second conductor; and a fourth insulator on the third insulator; the fifth oxide is in contact with a top surface of the second oxide, a first side surface of the first conductor, a first side surface of the second conductor, a first side surface of the third oxide, a first side surface of the fourth oxide, and a side surface of the third insulator, the fifth oxide is in contact with a side surface of an opening provided in the fourth insulator, the third conductor is provided to fill the opening, The second oxide has In, an element M (wherein M is Al, Ga, Y, or Sn), and Zn, The first oxide and the fifth oxide each have at least one of the constituent elements of the second oxide, The third oxide and the fourth oxide each have an element M, The third oxide and the fourth oxide have a region having a higher concentration of the element M than the second oxide.

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