Switching mode power converter with pulse skipping and method of controlling the same

Abstract

To provide a technique and a mechanism for switched mode power supplies to provide more efficient power conversion at light loads.SOLUTION: A control circuit is coupled to a power converter having an input voltage VIN and an output voltage VOUT. The control circuit includes a capacitor connected between a current source and ground. The current source is configured to charge the capacitor with a current αVIN or α(VIN-VOUT) when a pulse width modulation (PWM) signal of a PWM controller of the power converter is high, and to discharge the capacitor with a current α(-VOUT) or α(VIN-VOUT) when the PWM signal is low. α is a preconfigured constant. The control circuit is configured to trigger the PWM controller to skip a pulse when the voltage across the capacitor falls below a threshold before the end of a current switching cycle of the power converter.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001]

[0001] This disclosure generally relates to power supplies, and in certain embodiments, to techniques and mechanisms for a switching mode power converter having pulse skip and methods of controlling the same.

Background Art

[0002]

[0002] Switching mode power supplies, or switch mode power supplies, are widely used to provide a regulated output of power from an input power source, e.g., an input voltage. Regulation of the output power is typically provided by feeding back the output voltage of the switching mode power supply, based on which the input voltage is switched on and off by a controller, e.g., a pulse width modulation (PWM) controller. However, in a switching mode power supply, as the output load decreases, the ratio of the power consumed by the PWM controller to the total power consumption becomes significantly large, resulting in low efficiency when the output load is light. To provide more efficient power conversion at light loads, it is desirable to develop techniques and mechanisms for switching mode power supplies.

Summary of the Invention

Means for Solving the Problems

[0003]

[0003] Technical advantages are generally achieved by embodiments of this disclosure that describe a switching mode power converter having pulse skip and methods of controlling the same.

[0004]

[0004] According to one aspect of this disclosure, a circuit is provided that includes a control circuit coupled to a power converter having an input voltage V IN and an output voltage V OUT . The control circuit includes a current source and a capacitor connected between the current source and ground. The current source is α(V IN -V OUT when the pulse width modulation (PWM) signal of the PWM controller of the power converter is high.Charge the capacitor with a current equal to α(-V OUT ) and discharge the capacitor with a current equal to α(-V

[0005]

[0005] According to another aspect of the present disclosure, a method for controlling a pulse width modulation (PWM) controller of a power converter to skip one pulse (or multiple pulses) is provided. The method includes, in a switching cycle of the power converter, charging the capacitor with a current equal to α(V IN -V OUT ) when the PWM signal of the PWM controller is high, where α is a preconfigured constant and the power converter has an input voltage V IN and an output voltage V OUT ; discharging the capacitor with a current equal to α(-V OUT ) when the PWM signal of the PWM controller is low; and triggering the PWM controller to skip one pulse (or multiple pulses) when it is detected that the voltage across the capacitor has dropped below a skip threshold before the switching cycle ends.

[0006]

[0006] According to another aspect of the present disclosure, a power converter includes a power switch and an inductor connected between an input node and an output node. The input node has an input voltage V IN and the output node has an output voltage V OUTThere is provided an apparatus including a power converter, a pulse width modulation (PWM) controller coupled to the power converter and configured to control the power converter to operate in a PWM mode, and a control circuit coupled to the PWM controller. The control circuit includes a current source and a capacitor connected between the current source and ground. The current source charges the capacitor with a current equal to αV IN or α(V IN -V OUT ) when the PWM signal of the PWM controller is high, and discharges the capacitor with a current equal to α(-V OUT ) or α(V IN -V OUT ) when the PWM signal of the PWM controller is low, where α is a preconfigured constant. The control circuit is configured to trigger the PWM controller to skip turning on the power switch for one pulse (or multiple pulses) when the voltage at the common node of the current source and the capacitor drops below a skip threshold before the current switching cycle of the power converter ends.

[0007]

[0007] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

[0009]

[0016] Corresponding numbers and symbols in different figures generally refer to corresponding parts, unless otherwise indicated. The drawings are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale.

[0010]

[0017] The fabrication and use of embodiments of the present disclosure are discussed in detail below. However, it is understood that the concepts disclosed herein can be embodied in a variety of specific contexts, and the specific embodiments discussed herein are merely exemplary and do not serve to limit the scope of the claims. Further, it should be understood that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present disclosure as defined by the appended claims. Additionally, one or more features from one or more of the embodiments described below may be combined to create alternative embodiments not explicitly described, and features suitable for such combinations are understood to be within the scope of the present disclosure. Accordingly, the appended claims are intended to encompass any such modifications or embodiments.

[0011]

[0018] Embodiments of the present disclosure are described below using a buck converter as an example. However, embodiments of the present disclosure can be applied to various switching mode power supplies or converters having inductors or transformers.

[0012]

[0019] FIG. 1 is a schematic diagram of an exemplary conventional switching mode power supply 100. The switching mode power supply 100 includes a buck converter 110 and a general voltage mode pulse width modulation (PWM) controller 120.

[0013]

[0020] A buck converter is a type of switching mode power supply. As is known, a buck converter is a DC (direct current)-DC power converter that steps down the voltage from the input voltage provided at its input terminals to the output voltage provided at its output terminals. An adjustable buck converter uses feedback to adjust the output voltage. In this example, the buck converter operates in voltage mode control and the feedback is based on the output voltage.

[0014]

[0021] As shown, the buck converter 110 includes an input terminal (or node) 102 that receives an input power source, for example an input voltage V IN and an output terminal (node) 108 that outputs an output power, for example an output voltage V OUT to supply power to a load 112. The input terminal 102 is connected to a power switch S Main 104. An inductor 106 having an inductance L is connected between the power switch 104 and the output terminal 108. A capacitor 110 having a capacitance C is connected between the output terminal 108 and ground. The load 112 is connected in parallel with the capacitor 110. A diode 114 is connected between the common node 116 of the inductor 106 and the power switch 104 and ground.

[0015]

[0022] The voltage-mode PWM controller 120 is configured to receive the feedback of the output voltage of the buck converter 110 and control the power switch 104 to be switched on and off based on the feedback. The flow of the input power to the output of the buck converter 110 can be controlled by periodically turning the power switch 104 on and off. To provide the feedback, the output voltage V at the output terminal 108 OUT is divided by a resistor divider including resistors R1 and R2 connected in series between the output terminal 108 and the ground. The common node 118 of the resistors R1 and R2 is connected to the first input terminal of the operational amplifier 124 and the compensation network. The second input terminal of the operational amplifier 124 is connected to the reference voltage (V REF ) 126. The compensation network is formed by the resistor R3 and the capacitors C1 and C2. R3 and C2 are connected in series between the node 118 and the node 128. C1 is connected in parallel with the series-connected R3 and C2. The node 128 is connected to the output terminal 129 of the operational amplifier 124. The output signal of the compensation network and the output signal of the operational amplifier 124 are mixed as a voltage signal V COMP 130 (also referred to as the control force signal) at the node 129 and then supplied to the first input terminal of the comparator 132. The second input terminal of the comparator 132 is connected to the sawtooth generator 134, and the sawtooth generator generates a sawtooth signal / wave based on the clock signal 136. The output terminal of the comparator 132 is connected to the driver 138, and the driver generates a drive signal for turning the power switch 104 on or off based on the output signal D of the comparator 132 ON . The output signal D of the comparator 132 ON can be referred to as a PWM signal and controls the on and off of the power switch 104.

[0016]

[0023] During operation, the power switch 104 is repeatedly switched on and off in a switching cycle having an on-time and an off-time controlled by the voltage-mode PWM controller 120. In PWM, the switching cycles have the same period, and the on-time can be different in different switching cycles. By these switching operations, the input power is adjusted and supplied to the load. The combination of the inductor 106 and the capacitor 110 forms an LC filter that serves to smooth any ripple generated by the switching operation. The on-time (duty cycle) of the power switch 104 is based on the error between the reference voltage V REF 126 and the output voltage feedback from the buck converter 110 so that the output voltage of the buck converter 110 remains within the desired range. The operation of the buck converter 110 is well known in the art and will not be described in more detail herein.

[0017]

[0024] In the switching-mode power supply 100, since the voltage-mode PWM controller 120 continues to generate a drive signal for switching the power switch 104 on and off based on the feedback output voltage of the buck converter 110, as the output load decreases, the ratio of the power consumed by the PWM controller 120 to the total power consumption of the switching-mode power supply 100 can increase significantly. This leads to the result that the efficiency of the switching-mode power supply 100 is low when operating with a light output load.

[0018]

[0025] To reduce the power consumption when the load is light, existing methods can control the switching-mode power supply 100 to operate in pulse-skipping mode. Specifically, a threshold voltage / signal V SKIP is configured and compared with a control force signal V COMP to determine whether to enter the pulse-skipping mode. As shown in FIG. 1, the voltage-mode PWM controller 120 has its first input terminal connected to the threshold voltage V SKIP and its second input terminal connected to the control force signal V COMPIt may further include a comparator 140 connected to. The output of the comparator 140 is connected to a skip circuit / module 142, and the skip circuit / module 142 generates an output signal at the output terminal of the skip circuit / module 142 based on the output signal of the comparator 140. The output terminal of the skip circuit / module 142 is connected to a driver 138. The driver 138 is configured to determine whether to skip a (switching) pulse based on the output signal from the skip circuit 142. The driver 138 may output a drive signal to turn off the power switch 104.

[0019]

[0026] As the output load, for example, load 112 gradually decreases, the buck converter 110 transitions from continuous conduction mode (CCM) to discontinuous conduction mode (DCM). As is known, in CCM, current continuously flows through the inductor 106 throughout the switching cycle, while in DCM, the inductor current becomes zero for part of the switching cycle. When the buck converter 110 operates in DCM, the control force signal V COMP decreases as the load decreases. When the control force signal V COMP falls below the threshold voltage V SKIP , the driver 138 may skip one or more switching pulses to reduce the power consumption of the voltage mode PWM controller 120 until V COMP exceeds V SKIP . As an example, when V COMP falls below V SKIP , the output of the comparator 140 goes high, causing the skip module 142 to generate a skip signal indicating that the pulse is to be skipped. Based on the skip signal, the driver 138 then generates a drive signal to turn off the power switch 104 and may skip turning on the power switch 104 for one pulse (or multiple pulses). When V COMP exceeds V SKIPWhen it exceeds, the output of the comparator 140 goes low, and based on this, the skip module 142 is not triggered or can generate a no-skip signal (e.g., low). In this case, the driver 138 operates based on the output signal D ON There are various ways to implement a pulse skip circuit as set in FIG. 1, which is readily apparent to those skilled in the art.

[0020]

[0027] Generally, to avoid affecting normal operation in CCM, the threshold voltage V SKIP is usually set to a very low level, so the pulse skip mode occurs only with an extremely light output load. Therefore, existing methods enable pulse skipping only for a very limited load range.

[0021]

[0028] Embodiments of the present disclosure generally provide mechanisms and apparatuses that trigger pulse skipping in discontinuous conduction mode (DCM) and enable a PWM controller to skip one pulse (or multiple pulses) over a wider range of output loads. Specifically, embodiments of the present disclosure provide a mechanism for DCM detection and pulse skipping that does not require current sensing. Embodiments of the present disclosure eliminate the need to compare the output voltage feedback with the threshold voltage V SKIP to determine whether to skip switching pulses as used by existing technologies, and greatly relax the load size limitations required by the comparison.

[0022]

[0029] In some embodiments, whether to skip switching pulses in DCM can be determined by monitoring the inductor current I SIM with the analog signal V L . Specifically, an analog inductor current signal V L proportional to the inductor current I SIM can be established according to the magnetization / demagnetization voltage across both ends of the inductor. The PWM controller samples V SIMis the inductor current I L configured to skip one pulse (or multiple pulses) when it decreases to 0 in conjunction with this, which means the buck converter operates in DCM.

[0023]

[0030] FIG. 2 is a schematic diagram of an exemplary switching mode power supply 200 according to an embodiment of the present disclosure. The switching mode power supply 200 includes a buck converter 210 and a general voltage mode pulse width modulation (PWM) controller 220.

[0024]

[0031] The buck converter 210 is similar to the buck converter 110 of FIG. 1. As shown, the buck converter 210 includes an input terminal (or node) 202 that receives an input power source, for example, an input voltage V IN and an output terminal (or node) 208 that outputs output power, for example, an output voltage V OUT to supply power to the load 212. The input terminal 202 is connected to a main switch (or power switch) S Main 204. An inductor 206 having an inductance L is connected between the main switch 204 and the output terminal 208. A capacitor 210 having a capacitance C is connected between the output terminal 208 and ground. The load 212 is connected in parallel with the capacitor 210. A diode 214 is connected between a common node 216 of the inductor 206 and the main switch 204 and ground.

[0025]

[0032] The main switch 204 can be any controllable switch such as a metal oxide semiconductor field effect transistor (MOSFET) device, an insulated gate bipolar transistor (IGBT) device, an integrated gate commutated thyristor (IGCT) device, a gate turn-off thyristor (GTO) device, a silicon controlled rectifier (SCR) device, a junction gate field effect transistor (JFET) device, a MOS controlled thyristor (MCT) device, a gallium nitride (GaN)-based power device, a silicon carbide (SiC)-based power device, etc.

[0026]

[0033] The voltage mode PWM controller 220 is configured to control the buck converter 210 to operate in the PWM mode. The voltage mode PWM controller 220 may be configured to control the main switch 204 to be switched on and off based on the feedback voltage from the buck converter 210 and skip pulses. To provide feedback, the output voltage V at the output terminal 208 OUT is divided by a resistor divider including resistors R1 and R2 connected in series between the output terminal 208 and ground. Note that the resistor divider illustrated in FIG. 2 is merely used as an example. Those skilled in the art will recognize many variations, alternatives, and embodiments that can be used for the same purpose of the resistor divider in the example of FIG. 2. The common node 218 of the resistors R1 and R2 is connected to the first input terminal (negative terminal) of the operational amplifier 224 and the compensation network. The second input terminal (positive terminal) of the operational amplifier 224 is connected to the reference voltage (V REF ) 226. The compensation network is formed by a resistor R3 and capacitors C1 and C2. R3 and C2 are connected in series between the node 218 and the node 228. C1 is connected in parallel with the series-connected R3 and C2. The node 228 is connected to the respective terminals of C1 and R3. The node 228 is connected to the output terminal 229 of the operational amplifier 224. The output signal of the compensation network and the output signal of the operational amplifier 224 are mixed as a voltage signal V COMP 230 (also referred to as a control force signal) and supplied to the first input terminal (positive) of the comparator 232. The second input terminal (negative) of the comparator 232 is connected to a sawtooth generator 234, and the sawtooth generator generates a sawtooth voltage signal V SAW based on the clock signal from the clock generator 236, and the voltage signal V SAWis supplied to the second input terminal of the comparator 232. The clock signal functions as the switching frequency clock signal of the switching mode power supply 200. The output terminal of the comparator 232 is connected to the driver 238, and the driver generates a drive signal for turning on or off the main switch 204 based on the output signal D ON of the comparator 232. The output signal D ON of the comparator 232 may be referred to as a PWM signal, and the PWM signal controls the buck converter to operate in the PWM mode. In one example, the switching frequency may be 425 KHz or less, for example 400 KHz. The terms "output signal D ON " and "PWM signal D ON " are used interchangeably in the present disclosure.

[0027]

[0034] The voltage mode PWM controller 220 may further include a skip control circuit 250 including a voltage controlled current source 240, a capacitor C SIM 242, a buffer 246, and a skip circuit / module 248. In order to simulate the inductor current I L flowing through the inductor 206, in some embodiments, the voltage controlled current source 240 may be configured as I SIM =αV SIM to charge the capacitor C L , where V L is the voltage across the inductor 206 and α is a preconfigured constant. α may be configured to control the current amplitude of the voltage controlled current source 240 and is used therefor.

[0028]

[0035] As shown, the voltage controlled current source 240 and the capacitor C SIM 242 are connected in series, and the common node 244 of the voltage controlled current source 240 and the capacitor C SIM 242 is connected to the input terminal of the buffer 246. The capacitor C SIM242 is connected between node 244 and ground. The output terminal of buffer 246 is connected to the input terminal of skip circuit / module 248. The output node of skip circuit / module 248 is connected to driver 238. The skip signal can be generated / output at the output node of skip circuit / module 248 based on the output signal of buffer 246, i.e., the voltage V across capacitor C SIM across both ends of 242 SIM .

[0029]

[0036] Driver 238 is configured to determine whether to skip a pulse based on the skip signal from skip circuit 248. When the skip signal is high, driver 238 can output a drive signal to switch off power switch 204 for one or more pulses, i.e., driver 238 can skip switching on power switch 204 for one or more pulses. When the skip signal is low, driver 238 operates according to the output signal D ON from comparator 232. In some embodiments, driver 238 may include a general-purpose driver for driving power switch 204 on and off and a circuit for determining whether to skip a pulse. As an example, the circuit may include a logic circuit for detecting the skip signal and triggering the general-purpose driver to drive power switch 204 based on the detected skip signal. Those skilled in the art will recognize various ways to implement driver 238 having the functions as described in the embodiments of the present disclosure.

[0030]

[0037] The operation of switching mode power supply 200 will be described below with reference to FIGS. 2 and 3 using an exemplary scenario where the load is gradually decreasing. FIG. 3 is an exemplary waveform diagram 300 showing the operation of switching mode power supply 200 according to an embodiment of the present disclosure. FIG. 3 shows the clock signal output by clock generator 236, the voltage signal V at the first input terminal of comparator 232 reflecting the feedback of the output voltage of buck converter 210 COMP230, the sawtooth voltage signal V at the second input terminal of the comparator 232 SAW , the output signal D of the comparator 232 ON , the current I flowing through the inductor 206 L , the I of the voltage-controlled current source 240 SIM , the capacitor C SIM V across both ends of 242 SIM , shows the waveforms of the skip signal output by the skip module 248 and the drive signal output by the driver 238 for controlling the main switch 204.

[0031]

[0038] During the time interval t0 to t2 (for example, the first switching cycle), the buck converter 210 operates in CCM. The operation of the buck converter 210 in this switching cycle is well known and will not be described here.

[0032]

[0039] At t2, the next switching cycle (t2 to t5) starts. During the time interval t2 to t3, the control force signal V COMP 230 is greater than V SAW , the PWM signal D of the comparator 232 ON goes high, and based on this, the driver 238 drives the main switch S Main 204 to turn on. In this case, the diode 214 is reverse-biased, and the voltage V L across both ends of the inductor 206 is V L = (V IN - V OUT ), which magnetizes the inductor 206 and increases the current I L flowing through the inductor 206. On the other hand, the voltage-controlled current source 240 has I SIM = αV L = α(V IN - V OUT ) and charges the capacitor C SIM 242. Therefore, when the PWM signal D ON goes high, the voltage-controlled current source 240 charges the capacitor C SIM 242 with the current α(V IN - V OUT) is charged. As a result, the voltage V across the capacitor C SIM 242 rises in conjunction with the current I SIM through the inductor 206. L

[0033]

[0040] During the time interval t3 to t4, V COMP 230 is smaller than V SAW , and the PWM signal D ON of the comparator 232 goes low. Based on this, the driver 238 turns off the main switch S Main 204. In this case, the voltage V across the inductor L is V L = -V OUT , which demagnetizes the inductor 206, and thus the current I L decreases. On the other hand, the voltage-controlled current source 240 has I SIM = αV L = α(-V OUT ), which discharges the capacitor C SIM 242, and thus the voltage V SIM across the capacitor C SIM drops in conjunction with I L . Therefore, when the PWM signal D ON goes low, the voltage-controlled current source 240 discharges the capacitor C SIM 242 with the current α(-V OUT ).

[0034]

[0041] At time t4, before the switching frequency clock signal knocks in, i.e., before the next switching cycle starts or before the current switching cycle ends, V SIM is related to the current I LIt drops to zero in conjunction with the decrease. Next, the buck converter 210 enters DCM, and the skip signal output by the skip 248 transitions high, thereby stopping the switching in the driver 238. The skip signal can initially be set low. The switching mode power supply 200 enters the pulse skip mode. The skip signal remains high until t5 when the switching frequency clock signal knocks in, thereby resetting the skip signal low. A new switching cycle starts from t5. During the width of the skip signal pulse, V SIM and I SIM remain zero and are reset by the clock signal when a new switching cycle starts at t5. I SIM is V IN and V OUT has a value based on, and the capacitor C SIM continues to be charged and discharged by I SIM . When entering the pulse skip mode, the drive signal remains low (the main switch 204 remains off), and I L remains zero (0) even after a new switching cycle starts. The driver 238 can skip switching on the main switch 204 for one or more pulses. In this example, since the load continues to decrease in the new switching cycle starting at t5, the skip module 248 continues to generate a high skip signal triggered by V SIM dropping to zero as shown in FIG. 3. The switching mode power supply 200 can return from the pulse skip mode when the buck converter enters CCM.

[0035]

[0042] Based on the volt-second balance theory, the inductor current I L only drops to 0 before the end of the switching period in DCM. This means that only the alternating current (AC) ripple of the inductor current I L needs to be simulated without a DC offset.

[0036]

[0043] Furthermore, the magnetization and demagnetization voltages V at both ends of the inductor 206 L are always related to the input voltage V IN and the output voltage V OUT , that is, V L = (V IN - V OUT ) or V L = -V OUT . Therefore, in some embodiments, the voltage-controlled current source 240 having I SIM can be implemented by using two constant current sources having currents αV IN and αV OUT , respectively. FIG. 4 illustrates an example of such an implementation according to an embodiment of the present disclosure.

[0037]

[0044] FIG. 4 is a schematic diagram of an exemplary switching mode power supply 400 according to an embodiment of the present disclosure. The switching mode power supply 400 includes a buck converter 210 and a general voltage mode PWM controller 220 as described with respect to FIG. 2, but the skip control circuit 250 is implemented differently. The description of the buck converter 210 and the general voltage mode PWM controller 220 other than the skip control circuit 250 has been described above with reference to FIGS. 2 and 3 and will not be repeated here.

[0038]

[0045] In this example of FIG. 4, the skip control circuit 250 includes a first constant current source 252 having a current I C = αV IN and a second constant current source 254 having a current I D = αV OUT . The first constant current source 252 is connected in series with the first switch S1 between the ground and the node 256. The second constant current source 254, the capacitor 242, and the second switch S2 are connected in parallel with each other between the node 256 and the ground. The first switch S1 is the output signal D of the comparator 232 ONThe second switch S2 is turned on and off under the control of a clock signal from the clock generator 236. The node 256 is connected to a skip circuit / module 248. The skip circuit / module 248 is configured to generate / output a skip signal based on the signal at the node 256 and is reset based on the clock signal.

[0039]

[0046] The operation of the switched-mode power supply 400 will now be described with reference to Figures 4 and 5 using an example scenario in which the load is gradually decreasing. Figure 5 is an example waveform diagram 500 illustrating the operation of the switched-mode power supply 400, in accordance with an embodiment of the present disclosure. Figure 5 illustrates the clock signal output by the clock generator 236, the output voltage V of the buck converter 210, OUT A voltage signal V at a first input terminal of the comparator 232 reflecting the feedback of COMP 230, a sawtooth voltage signal V at a second input terminal of the comparator 232 SAW , the output signal D of the comparator 232 ON , the current I flowing through the inductor 206 L , capacitor C SIM Current I flowing through 242 SIM , capacitor C SIM Voltage across 242 V SIM 2 shows waveforms of the skip signal output by the skip module 248 and the drive signal output by the driver 238 for controlling the main switch 204.

[0040]

[0047] During the time interval t0 to t2 (e.g., the first switching cycle), the buck converter 210 operates in CCM. At t2, the next switching cycle (t2 to t5) starts. During the time interval t2 to t3, the control input signal V COMP 230 is V SAW Therefore, the PWM signal D of the comparator 232 is ON goes high, and based on that, the driver 238 turns on the main switch S Main204 is driven to turn on. In this case, the voltage across the inductor is V L =(V IN -V OUT ), which magnetizes the inductor 206 and causes a current I L On the other hand, the high PWM signal D ON turns on the first switch S1, and the capacitor C SIM The current flowing through 242 is I SIM = αV L =α(V IN -V OUT )=I C -I D PWM signal D ON During the high period, the current I SIM is the capacitor C SIM 242, thus charging the inductor 206 current I L In conjunction with the capacitor C SIM Voltage across 242 V SIM increases.

[0041]

[0048] During the time interval t3 to t4, V COMP 230 is V SAW Therefore, the PWM signal D of the comparator 232 ON goes low, and based on that, the driver 238 turns on the main switch S Main 204 is turned off. In this case, the voltage across the inductor is V L =-V OUT which demagnetizes the inductor 206 and thus the current I L On the other hand, the low PWM signal D ON turns off the first switch S1 and the capacitor C SIM The current passing through 242 is I SIM = αV L =α(-V OUT )=(-I D ), which results in a capacitor C SIM Discharge 242 and capacitor C SIM Voltage across 242 V SIM I L Therefore, the PWM signal DON When it goes low, current source I D 254 discharges capacitor C SIM 242.

[0042]

[0049] At time t4, before the switching frequency clock signal knocks in (i.e., before the current switching cycle ends), V SIM drops to zero. The buck converter 210 enters DCM, the skip signal output by skip 248 transitions high, and the driver 238 stops switching. The drive signal output by the driver 238 goes low, turning off the main switch 204. The switching mode power supply 400 enters the pulse skip mode. During the time interval t4 - t5, V SIM can be zero. In some cases, V SIM can go below zero during the time interval t4 - t5, as shown by the dashed line in FIG. 5. At t5, the switching frequency clock signal knocks in, thereby resetting V SIM (e.g., to zero), and resetting the skip signal (e.g., to low or zero), starting a new switching cycle. When the switching frequency clock signal knocks in, the second switch S2 is switched on to set the voltage V SIM to zero. This ensures that V SIM starts from zero when a new switching cycle starts. Then, the second switch S2 is switched off after a new switching cycle starts. That is, the second switch S2 is triggered by the clock signal at the start of each switching cycle, turned on, and then turned off.

[0043]

[0050] Generally, the first switch S1 and the second switch S2 are not turned on simultaneously at the start of a new switching cycle. The time that the second switch S2 is on is such that the voltage V SIM is reset to zero and the charging of capacitor C SIM at the start of the next switching cycle with VSIM It can be configured to start at =0. Ideally, the first switch S1 is turned on when the second switch is turned off by a clock signal. In practice, the second switch S2 can be configured to be turned on and off at least before the first switch S1 is turned on. In the examples of FIGS. 4 and 5, the second switch S2 is directly triggered by the next clock signal, and the first switch S1 is triggered by the next clock signal V COMP and V SAW is the result of comparing with, the PWM signal D ON is turned on when it goes high. Thus, in this example, when the next clock signal knocks in, the second switch S2 is turned on before the first switch S1 is turned on by the PWM signal D ON .

[0044]

[0051] Considering the imperfections of the actual circuit, in some embodiments, a mechanism for turning the second switch S2 on and off before the first switch S1 is turned on for the next switching cycle can be provided. As an example, the second switch S2 can be turned on and off within the current switching cycle when V SAW increases above a sawtooth voltage threshold, and the sawtooth voltage threshold is less than the peak value of V SAW . That is, the second switch S2 is turned on and off before the current switching cycle ends. The sawtooth voltage threshold can be configured such that the second switch S2 is turned on and off, for example, between t4 and t5 when the current switching cycle is approaching its end. As an example, the sawtooth voltage threshold can be set to 95% of the peak value of V SAW . As another example, a second clock signal having the same period as the clock signal of the clock generator 236 (referred to as the first clock signal) but starting earlier than the first clock signal in each cycle can be introduced. The second clock signal can be used to specifically trigger the on and off of the second switch S2. Those skilled in the art will recognize various embodiments for the same purpose as described herein.

[0045]

[0052] The skip circuit / module 248 is configured to generate / output a skip signal based on V SIM . In some embodiments, the skip signal can be initialized to low or zero. The skip signal is such that, as shown in the examples of FIGS. 2-5, when the skip circuit / module 248 detects that V SIM has dropped to zero (0) before the end of the current switching cycle, i.e., before the next switching cycle starts, it can be set high to indicate skipping one pulse (or multiple pulses). In some embodiments, the skip circuit / module 248 can compare V SIM with a threshold voltage V THR (e.g., with a comparator), and V THR is set to 0 (zero). When V SIM has decreased until it reaches V THR , the skip circuit / module 248 is triggered to output a high skip signal indicating pulse skipping. It will be apparent to those skilled in the art that the skip circuit / module 248 can be implemented in various ways for the same purposes as described in the embodiments of the present disclosure.

[0046]

[0053] In practice, the circuit may not operate ideally. For example, V SIM may not be able to drop to zero. In some embodiments, the threshold voltage V THR can be set to have a value higher than 0 or lower than 0, e.g., V THR = 50 mv. The skip module 248 can be configured to output a skip signal when it detects that V SIM ≤ V THR . The value of the threshold voltage V THR can be configurable according to the application of the switching mode power supply 200 or 400. It can be 0, a positive number, or a negative number. In this non-ideal scenario, the use of the second switch S2 allows V SIM to start from zero in each switching cycle.

[0047]

[0054] In some embodiments, in order to consider non-ideal scenarios and avoid the pulse skip mode being activated when the switching mode power supply operates in CCM, as shown in FIG. 6, a delay circuit 260 can be connected between the skip module 248 and the driver 238 to delay skipping the switching. FIG. 6 is a schematic diagram of an exemplary switching mode power supply 600 according to an embodiment of the present disclosure. The switching mode power supply 600 includes a buck converter 210 and a general voltage mode PWM controller 220 as described with respect to FIG. 4, but a delay circuit 260 is added. The delay circuit 260 includes a one-shot timer 262 and an AND logic gate 264. The one-shot timer 262 is connected between the first input terminal of the AND logic gate 264 and the skip module 248. The output signal of the one-shot timer 262 is supplied to the first input terminal of the AND logic gate 264, and its output signal is then inverted and supplied to the AND logic gate 264. The second input terminal of the AND logic gate 264 is connected to the skip module 248. The output terminal of the AND logic gate 264 is connected to the driver 238.

[0048]

[0055] In some embodiments, when the skip signal transitions high, the one-shot timer 262 can be triggered to go high and start counting based on a preset time T. The preset time T can be determined based on the switching frequency of the switching mode power supply 600. As an example, the switching frequency is f = 400 KHz, and the preset time T can be set to 100 nanoseconds (i.e., T = 1 / f × 4%). When the one-shot timer 262 finishes counting, its output can go low, and then it is inverted at the first input terminal of the AND gate 264 and supplied to the AND gate 264. Thus, the input at the first input terminal of the AND gate 264 becomes high. The high skip signal is also supplied to the second input terminal of the AND gate 264, and thus the input at the second input terminal of the AND gate 264 is high. As a result, the output of the AND logic gate 264 is high. At this time, if the clock has not knocked in, i.e., if the current switching cycle has not ended, the driver 238 controls the main switch 204 to skip the pulse based on the high output of the AND logic gate 264. When the one-shot timer 262 finishes counting and the current switching cycle has ended or is ending (the next switching cycle has started), the driver 238 can be configured not to skip the pulse. As an example, when the driver 238 receives the high output signal from the AND gate 264, the driver 238 can detect whether the next clock signal has started or whether the current switching cycle has ended, and based on that, determine whether to skip the pulse. The driver 238 can include circuitry for implementing these functions, which will be readily apparent to those skilled in the art.

[0049]

[0056] In one example, when the skip signal goes high, the one-shot timer 262 can be triggered to generate a pulse having a width of T. The one-shot timer 262 starts timing at the rising edge of the pulse, and the timing continues for the width of the pulse. The output of the one-shot timer 262 is high before the one-shot timer 262 expires, and its value is inverted and supplied to the AND logic gate 264. Thus, the input at the first input terminal of the AND logic gate 264 is low, the input (skip signal) at the second input terminal of the AND logic gate 264 is high, and thus, the output of the AND logic gate 264 is low, which does not trigger a pulse skip. At the falling edge of the pulse, the one-shot timer 262 stops timing. The output of the one-shot timer 262 goes low, and thus, the input at the first input terminal of the AND logic gate 264 goes high (the output of the one-shot timer 262, which is high, is inverted), the input (skip signal) at the second input terminal of the AND logic gate 264 is high, and thus, the output of the AND logic gate 264 goes high. Based on this, in combination with the clock signal, the driver 238 determines whether to skip the pulse. Thus, when V SIM decreases and reaches V THR , the delay provided by the delay circuit 260 gives the voltage-mode PWM controller 220 time to avoid skip pulses when operating in CCM.

[0050]

[0057] The skip control circuit 250 and the delay circuit 260 are shown as part of a general voltage-mode PWM controller 220, but may be separate circuits from the voltage-mode PWM controller 220. One or more of the above-described circuits and / or components may be implemented as an integrated circuit. One or more features of the above embodiments may be combined, changed, or modified to generate other embodiments, which fall within the scope of this disclosure. For example, the delay circuit may be added to the switching mode power supply 200 of FIG. 2 as described with respect to FIG. 6. Those skilled in the art will also recognize that there are various ways to implement the voltage-mode PWM controller 220 to control the buck converter 210 to operate in the PWM mode.

[0051]

[0058] FIG. 7 is a flowchart of an exemplary method 700 for controlling a PWM controller of a power converter to skip pulses, according to an embodiment of the present disclosure. The method may represent operations performed in a switching mode power supply during a switching cycle. The switching mode power supply may include a power converter having an input voltage V IN and an output voltage V OUT and a PWM controller. As shown, method 700 may include charging a capacitor with a current equal to α(V IN -V OUT ) when the PWM signal of the PWM controller is high, where α is a preconfigured constant (step 702). Method 700 may further include discharging the capacitor with a current equal to α(-V OUT ) when the PWM signal of the PWM controller is low (step 704). Method 700 may also include triggering the PWM controller to skip one pulse (or multiple pulses) when it is detected that the voltage across the capacitor has dropped below a skip threshold before the switching cycle ends (step 706). Method 700 may be implemented by the above-described embodiments.

[0052]

[0059] FIG. 8 is a block diagram of an apparatus 800 according to an embodiment of the present disclosure. The apparatus 800 includes a power converter 802, a PWM controller 804 connected to the power converter 802, and a pulse skip control circuit 806 connected to the PWM controller 804. The power converter 802 includes an input node having an input voltage V IN and an output node that may provide an output voltage V OUT capable of supplying power to a load. The power converter 802 may be a switching mode power converter including a power switch and an inductor or transformer connected in series between the input node and the output node. For example, the power converter 802 is a buck converter. The PWM controller 804 may be configured to control the power converter 802 to operate in a PWM mode based on feedback of the output voltage from the power converter 802. The PWM controller 804 may have a structure known in the art or developed in the future that performs a similar function.

[0053]

[0060] The pulse skip control circuit 806 is configured to trigger the PWM controller 804 to skip turning on the power converter 802 for one or more pulses. As an example, the pulse skip control circuit 806 may include a current source and a capacitor connected between the current source and ground. The current source charges the capacitor with a current equal to α(V IN -V OUT ) when the PWM signal of the PWM controller 804 is high, and charges the capacitor with a current equal to α(-V OUT) configured to discharge the capacitor with a current equal to α, where α is a preconfigured constant. The PWM signal of the PWM controller is generated by a PWM controller 804 used to drive the power converter 802. The pulse skip control circuit 806 is configured to trigger the PWM controller 804 to skip one pulse (or multiple pulses) when the voltage at the common node of the current source and the capacitor drops below the skip threshold before the current switching cycle ends. The pulse skip control circuit 806 can be similar to the skip control circuit 250 in FIG. 2 or FIG. 4.

[0054]

[0061] The circuit and method of the above embodiment are described by using a buck converter as an example, but other power converters are also applicable. For example, the embodiment may be applied to a buck-boost converter or a boost converter. In a buck-boost converter as an example, the inductor is magnetized at voltage V L =V IN and demagnetized at voltage V L =(-V OUT ). Therefore, the voltage-controlled current source 240 is configured with current I SIM 242 to charge the capacitor C SIM =αV L =αV IN and may be configured with current I SIM 242 to discharge the capacitor C SIM =αV L =α(-V OUT ). In a boost converter as an example, the inductor is magnetized at voltage V L =V IN and demagnetized at voltage V L =(V IN -V OUT ). Therefore, in this case, the voltage-controlled current source 240 is configured with current I SIM 242 to charge the capacitor C SIM =αV L =αV IN and configured with current I SIM 242 to discharge the capacitor C SIM =αV L =α(VIN -V OUT It may be composed of). The voltage-controlled current source 240 may be similarly configured for other power converters.

[0055]

[0062] Although the description has been detailed, it should be understood that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present disclosure as defined by the appended claims. Further, as one of ordinary skill in the art will readily understand from the present disclosure, processes, machines, manufactures, compositions of matter, means, methods, or steps that exist currently or are later developed may perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein. Accordingly, the scope of the present disclosure is not intended to be limited to the specific embodiments described herein. Correspondingly, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope.

Description of Reference Numerals

[0056] 100 Switching mode power supply 102 Input terminal (or node) 104 Power switch S Main 106 Inductor 108 Output terminal (node) 110 Buck converter, capacitor 112 Load 114 Diode 116 Common node of inductor 106 and power switch 104 118 Common node of resistors R1, R2 120 Voltage-mode pulse width modulation (PWM) controller 124 Operational amplifier 126 Reference voltage (V REF ) 128 Node 129 Output terminal of operational amplifier 124, node 130 Voltage signal V COMP 132 Comparator 134 Sawtooth Generator 136 Clock Signal 138 Driver 140 Comparator 142 Skip Circuit / Module 200 Switching Mode Power Supply 202 Input Terminal (or Node) 204 Main Switch (or Power Switch) S Main 206 Inductor 208 Output Terminal (or Node) 210 Buck Converter, Capacitor 212 Load 214 Diode 216 Common Node of Inductor 206 and Main Switch 204 218 Common Node of Resistors R1, R2 220 Voltage Mode Pulse Width Modulation (PWM) Controller 224 Operational Amplifier 226 Reference Voltage (V REF ) 228 Node 229 Output Terminal of Operational Amplifier 224 230 Voltage Signal V COMP 232 Comparator 234 Sawtooth Generator 236 Clock Generator 238 Driver 240 Voltage Controlled Current Source 242 Capacitor C SIM 244 Common Node of Voltage Controlled Current Source 240 and Capacitor C SIM 242 246 Buffer 248 Skip Circuit / Module 250 Skip Control Circuit 252 First Constant Current Source 254 Second Constant Current Source, Current Source I D 256 Node 260 Delay circuit 262 One-shot timer 264 AND logic gate, AND gate 300 Exemplary waveform diagram showing the operation of the switching mode power supply 200 400 Switching mode power supply 500 Exemplary waveform diagram showing the operation of the switching mode power supply 400 600 Switching mode power supply 700 Method 800 Apparatus 802 Power converter 804 PWM controller 806 Pulse skip control circuit

Claims

1. Input voltage V ＩＮ and the output voltage V ＯＵＴ a control circuit coupled to a power converter having: A current source; A capacitor connected between the current source and ground, the current source being α(V ＩＮ -V ＯＵＴ ) when the PWM signal of the PWM controller is low. ＯＵＴ ), where α is a preconfigured constant; and Including, the control circuitry is configured to trigger the PWM controller to skip a pulse (or pulses) when the voltage across the capacitor falls below a skip threshold before the end of a current switching cycle of the power converter. A control circuit, The circuit includes:

2. The current source is Current αV ＩＮ a first current source having a first terminal connected to a first terminal of the capacitor such that a direction of current flow of the first current source is from the first current source to the capacitor; Current αV ＯＵＴ a second current source having a first terminal and a second terminal connected in parallel with the capacitor, the ... The circuit of claim 1 , comprising:

3. 3. The circuit of claim 2, wherein the control circuit further comprises: a first switch connected between the first current source and the first terminal of the capacitor, the first switch configured to switch on when the PWM signal is high.

4. 3. The circuit of claim 2, wherein the control circuit further comprises: a second switch connected in parallel with the capacitor between the first terminal of the capacitor and the ground, the second switch configured to set the voltage across the capacitor to zero.

5. The control circuit includes: a skip circuit having an input terminal connected to the first terminal of the capacitor, the skip circuit configured to output a skip signal indicating to skip a switching pulse (or multiple switching pulses) when the voltage across the capacitor falls below the skip threshold before the current switching cycle ends; The circuit of claim 1 further comprising:

6. a driver connected between the power converter and the skip circuit, the driver configured to control a power switch of the power converter to skip switching on for one pulse (or multiple pulses) based on the skip signal; The circuit of claim 5 further comprising:

7. The delay circuit further includes a delay circuit connected between the skip circuit and the driver, the delay circuit comprising: an AND gate having a first input terminal connected to the output terminal of the skip circuit and an output terminal connected to the driver; a one-shot timer having an input terminal connected to the output terminal of the skip circuit and an output terminal connected to a second input terminal of the AND gate, the input at the second input terminal of the AND gate being inverted; Including, the one-shot timer is triggered by the skip signal to start timing according to a preset time, and the driver is configured to skip switching on the power switch for one pulse (or multiple pulses) when the one-shot timer expires before the current switching cycle ends.

7. The circuit of claim 6.

8. The circuit of claim 1 , wherein the skip threshold is zero or greater than zero.

9. 1. A method for controlling a pulse width modulation (PWM) controller of a power converter to skip a pulse (or multiple pulses) during a switching cycle of the power converter, the method comprising: When the PWM signal of the PWM controller is high, α(V ＩＮ -V ＯＵＴ ), where α is a preconfigured constant, and the power converter charges a capacitor with a current equal to an input voltage V ＩＮ and the output voltage V ＯＵＴ and charging the battery. When the PWM signal of the PWM controller is low, α(-V ＯＵＴ discharging said capacitor with a current equal to triggering the PWM controller to skip a pulse (or pulses) when it detects that the voltage across the capacitor drops below a skip threshold before the end of the switching cycle; The method includes:

10. generating a skip signal indicating to skip a pulse upon detecting that the voltage across the capacitor falls below the skip threshold before the end of the switching cycle; The method of claim 9 further comprising:

11. triggering the PWM controller to skip switching on a power switch of the power converter for one pulse (or multiple pulses) based on the skip signal; The method of claim 10 further comprising:

12. triggering the PWM controller to skip switching on the power switch for one pulse (or multiple pulses) based on the skip signal, triggering a driver of the PWM controller to drive the power switch to skip a pulse (or multiple pulses); The method of claim 11 , comprising:

13. starting a one-shot timer triggered by said skip signal; Further comprising: Triggering the PWM controller to skip a pulse (or multiple pulses) Triggering the PWM controller to skip a pulse (or pulses) when the one-shot timer expires before the switching cycle ends. Including, The method of claim 10.

14. resetting the skip signal at the start of a next switching cycle; The method of claim 10 further comprising:

15. setting the voltage across the capacitor to zero at or before the start of a next switching cycle; The method of claim 9 further comprising:

16. 1. A power converter comprising: a power switch and an inductor connected between an input node and an output node of a power converter, the input node being coupled to an input voltage V ＩＮ and the output node has an output voltage V ＯＵＴ a power converter for providing a pulse width modulation (PWM) controller coupled to the power converter and configured to control the power converter to operate in a PWM mode; A control circuit coupled to the PWM controller, the control circuit comprising: A current source; A capacitor connected between the current source and ground, the current source being αV ＩＮ Or α(V ＩＮ -V ＯＵＴ ) when the PWM signal of the PWM controller is low. ＯＵＴ ) or α(V ＩＮ -V ＯＵＴ ), where α is a preconfigured constant; and Including, a control circuit configured to trigger the PWM controller to skip switching on the power switch for one pulse (or multiple pulses) when a voltage at a common node of the current source and the capacitor falls below a skip threshold before a current switching cycle of the power converter ends; 13. An apparatus comprising:

17. The current source is Current αV ＩＮ a first current source having a first current flow direction from the first current source to the common node, the first current source being connected between the common node and the ground; Current αV ＯＵＴ a second current source having a first input terminal connected between the common node and the ground, with a direction of current flow of the second current source being from the common node to the ground, and the second current source being connected in parallel with the capacitor; 17. The apparatus of claim 16, comprising:

18. 20. The apparatus of claim 17, wherein the control circuit further comprises: a first switch connected between the first current source and the common node, the first switch configured to be switched on when the PWM signal is high.

19. 20. The apparatus of claim 17, wherein the control circuit further comprises: a second switch connected in parallel with the capacitor between the common node and the ground, the second switch configured to set the voltage across the capacitor to zero.

20. The control circuit includes: a skip circuit having an input terminal connected to the common node, the skip circuit configured to output a skip signal indicating to skip a switching pulse (or multiple switching pulses) when the voltage across the capacitor falls below the skip threshold before the current switching cycle ends; 20. The apparatus of claim 16, further comprising:

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