Drive circuit and range finding sensor

Abstract

To provide a drive circuit and a range finding sensor that can make a light-emitting element stably emit a light pulse having a short pulse width.SOLUTION: A drive circuit comprises: an n-channel field effect transistor including a gate, a drain and a source into which a current that constitutes a drive current for driving a light-emitting element flows; a capacitor which AC-grounds the gate; and a source drive circuit which drives the source with a signal corresponding to an input pulse signal.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to a drive circuit and a distance measurement sensor.

Background Art

[0002] Patent Document 1 discloses a time-of-flight (ToF) type distance measurement sensor. In the distance measurement sensor, a vertical cavity surface emitting laser (VCSEL) driver drives a VCSEL. Thereby, the VCSEL emits an optical pulse. A single photon avalanche diode (SPAD) array receives the light reflected by the detection target. Thereby, the SPAD array outputs a pulse signal (paragraphs 0017-0020 and 0022).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the distance measurement sensor disclosed in Patent Document 1, the accuracy of distance measurement improves as the pulse width of the optical pulse emitted by the VCSEL becomes shorter. However, in the distance measurement sensor, it is difficult to stably emit an optical pulse having a short pulse width from the VCSEL.

[0005] One aspect of the present disclosure has been made in view of this problem. One aspect of the present disclosure aims to provide, for example, a drive circuit and a distance measurement sensor capable of stably emitting an optical pulse having a short pulse width to a light emitting element.

Means for Solving the Problems

[0006] The drive circuit according to one aspect of the present disclosure includes an n-channel field effect transistor having a gate, a drain into which a current constituting a drive current for driving a light emitting element flows, and a source, a capacitor that alternately grounds the gate, and a source drive circuit that drives the source with a signal corresponding to an input pulse signal.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Embodiments for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Regarding the drawings, the same or equivalent elements are denoted by the same reference numerals, and redundant descriptions are omitted.

[0009] 1 First Embodiment 1.1 Distance Measurement Sensor FIG. 1 is a cross-sectional view schematically showing a distance measurement sensor according to the first embodiment and an object to be measured by the distance measurement sensor.

[0010] The distance measurement sensor 1 according to the first embodiment illustrated in FIG. 1 is a time-of-flight (ToF) type distance measurement sensor. For this reason, the distance measurement sensor 1 emits the second pulsed light 12, receives the reflected pulsed light 13 generated by the second pulsed light 12 being reflected by the object 2, and measures the distance to the object 2 from the time from when the second pulsed light 12 is emitted until the reflected pulsed light 13 is received.

[0011] As illustrated in FIG. 1, the distance measurement sensor 1 includes a package 21, a light emitting element 22, a first optical filter 23, a condenser lens 24, a second optical filter 25, a light receiving integrated circuit (IC) 26, and a light shielding wall 27. The light receiving IC 26 includes a first light receiving element 31 and a second light receiving element 32.

[0012] An internal space 21a, a first hole 21b, and a second hole 21c are formed in the package 21. The internal space 21a houses the light emitting element 22, the first optical filter 23, the second optical filter 25, the light receiving IC 26, and the light shielding wall 27. The first hole 21b extends from the internal space 21a to the outside of the package 21. The second hole 21c extends from the internal space 21a to the outside of the package 21. The second hole 21c houses the condenser lens 24.

[0013] The light-emitting element 22 emits pulsed light including the first pulsed light 11 and the second pulsed light 12. The first pulsed light 11 travels through the internal space 21a of the package 21 without being emitted to the outside of the package 21 and reaches the first light-receiving element 31 via the first optical filter 23. The second pulsed light 12 is emitted from the internal space 21a to the outside of the package 21 via the first hole 21b and reaches the object 2. The reflected pulsed light 13 generated by the reflection of the second pulsed light 12 by the object 2 reaches the second light-receiving element 32 via the condenser lens 24 and the second optical filter 25 from the outside of the package 21. The light-emitting element 22 is a vertical-cavity surface-emitting laser (VCSEL). The light-emitting element 22 may be a light-emitting element other than a VCSEL.

[0014] The first optical filter 23 transmits the first pulsed light 11. The first optical filter 23 selectively transmits light having the wavelength of the first pulsed light 11 and wavelengths close to the wavelength.

[0015] The first light-receiving element 31 receives the first pulsed light 11 that has passed through the first optical filter 23 and outputs a first pulse signal corresponding to the received first pulsed light 11. The first light-receiving element 31 is a single-photon avalanche diode (SPAD) array. The first light-receiving element 31 may be a light-receiving element other than a SPAD array.

[0016] The condenser lens 24 transmits the reflected pulsed light 13. The condenser lens 24 condenses the reflected pulsed light 13 onto the second light-receiving element 32.

[0017] The second optical filter 25 transmits the reflected pulsed light 13 that has passed through the condenser lens 24. The second optical filter 25 selectively transmits light having the wavelength of the second pulsed light 12 and wavelengths close to the wavelength.

[0018] The second light-receiving element 32 receives the reflected pulse light 13 that has passed through the second optical filter 25, and outputs a second pulse signal corresponding to the received reflected pulse light 13. The second light-receiving element 32 is a SPAD array. The second light-receiving element 32 may be a light-receiving element other than a SPAD array.

[0019] The light-shielding wall 27 separates the region where the second light-receiving element 32 is disposed from the regions where the light-emitting element 22 and the first light-receiving element 31 are disposed. The light-shielding wall 27 blocks light. Thereby, the light-shielding wall 27 inhibits the first pulse light 11 from reaching the second light-receiving element 32.

[0020] The light-receiving IC 26 obtains the distance between the ranging sensor 1 and the object 2 from the output first pulse signal and second pulse signal.

[0021] The first optical filter 23 and the first light-receiving element 31 are also referred to as a reference-side optical filter and a light-receiving element, respectively. The second optical filter 25 and the second light-receiving element 32 are also referred to as a return-side optical filter and a light-receiving element, respectively.

[0022] 1.2 Light-receiving IC FIG. 2 is a block diagram of a light-receiving IC and a light-emitting element provided in the ranging sensor according to the first embodiment.

[0023] As shown in FIG. 2, the light-receiving IC 26 includes a drive circuit 41, a first front-end circuit 42, a high-voltage generation circuit 43, a second front-end circuit 44, a third front-end circuit 45, a time measurement circuit 46, a time difference calculation unit 47, and a histogram generation / distance calculation unit 48.

[0024] A drive signal 51 is input to a drive circuit 41. The drive circuit 41 drives a light-emitting element 22 with a drive current 61 corresponding to the input drive signal 51. Thereby, the light-emitting element 22 emits light corresponding to the drive signal 51. The drive signal 51 includes a pulse signal. For this reason, the emitted light includes pulsed light emitted in synchronization with the pulse signal. The pulsed light includes a first pulsed light 11 and a second pulsed light 12. The drive circuit 41 outputs a drive signal 52 corresponding to the drive current 61.

[0025] An output drive signal 52 is input to a first front-end circuit 42. The first front-end circuit 42 shapes the waveform of the input drive signal 52 and outputs a drive signal having the shaped waveform.

[0026] A high-voltage generation circuit 43 generates a high voltage and outputs the generated high voltage. The output high voltage has a voltage value of, for example, 10 to 20 V.

[0027] The output high voltage is applied to a first light-receiving element 31. The first light-receiving element 31 operates by the applied high voltage. The first light-receiving element 31 receives the first pulsed light 11 and outputs a first pulse signal corresponding to the received first pulsed light 11.

[0028] An output first pulse signal is input to a second front-end circuit 44. The second front-end circuit 44 shapes the waveform of the input first pulse signal and outputs a first pulse signal having the shaped waveform.

[0029] The output high voltage is applied to a second light-receiving element 32. The second light-receiving element 32 operates by the applied high voltage. The second light-receiving element 32 receives the second pulsed light 12 and outputs a second pulse signal corresponding to the received second pulsed light 12.

[0030] The output second pulse signal is input to the third front-end circuit 45. The third front-end circuit 45 shapes the waveform of the input second pulse signal and outputs a second pulse signal having the shaped waveform.

[0031] The drive signal having the shaped waveform, the first pulse signal, and the second pulse signal are input to the time measurement circuit 46. The time measurement circuit 46 measures, from the input drive signal, first pulse signal, and second pulse signal, the absolute values of the emission time when the light-emitting element 22 emits the first pulse light 11, the first light reception time when the first light-receiving element 31 receives the first pulse light 11, and the second light reception time when the second light-receiving element 32 receives the second pulse light 12, respectively. The time measurement circuit 46 outputs the measured absolute values of the emission time, first light reception time, and second light reception time. The time measurement circuit 46 includes three time-to-digital converters (TDCs) for measuring the absolute values of the emission time, first light reception time, and second light reception time. The time measurement circuit 46 outputs a drive signal 51.

[0032] The absolute values of the output emission time, first light reception time, and second light reception time are input to the time difference calculation unit 47. The time difference calculation unit 47 calculates a first time difference from the input absolute values of the emission time and the first light reception time, from when the light-emitting element 22 emits the first pulse light 11 until the first light-receiving element 31 receives the first pulse light 11. Also, the time difference calculation unit 47 calculates a second time difference from the input absolute values of the emission time and the second light reception time, from when the light-emitting element 22 emits the first pulse light 11 until the second light-receiving element 32 receives the second pulse light 12. The time difference calculation unit 47 outputs the calculated first time difference and second time difference.

[0033] FIG. 3 is a diagram showing an example of a histogram of the first time difference and a histogram of the second time difference created by the histogram generation / distance calculation unit provided in the distance measurement sensor of the first embodiment.

[0034] The output first time difference and second time difference are input to the histogram generation / distance calculation unit 48. The histogram generation / distance calculation unit 48 creates a histogram 71 of the first time difference shown in FIG. 3 from a plurality of first time differences input at different timings. The histogram generation / distance calculation unit 48 calculates a first centroid time 81 that is the centroid of the created histogram 71 of the first time difference. Also, the histogram generation / distance calculation unit 48 creates a histogram 72 of the second time difference shown in FIG. 3 from a plurality of second time differences input at different timings. The histogram generation / distance calculation unit 48 calculates a second centroid time 82 that is the centroid of the created histogram 72 of the second time difference. The histogram generation / distance calculation unit 48 calculates a time difference 91 between the calculated first centroid time 81 and the calculated second centroid time 82. The histogram generation / distance calculation unit 48 calculates the distance between the ranging sensor 1 and the object 2 from the calculated time difference 91.

[0035] The histogram 71 of the first time difference is also called the reference-side histogram. The histogram 72 of the second time difference is also called the return-side histogram.

[0036] The time difference calculation unit 47 and the histogram generation / distance calculation unit 48 may be configured by an electronic circuit or may be configured by a processor that executes a program stored in a memory.

[0037] 1.3 Driving Circuit FIG. 4 is a circuit diagram of the driving circuit and the light emitting element provided in the ranging sensor of the first embodiment.

[0038] As shown in FIG. 4, the driving circuit 41 includes an anode connection terminal 101, a cathode connection terminal 102, a power supply 103, a ground 104, an anode-side circuit 105, and a cathode-side circuit 106. The light emitting element 22 includes an anode 22a and a cathode 22b.

[0039] The anode 22a and the cathode 22b of the light-emitting element 22 are electrically connected to the anode connection terminal 101 and the cathode connection terminal 102, respectively.

[0040] The power supply 103 and the ground 104 have a power supply potential and a ground potential, respectively.

[0041] The anode-side circuit 105 is electrically connected to the power supply 103 and the anode connection terminal 101. The anode-side circuit 105 causes the drive current 61 flowing out from the anode connection terminal 101 to flow from the power supply 103 to the anode connection terminal 101.

[0042] The cathode-side circuit 106 is electrically connected to the cathode connection terminal 102 and the ground 104. The cathode-side circuit 106 causes the drive current 61 flowing into the cathode connection terminal 102 to flow from the cathode connection terminal 102 to the ground 104.

[0043] Thus, the drive current 61 flows out from the anode connection terminal 101, flows through the light-emitting element 22, and flows into the cathode connection terminal 102.

[0044] 1.4 Connection between the drive circuit and the light-emitting element The anode 22a and the cathode 22b of the light-emitting element 22 are electrically connected to the anode connection terminal 101 and the cathode connection terminal 102 via an anode-side gold wire and a cathode-side gold wire, respectively.

[0045] Each of the anode-side gold wire and the cathode-side gold wire has a parasitic resistance and a parasitic inductance. The light-emitting element 22 has a parasitic capacitance. The parasitic resistance, the parasitic inductance, and the parasitic capacitance cause ringing in the drive current 61.

[0046] Measures are taken in the cathode-side circuit 106 to suppress the occurrence of ringing in the drive current 61.

[0047] 1.5 Anode-side circuit As shown in FIG. 4, the anode-side circuit 105 includes a p-channel field-effect transistor (FET) 111, a buffer 112, and a capacitor 113. The p-channel FET 111 includes a gate 111a, a source 111b, and a drain 111c. The buffer 112 includes an input terminal 112a and an output terminal 112b. The capacitor 113 includes a first terminal 113a and a second terminal 113b.

[0048] The source 111b of the p-channel FET 111 is electrically connected to the power supply 103. The drain 111c of the p-channel FET 111 is electrically connected to the anode connection terminal 101. Thereby, a conduction path from the power supply 103 to the anode connection terminal 101 is formed. Between the source 111b and the drain 111c is inserted into the formed conduction path. Thereby, when the drain 111c is conducting with the source 111b, the anode-side circuit 105 causes the drive current 61 to flow through the conduction path and causes the drive current 61 to flow out from the anode connection terminal 101. Also, when the drain 111c is not conducting with the source 111b, the anode-side circuit 105 does not cause the drive current 61 to flow through the conduction path and does not cause the drive current 61 to flow out from the anode connection terminal 101.

[0049] When an on potential is applied to the gate 111a of the p-channel FET 111, the p-channel FET 111 conducts the drain 111c with the source 111b and causes the drive current 61 to flow out from the drain 111c. When an off potential is applied to the gate 111a, the p-channel FET 111 does not conduct the drain 111c with the source 111b and does not cause the drive current 61 to flow out from the drain 111c. The on potential is a potential lower than the potential obtained by subtracting the threshold voltage of the p-channel FET 111 from the power supply potential, and is, for example, the ground potential. The off potential is a potential higher than the potential obtained by subtracting the threshold voltage of the p-channel FET 111 from the power supply potential, and is, for example, the power supply potential.

[0050] The p-channel FET 111 is a metal-oxide semiconductor (MOS) FET or the like.

[0051] The input terminal 112a of the buffer 112 is electrically connected to a control circuit that provides an on potential and an off potential. The output terminal 112b of the buffer 112 is electrically connected to the gate 111a of the p-channel FET 111.

[0052] When an on potential is applied to the input terminal 112a of the buffer 112, the buffer 112 applies an on potential to the output terminal 112b and applies an on potential to the gate 111a of the p-channel FET 111. Also, when an off potential is applied to the input terminal 112a, the buffer 112 applies an off potential to the output terminal 112b and applies an off potential to the gate 111a. The input terminal 112a of the buffer 112 has a high input impedance.

[0053] The first terminal 113a of the capacitor 113 is electrically connected to the drain 111c of the p-channel FET 111 and the anode connection terminal 101, and is electrically connected to the anode 22a of the light-emitting element 22 via the anode connection terminal 101. The second terminal 113b of the capacitor 113 is electrically connected to the ground 104. Thereby, the capacitor 113 is inserted between the drain 111c and the ground 104. Thereby, when the drive current 61 rapidly rises, the capacitor 113 can supply at least a part of the drive current 61. Thereby, it is possible to suppress the influence of the rapid rise of the drive current 61 on the power supply 103. Thereby, it is possible to suppress the occurrence of electromagnetic interference (EMI) caused by the rapid rise of the drive current 61.

[0054] 1.6 Cathode-side circuit As shown in FIG. 4, the cathode-side circuit 106 includes a bias current circuit 121, a reference current circuit 122, a mirror current circuit 123, a plurality of driver cells 124, a feedback circuit 125, and a snubber circuit 126.

[0055] The bias current circuit 121 is electrically connected to the cathode connection terminal 102 and the ground 104. The bias current circuit 121 flows a bias current 131 from the cathode connection terminal 102 to the ground 104. The flowing bias current 131 has a constant current value.

[0056] The reference current circuit 122 is electrically connected to the power supply 103 and the ground 104. The reference current circuit 122 flows a reference current 132 from the power supply 103 to the ground 104. The flowing reference current 132 has a constant current value.

[0057] The mirror current circuit 123 is electrically connected to the cathode connection terminal 102 and the ground 104. The mirror current circuit 123 flows a mirror current 133 from the cathode connection terminal 102 to the ground 104. The flowing mirror current 133 has the same current value as the current value of the reference current 132.

[0058] Each driver cell 124 included in the plurality of driver cells 124 is electrically connected to the cathode connection terminal 102 and is electrically connected to the ground 104 when turned on. Each driver cell 124 flows a mirror current 134 from the cathode connection terminal 102 to the ground 104. The mirror current 134 has a current value that is four times the current value of the reference current 132. The mirror current 134 may have a current value different from the current value. Each driver cell 124 is configured such that the current value of the mirror current 134 is four times the current value of the mirror current 133, whereby the current value of the mirror current 134 is configured to be four times the current value of the reference current 132.

[0059] A drive signal 51 is input to each driver cell 124. When the potential of the input drive signal 51 is at the H potential, each driver cell 124 allows a mirror current 134 to flow, and when the potential of the input drive signal 51 is at the L potential, each driver cell 124 does not allow the mirror current 134 to flow. The H potential is a potential higher than the potential obtained by adding the threshold voltage of an n-channel FET 171, which will be described later, to the ground potential, and is, for example, the power supply potential. The L potential is a potential lower than the potential obtained by adding the threshold voltage of the n-channel FET 171, which will be described later, to the ground potential, and is, for example, the ground potential.

[0060] When the current value of the mirror current 133 is greater than the current value of the reference current 132, the feedback circuit 125 controls the mirror current circuit 123 so that the current value of the mirror current 133 decreases, and controls each driver cell 124 so that the current value of the mirror current 134 decreases. When the current value of the mirror current 133 is less than the current value of the reference current 132, the feedback circuit 125 controls the mirror current circuit 123 so that the current value of the mirror current 133 increases, and controls each driver cell 124 so that the current value of the mirror current 134 increases. Thereby, the feedback circuit 125 mirrors the reference current 132 to the mirror current 133 so that the current value of the mirror current 133 becomes the same as the current value of the reference current 132, and mirrors the reference current 132 to the mirror current 134 so that the current value of the mirror current 134 becomes four times the current value of the reference current 132.

[0061] The reference current circuit 122, the mirror current circuit 123, and the feedback circuit 125 constitute a circuit that allows the reference current 132 to flow and mirrors the reference current 132 to the mirror current 134, and together with each driver cell 124, constitute a current mirror circuit. The circuit that allows the reference current 132 to flow and mirrors the reference current 132 to the mirror current 134 may be a circuit different from the circuit shown in FIG. 4.

[0062] The bias current circuit 121, the mirror current circuit 123, and the plurality of driver cells 124 are inserted between the cathode connection terminal 102 and the ground 104 and are electrically connected in parallel. Thereby, the drive current 61 flowing into the cathode connection terminal 102 is shunted to the bias current circuit 121, the mirror current circuit 123, and the plurality of driver cells 124. Therefore, the drive current 61 is composed of a bias current 131, a mirror current 133, and a plurality of mirror currents 134.

[0063] By electrically connecting the plurality of driver cells 124 in parallel, the light emitting element 22 can be driven by a drive current 61 having a current value larger than the current value of the mirror current 134 that each driver cell 124 can pass.

[0064] The snubber circuit 126 is electrically connected to the cathode connection terminal 102 and the ground 104. The snubber circuit 126 suppresses the occurrence of ringing in the drive current 61.

[0065] 1.7 Waveforms of Drive Signal and Drive Current FIG. 5 is a diagram showing waveforms of a drive signal input to a drive circuit provided in the distance measurement sensor of the first embodiment and a drive current output by the drive circuit.

[0066] As shown in FIG. 5, the drive signal 51 includes a pulse signal 51a. Further, the drive current 61 includes a pulse current 61a.

[0067] The drive circuit 41 outputs a pulse current 61a in response to the input of the pulse signal 51a.

[0068] The drive circuit 41 outputs a drive current 61 having a current value of the total of the current value of the bias current 131 and the current value of the mirror current 133, i.e., the current value IBAIS, during a period when the pulse signal 51a is not input. The drive circuit 41 outputs a drive current 61 having a total current value of the sum of the current value IBAIS and the total current value of the current values of the plurality of mirror currents 134, i.e., the current value DRV, during a period when the pulse signal 51a is input.

[0069] 1.8 Bias Current Circuit As shown in FIG. 4, the bias current circuit 121 includes a current source 141. The current source 141 includes a first terminal 141a and a second terminal 141b.

[0070] The first terminal 141a of the current source 141 is electrically connected to the cathode connection terminal 102. The second terminal 141b of the current source 141 is connected to the ground 104. Thereby, a conduction path from the cathode connection terminal 102 to the ground 104 is formed. The formed conduction path has the current source 141 inserted therein.

[0071] The current source 141 flows a bias current 131 from the first terminal 141a of the current source 141 to the second terminal 141b of the current source 141. Thereby, the bias current circuit 121 flows the bias current 131 from the cathode connection terminal 102 to the ground 104.

[0072] 1.9 Reference Current Circuit As shown in FIG. 4, the reference current circuit 122 includes a constant current source 151 and a resistor 152. The constant current source 151 includes a first terminal 151a and a second terminal 151b. The resistor 152 includes a first terminal 152a and a second terminal 152b.

[0073] The first terminal 151a of the constant current source 151 is electrically connected to the power supply 103. The second terminal 151b of the constant current source 151 is electrically connected to the first terminal 152a of the resistor 152. The second terminal 152b of the resistor 152 is electrically connected to the ground 104. Thereby, a conduction path from the power supply 103 to the ground 104 is formed. The formed conduction path has the constant current source 151 and the resistor 152 inserted therein. The inserted constant current source 151 and resistor 152 are electrically connected in series.

[0074] The constant current source 151 passes a reference current 132 from the first terminal 151a of the constant current source 151 to the second terminal 151b of the constant current source 151. Thereby, the reference current circuit 122 passes the reference current 132 from the power supply 103 to the ground 104. A potential corresponding to the current value of the reference current 132 flowing is applied to the second terminal 151b of the constant current source 151 and the first terminal 152a of the resistor 152. The potential applied is the product of the current value of the reference current 132 and the resistance value of the resistor 152.

[0075] 1.10 Mirror current circuit As shown in FIG. 4, the mirror current circuit 123 includes an n-channel FET 161 and a resistor 162. The n-channel FET 161 includes a gate 161a, a drain 161b, and a source 161c. The resistor 162 includes a first terminal 162a and a second terminal 162b.

[0076] The drain 161b of the n-channel FET 161 is electrically connected to the cathode connection terminal 102. Therefore, a mirror current 133 constituting the drive current 61 flows into the drain 161b. The source 161c of the n-channel FET 161 is electrically connected to the first terminal 162a of the resistor 162. The second terminal 162b of the resistor 162 is electrically connected to the ground 104. Thereby, a conduction path from the cathode connection terminal 102 to the ground 104 is formed. In the formed conduction path, the drain 161b-source 161c section and the resistor 162 are inserted. The inserted drain 161b-source 161c section and the resistor 162 are electrically connected in series.

[0077] The n-channel FET 161 conducts a mirror current 133 from the drain 161b of the n-channel FET 161 to the source 161c of the n-channel FET 161 according to the potential applied to the gate 161a of the n-channel FET 161. As a result, the mirror current circuit 123 conducts a mirror current 133 from the cathode connection terminal 102 to the ground 104 according to the potential applied to the gate 161a. The current value of the mirror current 133 that flows increases as the potential increases. A potential corresponding to the current value of the mirror current 133 that flows is applied to the source 161c of the n-channel FET 161 and the first terminal 162a of the resistor 162. The potential applied is the product of the current value of the mirror current 133 and the resistance value of the resistor 162.

[0078] The gate 161a of the n-channel FET 161 is electrically connected to the feedback circuit 125. As a result, a potential is applied to the gate 161a such that the current value of the mirror current 133 becomes the same as the current value of the reference current 132. Thereby, the mirror current circuit 123 is controlled so that a mirror current 133 having the same current value as the current value of the reference current 132 flows.

[0079] The source 161c of the n-channel FET 161 and the first terminal 162a of the resistor 162 are electrically connected to the feedback circuit 125. As a result, the mirror current circuit 123 can transmit a potential corresponding to the current value of the mirror current 133 to the feedback circuit 125.

[0080] The n-channel FET 161 is a MOSFET.

[0081] 1.11 Driver cell As shown in FIG. 4, each driver cell 124 includes an n-channel FET 171, a resistor 172, a capacitor 173, and a source drive circuit 174. The n-channel FET 171 includes a gate 171a, a drain 171b, and a source 171c. The resistor 172 includes a first terminal 172a and a second terminal 172b. The capacitor 173 includes a first terminal 173a and a second terminal 173b. The source drive circuit 174 includes a first terminal 174a and a second terminal 174b.

[0082] The drain 171b of the n-channel FET 171 is electrically connected to the cathode connection terminal 102. Therefore, the mirror current 134 that constitutes the drive current 61 flows into the drain 171b. The source 171c of the n-channel FET 171 is electrically connected to the first terminal 172a of the resistor 172. The second terminal 172b of the resistor 172 is electrically connected to the first terminal 174a of the source drive circuit 174. Thereby, a conduction path from the cathode connection terminal 102 to the first terminal 174a is formed. In the formed conduction path, the drain 171b-source 171c and the resistor 172 are inserted. The inserted drain 171b-source 171c and the resistor 172 are electrically connected in series.

[0083] The n-channel FET 171 flows a mirror current 134 corresponding to the potential applied to the gate 171a of the n-channel FET 171 from the drain 171b of the n-channel FET 171 to the source 171c of the n-channel FET 171. Thereby, each driver cell 124 flows a mirror current 134 corresponding to the potential applied to the gate 171a from the cathode connection terminal 102 to the first terminal 174a of the source drive circuit 174. The current value of the flowing mirror current 134 increases as the potential increases.

[0084] The gate 171a of the n-channel FET 171 is electrically connected to the feedback circuit 125. As a result, the gate 171a is given a potential at which the current value of the mirror current 134 is four times the current value of the reference current 132. Thereby, the mirror current circuit 123 is controlled so that a mirror current 133 having a current value four times the current value of the reference current 132 flows.

[0085] The n-channel FET 171 is a MOSFET.

[0086] The resistance value of the resistor 172 is 1 / 4 times the resistance value of the resistor 162. Thereby, the current value of the mirror current 134 can be made four times the current value of the mirror current 133.

[0087] The first terminal 173a of the capacitor 173 is electrically connected to the gate 171a of the n-channel FET 171. The second terminal 173b of the capacitor 173 is electrically connected to the ground 104. Thereby, the capacitor 173 is inserted between the gate 171a and the ground 104 to ground the gate 171a alternately. The capacitance value of the capacitor 173 is set to have a capacitive impedance that is sufficiently small at the frequency of the frequency component most contained in the drive signal 51.

[0088] The drive signal 51 is input to the second terminal 174b of the source drive circuit 174. The source drive circuit 174 outputs a signal 181 corresponding to the drive signal 51 input to the second terminal 174b from the first terminal 174a of the source drive circuit 174. The first terminal 174a is electrically connected to the source 171c of the n-channel FET 171 via the resistor 172. Therefore, the source drive circuit 174 drives the source 171c with the signal 181 so that the mirror current 134 flows.

[0089] When the potential of the drive signal 51 becomes the H potential, the source drive circuit 174 sets the potential of the signal 181 to the L potential so that the mirror current 134 flows. When the potential of the drive signal 51 becomes the L potential, the source drive circuit 174 sets the potential of the signal 181 to the H potential so that the mirror current 134 does not flow.

[0090] When the gate 171a of the n-channel FET 171 is AC grounded and the source 171c of the n-channel FET 171 is driven by the signal 181, the modulation by the signal 181 is less affected by the mirror capacitance of the n-channel FET 171. As a result, the modulation by the signal 181 can be performed at high speed, and pulsed light having a short pulse width can be emitted to the light-emitting element 22.

[0091] 1.12 Source drive circuit As shown in FIG. 4, the source drive circuit 174 includes a first inverter 201, a second inverter 202, a capacitor 203, and a constant voltage power supply 204. The first inverter 201 includes an input terminal 201a, an output terminal 201b, and a power supply terminal 201c. The second inverter 202 includes an input terminal 202a, an output terminal 202b, and a power supply terminal 202c. The capacitor 203 includes a first terminal 203a and a second terminal 203b.

[0092] The input terminal 201a of the first inverter 201 and the input terminal 202a of the second inverter 202 are electrically connected to the time difference measurement circuit 46. The output terminal 201b of the first inverter 201 is electrically connected to the second terminal 172b of the resistor 172. The output terminal 202b of the second inverter 202 is electrically connected to the first terminal 203a of the capacitor 203. The second terminal 203b of the capacitor 203 is electrically connected to the second terminal 172b of the resistor 172. As a result, the output terminal 201b of the first inverter 201 is directly connected to the second terminal 172b. The output terminal 202b of the second inverter 202 is connected to the second terminal 172b via the capacitor 203. The power supply terminal 201c of the first inverter 201 and the power supply terminal 202c of the second inverter 202 are electrically connected to the constant voltage power supply 204.

[0093] A drive signal 51 is input to the input terminal 201a of the first inverter 201 and the input terminal 202a of the second inverter 202. The first inverter 201 and the second inverter 202 output an inverted pulse signal obtained by inverting the input drive signal 51 to the output terminal 201b of the first inverter 201 and the output terminal 202b of the second inverter 202, respectively. Thereby, a potential corresponding to the inverted pulse signal is applied to the second terminal 172b of the resistor 172. As a result, the signal for driving the source 171c of the n-channel FET 171 becomes an inverted pulse signal obtained by inverting the drive signal 51.

[0094] The output terminal 202b of the second inverter 202 is connected to the second terminal 172b of the resistor 172 via the capacitor 203, whereby the second terminal 172b is AC-coupled. Thereby, the rising of the potential in the inverted pulse signal can be accelerated.

[0095] FIG. 6 is a diagram showing waveforms of a drive signal input to the input terminals of the first inverter and the second inverter of the drive circuit provided in the distance measurement sensor according to the first embodiment, and an inverted pulse signal output from the output terminals of the first inverter and the second inverter.

[0096] As shown in FIG. 6, the potential of the inverted pulse signal 211 output from the output terminal 201b of the first inverter 201 and the output terminal 202b of the second inverter 202 drops from the H potential to the L potential at the timing 231 when the potential of the drive signal 51 input to the input terminal 201a of the first inverter 201 and the input terminal 202a of the second inverter 202 rises and exceeds the threshold potential 221, and rises from the L potential to the H potential at the timing 232 when the potential of the drive signal 51 drops and exceeds the threshold potential 221.

[0097] It takes time for the potential of the drive signal 51 to rise from the L potential to the H potential, and it also takes time for the potential of the drive signal 51 to drop from the H potential to the L potential. For this reason, when the threshold potential 221 changes, the timings 231 and 232 change, and the waveform of the inverted pulse signal 211 also changes.

[0098] The threshold potential 221 changes when the potential applied to the power supply terminal 201c of the first inverter 201 and the power supply terminal 202c of the second inverter 202 changes. Therefore, the waveform of the inversion pulse signal 211 changes when the potential applied to the power supply terminal 201c and the power supply terminal 202c changes. However, when the power supply terminals 201c and 202c are electrically connected to the constant voltage power supply 204 and a stable potential is applied to the power supply terminals 201c and 202c, the waveform of the inversion pulse signal 211 can be made into a stable waveform.

[0099] 1.13 Feedback Circuit As shown in FIG. 4, the feedback circuit 125 includes an operational amplifier 241. The operational amplifier 241 includes a non-inverting input terminal 241a, an inverting input terminal 241b, and an output terminal 241c.

[0100] The non-inverting input terminal 241a is electrically connected to the second terminal 151b of the constant current source 151 and the first terminal 152a of the resistor 152. The inverting input terminal 241b is electrically connected to the source 161c of the n-channel FET 161 and the first terminal 162a of the resistor 162. The output terminal 241c is electrically connected to the gate 161a of the n-channel FET 161 and the gate 171a of the n-channel FET 171.

[0101] Thereby, a potential corresponding to the product of the current value of the reference current 132 and the resistance value of the resistor 152 is applied to the non-inverting input terminal 241a. A potential corresponding to the product of the current value of the mirror current 133 and the resistance value of the resistor 162 is applied to the inverting input terminal 241b.

[0102] The operational amplifier 241 applies, to the output terminal 241c of the operational amplifier 241, a potential obtained by multiplying the potential difference obtained by subtracting the potential applied to the inverting input terminal 241b of the operational amplifier 241 from the potential applied to the non-inverting input terminal 241a of the operational amplifier 241 by the gain.

[0103] The resistance value of resistor 162 is the same as that of resistor 152. Therefore, the potential difference is proportional to the current value difference obtained by subtracting the current value of mirror current 133 from the current value of reference current 132. Thus, the potentials applied to output terminal 241c of operational amplifier 241, gate 161a of n-channel FET 161, and gate 171a of n-channel FET 171 are proportional to the current value difference. As a result, when the current value difference is greater than 0, feedback circuit 125 increases the potential applied to gate 161a of n-channel FET 161 and gate 171a of n-channel FET 171, increasing the current values of mirror current 133 and mirror current 134. Also, when the current value difference is less than 0, feedback circuit 125 decreases the potential applied to gate 161a of n-channel FET 161 and gate 171a of n-channel FET 171, decreasing the current values of mirror current 133 and mirror current 134. Thereby, feedback circuit 125 mirrors reference current 132 to mirror current 133 so that the current value of mirror current 133 becomes the same as the current value of reference current 132, and mirrors reference current 132 to mirror current 134 so that the current value of mirror current 134 becomes four times the current value of reference current 132.

[0104] 1.14 Snubber Circuit As shown in FIG. 4, snubber circuit 126 includes resistor 251 and capacitor 252. Resistor 251 includes a first terminal 251a and a second terminal 251b. Capacitor 252 includes a first terminal 252a and a second terminal 252b.

[0105] The first terminal 251a of resistor 251 is electrically connected to cathode connection terminal 102. The second terminal 251b of resistor 251 is electrically connected to the first terminal 252a of capacitor 252. The second terminal 252b of capacitor 252 is electrically connected to ground 104. Thereby, a conduction path 261 from cathode connection terminal 102 to ground 104 is formed. Resistor 251 and capacitor 252 are inserted into the formed conduction path 261. The inserted resistor 251 and capacitor 252 are electrically connected in series to form snubber circuit 126.

[0106] The snubber circuit 126 functions as a ringing correction circuit that suppresses the occurrence of ringing in the drive current 61.

[0107] 1.15 Suppression of Ringing FIG. 7 is a circuit diagram showing an equivalent circuit of a light-emitting element, an anode-side gold wire, a cathode-side gold wire, and a snubber circuit provided in the distance measuring sensor of the first embodiment. FIG. 8 is a graph showing an example of the waveform of the drive current output by the drive circuit provided in the distance measuring sensor of the first embodiment and the waveform of the drive current output by the drive circuit when the snubber circuit is omitted from the drive circuit.

[0108] As shown in FIG. 7, the anode-side gold wire 271 that electrically connects the anode 22a of the light-emitting element 22 to the anode connection terminal 101 has a parasitic resistance 281 and a parasitic inductor 282. In FIG. 7, a case where the resistance value of the parasitic resistance 281 is 0.46 Ω and the inductance value of the parasitic inductor 282 is 1.07 nH is illustrated.

[0109] The cathode-side gold wire 272 that electrically connects the cathode 22b of the light-emitting element 22 to the cathode connection terminal 102 has a parasitic resistance 291 and a parasitic inductor 292. In FIG. 7, a case where the resistance value of the parasitic resistance 291 is 0.21 Ω and the inductance value of the parasitic inductor 292 is 0.46 nH is illustrated.

[0110] The light-emitting element 22 has a parasitic capacitor 300. In FIG. 7, a case where the capacitance value of the parasitic capacitor 300 is 15 pF is illustrated.

[0111] When the snubber circuit 126 is not provided despite the presence of parasitic resistance 281, parasitic inductor 282, parasitic resistance 291, parasitic inductor 292, and parasitic capacitor 300, as shown in waveform 312 of FIG. 8, large ringing occurs in the drive current 61. However, when the snubber circuit 126 is provided despite the presence of parasitic resistance 281, parasitic inductor 282, parasitic resistance 291, parasitic inductor 292, and parasitic capacitor 300, as shown in waveform 311 of FIG. 8, large ringing does not occur in the drive current 61.

[0112] The resistance value of resistor 251 and the capacitance value of capacitor 252 are adjusted according to the resistance value of parasitic resistance 281, the inductance value of parasitic inductor 282, the resistance value of parasitic resistance 291, the inductance value of parasitic inductor 292, and the capacitance value of parasitic capacitor 300. FIG. 7 illustrates a case where the resistance value of resistor 251 is 10 Ω and the capacitance value of capacitor 252 is 10 pF.

[0113] 2 Second Embodiment Hereinafter, differences between the second embodiment and the first embodiment will be described. For points not described, the same configurations as those employed in the first embodiment are also employed in the second embodiment.

[0114] FIG. 9 is a circuit diagram of a drive circuit provided in the distance measurement sensor of the second embodiment.

[0115] In the second embodiment, as shown in FIG. 9, each driver cell 124 includes a conduction path 261 and a snubber circuit 126.

[0116] The conduction path 261 extends from the cathode connection terminal 102 to the ground 104. The snubber circuit 126 is inserted into the conduction path 261.

[0117] Since each driver cell 124 includes a snubber circuit 126, the plurality of driver cells 124 each include a plurality of snubber circuits 126. The plurality of snubber circuits 126 are electrically connected in parallel to each other.

[0118] Accordingly, when the number of a plurality of driver cells 124 is N, the resistance value of the resistor 251 in the second embodiment can be set to N times the resistance value of the resistor 251 in the first embodiment. Also, the capacitance value of the capacitor 252 in the second embodiment can be set to 1 / N times the capacitance value of the capacitor 252 in the first embodiment. This makes it easier to mount the snubber circuit 126 on the light-receiving IC 26 in which it is difficult to mount a resistor having a small resistance value and a capacitor having a large capacitance value.

[0119] 3 Third Embodiment Hereinafter, differences between the third embodiment and the second embodiment will be described. For points not described, the same configurations as those employed in the second embodiment are also employed in the third embodiment.

[0120] FIG. 10 is a circuit diagram of a drive circuit provided in the distance measurement sensor according to the third embodiment.

[0121] In the third embodiment, as shown in FIG. 10, each driver cell 124 includes a plurality of conduction paths 261, a plurality of snubber circuits 126, and a plurality of switches 253.

[0122] The plurality of snubber circuits 126 are respectively inserted into the plurality of conduction paths 261. The plurality of switches 253 are respectively inserted into the plurality of conduction paths 261.

[0123] The plurality of switches 253 each switch between a state in which the plurality of conduction paths 261 are closed and a state in which the plurality of conduction paths 261 are open.

[0124] The snubber circuit 126 inserted into the closed conduction path 261 contributes to suppressing the occurrence of ringing in the drive current 61.

[0125] In the third embodiment, by selecting the number of closed conduction paths 261, it is possible to suppress ringing according to parasitic resistance, parasitic capacitance, and parasitic inductance.

[0126] The present disclosure is not limited to the above-described embodiments, and may be replaced with a configuration that is substantially the same as the configuration shown in the above-described embodiments, a configuration that exhibits the same operational effects, or a configuration that can achieve the same object.

Description of Reference Numerals

[0127] 1 Distance measurement sensor, 2 Object, 11 First pulsed light, 12 Second pulsed light, 13 Reflected pulsed light, 21 Package, 21a Internal space, 21b First hole, 21c Second hole, 22 Light emitting element, 22a Anode, 22b Cathode, 23 First optical filter, 24 Condensing lens, 25 Second optical filter, 26 Light receiving integrated circuit (IC), 27 Light shielding wall, 31 First light receiving element, 32 Second light receiving element, 41 Driving circuit, 42 Front end circuit, 43 High voltage generation circuit, 44 First front end circuit, 45 Second front end circuit, 46 Time difference measurement circuit, 47 Conversion circuit, 48 Histogram generation / distance calculation unit, 51 Driving signal, 52 Driving signal, 61 Driving current, 71 Histogram of first time difference, 72 Histogram of second time difference, 81 First centroid time, 82 Second centroid time, 91 Time difference, 101 Anode connection terminal, 102 Cathode connection terminal, 103 Power supply, 104 Ground, 105 Anode side circuit, 106 Cathode side circuit, 111p Channel field effect transistor (FET), 111a Gate, 111b Source, 111c Drain, 112 Buffer, 112a Input terminal, 112b Output terminal, 113 Capacitor, 113a First terminal, 113b Second terminal, 121 Bias current circuit, 122 Reference current circuit, 123 Mirror current circuit, 124 Driver cell, 125 Feedback circuit, 126 Snubber circuit, 131 Bias current, 132 Reference current, 133 Mirror current, 134 Mirror current, 141 Current source, 141a First terminal, 141b Second terminal, 151 Constant current source, 151a First terminal, 151b Second terminal, 152 Resistor, 152a First terminal, 152b Second terminal, 161 n Channel FET, 161a Gate, 161b Drain, 161c Source, 162 Resistor, 162a First terminal, 162b Second terminal, 171 n Channel FET, 171a Gate, 171b Drain, 171c Source, 172 Resistor, 172a First terminal, 172b Second terminal, 173 Capacitor, 173a First terminal, 173b Second terminal, 174 Source drive circuit, 174a First terminal, 174b Second terminal, 181 Signal, 201 First inverter, 201a Input terminal, 201bOutput terminal, 201c Power supply terminal, 202 Second inverter, 202a Input terminal, 202b Output terminal, 202c Power supply terminal, 203 Capacitor, 203a First terminal, 203b Second terminal, 204 Constant voltage power supply, 211 Inversion pulse signal, 221 Threshold potential, 231 Timing, 232 Timing, 241 Operational amplifier, 241a Non-inverting input terminal, 241b Inverting input terminal, 241c Output terminal, 251 Resistor, 251a First terminal, 251b Second terminal, 252 Capacitor, 252a First terminal, 252b Second terminal, 261 Conductive path, 271 Anode-side gold wire, 272 Cathode-side gold wire, 281 Parasitic resistance, 282 Parasitic inductor, 291 Parasitic resistance, 292 Parasitic inductor, 300 Parasitic capacitor, 311 Waveform, 312 Waveform.

Claims

1. An n-channel field effect transistor including a drain and a source into which a current constituting a drive current for driving a gate and a light emitting element flows, A capacitor that alternately grounds the gate, A source drive circuit that drives the source with a signal corresponding to an input pulse signal, And a drive circuit including the same.

2. The source drive circuit includes An inverter including an input terminal to which the pulse signal is input, an output terminal that outputs an inverted pulse signal obtained by inverting the pulse signal, and a power supply terminal, A constant voltage power supply electrically connected to the power supply terminal, And includes The signal is the inverted pulse signal The drive circuit according to claim 1.

3. Ground, A conduction path from the drain to the ground, A snubber circuit inserted into the conduction path, And includes The drive circuit according to claim 1.

4. Including a plurality of driver cells, Each of the plurality of driver cells includes the n-channel field effect transistor, the capacitor, the source drive circuit, the conduction path, and the snubber circuit The drive circuit according to claim 3.

5. Ground, a plurality of conduction paths from the drain to the ground, a plurality of snubber circuits respectively inserted into the plurality of conduction paths, and a plurality of switches respectively inserted into the plurality of conduction paths. The drive circuit according to claim 1.

6. The gate is a first gate, The drain is a first drain, The source is a first source, a p-channel field-effect transistor including a second gate, a second drain through which the drive current flows out, and a second source, a power supply electrically connected to the second source, a ground, a capacitor inserted between the second drain and the ground, The drive circuit according to claim 1, comprising:

7. A circuit that passes a reference current and mirrors the reference current to the current. The drive circuit according to claim 1.

8. The light-emitting element is a vertical cavity surface emitting diode. The drive circuit according to claim 1.

9. The drive circuit according to claim 1, the light-emitting element, a light-receiving element, A distance measurement sensor comprising:

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