Semiconductor device and manufacturing method thereof

Abstract

To a memory cell with small in size and high operation speed.SOLUTION: A first memory gate is provided on a substrate. A second memory gate is provided on the substrate. The selector gate is provided between the first memory gate and the second memory gate on the substrate. An internal spacer is provided on a side face of the selector gate. The first memory gate and the second memory gate each include capping layer at a top edge. The capping layers each have a curved side face facing the selector gate. A top edge of the internal spacer is adjacent to bottom edges of the capping layers.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and more particularly, to a semiconductor device applied to a memory cell and a method for manufacturing the same.

Background Art

[0002] With the active development of cutting-edge technologies such as the Internet of Things, edge computing, and artificial intelligence, the ability to process huge amounts of information is required, and memory cells play an indispensable role. When the information to be processed is huge, the necessary memory cells increase accordingly. Even electronic products with only basic functions include millions of memory cells. Therefore, how to improve the characteristics of memory cells, such as simplifying the manufacturing process and reducing the volume, to reduce costs and meet the current requirements for miniaturized electronic products is the goal of the related industries.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] According to one aspect of the present invention, a semiconductor device includes a first memory gate, a second memory gate, a selection gate, and an internal spacer. The first memory gate is disposed on a substrate. The second memory gate is disposed on the substrate. The selection gate is on the substrate and is disposed between the first memory gate and the second memory gate. The internal spacer is disposed on a side surface of the selection gate. The first memory gate and the second memory gate include a capping layer disposed at an upper end, and a side surface of the capping layer facing the selection gate is formed in a curved shape, and an upper end of the internal spacer is adjacent to a lower end of the capping layer.

[0005] According to another aspect of the present invention, a method of manufacturing a semiconductor device includes the following steps. A first gate material stack and a hard mask are sequentially formed on a substrate. A part of the hard mask is removed to form a first recess. A first spacer is formed on a side surface of the hard mask facing the first recess. A part of the first gate material stack not covered by the first spacer and the hard mask is removed to form a second recess. An internal spacer is formed on a side surface of the first gate material stack facing the second recess. A second gate material stack is formed in the first recess and the second recess. The remaining part of the hard mask is removed. Another part of the first gate material stack not covered by the first spacer, a part of the second gate material stack, and a part of the first spacer are removed to form a first memory gate, a second memory gate, and a select gate on the substrate, and the remaining part of the first spacer forms a capping layer of the first memory gate and a capping layer of the second memory gate.

Brief Description of the Drawings

[0006] These and other objects of the present invention will become apparent to those skilled in the art without doubt after reading the following detailed description of the preferred embodiments shown in various figures and drawings.

[0007]

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Embodiments for Carrying Out the Invention

[0008] In the following detailed description of the embodiments, reference is made to the accompanying drawings which illustrate specific embodiments in which a part is formed and in which the present disclosure may be implemented. In this regard, terms indicating directions such as up, down, left, right, front, back, bottom, or top are used with respect to the orientation of the illustrated figures. The elements of the present disclosure can be positioned in several different orientations. Accordingly, the terms indicating directions are used for illustrative purposes and are in no way limiting. Also, in the following embodiments, the same reference numerals or similar reference numerals are used for the same elements or similar elements.

[0009] Hereinafter, the description "the first pattern is formed on the second pattern" may mean that "the first pattern is in direct contact with the second pattern", or that the first pattern is not in direct contact with the second pattern and "there is another pattern between the first pattern and the second pattern".

[0010] Terms such as "first", "second", etc. may be used in this specification to describe various elements, regions, layers, and / or sections, but it should be understood that these elements, regions, layers, and / or sections should not be limited by these terms. These terms may only be used to distinguish one element, region, layer, and / or section from another. Terms such as "first", "second", etc., and other numerical terms, when used in this specification, do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, region, layer, and / or section described below may be referred to as a second element, region, layer, and / or section without departing from the teachings of the embodiments. The terms used in the claims may also not be the same as those used in the specification and may be used according to the order of the elements claimed in the claims.

[0011] Figs. 1 to 10 are schematic cross-sectional views showing the steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. In this embodiment, a case where the semiconductor device 1 (see Fig. 10) is an NMOS transistor will be described as an example. In Fig. 1, a substrate 100 is first provided. The substrate 100 may be a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate. Next, at least one shallow trench isolation (STI) surrounding each active region is formed in the substrate 100. For example, the two insulating structures 110 in Fig. 1 may be the left and right portions of the shallow trench isolation, and the region between the two insulating structures 110 may be an active region. The material of the insulating structure 110 can include a dielectric material such as silicon dioxide. Next, an ion implantation process is performed to form a well region (not shown) in the substrate 100. The dopant of the well region is adjusted according to whether the semiconductor element 1 formed in a subsequent process is applied to an NMOS transistor or a PMOS transistor. In this embodiment, the semiconductor device 1 is, exemplarily, an NMOS transistor. Therefore, the well region is a P-type well region, and the well region may be doped with a P-type dopant such as boron or indium.

[0012] Next, a first gate material stack 20 and a hard mask 30 are sequentially formed on a substrate 100. Forming the first gate material stack 20 includes sequentially forming a gate insulating material layer 21, a charge storage material layer 22, a blocking insulating material layer 23, and a conductive gate material layer 24 on the substrate 100. The material of the gate insulating material layer 21 may include an oxide or a high-k material. The oxide may include, for example, silicon dioxide (SiO2). The high-k material can include, for example, a dielectric material having a dielectric constant greater than 10. The material of the charge storage material layer 22 may include a conductor for storing charges, such as doped polycrystalline silicon, or a non-conductor for capturing charges, such as silicon nitride (SiN), to form a charge trap layer for storing charges. The material of the blocking insulating layer 23 can include an oxide or a high-k material. The oxide may include silicon dioxide. The high-k material can include, for example, a dielectric material having a dielectric constant greater than 10. The material of the conductive gate material layer 24 can include a conductive material such as doped polycrystalline silicon, doped amorphous silicon, a metal, or a metal compound. The material of the hard mask 30 can include, but is not limited to, silicon dioxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), and / or silicon oxynitride (SiON). According to an embodiment of the present invention, the material of the hard mask 30 includes silicon nitride.

[0013] Next, as shown in FIG. 2, a part of the hard mask 30 is removed through a semiconductor process such as a lithography process and an etching process so that a part of the upper surface 20U of the first gate material stack 20 is exposed, and a first recess 50 can be formed.

[0014] Next, as shown in FIG. 3, a first spacer 60 is formed on the side surface 30S of the hard mask 30 facing the first recess 50. For example, a first spacer material layer (not shown) may be formed through a deposition process so as to completely cover the upper surface 30U and the side surface 30S of the hard mask 30, and the upper surface 20U of the first gate material stack 20 exposed from the first recess 50. Thereafter, a part of the first spacer material layer is removed by an etch-back process to form the first spacer 60. The first spacer 60 may be a single material layer or a stack of material layers. The material of the first spacer 60 can include oxides and / or nitrides such as silicon dioxide, silicon nitride, silicon oxynitride, or silicon carbonitride. According to an embodiment of the present invention, the material of the first spacer 60 includes silicon dioxide.

[0015] Next, as shown in FIG. 4, a self-aligned etching process P1 can be performed using the first spacer 60 and the hard mask 30 as an etching mask, and a single etching or a plurality of etchings are performed downward along the first spacer 60 to remove the portion of the first gate material stack 20 not covered by the first spacer 60 and the hard mask 30 to form a second recess 70. As a result, a part of the upper surface 100U of the substrate 100 is exposed, and the second recess 70 communicates with the first recess 50. Since the first spacer 60 and the hard mask 30 are an etching mask for performing the self-aligned etching process P1, there is no need to manufacture an extra etching mask, which is beneficial for simplifying the process.

[0016] Next, as shown in FIG. 5, an internal spacer 500 is formed on a side surface 20S of the first gate material stack 20 facing the second recess 70. Here, the internal spacer 500 includes a first internal spacer layer 510 and a second internal spacer layer 520 from the inside to the outside. For example, a first internal spacer material layer (not shown) and a second internal spacer material layer (not shown) may be sequentially formed by a deposition process so as to completely cover the upper surface 100U of the substrate 100 exposed from the hard mask 30, the first spacer 60, and the second recess 70. Then, a part of the first internal spacer material layer and a part of the second internal spacer material layer are removed by an etching process to form the first internal spacer layer 510 and the second internal spacer layer 520. The first internal spacer layer 510 has an L-shaped cross section, and the second internal spacer layer 520 has an I-shaped cross section. That is, the first internal spacer layer 510 includes a vertical portion 511 and a horizontal extension portion 512. The extending direction of the vertical portion 511 is perpendicular to the extending direction of the horizontal extension portion 512, and the second inner spacer layer 520 does not have a horizontal extension portion. In other embodiments, the first internal spacer layer 510 and the second internal spacer layer 520 having an I-shaped cross section may be sequentially formed through a continuous process of deposition, etching, deposition, and etching. The materials of the first internal spacer layer 510 and the second internal spacer layer 520 can independently include oxides and / or nitrides such as silicon dioxide, silicon nitride, silicon oxynitride, or silicon carbonitride. According to an embodiment of the present invention, the material of the first internal spacer layer 510 includes silicon dioxide, and the material of the second internal spacer layer 520 includes silicon nitride.

[0017] Next, as shown in FIG. 6, a second gate material stack 40 is formed within the first recess 50 and the second recess 70. Forming the second gate material stack 40 may include sequentially forming a gate insulating layer 410 and a conductive gate material layer 42 on the substrate 100. The material of the gate insulating layer 410 may include an oxide, and the material of the conductive gate material layer 42 may include a conductive material such as doped polycrystalline silicon, doped amorphous silicon, a metal, or a metal compound. For example, the gate insulating film 410 is formed by a thermal growth process. In this case, as shown in FIG. 6, the gate insulating layer 410 has a rectangular cross-section. The thermal oxidation process may include, but is not limited to, an ISSG (In-Situ Steam Generation) oxidation process, a wet oxidation process, a dry oxidation process, etc. Thereafter, the conductive gate material layer 42 is formed by a deposition process, and then a planarization process such as a chemical mechanical polishing (CMP) process and / or an etch-back process is performed to remove a part of the conductive gate material layer 42. As a result, the upper surface 42U of the conductive gate material layer 42 is aligned with the upper surface 30U of the hard mask 30. In other embodiments, the gate insulating layer 410 may be formed by a deposition process. In this case, a gate insulating film (not shown) having a U-shaped cross-section is obtained within the first recess 50 and the second recess 70. In FIG. 6, the thickness T2 of the gate insulating layer 410 is the same as the thickness T1 of the gate insulating material layer 21. However, this is merely exemplary and the present invention is not limited thereto.

[0018] Next, as shown in FIG. 7, by semiconductor processes such as an etching process and a cleaning process, the remaining portion of the hard mask 30 can be removed to expose the portion of the first gate material stack 20 that is not covered by the first spacer 60 and the second gate material stack 40.

[0019] Next, as shown in FIG. 8, a self-aligned etching process P2 may be performed using the first spacer 60 as an etching mask. In this process, a single etching or multiple etchings may be performed downward along the first spacer 60 to remove a portion of the first gate material stack 20 that is not covered by the first spacer 60. During the self-aligned etching process P2, a portion of the second gate material stack 40 (here, a portion of the conductive gate material layer 42) and a portion of the first spacer 60 are also removed, forming a first memory gate 201, a second memory gate 202, and a select gate 400 on the substrate 100. The remaining portions of the first spacer 60 form the capping layer 250 of the first memory gate 201 and the capping layer 250 of the second memory gate 202. Each of the capping layers 250 has a curved side surface 250S facing the select gate 400. The remaining portions of the conductive gate material layer 24, the blocking insulating material layer 23, the charge storage material layer 22, and the gate insulating material layer 21 form the conductive gate layer 240, the blocking insulating layer 230, the charge storage layer 220, and the gate insulating layer 210 of the first memory gate 201 and the second memory gate 202. The remaining portion of the conductive gate material layer 42 forms the conductive gate layer 420 of the select gate 400.

[0020] When compared with the first spacer 60 of FIG. 7, the height H3 of the capping layer 250 is lower than the height H1 of the first spacer 60 and has a flat upper surface 250U. When compared with the conductive gate material layer 42 of FIG. 7, the height H4 of the conductive gate material layer 420 is lower than the height H2 of the conductive gate material layer 42 and does not completely cover the curved side surface 250S of the capping layer 250.

[0021] Next, as shown in FIG. 9, an outer spacer 600 is formed on the outer surface 201S of the first memory gate 201 and the outer surface 202S of the second memory gate 202, and the upper end 600T of the outer spacer 600 is aligned with the upper surface 250U of the capping layer 250. Also, the external spacer 600 includes a first external spacer layer 610, a second external spacer layer 620, and a third external spacer layer 630 from the inside to the outside. For example, a first external spacer material layer (not shown) and a second external spacer material layer (not shown) are sequentially formed through a deposition process so as to completely cover the exposed upper surfaces 100U of the first memory gate 201, the second memory gate 202, the select gate 400, and the substrate 100, and then a part of the first external spacer material layer and the second external spacer material layer is removed through an etching process to form the first external spacer layer 610 and the second external spacer layer 620. Next, the third outer spacer layer 630 is formed by a semiconductor process such as a deposition process and an etching process. The first outer spacer layer 610 has an L-shaped cross section, the second outer spacer layer 620 has an I-shaped cross section, and the third outer spacer layer 630 has an I-shaped cross section. That is, the first external spacer layer 610 includes a vertical portion 611 and a horizontal extension portion 612. The extending direction of the vertical portion 611 is perpendicular to the extending direction of the horizontal extension portion 612, and the second outer spacer layer 620 and the third outer spacer layer 630 do not have a horizontal extension portion. The materials of the first outer spacer layer 610, the second outer spacer layer 620, and the third outer spacer layer 630 can independently include oxides and / or nitrides such as silicon dioxide, silicon nitride, silicon oxynitride, or silicon carbonitride. According to an embodiment of the present disclosure, the material of the first outer spacer layer 610 includes silicon dioxide, the material of the second outer spacer layer 620 includes silicon nitride, and the material of the third outer spacer layer 630 includes silicon dioxide. In other embodiments, the first outer spacer layer 610, the second outer spacer layer 620, and the third outer spacer layer 630 having an I-shaped cross section may be sequentially formed by a continuous process of deposition, etching, deposition, etching, deposition, and etching.

[0022] Next, as shown in FIG. 10, an ion implantation process P3 can be executed to form two doped regions 710 and 720 in the substrate 100. The doped region 710 is adjacent to the first memory gate 201, and the other doped region 720 is adjacent to the second memory gate 202. The conductivity types of the two doped regions 710 and 720 are the same as each other and different from the conductivity type of the well region. In this embodiment, the well region is a P-type well region, and the two doped regions 710 and 720 are N-type doped regions. Therefore, the ion implantation process P3 is a process of implanting an N-type dopant into the substrate 100. For example, the N-type dopant may include, but is not limited to, arsenic, phosphorus, etc. Thereby, the manufacturing of the semiconductor device 1 is completed.

[0023] The foregoing film layers such as the gate insulating material layer 21, the charge storage material layer 22, the blocking insulating material layer 23, the conductive gate material layer 24, the hard mask 30, the first spacer material layer, the first inner spacer material layer, the second inner spacer material layer, the gate insulating layer 410, the conductive gate material layer 42, the first outer spacer material layer, the second outer spacer material layer, and the third outer spacer material layer can be formed by any suitable method. For example, the method may be, but is not limited to, molecular beam epitaxy (MBE), chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), and atomic layer deposition (ALD).

[0024] Referring to FIG. 10, FIG. 10 is a schematic cross-sectional view of a semiconductor device 1 according to an embodiment of the present disclosure. The semiconductor device 1 includes a first memory gate 201, a second memory gate 202, a select gate 400, and an internal spacer 500. The first memory gate 201 is disposed on a substrate 100, the second memory gate 202 is disposed on the substrate 100, and the select gate 400 is on the substrate 100 and disposed between the first memory gate 201 and the second memory gate 202. The internal spacer 500 is disposed on a side surface 400S of the select gate 400. Each of the first memory gate 201 and the second memory gate 202 includes a capping layer 250 disposed at its upper end (without label). Each of the capping layers 250 has a curved side surface 250S facing the select gate 400, and the upper end 500T of the internal spacer 500 is adjacent to the lower end 250B of each of the capping layers 250. The above-mentioned "the upper end 500T of the internal spacer 500 is adjacent to the lower end 250B of the capping film 250" means that the upper end 500T of the internal spacer 500 is slightly higher than the lower end 250B of the capping film 250 that it directly contacts, or the vertical distance between the upper end 500T of the internal spacer 500 and the lower end B of the capping film 250 that it directly contacts is smaller than the vertical distance between the upper end 500T of the internal spacer 500 and the upper surface 250U of the capping film 250 that it directly contacts.

[0025] Specifically, the first memory gate 201 includes a gate insulating film 210, a charge storage layer 220, a blocking insulating film 230, a conductive gate film 240, and a capping film 25 sequentially disposed on the substrate 100 from bottom to top. The second memory gate 202 includes a gate insulating film 210, a charge storage layer 220, a blocking insulating film 230, a conductive gate film 240, and a capping film 250 sequentially disposed on the substrate 100 from bottom to top. Each of the capping layers 250 may have a side surface 250F perpendicular to the opposite side of the curved side surface 250S. That is, the capping layer 250 has an asymmetric cross-sectional shape.

[0026] The materials of the gate insulating layer 210, charge storage layer 220, blocking insulating layer 230, conductive gate layer 240, and capping layer 250 may each be the same as the gate insulating material layer 21, charge storage material layer 22, blocking insulating material layer 23, conductive gate material layer 24, and the first spacer 60, which will not be repeated here. The first memory gate 201 and the second memory gate 202 are charge trap type memory cells. According to an embodiment of the present invention, the materials of the gate insulating film 210, charge storage film 220, and blocking insulating film 230 can be an oxide, a nitride, and an oxide, respectively. That is, the first memory gate 201 and the second memory gate 202 can be ONO type memory cells. The operating principle of the ONO type memory cell is well known in the art and will not be repeated herein.

[0027] The select gate 400 includes a gate insulating film 410 and a conductive gate film 420 sequentially arranged from bottom to top on the substrate 100. The material of the conductive gate layer 420 may be the same as the material of the conductive gate material layer 42, which will not be repeated here. The upper surface 400U of the select gate 400 is lower than the upper surface 250U of the cap layer 250 and is between the upper surface 250U and the lower end 250B of the cap layer 250. The upper surface 400U of the select gate 400 is higher than the upper end 500T of the internal spacer 500, and the upper end 500T of the internal spacer 500 is higher than the upper surface 240U of the conductive gate layer 240. Thereby, the influence of the upper corner of the conductive gate layer 240 on the select gate 400 can be effectively isolated.

[0028] The semiconductor device 1 may further include an outer spacer 600. The outer spacer 600 is disposed on the outer surface 201S (see FIG. 9) of the first memory gate 201 and the outer surface 202S (see FIG. 9) of the second memory gate 202. The upper end 600T of the external spacer 600 is aligned with the upper surface 250U of the capping layer 250. Each of the inner spacer 500 and the outer spacer 600 may have a multilayer structure. Here, the inner spacer 500 has a two-layer structure and includes a first inner spacer layer 510 and a second inner spacer layer 520 from the inside to the outside. The outer spacer 600 has a three-layer structure and includes a first outer spacer layer 610, a second outer spacer layer 620, and a third outer spacer layer 630 from the inside to the outside. That is, the number of layers of the outer spacer 600 is greater than the number of layers of the inner spacer 500. For details of the inner spacer 500 and the outer spacer 600, reference may be made to the above description and will not be repeated here.

[0029] The semiconductor device 1 may further include two doped regions 710 and 720 disposed in the substrate 100. The doped region 710 is disposed adjacent to the first memory gate 201, and the other doped region 720 is disposed adjacent to the second memory gate 202. As described above, the semiconductor device 1 is exemplarily an NMOS transistor. The well region in the substrate 100 is a P-type well region, and the two doped regions 710 and 720 are N-type doped regions. The two doped regions 710 and 720 may be configured as the source line and the bit line of the first memory gate 201 and the second memory gate 202, respectively. In the semiconductor device 1, the first memory gate 201 and the second memory gate 202 share a select gate 400 to form a dual-bit memory cell, which is beneficial for increasing the memory density and reducing the volume. The first memory gate 201 and the second memory gate 202 are erased, for example, through Fowler-Nordheim (F-N) tunneling or hot hole injection, and programmed by source-side injection.

[0030] Compared with the prior art, the method for manufacturing a semiconductor device of the present disclosure can simultaneously form a first memory gate and a second memory gate on both sides of a select gate. As a result, the first memory gate and the second memory gate can share the select gate. Compared with the configuration of one memory gate using one select gate, the present disclosure is beneficial for increasing the memory density and reducing the volume. Further, in the method for manufacturing a semiconductor device of the present invention, the first spacer is used as part of an etching mask when forming a second recess that defines the select gate, and is also used as an etching mask when defining the first memory gate and the second memory gate. The remaining portion of the first spacer can be used as part of the first memory gate and as part of the second memory gate. Therefore, the material constituting the semiconductor device can be used as an etching mask during the process, and there is no need to separately form an etching mask for forming the second recess that defines the select gate, nor is there a need to separately form an etching mask for defining the first memory gate and the second memory gate. Thus, it is beneficial to simplify the process and reduce the manufacturing cost. As described above, the semiconductor device of the present invention has the advantages of improving the memory density, reducing the volume, and reducing the manufacturing cost.

[0031] Those skilled in the art will readily recognize that numerous modifications and changes can be made to the apparatus and methods while retaining the teachings of the present invention. Accordingly, the foregoing disclosure should be construed as being limited only by the boundaries of the appended claims.

Claims

1. A semiconductor device comprising: a first memory gate disposed on a substrate; a second memory gate disposed on the substrate; a select gate disposed on the substrate between the first memory gate and the second memory gate; and an inner spacer disposed on a side of the select gate, wherein each of the first memory gate and the second memory gate includes a capping layer disposed at an upper end thereof, each of the capping layers having a curved side facing the select gate, and an upper end of the inner spacer adjacent to a lower end of each of the capping layers.

2. 2. The semiconductor device of claim 1, further comprising an outer spacer disposed on an outer surface of the first memory gate and on an outer surface of the second memory gate, an upper end of the outer spacer being aligned with an upper surface of each of the capping layers.

3. 3. The semiconductor device according to claim 2, wherein each of said inner spacer and said outer spacer has a multi-layer structure, and the number of layers of said outer spacer is greater than the number of layers of said inner spacer.

4. 2. The semiconductor device of claim 1, further comprising: two doped regions disposed in the substrate, one of the doped regions adjacent to the first memory gate and another of the doped regions adjacent to the second memory gate.

5. 2. The semiconductor device according to claim 1, wherein each of the first memory gate and the second memory gate further includes a gate insulating layer, a charge storage layer, a blocking insulating layer, and a conductive gate layer, which are sequentially disposed on the substrate.

6. 2. The semiconductor device of claim 1, wherein the select gate comprises a gate insulating layer and a conductive gate layer disposed in sequence on the substrate.

7. The semiconductor device of claim 1 , wherein each of said capping layers has an asymmetric cross-sectional shape.

8. The semiconductor device of claim 1 , wherein each of said capping layers has a vertical side opposite said curved side.

9. The semiconductor device of claim 1 , wherein a top surface of said select gate is lower than a top surface of each of said capping layers.

10. The semiconductor device according to claim 1 , wherein a top surface of said select gate is higher than said top end of said inner spacer.

11. 1. A method for manufacturing a semiconductor device, the method comprising: sequentially forming a first gate material stack and a hard mask over a substrate; removing a portion of the hard mask to form a first recess; forming a first spacer on a side of the hard mask facing the first recess; removing portions of the first gate material stack not covered by the first spacers and the hard mask to form a second recess; forming an inner spacer on a side of the first gate material stack facing the second recess; forming a second gate material stack in the first recess and in the second recess; removing remaining portions of the hard mask; and and removing another portion of the first gate material stack not covered by the first spacer, a portion of the second gate material stack, and a portion of the first spacer to form a first memory gate, a second memory gate, and a select gate on the substrate, wherein a remaining portion of the first spacer forms a capping layer of the first memory gate and a capping layer of the second memory gate.

12. 12. The method of claim 11, further comprising forming outer spacers on an outer surface of the first memory gate and on an outer surface of the second memory gate, wherein upper ends of the outer spacers are aligned with a top surface of each of the capping layers.

13. The method of claim 12 , wherein the inner spacer and the outer spacer each have a multi-layer structure, the outer spacer having a greater number of layers than the inner spacer.

14. 12. The method of claim 11, further comprising forming two doped regions in the substrate, one of the doped regions adjacent to the first memory gate and another of the doped regions adjacent to the second memory gate.

15. 12. The method of claim 11, wherein forming the first gate material stack comprises sequentially forming a gate insulating material layer, a charge storage material layer, a blocking insulating material layer, and a conductive gate material layer over the substrate.

16. 12. The method of claim 11, wherein forming the second gate material stack comprises sequentially forming a gate insulating material layer and a conductive gate material layer over the substrate.

17. The method of claim 11 , wherein each of the capping layers has a curved side facing the select gate.

18. The method of claim 11 , wherein the inner spacers are disposed on sides of the select gate, and a top edge of the inner spacers is adjacent a bottom edge of each of the capping layers.

19. 12. The method of claim 11, wherein removing portions of the first gate material stack not covered by the first spacers and the hard mask is performed by a self-aligned etching process using the first spacers and the hard mask as an etch mask.

20. 12. The method of claim 11, wherein removing another portion of the first gate material stack not covered by the first spacer is performed by a self-aligned etching process using the first spacer as an etch mask.

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