Solid-state imaging element

Abstract

To provide a solid-state imaging element that can suppress the increase in man-hours and complexity involved in the development of a solid-state imaging element while preventing a decrease in spatial resolution.SOLUTION: A solid-state imaging element 100 includes a plurality of pixel blocks 200. Each of the pixel blocks 200 includes a plurality of SPAD pixels 210 for imaging. At least one SPAD pixel 210 of the pixel block 200 has a detection function for detecting a change in light incident on the SPAD pixel 210.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device.

Background Art

[0002] In recent years, solid-state imaging devices (image sensors) using single-photon avalanche diodes (SPADs) have attracted attention. A SPAD utilizes avalanche amplification in which a large number of carriers are generated when one photon is incident on a PN junction to which a reverse bias exceeding the breakdown voltage is applied in an avalanche photodiode (hereinafter also referred to as "APD"). A solid-state imaging device using a SPAD includes an APD in each of a plurality of pixels arranged in a row direction and a column direction. The solid-state imaging device using a SPAD images by counting pulses generated by carriers due to avalanche amplification in these APDs.

[0003] As a solid-state imaging device having such a structure, for example, a solid-state imaging device shown in Patent Document 1 below is known. This solid-state imaging device has a pixel array unit composed of a plurality of pixel blocks, and each pixel block of the pixel array unit includes a detection pixel and a plurality of counting pixels. The detection pixel detects a change in incident light, and the counting pixel counts incident photons by an APD. More specifically, the detection pixel includes a photodiode (PD) and notifies an on event and an off event. The on event indicates that the change amount of incident light exceeds the upper limit value, and the off event indicates that the change amount of incident light is less than the lower limit value.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the solid-state image sensor of Patent Document 1, since photons cannot be counted in the detection pixels, there is a problem that the spatial resolution in imaging decreases. Further, since the SPAD and the PD have different device configurations and drive voltages, in the development of a solid-state image sensor, device development and circuit development specialized for each are required. Therefore, there is also a problem that the man-hours and complexity in the development of the solid-state image sensor may increase.

[0006] The present invention has been made to solve the above-described problems. Therefore, a main object of the present invention is to provide a solid-state image sensor capable of suppressing a decrease in spatial resolution in imaging and suppressing an increase in man-hours and complexity in the development of the solid-state image sensor.

Means for Solving the Problems

[0007] The above object of the present invention is achieved by the following.

[0008] (1) A solid-state image sensor having a plurality of pixel blocks, wherein each of the pixel blocks has a plurality of SPAD pixels for imaging, and at least one SPAD pixel of the pixel blocks has a detection function of detecting a change in light incident on the SPAD pixel. A solid-state image sensor characterized by that.

[0009] (2) The at least one SPAD pixel is a detection shared pixel that also has a detection function of detecting a change in light incident on the pixel block in addition to a counting function of counting photons incident on the SPAD pixel. The detection shared pixel has a counter that counts photons incident on the detection shared pixel and a latch that holds a count value of photons counted one frame before by the counter. The detection function compares the count value in the previous frame and the count value in the current frame counted by the counter to detect the change in light. The solid-state image sensor according to (1) above.

[0010] (3) The detection shared pixel has an exposure control unit, and when the exposure control unit detects a change in predetermined light by the detection function, the exposure control unit enables the counting function of other SPAD pixels in the pixel block having the detection shared pixel. The solid-state imaging device according to (2) above.

[0011] (4) Each SPAD pixel excluding the detection shared pixel in the pixel block has a gate unit, and when the exposure control unit detects a change in predetermined light by the detection function, the exposure control unit controls the gate unit to enable the counting function of the corresponding each SPAD pixel. The solid-state imaging device according to (3) above.

[0012] (5) The detection function is shared by at least two SPAD pixels in the pixel block. The solid-state imaging device according to any one of (1) to (2) above.

[0013] (6) The detection function sets an upper limit value and a lower limit value of a variation range with respect to the count value in the previous frame, and compares the count value in the current frame with the upper limit value and the lower limit value to detect a change in light. The solid-state imaging device according to any one of (2) to (4) above.

[0014] (7) The detection function compares the count value in the previous frame and the count value in the current frame using a value obtained by bit compression to detect a change in light. The solid-state imaging device according to any one of (2) to (4) above.

[0015] (8) The solid-state imaging device according to any one of (2) to (4), (6) above, having a first wafer on which the counting function is formed and a second wafer on which the detection function is formed and which is stacked on the first wafer.

Advantages of the Invention

[0016] According to the present invention, at least one SPAD pixel of a pixel block has a detection function of detecting a change in light incident on the SPAD pixel. That is, at least one SPAD pixel has both a counting function and a detection function. Therefore, it is possible to suppress an increase in man-hours and complexity in the development of a solid-state imaging device while preventing a decrease in spatial resolution.

Brief Description of the Drawings

[0017]

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Embodiments for Carrying Out the Invention

[0018] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals refer to the same components, and on the drawings, the sizes of the respective components are represented at ratios different from the actual state for the sake of clarity and convenience of explanation. On the other hand, the embodiments described below are merely exemplary, and various modifications are possible from such embodiments.

[0019] In the following, the places described as "upper part" or "above" may include not only those in direct contact and directly above but also those above without contact.

[0020] Components expressed in the singular include a plurality of components unless they clearly have different meanings in the context. Also, when a certain part "includes" or "has" a certain component, it means that, unless there is a special contrary description, it does not exclude other components and may further include other components.

[0021] Also, the use of the term "the foregoing" and similar directive terms applies to both the singular and the plural.

[0022] For the steps that make up the method, if the order is clearly described, or if there is no description to the contrary, the steps are executed in an appropriate order. It is not necessarily limited to the order of description of the above steps. The use of all examples or exemplary terms (e.g., etc.) is merely for explaining the technical idea, and as long as it is not limited by the claims, the scope is not limited by the above examples or exemplary terms.

[0023] (First Embodiment) <Configuration Example of Solid-State Image Sensor> FIG. 1 is a schematic diagram illustrating the configuration of a solid-state image sensor according to the first embodiment. Further, FIG. 2 is a schematic diagram illustrating the configuration of a pixel block included in the pixel array unit shown in FIG. 1.

[0024] As shown in FIG. 1, the solid-state image sensor 100 includes a driving unit 110, a pixel array unit 120, and an image processing unit 140.

[0025] The driving unit 110 inputs or generates various signals such as a clock (CLK) signal, a reset (LRST, CRST) signal, and a control signal (Psig, Dsig) (see FIGS. 3 and 4). The driving unit 110 supplies the above various signals to the pixel array unit 120 to drive the pixel array unit 120. Details of the generation timing of the reset signal and the control signal will be described later.

[0026] The pixel array unit 120 includes a plurality of pixel blocks 200 arranged in a two-dimensional lattice (row direction and column direction) when viewed in plan from a direction perpendicular to the substrate surface of the solid-state image sensor 100. As shown in FIG. 2, each pixel block 200 includes a plurality of SPAD pixels 210 arranged in a two-dimensional lattice. Each pixel block 200 detects a change in incident light (hereinafter also referred to as an "event") and outputs it as a detection signal. Further, each pixel block 200 counts the photons incident on each SPAD pixel 210 and outputs it as a pixel signal.

[0027] The image processing unit 140 performs predetermined image processing on the detection signals and pixel signals from the pixel array unit 120 and outputs the processing results. The predetermined image processing is not particularly limited, and can be, for example, pattern recognition processing, image compression processing, etc.

[0028] The pixel block 200 has a plurality (for example, M pieces) of SPAD pixels 210 for imaging. Here, M is a natural number of 2 or more. At least one (for example, m pieces) of the M SPAD pixels has a detection function in addition to the counting function. Here, m is a natural number of 1 or more and less than M. The counting function is a function of counting photons incident on the SPAD pixel, and the detection function is a function of detecting a change in light incident on the SPAD pixel.

[0029] That is, all (M pieces) of the M SPAD pixels 210 have a counting function, and m of these SPAD pixels 210 also have a detection function. On the other hand, (M - m) SPAD pixels 210 do not have a detection function. In this specification, the SPAD pixel 210 having both a counting function and a detection function is called a "detection-sharing pixel". In FIG. 2, the SPAD pixel 210 that is a detection-sharing pixel is denoted as "SPAD DVS", and the SPAD pixel 210 other than the detection-sharing pixel is denoted as "SPAD". Note that DVS is an abbreviation of Dynamic Vision Sensor, and in this specification, it means an additional detection function added to the SPAD pixel.

[0030] For example, each pixel block 200 has 16 SPAD pixels 210 arranged in 4 rows and 4 columns. Among these 16 SPAD pixels 210, one SPAD pixel 210 can be a detection-sharing pixel. The detection-sharing pixel is arranged at a specific position within the pixel block 200. In this embodiment, for example, assuming that the relative coordinates in the orthogonal coordinate system within the pixel block 200 are (x, y), the detection-sharing pixel can be arranged at the coordinates (0, 0) (the upper left corner). Here, x and y are positive numbers. The position of the detection-sharing pixel is not limited to the upper left corner, and can be other locations, for example, the central part of the pixel block 200.

[0031] Note that the number of SPAD pixels 210 included in each pixel block 200 is not limited to 4 rows × 4 columns = 16. For example, the number of SPAD pixels 210 may be 2 rows × 2 columns = 4, or 3 rows × 3 columns = 9.

[0032] The detection shared pixel detects an event by determining whether a change in the measured light amount of incident light (e.g., luminance, light amount, luminous intensity, etc.) is equal to or greater than a predetermined threshold value. The predetermined threshold value can be experimentally obtained and set in advance, for example. In the present embodiment, the value of the measured light amount of incident light in the previous frame is compared with (the difference is taken from) the value of the measured light amount of incident light in the current frame. Thereby, it is determined whether the change (difference) in the measured light amount of incident light is equal to or greater than the predetermined threshold value.

[0033] The detection shared pixel counts photons incident on the detection shared pixel by a counting function. Further, when the detection shared pixel detects a predetermined change in the incident light by a detection function, it controls the driving of SPAD pixels 210 other than the detection shared pixel. More specifically, the detection shared pixel controls the start and end of exposure (counting of incident photons) in each SPAD pixel 210. Details of the method for controlling photon counting in the SPAD pixel 210 will be described later.

[0034] <Configuration example of pixel block 200> FIG. 3 is a block diagram illustrating the functions of the SPAD pixel 210 of the pixel block 200 shown in FIG. 2. As described above, M SPAD pixels 210 are arranged in each pixel block 200, and m of the M SPAD pixels 210 have a detection function. Hereinafter, for convenience of explanation, the case where m is 1 will be exemplified and described. FIG. 3 illustrates one detection shared pixel and one SPAD pixel 210 adjacent to the detection shared pixel (corresponding to the region indicated by the thick line in FIG. 2).

[0035] [Counting function of detection shared pixel] As shown in FIG. 3, the counting function of the detection-sharing pixel can be configured by a circuit including, for example, an avalanche photodiode 1 (hereinafter also referred to as "APD1") and an N-bit first counter (Counter1). APD1 operates in Geiger mode when a reverse bias exceeding the breakdown voltage is applied to the PN junction, and outputs a pulse signal in response to the detection of photons. The first counter counts the pulse signal from APD1 in synchronization with the clock input CLK. Thereby, the photons incident on the detection-sharing pixel are counted. The first counter is reset by the CRST signal.

[0036] [Detection function of detection-sharing pixel] The detection function of the detection-sharing pixel can be configured by a circuit including a first latch (P-Lat), a differential circuit (D-Diff), and an exposure control circuit (exposure control unit).

[0037] The first latch is an N-bit latch circuit, and holds the count value of the photons counted by the first counter in synchronization with the Psig signal.

[0038] The differential circuit can be further configured by a circuit including a differential module (Diff), a second latch (Lat_UP), and a third latch (Lat_DN). In the differential module, the differential circuit compares (takes the difference between) the count value counted and held in the latch in the previous frame and the count value in the current frame.

[0039] Also, the difference circuit holds the comparison result between the count value of the previous frame and the count value of the current frame. The second latch activates (enables) the UP signal when the count value of the current frame is greater than the count value of the previous frame and the difference between the two count values is greater than a predetermined threshold. The second latch holds the active state of the UP signal. Further, the third latch activates (enables) the DN signal when the count value of the previous frame is greater than the count value of the current frame and the difference between the two count values is greater than a predetermined threshold. The third latch holds the active state of the DN signal. The difference circuit is reset by the LRST signal.

[0040] The exposure control circuit has an enable signal output section (not shown). The enable signal output section generates the Sgate signal based on the UP signal from the second latch, the DN signal from the third latch, and the Dsig signal. Specifically, the enable signal output section activates the Sgate signal in synchronization with the Dsig signal when the UP signal or the DN signal is active.

[0041] Also, the exposure control circuit may further have an exposure timer. The exposure timer measures the time corresponding to the exposure period from the start of each frame. The exposure period is set in advance by the user. The exposure timer generates an exposure control signal that is active until the time corresponding to the exposure period has elapsed from the start of each frame.

[0042] [Counting Function of SPAD Pixel 210] The counting function of the SPAD pixel 210 can be configured by a circuit including, for example, an input gate (gate section) IG, an avalanche photodiode APD2 (hereinafter also referred to as "APD2"), and an N-bit second counter (Counter2). The APD2 operates in Geiger mode when a reverse bias exceeding the breakdown voltage is applied to the PN junction and outputs a pulse signal in response to the detection of a photon. The second counter counts the pulse signals from the APD2 in synchronization with the CLKs signal. Thereby, the photons incident on the SPAD pixel 210 are counted. Also, the second counter is reset by the CRSTs signal. The CLKs signal and the CRSTs signal are activated by the Sgate signal generated by the detection function of the detection-sharing pixel and input to the input gate IG. That is, the second counter is enabled by the Sgate signal.

[0043] Although the counting function of one SPAD pixel 210 adjacent to the detection-sharing pixel has been exemplified and described, the counting functions of the other SPAD pixels 210 in the pixel block 200 are the same, so the description is omitted.

[0044] Also, in the above example, the case where the pixel block 200 has one detection-sharing pixel (when m = 1) has been mainly described, but the case where the pixel block 200 has a plurality of detection-sharing pixels (when m is 2 or more) can be configured in the same way.

[0045] [Other Configuration Examples of Pixel Block] FIG. 4 is a schematic diagram illustrating a configuration in which the pixel block 200 shown in FIG. 2 has two detection-sharing pixels. In the pixel block 200, in addition to the first detection-sharing pixel at the relative coordinates (0, 0), a second detection-sharing pixel can be arranged at (xmax, ymax). Here, xmax and ymax are the maximum values of the x and y coordinates in the pixel block 200. In this case, the target of the SPAD pixels 210 to be exposure-controlled by the first detection-sharing pixel can be configured, for example, as the upper range obtained by dividing the pixel block 200 along the dashed-dotted line in the figure. Also, the target of the SPAD pixels 210 to be exposure-controlled by the second detection-sharing pixel can be configured, for example, as the lower range obtained by the above division.

[0046] In this way, since the pixel block 200 has a plurality of detection-sharing pixels, the position of the detection-sharing pixel and the position of the SPAD pixels 210 to be exposure-controlled can be brought closer within the pixel block 200. Thereby, the detection accuracy of events for the SPAD pixels 210 to be exposure-controlled by the detection-sharing pixel can be improved. Also, by arranging the detection-sharing pixel at the central portion in each target range of the pixel block 200, it can be brought closer to the SPAD pixels 210 to be exposure-controlled.

[0047] FIG. 5 is a schematic diagram illustrating a configuration in which the pixel block 200 shown in FIG. 2 has four detection-sharing pixels. In the pixel block 200, in addition to the first detection-sharing pixel at the relative coordinates (0, 0), the second to fourth detection-sharing pixels can be arranged at (x1, 0), (0, y1), and (x1, y1), respectively. In this case, the target of the SPAD pixel 210 whose exposure is controlled by the first detection-sharing pixel can be configured, for example, as the upper left range obtained by dividing the pixel block 200 along the dashed-dotted line in the figure. Also, the target of the SPAD pixel 210 whose exposure is controlled by the second detection-sharing pixel can be configured, for example, as the upper right range obtained by the above division. Also, the target of the SPAD pixel 210 whose exposure is controlled by the third detection-sharing pixel can be configured as the lower left range obtained by the above division. Also, the target of the SPAD pixel 210 whose exposure is controlled by the fourth detection-sharing pixel can be configured as the lower right range obtained by the above division. Also, similar to the example of FIG. 4, by arranging the detection-sharing pixel at the center in each target range of the pixel block 200, it is possible to bring it closer to the SPAD pixel 210 to be exposure-controlled.

[0048] In this way, by further increasing the number of detection-sharing pixels in the pixel block 200, it is possible to bring the position of the detection-sharing pixel closer to the position of the SPAD pixel 210 to be exposure-controlled within the pixel block 200. Thereby, the detection accuracy of the event with respect to the SPAD pixel 210 to be exposure-controlled by the detection-sharing pixel can be further improved.

[0049] <An example of the operation timing of the SPAD pixel 210> FIG. 6 is a timing chart illustrating the operation timing of the SPAD pixel 210. The operation timing in the first to fourth frames is illustrated in the figure. After the initial period is executed, the first to fourth frames are executed in order. Each of the first to fourth frames consists of an exposure period, a readout period, and a detection period.

[0050] [Operation in the initial period] First, in the initial period, the driving unit 110 outputs the (1) LRST signal, (2) Dsig signal, (3) Psig signal, and (4) CRST signal as pulse signals in this order, synchronized with the CLK signal. The second latch and the third latch of the detection shared pixel are reset by the LRST signal. Also, the first counter is reset by the CRST signal. The first latch holds the initial value 0 (zero) of the first counter by the Psig signal.

[0051] [Operation in the First Frame] Next, in the exposure period of the first frame following the initial period, the detection shared pixel counts the photons incident on the detection shared pixel in synchronization with the CLK signal by the first counter (Counter1). The first counter outputs a count value. The driving unit 110 supplies the detection shared pixel with the CLK signal having a number of pulses corresponding to a preset exposure period. Thereby, the first counter counts the photons during the exposure period. On the other hand, since the Sgate signal is inactive, the CLKs signal and the CRSTs signal of the other SPAD pixels 210 included in the pixel block 200 are not activated, and the second counter does not count the photons incident on the SPAD pixels 210.

[0052] Next, in the readout period following the exposure period, the first counter reads out the determined count value num1.

[0053] Next, in the detection period following the readout period, the driving unit 110 outputs the (1) LRST signal, (2) Dsig signal, (3) Psig signal, and (4) CRST signal as pulse signals synchronized with the CLK signal in this order. The second latch and the third latch of the detection shared pixel are reset by the LRST signal. Subsequently, the differential circuit compares the count value in the previous frame (one frame before) with the count value in the current frame in synchronization with Dsig, and holds the state in the second latch and the third latch. Here, the first latch holds the count value num1 of the first counter by the subsequent Psig signal, but at the time of comparison by the differential circuit, the initial value 0 (zero) or a predetermined value of the first counter is held in the first latch. In the example of FIG. 6, it is assumed that a predetermined value other than zero is held as the initial value. As a result of the comparison by the differential circuit, when num1 is less than a predetermined threshold value, the UP signal and the DN signal become inactive, and the Sgate signal also transitions while remaining inactive. Subsequently, the first latch holds the count value num1 of the first counter by the Psig signal. Then, the first counter is reset by the CRST signal. Incidentally, when the initial value is zero and the Sgate signal becomes active in the detection period of the first frame, other SPAD pixels 210 (CLKs signal, CRSTs signal) included in the pixel block 200 can be driven from the second frame (not shown).

[0054] [Operation in the Second Frame] Next, in the exposure period of the second frame, the detection shared pixel counts the photons incident on the detection shared pixel in synchronization with the CLK signal by the first counter. The first counter outputs the count value. The driving unit 110 supplies the detection shared pixel with the CLK signal having a number of pulses corresponding to a preset exposure period. Thereby, the photons are counted by the first counter during the exposure period. On the other hand, since the Sgate signal is inactive, the CLKs signal and the CRSTs signal of the other SPAD pixels 210 included in the pixel block 200 are not enabled, and the second counter does not count the photons incident on the SPAD pixel 210.

[0055] Next, in the readout period following the exposure period, the first counter reads out the determined count value num2.

[0056] Next, in the detection period following the readout period, the driving unit 110 outputs (1) the LRST signal, (2) the Dsig signal, (3) the Psig signal, and (4) the CRST signal as pulse signals in synchronization with the CLK signal in this order. The second latch and the third latch of the detection shared pixel are reset by the LRST signal. Subsequently, the differential circuit compares the count value in the previous frame with the count value in the current frame in synchronization with Dsig, and holds the state in the second latch and the third latch. Here, the first latch holds the count value num2 of the first counter by the subsequent Psig signal, but the count value num1 in the previous frame is held in the first latch at the time of comparison by the differential circuit. Here, it is assumed that num1 < num2. As in the example shown in FIG. 6, when (num2 - num1) is equal to or greater than a predetermined threshold, the UP signal becomes active as a result of the comparison by the differential circuit, so the Sgate signal becomes active. Subsequently, the first latch holds the count value num2 of the first counter by the Psig signal. Then, the first counter is reset by the CRST signal.

[0057] [Operation in the Third Frame] Next, in the exposure period of the third frame, the detection shared pixel counts the photons incident on the detection shared pixel in synchronization with the CLK signal by the first counter. The first counter outputs a count value. The driving unit 110 supplies the detection shared pixel with the CLK signal having a number of pulses corresponding to a preset exposure period. Thereby, the photons are counted by the first counter during the exposure period. As a result of the comparison in the second frame, since the Sgate signal is active, the CLKs signal and the CRSTs signal of the other SPAD pixels 210 included in the pixel block 200 become valid, and the SPAD pixel 210 counts the photons incident on the SPAD pixel 210 in synchronization with the CLKs signal by the second counter. The second counter outputs a count value.

[0058] Next, in the readout period following the exposure period, the first counter reads out the determined count value num3.

[0059] Next, in the detection period following the readout period, the driving unit 110 outputs (1) the LRST signal, (2) the Dsig signal, (3) the Psig signal, and (4) the CRST signal as pulse signals in synchronization with the CLK signal in this order. The second latch and the third latch of the detection shared pixel are reset by the LRST signal. Subsequently, the differential circuit synchronizes with Dsig and compares the count value in the previous frame with the count value in the current frame, and holds the state in the second latch and the third latch. Here, the first latch holds the count value num3 of the first counter by the subsequent Psig signal, but the count value num2 in the previous frame is held in the first latch at the time of comparison by the differential circuit. Here, it is assumed that num2 < num3. As in the example shown in FIG. 6, when (num3 - num2) is equal to or greater than a predetermined threshold, as a result of the comparison by the differential circuit, the UP signal becomes active, so the Sgate signal becomes active. Subsequently, the first latch holds the count value num3 of the first counter by the Psig signal. Then, the first counter is reset by the CRST signal.

[0060] [Operation in the Fourth Frame] Next, in the exposure period of the fourth frame, the detection shared pixel counts the photons incident on the detection shared pixel in synchronization with the CLK signal by the first counter. The first counter outputs a count value. The driving unit 110 supplies the detection shared pixel with the CLK signal having a number of pulses corresponding to a preset exposure period. Thereby, the first counter counts the photons during the exposure period. As a result of the comparison in the third frame, since the Sgate signal is active, the other CLKs signals and the CRSTs signals included in the pixel block 200 become valid, and the SPAD pixel 210 counts the photons incident on the SPAD pixel 210 in synchronization with the CLKs signal by the second counter. The second counter outputs a count value.

[0061] Next, in the read period following the exposure period, the first counter reads out the determined count value num4.

[0062] Next, in the detection period following the read period, the drive unit 110 outputs (1) the LRST signal, (2) the Dsig signal, (3) the Psig signal, and (4) the CRST signal as pulse signals synchronized with the CLK signal in this order. The second and third latches of the detection shared pixel are reset by the LRST signal. Subsequently, the differential circuit compares the count value in the previous frame with the count value in the current frame in synchronization with Dsig, and holds the state in the second and third latches. Here, the first latch holds the count value num4 of the first counter by the subsequent Psig signal, but the count value num3 in the previous frame is held in the first latch at the time of comparison by the differential circuit. Here, it is assumed that num3 > num4. As in the example shown in FIG. 6, when (num3 - num4) is equal to or greater than a predetermined threshold, as a result of the comparison by the differential circuit, the DN signal becomes active, so the Sgate signal becomes active. Subsequently, the first latch holds the count value num4 of the first counter by the Psig signal. Then, the first counter is reset by the CRST signal.

[0063] As described above, it is possible to repeatedly perform a series of operations of comparing the count value in the previous frame with the count value in the current frame in the detection shared pixel and determining whether to drive the SPAD pixel 210 in the next frame.

[0064] <Arrangement of the counting function and the detection function on the wafer> In the SPAD pixel 210 of the present embodiment, since the counting function and the detection function can be configured by a logic circuit, area reduction due to process shrinkage becomes possible. The logic circuit that realizes the counting function and the logic circuit that realizes the detection function may be arranged on the same wafer or on different wafers. For example, one of the logic circuits of the counting function and the detection function can also be formed by stacking it on the wafer on which the other logic circuit is formed. More specifically, the solid-state imaging device 100 has a first wafer on which the counting function is formed and a second wafer on which the detection function is formed and which is stacked on the first wafer.

[0065] The solid-state imaging device 100 of the present embodiment described above has the following specific effects.

[0066] At least one SPAD pixel 210 of the pixel block 200 has a detection function of detecting a change in the light incident on the SPAD pixel 210. That is, at least one SPAD pixel 210 of the pixel block 200 has both a counting function and a detection function. Therefore, all the SPAD pixels 210 of the pixel block 200 can be configured to have a counting function without adding a detection function. Thereby, while preventing a decrease in spatial resolution, an increase in man-hours and complexity in the development of the solid-state imaging device can be suppressed.

[0067] Also, by adopting a configuration in which at least one SPAD pixel 210 has both a counting function and a detection function, there is no need to add a detection function, so an increase in the area of the solid-state imaging device 100 can be suppressed.

[0068] Also, since at least one SPAD pixel 210 has both a counting function and a detection pixel portion, the power for driving the pixel block 200 can be reduced.

[0069] Also, since both the counting function and the detection function can be configured by a logic circuit, area reduction due to process shrinkage becomes possible.

[0070] (Second Embodiment) In the first embodiment, the case where the pixel block 200 has one or a plurality of independent detection - shared pixels has been described. In the second embodiment, the case where the pixel block 200 has a plurality of detection - shared pixels and these plurality of detection - shared pixels share a detection function will be described.

[0071] FIG. 7 is a schematic diagram illustrating the configuration of a pixel block of a solid - state imaging device according to the second embodiment. FIG. 8 is a block diagram illustrating the functions of the SPAD pixels 210 of the pixel block 200 shown in FIG. 7. To avoid redundant explanations, the description of the same configuration as in the first embodiment will be simplified or omitted.

[0072] As shown in FIG. 7, in the present embodiment, at least two (for example, p) of the M SPAD pixels 210 of the pixel block 200 have a detection function in addition to the counting function. Here, p is a natural number greater than or equal to 2 and less than M.

[0073] That is, all (M) of the M SPAD pixels 210 have a counting function. Among these, p SPAD pixels 210 also have a detection function, while (M - p) SPAD pixels 210 do not have a detection function.

[0074] For example, each pixel block 200 has 16 SPAD pixels 210 arranged in 4 rows × 4 columns. Two of these 16 SPAD pixels 210 can be a first detection pixel and a second detection - shared pixel. The first detection - shared pixel is at the position (0,0) in the rectangular coordinate system, and the second detection - shared pixel is at the position (0,1) adjacent to the first detection - shared pixel (the range of the dashed line in FIG. 8). The first and second detection - shared pixels are not limited to an adjacent positional relationship and may be at separated positions.

[0075] In this embodiment, the first detection shared pixel and the second detection shared pixel share a detection function (DVS). The detection function has a selector that selects, based on the SEL signal, which counter's count value among the first detection shared pixel and the second detection shared pixel to use. The count value selected by the selector is held in the first latch (P-Lat) by the Psig signal. Since the functions of the differential circuit (D-Diff) and the exposure control circuit are the same as those in the first embodiment, detailed descriptions thereof are omitted. Also, in FIG. 8, the descriptions of the second latch (Lat_UP) and the third latch (Lat_DN) are omitted. The functions of the second latch and the third latch are also the same as those of the second latch and the third latch in the first embodiment.

[0076] In the above description, the case where there are two detection shared pixels (when p = 2) has been described, but the configuration can be similarly made when there are three or more detection shared pixels (when p ≥ 3). For example, when there are three detection shared pixels, the three detection shared pixels share the detection function.

[0077] The solid-state imaging device 100 of this embodiment described above has the following specific effects in addition to the effects of the first embodiment.

[0078] Any detection function of a plurality of detection shared pixels can be appropriately selected. Since the plurality of detection shared pixels share the detection function, while suppressing an increase in the area of the solid-state imaging device 100, events can be detected at different positions within the pixel block 200, and the accuracy of event detection is improved.

[0079] (Third Embodiment) In the second embodiment, the case where the pixel block 200 has a plurality of detection shared pixels and these plurality of detection shared pixels share the detection function has been described. In the third embodiment, the case where a plurality of detection shared pixels share the detection function and further the detection function performs event detection based on the count values of the detection functions of these plurality of detection shared pixels will be described.

[0080] FIG. 9 is a schematic diagram illustrating the configuration of a pixel block of the solid-state imaging device 100 according to the third embodiment. FIG. 10 is a block diagram illustrating the functions of the SPAD pixel 210 of the pixel block 200 shown in FIG. 9. To avoid redundant explanations, the descriptions of the same configurations as those in the first and second embodiments are simplified or omitted.

[0081] In this embodiment, the first detection shared pixel and the second detection shared pixel share a detection function (DVS). The detection function inputs the count values by the counters of the first detection shared pixel and the second detection shared pixel by a Csig signal, performs a predetermined operation (Calc), and outputs the result to the first latch (P-Lat). The predetermined operation can be, for example, merging or averaging the count values by the counters of the first and second detection shared pixels. The count value selected by the selector is held in the first latch by a Psig signal. Since the functions of the differential circuit (D-Diff) and the exposure control circuit are the same as those in the first embodiment, detailed descriptions thereof are omitted. Also, in FIG. 9, the descriptions of the second latch (Lat_UP) and the third latch (Lat_DN) are omitted. The functions of the second latch and the third latch are also the same as those of the second latch and the third latch in the first embodiment.

[0082] In the above description, the case where there are two detection shared pixels (when p = 2) has been described, but the configuration can be similarly made when there are three or more detection shared pixels (when p ≥ 3). For example, when there are three detection shared pixels, an event is detected based on the count values of the detection functions of the three detection shared pixels.

[0083] The solid-state imaging device 100 of this embodiment described above has the following specific effects in addition to the effects of the first and second embodiments.

[0084] Since an event is detected based on the count values of the detection functions of a plurality of detection shared pixels, it is possible to suppress a decrease in the detection accuracy of the event due to variations in the detection functions.

[0085] (Fourth Embodiment) In the fourth embodiment, a case where an offset is set with respect to the photon count value in the previous frame will be described. In the fourth embodiment, exposure control is performed based on the comparison result between the count value obtained by adding a predetermined offset value to the photon count value in the previous frame and the count value of the current frame.

[0086] FIG. 11 is a block diagram illustrating the functions of the detection shared pixel according to the fourth embodiment. FIG. 12 is a diagram illustrating an operation of detecting a change in light incident on the detection shared pixel shown in FIG. 11. To avoid duplication of description, the description of the same configuration as that of the first embodiment will be simplified or omitted.

[0087] [Detection Function of Detection Shared Pixel] As shown in FIG. 11, the detection function of the detection shared pixel in the present embodiment can be configured by a circuit including a first latch (P-Lat), a differential circuit (D-Diff), and an exposure control circuit.

[0088] The first latch is configured by a circuit including a latch circuit (Latch) and an offset setting unit (SetU / D). The latch circuit holds the photon count value counted by the counter (Counter) of the counting function in synchronization with the Psig signal. The offset setting unit sets an UP offset value and a DOWN offset value by bit shifting with respect to the count value held in the previous frame. The UP offset value and the DOWN offset value respectively correspond to the upper limit value and the lower limit value of the variation range with respect to the count value of the previous frame.

[0089] The offset setting unit can be configured to set the offset in steps of 2 to the power of a (where a is a natural number) by bit shift. Also, the offset setting unit can be configured to set the UP offset value and the DOWN offset value in multiple stages. Further, the offset setting unit can be configured to fixedly set the UP offset value and the DOWN offset value. Alternatively, the offset setting unit can be configured to dynamically change the setting range of the UP offset value and the DOWN offset value. Also, the offset setting unit can be configured to set the UP offset value and the DOWN offset value to N bits and set the fluctuation range. In this way, the count values obtained by adding a predetermined offset value to the photon count value in the previous frame are herein referred to as the UP reference count value (UP_ref) and the DOWN reference count value (DN_ref), respectively.

[0090] The difference circuit can further be constituted by a circuit including a difference module (D+, D-), a second latch (Lat_UP), and a third latch (Lat_DN). The difference circuit compares (takes the difference between) the UP reference count value and the count value in the current frame counted by the counter in the difference module. Also, the difference circuit compares (takes the difference between) the DOWN reference count value and the count value in the current frame counted by the first counter in the difference module.

[0091] The second latch activates (enables) the UP signal when the count value of the current frame is greater than the UP reference count value. The second latch holds the active state of the UP signal. Also, the third latch activates (enables) the DN signal when the count value of the current frame is less than the DOWN reference count value. The third latch holds the active state of the DN signal. If neither condition is met, the UP signal and the DN signal are set to the inactive state. Thereby, a dead zone where no event is detected can be generated between the UP offset value and the DOWN offset value, and the sensitivity of event occurrence can be adjusted.

[0092] As shown in FIG. 12, during the detection period, the detection shared pixel counts the photons incident on the detection shared pixel by the counting function using a counter. Also, the detection shared pixel sets the UP reference count value and the DOWN reference count value based on the count value held in the previous frame. Then, the detection shared pixel compares these UP / DOWN reference count values with the count value in the current frame. Further, during the counting period, the detection shared pixel generates a UP signal / DN signal based on the comparison result. Not limited to the above method, for example, a differential circuit may hold the comparison result (difference) between the count value of the previous frame and the count value of the current frame, and control Sgate to be active or inactive by comparing the difference with the UP offset value and the DOWN offset value.

[0093] Note that in FIG. 12, the detection period and the counting period are set to the same time, but they may be different times.

[0094] Also, the offset setting unit may be configured such that the UP offset value and the DOWN offset value are adjusted (controlled) based on the UP signal / DN signal. For example, the offset setting unit may be configured such that the UP offset value increases when the UP signal is active. Also, the offset setting unit may be configured such that the absolute value of the DOWN offset value decreases when the DOWN signal is active.

[0095] Alternatively, instead of adjusting the UP offset value and the DOWN offset value, the exposure timer of the exposure control circuit may be configured to adjust the exposure period. The detection shared pixel may be configured to control the start and end of photon counting by the counter based on the UP signal / DN signal. For example, when the UP signal is active, the detection shared pixel adjusts the set value of the exposure period of the exposure timer so that the exposure period becomes shorter. Also, for example, when the DOWN signal is active, the detection shared pixel adjusts the set value of the exposure period of the exposure timer so that the exposure period becomes longer.

[0096] <Modification Example 1> FIG. 13 is a block diagram showing a modification (Modification Example 1) of the solid-state imaging device 100 according to the fourth embodiment.

[0097] In this modification example, the exposure control circuit generates an exposure control signal for controlling the offset setting unit based on the UP signal / DN signal. The offset setting unit changes (adjusts) the UP offset value and the DOWN offset value based on the exposure control signal. The exposure timer can change the exposure control signal based on the UP signal and / or the DN signal. For example, when the UP signal is active, the exposure timer changes the exposure period to be shorter. Also, for example, when the DOWN signal is active, the exposure timer changes the exposure period to be longer.

[0098] <Modification Example 2> FIG. 14 is a block diagram showing a modification (Modification Example 2) of the solid-state imaging device 100 according to the fourth embodiment.

[0099] In this modification example, the first latch (P-Lat) is constituted by a circuit including a latch circuit, an offset setting unit (SetU / D), and a LUT (Look Up Table) unit.

[0100] The latch circuit holds the count value of photons counted by a counter in the previous frame. Also, the LUT unit is a table that returns the UP offset value and the DOWN offset value with respect to the count value held in the latch circuit. Therefore, in the offset setting unit, the UP offset value and the DOWN offset value corresponding to the photometric amount in the previous frame are reflected.

[0101] The solid-state imaging device 100 of the present embodiment described above has the following specific effects in addition to the effects of the first to third embodiments.

[0102] An insensitive zone where no event is detected can be generated between the UP offset value and the DOWN offset value, and the sensitivity of event occurrence can be adjusted.

[0103] (The Fifth Embodiment) In the fifth embodiment, the case where the count value of the N-bit counter in the counting function is compressed to K (K < N) bits and the comparison is performed with K bits in the detection function will be described.

[0104] FIG. 15 is a block diagram illustrating the functions of the detection shared pixel according to the fifth embodiment. In order to avoid duplication of description, the description of the same configuration as that in the first embodiment will be simplified or omitted.

[0105] [Counting Function of Detection Shared Pixel] In this embodiment, the detection function has a bit compression unit in addition to the APD1 and the counter. The functions of the APD1 and the counter are the same as those of the ADP1 and the counter in the first embodiment. The bit compression unit compresses the count value of the N-bit counter to K (K < N) bits. The bit compression unit is configured to output, for example, the upper K bits of the input N-bit data.

[0106] [Detection Function of Detection Shared Pixel] The detection function of the detection shared pixel can be configured by a circuit including a first latch (P-Lat), a differential circuit (D-Diff), and an exposure control circuit.

[0107] The first latch is a K-bit latch circuit, and holds the count value of the photons counted by the counter of the detection function in synchronization with the Psig signal.

[0108] The differential circuit in the differential module compares (takes the difference between) the count value (K bits) counted by the first counter and held in the latch in the previous frame and the count value (K bits) in the current frame counted by the first counter. Since the function of the exposure control circuit is the same as that in the first embodiment, detailed description thereof is omitted. Also, in FIG. 15, the description of the second latch (Lat_UP) and the third latch (Lat_DN) is omitted. The functions of the second latch and the third latch are also the same as those of the second latch and the third latch in the first embodiment.

[0109] In addition to the effects of the first to fourth embodiments, the solid-state imaging device 100 of the present embodiment described above has the following specific effects.

[0110] Since comparison is performed in K bits in the detection function, the chip area of the pixel array unit 120 can be reduced.

[0111] As described above, the solid-state imaging device of the present invention has been described in the embodiment. However, it goes without saying that those skilled in the art can appropriately add, modify, and omit within the scope of the technical idea of the present invention.

Description of Reference Numerals

[0112] 100 Solid-state imaging device, 110 Driving unit, 120 Pixel array unit, 140 Image processing unit, 200 Pixel block, 210 SPAD pixel, IG Input gate, APD1, APD2 Avalanche photodiode.

Claims

1. A solid-state imaging device having a plurality of pixel blocks, each of said pixel blocks having a plurality of SPAD pixels for imaging, wherein at least one SPAD pixel of said pixel blocks has a detection function of detecting a change in light incident on said SPAD pixel, characterized in that it is a solid-state imaging device.

2. Said at least one SPAD pixel is a detection shared pixel having a detection function of detecting a change in light incident on said pixel block in addition to a counting function of counting photons incident on said SPAD pixel, said detection shared pixel having a counter for counting photons incident on said detection shared pixel and a latch for holding a count value of photons counted one frame before by said counter, said detection function comparing a count value in the previous frame and a count value in the current frame counted by said counter to detect a change in said light, according to the solid-state imaging device of claim 1.

3. Said detection shared pixel has an exposure control unit, and when said exposure control unit detects a change in a predetermined light by said detection function, said exposure control unit enables the counting function of other SPAD pixels of the pixel block having said detection shared pixel, according to the solid-state imaging device of claim 2.

4. Each SPAD pixel excluding said detection shared pixel of said pixel block has a gate unit, and when said exposure control unit detects a change in a predetermined light by said detection function, said exposure control unit controls said gate unit to enable the counting function of each corresponding SPAD pixel, according to the solid-state imaging device of claim 3.

5. Said detection function is shared by at least two SPAD pixels of said pixel block, according to the solid-state imaging device of claim 1 or 2.

6. Said detection function sets an upper limit value and a lower limit value of a variation range with respect to the count value in the previous frame, and compares the count value in the current frame with said upper limit value and said lower limit value to detect a change in light, according to the solid-state imaging device of claim 2 or 3.

7. Said detection function compares a count value in the previous frame and a count value in the current frame using a value obtained by bit compression to detect a change in light, according to the solid-state imaging device of claim 2 or 3.

8. A first wafer on which said counting function is formed, and a second wafer on which said detection function is formed and laminated on said first wafer, according to the solid-state imaging device of claim 2 or 3.

Images