Controller and storage device
By employing pre-allocated logical memory addresses for buffer area management, the controller optimizes firmware loading in storage devices, addressing inefficiencies and enhancing operational efficiency.
Patent Information
- Application Number
- JP2024140674
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-12-12
- Filing Date
- 2024-08-22
- Publication Date
- 2025-06-24
Smart Images
Figure 2025093849000001_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure relate to a controller and a storage device.
Background Art
[0002] A storage device can include a memory including a plurality of memory cells for storing data. The storage device can include a controller for controlling the operation of the memory. The controller can control operations such as writing data to the memory, or reading and erasing data stored in the memory.
[0003] The controller can control the memory in a manner of executing firmware, for example. The firmware may be stored and used in the memory included in the storage device in some cases.
[0004] When execution of the firmware is requested, the controller can load the firmware stored in the memory into a buffer area and execute it. There may be cases where the buffer area available to the controller is not sufficient and it is not easy to load the firmware. In such cases, there is a problem that the operating efficiency of the firmware may decrease.
Summary of the Invention
Problems to be Solved by the Invention
[0005] Embodiments of the present disclosure can provide a solution that can efficiently use the buffer area available by a controller included in a storage device and improve the operating efficiency of the firmware loaded into the buffer area.
Means for Solving the Problems
[0006] Embodiments of the present disclosure store a plurality of codes, the plurality of codes including a plurality of overlay codes and a plurality of non-overlay codes, the plurality of non-overlay codes being used more frequently than at least one of the plurality of overlay codes. There is provided a storage device including a first memory, a second memory including a plurality of buffer areas into which the plurality of codes are loaded, and at least one occupied logical memory address pre-allocated for loading the plurality of codes. When loading the first overlay code, the first occupied logical memory address is connected to at least one of the plurality of buffer areas, and a controller for loading the first overlay code into at least one buffer area connected to the first occupied logical memory address can be provided.
[0007] Embodiments of the present disclosure provide a controller including a buffer memory including a plurality of buffer areas into which a plurality of codes are loaded, and at least one occupied logical memory address pre-allocated for loading the plurality of codes. When loading the first code, the first occupied logical memory address is connected to at least one of the plurality of buffer areas, and the first code is loaded into at least one buffer area connected to the first occupied logical memory address.
[0008] Embodiments of the present disclosure pre-allocate and set at least one occupied logical memory address used for loading a plurality of overlay codes, and when loading at least one of the plurality of overlay codes, load at least one overlay code into at least one first buffer area connected to the at least one occupied logical memory address. A controller can be provided.
Advantages of the Invention
[0009] According to the embodiments of the present disclosure, the buffer areas used by the controller can be efficiently utilized, and the operating efficiency of the firmware loaded and executed in the buffer areas can be improved.
Brief Description of the Drawings
[0010]
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Best Mode for Carrying Out the Invention
[0011] When adding reference numerals to the components of each drawing, for the same components, even if they are shown on other drawings, the same numerals may be used as much as possible. In addition, when explaining the present disclosure, if it is determined that a specific description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description thereof will be omitted. When terms such as "including", "having", "composed of", etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it can include the case of including a plurality, unless there are specific descriptions to the contrary.
[0012] Also, when explaining the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. can be used. These terms are only for distinguishing the components from other components, and the essence, order, sequence, number, etc. of the components are not limited by these terms.
[0013] In the description of the positional relationship of components, when it is described that two or more components are "connected", "coupled", or "joined", it should be understood that two or more components can be directly "connected", "coupled", or "joined", but it is also possible that two or more components and other components are further "interposed" and "connected", "coupled", or "joined". Here, the other components may be included in one or more of the two or more components that are "connected", "coupled", or "joined" to each other.
[0014] In the description of the relationship of the time flow regarding components, operation methods, manufacturing methods, etc., for example, when the time sequence relationship or the flow sequence relationship is described by "after ~", "subsequent to ~", "next to ~", "before ~", etc., it may include cases that are not continuous unless "immediately" or "directly" is used.
[0015] On the one hand, when numerical values related to components or their corresponding information (e.g., levels, etc.) are mentioned, even without separate explicit description, the numerical values or their corresponding information can be interpreted as including the range of errors that can occur due to various factors (e.g., process factors, internal or external impacts, noise, etc.).
[0016] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
[0017] FIG. 1 is a diagram showing an example of a schematic configuration of a storage device 100 according to an embodiment of the present disclosure.
[0018] Referring to FIG. 1, a storage device 100 according to an embodiment of the present disclosure can include at least one memory 110. The storage device 100 can include a controller 120 that controls the operation of at least one memory 110.
[0019] The memory 110 may be a non-volatile memory, and can be implemented in various types, for example, NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory, phase change memory, self-resistive memory, ferroelectric memory, or spin injection magnetization reversal memory. Also, the memory 110 may be realized in a three-dimensional array structure.
[0020] The embodiments of the present disclosure are applicable not only to flash memories in which the charge storage layer is composed of a floating gate, but also to charge trap type flash memories in which the charge storage layer is composed of an insulating film.
[0021] The memory 110 can operate in response to the control of the controller 120. The operations of the memory 110 can include, for example, a program operation (also called a "write operation"), an erase operation, and a read operation.
[0022] The controller 120 can control the program, erasure, reading, and background operations of the memory 110. The background operations may include, for example, one or more of garbage collection, wear leveling, read reclaim, or bad block management operations.
[0023] The controller 120 can control the operation of the memory 110 in response to requests from devices located outside the storage device 100. Also, the controller 120 can control the operation of the memory 110 regardless of external requests.
[0024] The controller 120 can control the operation of the memory 110, for example, in response to requests from the host device 200. A computing system can be said to include the storage device 100 and the host device 200.
[0025] The host device 200 may be, for example, a computer, a UMPC (Ultra Mobile PC), a workstation, a PDA (Personal Digital Assistant), a tablet, a mobile phone, a smartphone, an e-book, a PMP (Portable Multimedia Player), a portable game console, a navigation device, a black box, a digital camera, a DMB (Digital Multimedia Broadcasting) player, a smart TV, a digital voice recorder, a digital voice player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, storage that constitutes a data center, one of various electronic devices that constitute a home network, one of various electronic devices that constitute a telematics network, an RFID (Radio Frequency Identification) device, a mobile device (e.g., a vehicle, a robot, a drone) that can travel or autonomously drive according to human control, etc. Alternatively, the host device 200 may be a virtual / augmented reality device that provides two-dimensional or three-dimensional virtual reality images or augmented reality images. The host device 200 may also be any of various electronic devices that require the storage device 100 capable of storing data.
[0026] The host device 200 can include at least one operating system. The operating system can manage and control the functions and operations of the host device 200 as a whole and can control the interaction between the host device 200 and the storage device 100. The operating system can be classified into a general operating system and a mobile operating system according to the mobility of the host device 200.
[0027] The controller 120 and the host device 200 may be separate devices from each other. In some cases, the controller 120 and the host device 200 can be integrated and implemented in a single device. Hereinafter, for convenience of explanation, a case where the controller 120 and the host device 200 are separate devices from each other will be described as an example.
[0028] The controller 120 can include a host interface that provides an interface for communicating with the host device 200. The controller 120 can include a memory interface that provides an interface for communicating with the memory 110.
[0029] The controller 120 may include a control circuit that controls the overall operation of the controller 120. The control circuit can include a processor 121 as in the example shown in FIG. 1. The processor 121 can include a working memory used for the operation of the processor 121 and, in some cases, may optionally include an error detection and correction circuit. The working memory may, in some cases, be disposed outside the processor 121.
[0030] The processor 121 can communicate with the host device 200 via the host interface and communicate with the memory 110 via the memory interface.
[0031] The processor 121 can execute a function of analyzing a command input from the host device 200 and transmitting it to the memory 110.
[0032] The processor 121 may include, for example, a flash translation layer or be capable of corresponding to a flash translation layer. The processor 121 can convert a logical block address provided by the host device 200 into a physical block address. The processor 121 can use a mapping table to input a logical block address and convert it into a physical block address.
[0033] The processor 121 can control the operation of the controller 120 by executing, for example, firmware. The operation of the storage device 100 described in the embodiments of the present disclosure can be implemented such that the processor 121 executes the firmware in which its operation is defined.
[0034] The firmware is a program executed within the storage device 100 to drive the storage device 100 and can include various functional layers corresponding to the aforementioned processor 121. For example, the firmware may include binary data in which the code for executing each of the aforementioned functional layers is defined.
[0035] The firmware can be loaded from, for example, the memory 110 or a separate non-volatile memory (e.g., ROM, NOR flash) located outside the memory 110 into the working memory. After power-on, when executing the startup operation, the processor 121 can first load all or part of the firmware into the working memory.
[0036] The processor 121 can execute the logical operations defined by the firmware loaded in the working memory to control the overall operation of the controller 120. The processor 121 can control the controller 120 to generate a command or signal according to the result of executing the logical operations defined by the firmware. When the part of the firmware in which the logical operations to be executed are defined is not loaded into the working memory, the processor 121 can generate an event (e.g., an interrupt) to load the corresponding part of the firmware into the working memory.
[0037] The working memory can store the firmware, program code, commands, or data necessary to drive the controller 120. The working memory may be located inside or outside the controller 120. In some cases, the working memory may be arranged both inside and outside the controller 120.
[0038] The working memory may be the buffer memory 122 shown in FIG. 1. Alternatively, the working memory can be arranged separately from the buffer memory 122 shown in FIG. 1. FIG. 1 illustrates the case where the buffer memory 122 is arranged inside the controller 120. However, in some cases, the buffer memory 122 may be arranged inside or outside the controller 120.
[0039] The working memory and the buffer memory 122 can include, for example, one or more of SRAM (Static RAM), DRAM (Dynamic RAM), SDRAM (Synchronous RAM), etc. as volatile memory.
[0040] FIG. 2 is a diagram showing an example of a method for loading the code stored in the memory 110 into the buffer memory 122 in the storage device 100 according to an embodiment of the present disclosure.
[0041] Referring to FIG. 2, the memory 110 included in the storage device 100 can include a plurality of memory areas. A part of the memory areas included in the memory 110 may be an area for storing firmware. The firmware is stored in the form of binary data and may be defined, for example, in the form of code.
[0042] As an example, the first firmware code can be stored in the first memory area mem1 and the second memory area mem2. The second firmware code can be stored in the third memory area mem3 and the fourth memory area mem4. The third firmware code can be stored in the fifth memory area mem5 and the sixth memory area mem6.
[0043] Processor 121 can load the code stored in memory 110 into buffer memory 122 included in controller 120 as needed. In this specification, memory 110 may be referred to as the first memory, and buffer memory 122 may be referred to as the second memory.
[0044] Buffer memory 122 can include a plurality of buffer areas. FIG. 2 exemplarily shows ten buffer areas (buf1, …, buf10).
[0045] As an example, processor 121 may be allocated buffer areas from buffer memory 122 when a request is made to load the first firmware code. For example, processor 121 may be allocated the sixth buffer area buf6 and the seventh buffer area buf7 among the buffer areas included in buffer memory 122.
[0046] Processor 121 can load the first firmware code stored in the first memory area mem1 and the second memory area mem2 of memory 110 into the sixth buffer area buf6 and the seventh buffer area buf7 of buffer memory 122. Processor 121 can execute the first firmware code loaded into buffer memory 122 to control the operation of memory 110 or storage device 100.
[0047] When the use of the first firmware code is completed by processor 121, the allocation of the sixth buffer area buf6 and the seventh buffer area buf7 in which the first firmware code is loaded can be released. The sixth buffer area buf6 and the seventh buffer area buf7 can be used to load other data.
[0048] The buffer area of the buffer memory 122 can be used to load other data than the firmware code. Embodiments of the present disclosure can provide a method for efficiently using the buffer area of the buffer memory 122 and improving the operation efficiency of the firmware by loading the firmware code.
[0049] FIGS. 3 to 5 are diagrams showing an example of a method for loading the overlay code stored in the memory 110 into the buffer memory 122 in the storage device 100 according to an embodiment of the present disclosure.
[0050] Referring to FIG. 3, when the controller 120 allocates a buffer area for loading the firmware code, the buffer area of the buffer memory 122 can be allocated using a logical memory address. Although embodiments of the present disclosure have been exemplarily described for the case of loading the firmware code into the buffer memory 122, they can also be applied to the case where data other than the firmware code is allocated and loaded into the buffer area of the buffer memory 122.
[0051] A part of the memory area of the memory 110 included in the storage device 100 can store the firmware code. FIG. 3 exemplarily shows the case where the firmware code is stored in six memory areas.
[0052] The buffer memory 122 included in the controller 120 of the storage device 100 can provide a plurality of buffer areas. In some cases, the embodiments of the present disclosure can be applied even when the buffer memory 122 is disposed outside the controller 120.
[0053] The processor 121 included in the controller 120 of the storage device 100 can allocate a buffer area for loading firmware code using a logical memory address. Also, the processor 121 can distinguish firmware codes according to the type and usage frequency of the firmware codes, etc., and control the settings of the logical memory addresses for the firmware codes to be different.
[0054] As an example, the processor 121 can classify firmware codes into overlay codes and non - overlay codes. The overlay code may mean a firmware code with a low usage frequency. The non - overlay code may mean a firmware code with a high usage frequency.
[0055] The non - overlay code can be, for example, a firmware code loaded into the buffer memory 122 when the storage device 100 is started up. The non - overlay code can be, for example, a firmware code continuously loaded into the buffer memory 122 during the operation of the storage device 100. Alternatively, the non - overlay code may mean a firmware code whose loading period or frequency into the buffer memory 122 during the operation of the storage device 100 is equal to or greater than a certain value.
[0056] The overlay code may mean, for example, a firmware code whose usage period or frequency is smaller than that of the non - overlay code, or a firmware code whose loading period or frequency into the buffer memory 122 during the operation of the storage device 100 is smaller than a certain value.
[0057] The processor 121 of the controller 120 can pre-assign and set the logical memory address used to load the overlay code into the buffer memory 122. As an example, the processor 121 can pre-assign at least one occupied logical memory address lma and set it as the logical memory address used to load the overlay code.
[0058] The occupied logical memory address lma can be a fixed logical memory address. The occupied logical memory address lma can be the logical memory address used for loading the overlay code, and can be used for loading each of multiple overlay codes.
[0059] For example, referring to FIG. 3, the processor 121 can pre-assign and set a first occupied logical memory address lma1 and a second occupied logical memory address lma2 as the logical memory addresses for loading the overlay code. The occupied logical memory address lma can be set in various ways according to the size of the firmware code. FIG. 3 exemplarily shows the case where two occupied logical memory addresses lma are assigned for loading one firmware code.
[0060] The first occupied logical memory address lma1 and the second occupied logical memory address lma2 may not be connected to the buffer area included in the buffer memory 122. Even if the first occupied logical memory address lma1 and the second occupied logical memory address lma2 are pre-assigned, since they are not connected to the buffer area of the buffer memory 122, the buffer area of the buffer memory 122 may not be assigned for loading the firmware code.
[0061] When a situation occurs where the loading of the first firmware code among the overlay codes is necessary, the processor 121 can allocate buffer areas of the buffer memory 122 for the first occupied logical memory address lma1 and the second occupied logical memory address lma2. The buffer areas allocated for the first occupied logical memory address lma1 and the second occupied logical memory address lma2 may or may not be continuous. The buffer areas allocated for the first occupied logical memory address lma1 and the second occupied logical memory address lma2 can be indicated by a buffer ID, for example. Alternatively, it can be indicated by a buffer ID and a plurality of slots included in each buffer ID. As an example, one occupied logical memory address lma can be allocated one buffer ID and a plurality of slots, but it is not limited to this.
[0062] For example, for the first occupied logical memory address lma1 and the second occupied logical memory address lma2, the second buffer area buf2 and the fourth buffer area buf4 included in the buffer memory 122 can be allocated.
[0063] The processor 121 can connect each of the first occupied logical memory address lma1 and the second occupied logical memory address lma2 to each of the second buffer area buf2 and the fourth buffer area buf4.
[0064] The processor 121 can load the first firmware code, which is the overlay code, into the second buffer area buf2 connected to the first occupied logical memory address lma1 and the fourth buffer area buf4 connected to the second occupied logical memory address lma2.
[0065] Since the usage period or frequency of the overlay code is not relatively high, the processor 121 can load the overlay code using only the pre-assigned and set occupancy logical memory address lma. The overlay code can be loaded into the buffer area connected to the occupancy logical memory address lma via the occupancy logical memory address lma, and the loading of multiple overlay codes can be efficiently managed.
[0066] Also, since the occupancy logical memory address lma is not connected to the buffer area included in the buffer memory 122 before the overlay code is loaded, the buffer memory 122 does not need to pre-assign a buffer area for loading the overlay code. The allocation of the buffer area included in the buffer memory 122 can be efficiently managed.
[0067] When the use of the first firmware code loaded into the buffer memory 122 is completed via the first occupancy logical memory address lma1 and the second occupancy logical memory address lma2, the processor 121 can release the connection between the first occupancy logical memory address lma1 and the second occupancy logical memory address lma2 and the buffer area.
[0068] As an example, referring to FIG. 4, the connection between the first occupancy logical memory address lma1 and the second buffer area buf2 can be released. The connection between the second occupancy logical memory address lma2 and the fourth buffer area buf4 can be released.
[0069] The second buffer area buf2 and the fourth buffer area buf4 may be managed as areas where invalid data is loaded, and the first firmware code may be deleted from the second buffer area buf2 and the fourth buffer area buf4.
[0070] After the use of the first firmware code is completed, when a situation occurs where it is necessary to load a second firmware code, which is another overlay code, the first occupied logical memory address lma1 and the second occupied logical memory address lma2 can be used for loading the second firmware code.
[0071] Processor 121 can connect each of the first occupied logical memory address lma1 and the second occupied logical memory address lma2 to a buffer area included in buffer memory 122. As an example, processor 121 can connect each of the first occupied logical memory address lma1 and the second occupied logical memory address lma2 to the sixth buffer area buf6 and the ninth buffer area buf9 included in buffer memory 122. Processor 121 can load the second firmware code into the sixth buffer area buf6 and the ninth buffer area buf9.
[0072] Since the overlay code is loaded into the buffer area of buffer memory 122 via the pre-assigned and set occupied logical memory address lma, the size of the buffer area in buffer memory 122 where the overlay code is loaded can be maintained below a certain size. The overlay code can be loaded while efficiently using the buffer area of buffer memory 122 and minimizing the impact on the loading of other data.
[0073] For loading the overlay code, only the occupied logical memory address lma is pre-assigned and set, and the buffer area is not pre-assigned. Therefore, the buffer area where the overlay code is loaded may vary depending on the time.
[0074] For example, as in the example shown in FIG. 4, the buffer area where the first firmware code is loaded may be different from the buffer area where the second firmware code is loaded. Also, when the first firmware code is loaded into the buffer area and then loaded again into the buffer area after use is completed, the buffer area where the first firmware code is loaded at the first time may be different from the buffer area where the first firmware code is loaded at the second time.
[0075] The occupancy logical memory address lma is fixed, and the buffer area connected to the occupancy logical memory address lma can be variable according to the usage state of the buffer memory 122.
[0076] For loading the overlay code, only the occupancy logical memory address lma is pre-assigned and fixed, and the buffer area of the buffer memory 122 is variably connected, so that the buffer area of the buffer memory 122 can be used efficiently.
[0077] Also, for loading the overlay code, a pre-assigned and set occupancy logical memory address lma is provided, and the overlay code is loaded into the buffer area of the buffer memory 122 via the occupancy logical memory address lma, so that the usage efficiency of the buffer area due to loading of the overlay code with low usage frequency can be improved.
[0078] Also, since the overlay code is loaded into the buffer area via the occupancy logical memory address lma, in some cases, the processor 121 can also maintain the connection between the occupancy logical memory address lma and the buffer area after the use of the overlay code is completed.
[0079] For example, referring to FIG. 5, FIG. 3 exemplarily shows a state after the first firmware code is loaded into the buffer area of the buffer memory 122 and after the use of the first firmware code is completed.
[0080] After the use of the first firmware code is completed, the processor 121 can, in some cases, hold the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area without releasing it.
[0081] For example, if the remaining capacity of the buffer area in the buffer memory 122 is equal to or greater than a preset value, the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area can be held. Each of the first occupied logical memory address lma1 and the second occupied logical memory address lma2 can hold the connection with the second buffer area buf2 and the fourth buffer area buf4.
[0082] When a situation occurs where the use of the second firmware code, which is another overlay code, is required after the use of the first firmware code is completed, the processor 121 can load the second firmware code into the second buffer area buf2 and the fourth buffer area buf4 connected to the first occupied logical memory address lma1 and the second occupied logical memory address lma2.
[0083] By using the occupied logical memory address lma to load the overlay code, the processor 121 enables efficient use of the buffer area. When there is a margin in the buffer area, the connection between the occupied logical memory address lma and the buffer area is held, and the buffer area connected to the occupied logical memory address lma can be used as a buffer area for loading the overlay code.
[0084] The processor 121 can pre-assign and set the occupied logical memory address lma, efficiently use the buffer area included in the buffer memory 122 for loading the overlay code, efficiently execute the loading of the overlay code, and improve the performance of the operation of executing the firmware code.
[0085] Since the processor 121 pre-allocates and uses the occupancy logical memory address lma for loading the overlay code, it can use a logical memory address other than the occupancy logical memory address to load the non-overlay code.
[0086] FIGS. 6 and 7 are diagrams showing an example of a method for loading non-overlay code stored in the memory 110 into the buffer memory 122 in the storage device 100 according to an embodiment of the present disclosure.
[0087] Referring to FIG. 6, an example is illustratively shown in which the first firmware code and the second firmware code, which are overlay codes, are stored in the memory area included in the memory 110, and the third firmware code, which is non-overlay code, is stored.
[0088] When the processor 121 of the controller 120 is requested to load the first firmware code, which is an overlay code, it can use the first pre-allocated and set occupancy logical memory address lma1 and the second occupancy logical memory address lma2 for loading the overlay code.
[0089] As an example, the processor 121 can connect the first occupancy logical memory address lma1 and the second occupancy logical memory address lma2 to the second buffer area buf2 and the fourth buffer area buf4 among the buffer areas included in the buffer memory 122. The processor 121 can load and use the first firmware code in the second buffer area buf2 and the fourth buffer area buf4.
[0090] When a load of third firmware code, which is non-overlay code, is requested, the processor 121 can allocate a non-occupied logical memory address nma for loading the non-overlay code. The non-occupied logical memory address nma may be a logical memory address other than the pre-allocated and set occupied logical memory address lma.
[0091] As an example, the processor 121 can allocate a first non-occupied logical memory address nma1 and a second non-occupied logical memory address nma2 for loading third firmware code, which is non-overlay code. The processor 121 can connect the first non-occupied logical memory address nma1 and the second non-occupied logical memory address nma2 to buffer areas included in the buffer memory 122. As an example, each of the first non-occupied logical memory address nma1 and the second non-occupied logical memory address nma2 can be connected to a sixth buffer area buf6 and an eighth buffer area buf8 included in the buffer memory 122.
[0092] The processor 121 can load and use the third firmware code in the sixth buffer area buf6 and the eighth buffer area buf8 connected to the first non-occupied logical memory address nma1 and the second non-occupied logical memory address nma2.
[0093] Since the occupied logical memory address lma is pre-allocated and set for the overlay code, the processor 121 can allocate a logical memory address other than the occupied logical memory address lma and use it for loading the non-overlay code.
[0094] When the use of the overlay code or non-overlay code loaded in the buffer memory 122 is completed, the processor 121 can release the connection between the logical memory address and the buffer area.
[0095] For example, referring to FIG. 7, when the use of the first firmware code is completed, the processor 121 can release the connection between the first occupied logical memory address lma1, the second occupied logical memory address lma2, and the buffer area. When the use of the third firmware code is completed, the processor 121 can release the connection between the first non-occupied logical memory address nma1, the second non-occupied logical memory address nma2, and the buffer area.
[0096] The buffer area whose connection with the logical memory address is released is managed as if invalid data is loaded, or the data loaded in the corresponding buffer area may be deleted.
[0097] After the connection between the occupied logical memory address lma and the buffer area is released, the processor 121 can retain the setting of the occupied logical memory address lma. The processor 121 retains the setting of the occupied logical memory address lma, and then, when a situation where the loading of the overlay code is requested occurs, the processor 121 can execute the loading of the overlay code using the occupied logical memory address lma.
[0098] After the connection between the non-occupied logical memory address nma and the buffer area is released, the processor 121 can release the allocation of the non-occupied logical memory address nma. The processor 121 can release the allocation of the non-occupied logical memory address nma used for the allocation of data such as non-overlay code when the use of the data is completed.
[0099] Embodiments of the present disclosure efficiently execute the loading of the overlay code by using a fixed occupied logical memory address lma, and the logical memory address for loading data other than the overlay code is used without pre-assigning a logical memory address other than the occupied logical memory address lma, so that the buffer memory 122 can be easily accessed via the logical memory address.
[0100] Furthermore, embodiments of the present disclosure use logical memory addresses to manage an area where data is loaded into consecutive addresses, and use buffer areas corresponding to consecutive or non-consecutive addresses in buffer memory 122 that provides a physical storage space, so that the buffer areas can be used efficiently according to the usage state of buffer memory 122.
[0101] Also, embodiments of the present disclosure use logical memory addresses to load overlay code, so that multiple logical memory addresses can be used to efficiently load overlay code without degrading the usage efficiency of buffer memory 122.
[0102] FIGS. 8 to 10 are diagrams showing another example of a method for loading overlay code and non-overlay code stored in memory 110 into buffer memory 122 in storage device 100 according to embodiments of the present disclosure.
[0103] Referring to FIG. 8, the processor 121 of the controller 120 can pre-assign and set two or more occupied logical memory addresses lma for loading overlay code.
[0104] For example, the processor 121 can pre-assign and set a first occupied logical memory address lma1 and a second occupied logical memory address lma2 for loading one overlay code. The processor 121 can pre-assign and set a third occupied logical memory address lma3 and a fourth occupied logical memory address lma4 for loading another overlay code.
[0105] For loading one overlay code, two occupied logical memory addresses lma can be pre-assigned and set.
[0106] The occupied logical memory address lma may be in a state not connected to the buffer area of the buffer memory 122 before the overlay code is loaded. Only the occupied logical memory address 1ma is pre-assigned and set, and the buffer area of the buffer memory 122 may not be pre-assigned.
[0107] When the processor 121 is requested to load the first firmware code which is the overlay code, it can connect the first occupied logical memory address lma1 and the second occupied logical memory address lma2 to the second buffer area buf2 and the fourth buffer area buf4 included in the buffer memory 122 respectively.
[0108] The first firmware code may be loaded into the second buffer area buf2 and the fourth buffer area buf4.
[0109] When the use of the first firmware code is completed, the processor 121 can disconnect the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area. Alternatively, when the use of the first firmware code is completed, the processor 121 can maintain the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area.
[0110] In addition to the first occupied logical memory address lma1 and the second occupied logical memory address lma2, the third occupied logical memory address lma3 and the fourth occupied logical memory address lma4 are pre-assigned and set for the loading of the overlay code. Therefore, the processor 121 can maintain the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area even after the use of the first firmware code is completed.
[0111] As an example, referring to FIG. 9, when the loading of the second firmware code is requested after the first firmware code is loaded, the processor 121 can connect the third occupied logical memory address lma3 and the fourth occupied logical memory address lma4 to the sixth buffer area buf6 and the ninth buffer area buf9, respectively.
[0112] The processor 121 can load the second firmware code into the sixth buffer area buf6 and the ninth buffer area buf9 connected to the third occupied logical memory address lma3 and the fourth occupied logical memory address lma4.
[0113] For example, when the loading of the second firmware code is requested while the first firmware code is loaded and in use, the processor 121 can use the third occupied logical memory address lma3 and the fourth occupied logical memory address lma4 to load the second firmware code into the buffer memory 122.
[0114] Since the occupied logical memory address lma can be pre-allocated without being connected to a buffer area, multiple occupied logical memory addresses lma can be pre-allocated and used when loading the overlay code, thereby improving the loading efficiency of the overlay code.
[0115] In addition, the processor 121 can also determine whether the occupied logical memory address lma is used when loading the second firmware code based on the remaining capacity of the buffer area included in the buffer memory 122.
[0116] As an example, when the remaining capacity of the buffer area is equal to or greater than a preset value, the second firmware code can be loaded using the third occupied logical memory address lma3 and the fourth occupied logical memory address lma4 as in the previous example.
[0117] Alternatively, when the remaining capacity of the buffer area is smaller than a preset value, after the use of the first firmware code is completed, an operation of loading the second firmware code can be performed. In this case, the loading of the second firmware code may be executed using the first occupied logical memory address lma1 and the second occupied logical memory address lma2, or may be executed using the third occupied logical memory address lma3 and the fourth occupied logical memory address lma4.
[0118] As another example, when the second firmware code is requested to be loaded while the first firmware code is loaded and the use of the first firmware code is completed, the processor 121 can load the second firmware code into the buffer memory 122 using the third occupied logical memory address lma3 and the fourth occupied logical memory address lma4.
[0119] After the use of the first firmware code is completed, the processor 121 can maintain the connection between the first occupied logical memory addresses lma1 and lma2 and the buffer area. When the situation where the use of the first firmware code is requested occurs again, the processor 121 can use the first firmware code loaded in the buffer area connected to the first occupied logical memory addresses lma1 and lma2. The operation of reading the first firmware code from the memory 110 to load the first firmware code can be reduced.
[0120] The processor 121 can also determine whether to maintain the connection between the buffer area where the first firmware code is loaded and the occupied logical memory address lma based on the remaining capacity of the buffer area included in the buffer memory 122.
[0121] For example, when the remaining capacity of the buffer area is equal to or greater than a preset value, after the use of the first firmware code is completed, the processor 121 can maintain the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area. When the remaining capacity of the buffer area is less than the preset value, the processor 121 can release the connection between the first occupied logical memory address lma1 and the second occupied logical memory address lma2 and the buffer area. The buffer area where the first firmware code is loaded may be used to load other data.
[0122] In this way, by using a plurality of occupied logical memory addresses lma to load the overlay code, the loading efficiency of the overlay code is improved, and by controlling whether the connection between the plurality of occupied logical memory addresses lma and the buffer area is maintained according to the remaining capacity of the buffer area, efficient use of the buffer area becomes possible.
[0123] When the overlay code is loaded using a plurality of occupied logical memory addresses lma, the non-overlay code can be loaded using the non-occupied logical memory address nma.
[0124] As an example, referring to FIG. 10, the state where the use of the first firmware code loaded in the buffer area is completed is shown using the first occupied logical memory address lma1 and the second occupied logical memory address lma2. The state where the second firmware code loaded in the buffer area is in use is shown using the third occupied logical memory address lma3 and the fourth occupied logical memory address lma4.
[0125] When a non-overlay code load is requested, the processor 121 can allocate a non-occupied logical memory address nma other than the aforementioned occupied logical memory address lma for the non-overlay code load.
[0126] The processor 121 can, for example, assign a first non-occupied logical memory address nma1 and a second non-occupied logical memory address nma2. Each of the first non-occupied logical memory address nma1 and the second non-occupied logical memory address nma2 may be connected to the eighth buffer area buf8 and the tenth buffer area buf10 of the buffer memory 122. The third firmware code, which is non-overlay code, may be loaded into the eighth buffer area buf8 and the tenth buffer area buf10.
[0127] When the use of the first firmware code, which is overlay code, is completed and the non-overlay code is loaded, it is possible to control whether the buffer area in which the first firmware code is loaded is retained according to the remaining capacity of the buffer area.
[0128] As in the example shown in FIG. 10, when the third firmware code is loaded, if the remaining capacity of the buffer area is smaller than a preset value, the processor 121 can disconnect the connection between the buffer area in which the first firmware code is loaded and the occupied logical memory address 1ma. The processor 121 can delete the first firmware code loaded into the buffer area or manage it as invalid data.
[0129] When the remaining capacity of the buffer area is equal to or greater than the preset value, the processor 121 can maintain the connection between the buffer area in which the first firmware code is loaded and the occupied logical memory address lma. When the reuse of the overlay code is required without affecting the loading of other data into the buffer memory 122, the overlay code can be loaded without performing repeated reading from the memory 110.
[0130] The above description merely exemplarily explains the technical idea of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure pertains will be able to make various modifications and deformations without departing from the essential characteristics of the present disclosure. Also, the embodiments shown in the present disclosure do not limit the technical idea of the present disclosure but are for the purpose of explanation. Therefore, the scope of the technical idea of the present disclosure is not limited by these embodiments.
Claims
1. a first memory storing a plurality of codes, the plurality of codes including a plurality of overlay codes and a plurality of non-overlay codes, the plurality of non-overlay codes being used more frequently than at least one of the plurality of overlay codes; a second memory including a plurality of buffer areas into which the plurality of codes are loaded; and A storage device comprising: a controller that sets at least one pre-assigned exclusive logical memory address for loading the plurality of codes, and when loading a first overlay code, connects the first exclusive logical memory address to at least one of the plurality of buffer areas, and loads the first overlay code into the at least one buffer area connected to the first exclusive logical memory address.
2. The controller: The storage device according to claim 1 , further comprising: a storage unit that releases a connection between the first occupied logical memory address and the at least one buffer area when use of the first overlay code is completed.
3. The controller:
3. The storage device of claim 2, wherein after use of the first overlay code is completed, when loading a second overlay code, the first occupied logical memory address is connected to at least one of the plurality of buffer areas, and the second overlay code is loaded into the at least one buffer area connected to the first occupied logical memory address.
4. 4. The storage device of claim 3, wherein the at least one buffer area into which the first overlay code is loaded is different from the at least one buffer area into which the second overlay code is loaded.
5. The controller:
3. The storage device according to claim 2, further comprising: a setting of said first occupied logical memory address being maintained after said connection between said first occupied logical memory address and said at least one buffer area is released.
6. The controller:
2. The storage device according to claim 1, further comprising: a storage unit configured to store a first overlay code for storing a first overlay code, the first overlay code being stored in the first overlay code storage unit, the storage unit configured to store a second overlay code for storing the first overlay code, and a second overlay code configured to store the second overlay code.
7. The controller:
7. The storage device according to claim 6, wherein, when the second overlay code is loaded, the second overlay code is loaded into the at least one buffer area connected to the first occupied logical memory address.
8. The controller:
7. The storage device according to claim 6, further comprising: a storage unit that releases a connection between the first occupied logical memory address and the at least one buffer area when the remaining capacity of the plurality of buffer areas in the second memory is smaller than a previously set value.
9. The controller:
2. The storage device of claim 1, wherein when a second overlay code is loaded while the first overlay code is in use, a second exclusive logical memory address is connected to at least one of the plurality of buffer areas, and the second overlay code is loaded into the at least one buffer area connected to the second exclusive logical memory address.
10. The controller:
10. The storage device of claim 9, further comprising: a storage device that maintains a connection between the first occupied logical memory address and the at least one buffer area when the remaining capacity of the plurality of buffer areas in the second memory is equal to or greater than a previously set value while the use of the first overlay code is completed and the second overlay code is being used.
11. The controller:
2. The storage device according to claim 1, wherein, when loading at least one of the plurality of non-overlay codes, a non-occupied logical memory address other than the at least one occupied logical memory address is assigned, the non-occupied logical memory address is connected to at least one of the plurality of buffer areas, and the at least one non-overlay code is loaded into the at least one buffer area connected to the non-occupied logical memory address.
12. The storage device according to claim 11 , wherein the occupied logical memory addresses are fixed and the unoccupied logical memory addresses are variable.
13. 2. The storage device of claim 1, wherein the at least one buffer area into which the first overlay code is loaded at a first time point is different from the at least one buffer area into which the first overlay code is loaded at a second time point.
14. a buffer memory including a plurality of buffer areas into which a plurality of codes are loaded; and A controller comprising a processor that sets at least one occupied logical memory address pre-assigned for loading the plurality of codes, and when loading a first code, connects the first occupied logical memory address to at least one of the plurality of buffer areas, and loads the first code into the at least one buffer area connected to the occupied logical memory address.
15. The processor, 15. The controller of claim 14, further comprising: a controller for loading the second code into the at least one buffer area connected to the first occupied logical memory address when the second code is loaded after use of the first code is completed.
16. The processor, 15. The controller of claim 14, wherein when a second code is loaded while the first code is in use, a second occupied logical memory address is connected to at least one of the plurality of buffer areas, and the second code is loaded into the at least one buffer area connected to the second occupied logical memory address.
17. The processor, 15. The controller of claim 14, wherein when loading a third code, a non-occupied logical memory address other than the at least one occupied logical memory address is connected to at least one of the plurality of buffer areas, and the third code is loaded into the at least one buffer area connected to the non-occupied logical memory address.
18. 15. The controller of claim 14, wherein the first occupied logical memory address used to load the first code is fixed and the at least one buffer area into which the first code is loaded is variable.
19. A controller that pre-allocates and sets at least one dedicated logical memory address used for loading a plurality of overlay codes, and when loading at least one of the plurality of overlay codes, loads the at least one overlay code into at least one first buffer area connected to the at least one dedicated logical memory address.
20. 20. The controller of claim 19, wherein when loading non-overlay code, a non-occupied logical memory address other than the at least one occupied logical memory address is used to load the non-overlay code into at least one second buffer area connected to the non-occupied logical memory address.