Protection circuit and semiconductor device with protection circuit

Abstract

To provide a protection circuit, etc., capable of protecting a protection target from application of a power supply voltage of reverse polarity.SOLUTION: A protection circuit 20A is formed in a semiconductor substrate 50 including in at least a portion a triple well structure including a substrate region 510, a partition wall region 531 and a well region 541 and protects a protected circuit from application of a power supply voltage of reverse polarity with respect to a normal state. The protected circuit includes a noise generation source and is connected with a GND terminal 2 via the protection circuit 20A between a VDD terminal and the GND terminal 2. The protection circuit 20A comprises: a first protection transistor (Tr) including a source and a back gate connected with a nodal point with a first circuit and a second protection Tr including a source and a back gate connected with a nodal point which is connected with a second circuit while being non-connected with the first circuit. The partition wall region in the substrate region 510 or the substrate region 510 is connected with a drain D of the protection Tr formed in the well region in the partition wall region.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a protection circuit and a semiconductor device including the protection circuit.

Background Art

[0002] A power supply device (for example, a secondary battery, etc.) that supplies power to a semiconductor device may apply a power supply voltage with a polarity opposite to the polarity applied in a steady state (hereinafter simply referred to as "reverse polarity") due to reverse connection of a connector, noise, etc. A general semiconductor device is configured to include a parasitic diode that is forward-biased with respect to a reverse-polarity power supply voltage. Therefore, when a reverse-polarity power supply voltage is applied to a semiconductor device that does not consider the application of a reverse-polarity power supply voltage, an excessive forward current flows through the parasitic diode, and the elements constituting the semiconductor device may be damaged. From the viewpoint of preventing damage to elements caused by the application of such a reverse-polarity power supply voltage, a technique for protecting an integrated circuit has been disclosed (see, for example, Patent Document 1).

[0003] The protection circuit to which the technique disclosed in Patent Document 1 is applied has an NPN bipolar transistor including a base connected to a VCC terminal that supplies a power supply voltage VCC (≠0V) via a resistor, a collector connected to an internal circuit to be protected (hereinafter referred to as "protection target" or "protected circuit"), and an emitter connected to a GND terminal that supplies a power supply voltage of 0V.

[0004] In a state where a reverse-polarity power supply voltage is not applied, that is, in a steady state where the power supply voltage VCC is a positive voltage (VCC>0), if the power supply voltage VCC is sufficiently higher than the forward voltage Vf of the base-emitter junction diode of the NPN bipolar transistor, the current driving force increases and the collector-emitter voltage can be regarded as substantially 0V. Therefore, in a steady state, the internal circuit can be regarded as being directly connected to the GND terminal.

[0005] On the other hand, in a state where a reverse-polarity power supply voltage is applied, that is, in a power supply reverse connection state where the power supply voltage VCC is a negative voltage (VCC < 0), the base voltage follows the power supply voltage VCC and the base current stops flowing. For this reason, the NPN bipolar transistor included in the protection circuit enters a cut-off state, and the collector current is cut off. By cutting off the collector current, it is possible to cut off an excessive forward current passing through a parasitic diode that causes element damage when the internal circuit is directly connected to the GND terminal. As a result, it is possible to protect the protected object from element damage caused by the application of a reverse-polarity power supply voltage.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] However, in a conventional protection circuit applying the technique disclosed in Patent Document 1 and a semiconductor device including the protection circuit, depending on the circuit configuration to be protected, there is room for improvement in that it may have an unfavorable influence on the object to be protected. For example, when the circuit to be protected is a circuit in which an analog circuit that handles a DC voltage or a continuous signal in the internal circuit, a switching power supply, a charge pump, or a digital circuit that handles a discrete signal in which a large current flows with a switching operation are mixed, in a steady state, the collector voltage fluctuates due to the current flowing from the digital circuit or the DCDC converter to the NPN bipolar transistor. The fluctuation of the collector voltage becomes noise in the analog circuit and has an unfavorable influence on the signal processing of the analog circuit.

[0008] In order to reduce the noise of an analog circuit, the NPN bipolar transistor included in the protection circuit can be changed to an NPN bipolar transistor having a higher current driving force. However, the area of the bipolar transistor tends to increase as the current driving force increases. Therefore, the application of an NPN bipolar transistor having a high current driving force leads to an increase in the area of the protection circuit and thus an increase in cost.

[0009] The present invention has been made in consideration of the above-described circumstances, and an object thereof is to provide a protection circuit capable of protecting a protected object from the application of a reverse-polarity power supply voltage while suppressing an increase in cost and an unfavorable influence on the protected object, and a semiconductor device including the protection circuit.

Means for Solving the Problems

[0010] The protection circuit according to an embodiment of the present invention is formed on a semiconductor substrate having at least a part of a triple well structure including a substrate region of a first conductivity type, a partition region formed in the substrate region and including a semiconductor region of a second conductivity type at least in part, and a well region of the first conductivity type formed inside the partition region. The protection circuit protects a circuit to be protected from the application of a power supply voltage of a polarity opposite to the steady state. The circuit to be protected includes a noise source and includes a first circuit between a first power supply terminal and a second power supply terminal, the first circuit being connected to the second power supply terminal via the protection circuit, and a second circuit connected in parallel with the first circuit between the first power supply terminal and the second power supply terminal via the protection circuit. On the other hand, the protection circuit includes a first protection transistor including a drain connected to the second power supply terminal, a gate receiving a supply of a first control voltage, and a source and a back gate connected to the first circuit, a drain connected to the drain of the first protection transistor, a gate receiving a supply of a second control voltage, and a source and a back gate that are not connected to a connection point between the source and the back gate of the first protection transistor and the first circuit and are connected to the second circuit. At least one of the first protection transistor and the second protection transistor is formed in the well region, and the drain of the protection transistor formed in the well region is connected to either the semiconductor region or the substrate region included in the partition region surrounding the well region. The semiconductor device according to an embodiment of the present invention includes the above protection circuit.

Advantages of the Invention

[0011] According to the present invention, it is possible to protect a protection target from the application of a power supply voltage of a polarity opposite to the steady state while suppressing an increase in cost and an unfavorable influence on the protection target.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0013] Hereinafter, a circuit in which a circuit including a noise source and a circuit that can be affected by noise are mixed is given as an example of a protection target, that is, a circuit to be protected, which is protected by a protection circuit according to an embodiment of the present invention. The protection circuit according to the embodiment of the present invention and a semiconductor device including the protection circuit will be described with reference to the accompanying drawings.

[0014] [First Embodiment] FIG. 1 is a circuit diagram of a semiconductor device 10A including a protection circuit 20A, which is an example of a semiconductor device including a protection circuit according to the first embodiment. FIG. 2(A) is a circuit diagram showing a current source 171, which is a first configuration example of the load 17, and FIGS. 2(B) and 2(C) are circuit diagrams showing the first configuration example and the second configuration example of the current source 171, respectively.

[0015] Referring to FIG. 1, the protection circuit 20A and the semiconductor device 10A will be described. The semiconductor device 10A includes an analog circuit 11, a digital circuit 12, a protection circuit 20A, and a step-down circuit 15. The analog circuit 11, the digital circuit 12, the protection circuit 20A, and the step-down circuit 15 constitute a semiconductor integrated circuit formed on a semiconductor substrate.

[0016] Here, the digital circuit 12 as the first circuit generally has larger current fluctuations and maximum values during operation than the analog circuit 11 because it handles switching power supplies, charge pumps, and discrete signals in which a large current flows due to the switching operation. Therefore, in the description of the present embodiment, the digital circuit 12 is assumed to include a noise source.

[0017] Further, the analog circuit 11 as the second circuit is a circuit that can be affected by noise. When no noise countermeasures are taken, the analog circuit 11 is affected by the noise generated by the noise source. However, in the semiconductor device 10A configured to be able to suppress the influence of the noise generated by the noise source, as will be described later, the analog circuit 11 can operate stably. Furthermore, the analog circuit 11 and the digital circuit 12 are protection targets that the protection circuit 20A protects from the application of a power supply voltage with a reverse polarity to the steady state, that is, circuits to be protected by the protection circuit 20A.

[0018] The analog circuit 11, the digital circuit 12, and the step-down circuit 15 each have a first end connected to a VDD terminal 1 that supplies a voltage VDD, which is an example of a power supply voltage, and a second end connected to a GND terminal 2 that supplies a voltage GND, which is another example of a power supply voltage when not passing through the protection circuit 20A. The analog circuit 11, the digital circuit 12, and the step-down circuit 15 each have their second ends connected to the protection circuit 20A and are connected to the GND terminal 2 via the protection circuit 20A. Here, the connection point between each first end of the analog circuit 11, the digital circuit 12, and the step-down circuit 15 and the VDD terminal 1 is referred to as a node N1.

[0019] The step-down circuit 15 as a gate voltage control circuit has, for example, a depletion-type NMOS transistor 16, a load 17, and an output terminal 15o connected to the connection point of the depletion-type NMOS transistor 16 and the load 17. The second end, which is the other end of the load 17 with respect to the first end connected to the depletion-type NMOS transistor 16 and the output terminal 15o, is connected to the second end of the analog circuit 11. Here, the connection point between the load 17 and the analog circuit 11 is referred to as a node N2. The step-down circuit 15 having the depletion-type NMOS transistor 16 is a so-called source follower that further has an input terminal 15i connected to the gate of the depletion-type NMOS transistor 16.

[0020] Here, with reference to FIGS. 2(A) to 2(C), a configuration example of the load 17 will be described. The load 17 is, for example, a current source 171 that supplies a constant current I1 in the direction from the node N5 to the node N2 as shown in FIG. 2(A). The current source 171 is configured to have, for example, a depletion-type NMOS transistor 31 with its gate and source connected (see FIG. 2(B)), or to have a current source 33 that supplies a constant current I2 to the drain of the NMOS transistor 322 and a current mirror circuit 32 (see FIG. 2(C)).

[0021] The current mirror circuit 32 is configured to include, for example, an NMOS transistor 321 and an NMOS transistor 322 including a gate connected to the gate and the own drain of the NMOS transistor 321. The current mirror circuit 32 causes a constant current I1 (= mI2) obtained by copying a constant current I2 at a predetermined mirror ratio m (m is an arbitrary positive number) to flow through the drain of the NMOS transistor 321.

[0022] Returning to FIG. 1, the protection circuit 20A will be described. The protection circuit 20A includes an NMOS transistor 21 connected between the analog circuit 11 and the GND terminal 2, and an NMOS transistor 22 connected between the digital circuit 12 and the GND terminal 2.

[0023] The NMOS transistor 21 as the second protection transistor includes, for example, a source and a back gate connected to the node N2 in addition to the drain and the gate. The node N2 is a reference node for the analog circuit 11.

[0024] The NMOS transistor 22 as the first protection transistor includes, for example, a drain connected to the drain of the NMOS transistor 21, a gate connected to the gate of the NMOS transistor 21, and a source and a back gate connected to the node N3. The node N3 is a reference node for the digital circuit 12.

[0025] The drain of the NMOS transistor 21 and the drain of the NMOS transistor 22 are connected. Here, the connection point of the drain of the NMOS transistor 21 and the drain of the NMOS transistor 22 is referred to as the node N4. The node N4 is connected to the GND terminal 2. A node N5, which is the connection point of the gate of the NMOS transistor 21 and the gate of the NMOS transistor 22, is connected to the output terminal 15o of the step-down circuit 15.

[0026] FIG. 3 is a cross-sectional view of the protection circuit 20A. The protection circuit 20A is formed on the semiconductor substrate 50 as a semiconductor integrated circuit. The semiconductor substrate 50 has at least a part of a so-called triple well structure. For example, the semiconductor substrate 50 in the semiconductor device 10A includes a P-type substrate region 510 as the first conductivity type, partition regions (described as "Nwell (NBL)" in the figure) 531 and 532 which are N-type well regions as the second conductivity type, and a triple well structure including P-type well regions 541 and 542 as the first conductivity type.

[0027] The partition regions 531 and 532 are formed in the substrate region 510. The well region 541 is formed inside surrounded by the partition region 531. The well region 542 is formed inside surrounded by the partition region 532. NMOS transistors 21 and 22 are respectively formed in the well regions 541 and 542. The gate G of the NMOS transistor 21 is provided via an insulating layer 551 with the well region 541. The gate G of the NMOS transistor 22 is provided via an insulating layer 552 with the well region 542.

[0028] Here, the partition regions 531 and 532, and the drains D and sources S of the NMOS transistors 21 and 22 are formed with a higher impurity concentration (N+) with respect to an N-type semiconductor region (not shown in the figure) among N-type semiconductor regions. The back gates B of the NMOS transistors 21 and 22 are formed with a higher impurity concentration (P+) with respect to the substrate region 510 and the well regions 541 and 542.

[0029] The drain D of the NMOS transistor 21 is connected to the partition region 531. The drain D of the NMOS transistor 22 is connected to the partition region 532. The connection point of the drain D of the NMOS transistor 21 and the partition region 531 is connected to the connection point of the drain D of the NMOS transistor 22 and the partition region 532, forming a node N4.

[0030] Next, the operations of the protection circuit 20A and the semiconductor device 10A will be described. In describing the operations of the protection circuit 20A and the semiconductor device 10A, it is assumed that the analog circuit 11 and the digital circuit 12 are circuits that conduct a reverse leakage current through parasitic diodes in a state where the protection circuit 20A is not connected and a negative voltage is applied to the VDD terminal 1, that is, in a state where a power supply voltage of the opposite polarity to the steady state is applied.

[0031] First, in the case where a positive voltage is applied to the VDD terminal 1, that is, in the steady state, the current flowing inside the analog circuit 11 flows in the direction from the node N1 to the node N2, and the current flowing inside the digital circuit 12 flows in the direction from the node N1 to the node N3. The step-down circuit 15 supplies the gate voltage Vg of the NMOS transistor 22 as the first control voltage and the gate voltage Vg of the NMOS transistor 21 as the second control voltage to the gates of the respective NMOS transistors 21 and 22.

[0032] When controlling the NMOS transistor 21 and the NMOS transistor 22 by the step-down circuit 15 using the source follower illustrated in FIG. 1, the bias voltage Vbias, which is the gate voltage of the depletion-type NMOS transistor 16 that is the step-down transistor, that is, the voltage input to the input terminal 15i, may be appropriately set so that the voltage of the node N5, which is each gate voltage Vg, becomes higher than the threshold voltage Vth1 of the NMOS transistor 21 and the threshold voltage Vth2 of the NMOS transistor 22.

[0033] When the NMOS transistor 21 and the NMOS transistor 22 are on and currents are flowing from their respective sources (nodes N2 and N3) toward the drains (node N4), using the bias voltage Vbias, the gate-source voltage Vgs of the depletion-type NMOS transistor 16, and the threshold voltage Vth_sf of the depletion-type NMOS transistor 16, the gate voltage Vg is given by the following equations (1) and (2), respectively Vg = Vbias - Vgs ≒ Vbias - Vth_sf > Vth1 ···(1) Vg = Vbias - Vgs ≒ Vbias - Vth_sf > Vth2 ···(2) The bias voltage Vbias is set so as to satisfy the relationship shown in

[0034] When applying a depletion-type transistor to the step-down transistor, since the threshold voltage Vth_sf becomes negative, the gate voltage Vg can be set to be equal to or higher than the bias voltage Vbias (Vg ≧ Vbias). That is, by applying a depletion-type transistor such as the depletion-type NMOS transistor 16 to the step-down transistor, it becomes easier to turn on the NMOS transistor 21 and the NMOS transistor 22.

[0035] Also, for the stable operation of the analog circuit 11 and the digital circuit 12, it is desirable to operate the nodes N2 and N3 at voltages close to the voltage GND. In this case, the NMOS transistors 21 and 22 as protection transistors operate in a resistance region where the drain-source voltage is close to 0V. Therefore, the current flowing from the VDD terminal 1 to the node N2 flows to the GND terminal 2 through the on-resistance of the NMOS transistor 21. The current flowing from the VDD terminal 1 to the node N3 flows to the GND terminal 2 through the on-resistance of the NMOS transistor 22.

[0036] Here, when the NMOS transistors 21 and 22 operate in a resistance region where the drain-source voltage is close to 0V, the voltage Vint_gnd1_ope of the node N2 can be expressed by Equation (3) using the resistance value of the on-resistance of the NMOS transistor 21 as Ron21 and the current value of the current flowing from the node N2 to the node N4 as Iope_gnd1. Also, the voltage Vint_gnd2_ope of the node N3 can be expressed by Equation (4) using the resistance value of the on-resistance of the NMOS transistor 22 as Ron22 and the current value of the current flowing from the node N3 to the node N4 as Iope_gnd2. Vint_gnd1_ope = Ron21 × Iope_gnd1 ···(3) Vint_gnd2_ope = Ron22 × Iope_gnd2 ···(4)

[0037] When the NMOS transistor 22 is separated from the NMOS transistor 21 by being formed in the well region 542 within the partition region 532 as in the protection circuit 20A illustrated in FIGS. 1 and 3, the current from the digital circuit 12 flows into the NMOS transistor 22 via the node N3. The variation in the current from the digital circuit 12 is converted into a voltage variation at the source S by the on-resistance (resistance value Ron22) of the NMOS transistor 22.

[0038] At this time, the voltage of the well region 542, which is the back gate B of the NMOS transistor 22, also varies. Here, when the direction from the well region 542 to the substrate region 510 is defined as the forward direction, the voltage variation of the well region 542 propagates to the partition region 532 via the parasitic diode 561 biased in the forward direction between the well region 542 and the partition region 532. However, since the parasitic diode 562 between the partition region 532 and the substrate region 510 forming the junction surface is biased in the reverse direction, the propagation of the voltage variation of the well region 542, that is, the noise to the substrate region 510, is blocked.

[0039] Subsequently, when a negative voltage is applied to the VDD terminal 1, that is, when a power supply voltage with a polarity opposite to the steady state is applied, in the analog circuit 11, a reverse current flows from the node N2 to the node N1 via the parasitic diode. In the digital circuit 12, a reverse current flows from the node N3 to the node N1 via the parasitic diode. At this time, the gate voltages Vg of the NMOS transistors 21 and 22, the voltage Vint_gnd1_ope of the node N2, and the voltage Vint_gnd2_ope of the node N3 decrease following the voltage of the VDD terminal 1. As a result, the gate-source voltage of the NMOS transistor 21 falls below the threshold voltage Vth1 and turns off. The gate-source voltage of the NMOS transistor 22 falls below the threshold voltage Vth2 and turns off.

[0040] Focusing on the cross-sectional structure, when a negative voltage is applied to the VDD terminal 1, the voltages of the well regions 541 and 542 and the substrate region 510 become equal to or lower than the voltage GND of the GND terminal 2, and are lower than the voltages of the partition regions 531 and 532. Therefore, parasitic diodes (not shown) between the well region 541 and the partition region 531, parasitic diodes (not shown) between the partition region 531 and the substrate region 510, a parasitic diode 561 between the well region 542 and the partition region 532, and a parasitic diode 562 between the partition region 532 and the substrate region 510 are all biased in the reverse direction. In short, when a negative voltage is applied to the VDD terminal 1, all the parasitic diodes formed in the triple-well structure including the well regions 541 and 542, the partition regions 531 and 532, and the substrate region 510 are reverse-biased, so the reverse current is blocked.

[0041] As described above, according to the protection circuit 20A and the semiconductor device 10A, since the protection circuit 20A has the NMOS transistors 21 and 22, the analog circuit 11 and the digital circuit 12 can be protected from the application of power supply voltages of opposite polarities.

[0042] More specifically, by satisfying at least one of forming the NMOS transistor 21 in the well region 541 in the partition region 531 and forming the NMOS transistor 22 in the well region 542 in the partition region 532, the nodes N2 and N3 are physically and electrically separated by the partition regions 531 and 532. Therefore, the semiconductor device 10A can suppress an increase in cost while suppressing an adverse influence of noise from a noise source. That is, according to the protection circuit 20A and the semiconductor device 10A, the voltage fluctuation represented by the above formula (4) can be blocked from propagating from the digital circuit 12 to other circuits such as the analog circuit 11.

[0043] Also, in a state where a negative voltage is applied to the VDD terminal 1, all the parasitic diodes formed in the triple-well structure including the well regions 541 and 542, the partition regions 531 and 532, and the substrate region 510 are reverse-biased, so the reverse current can be blocked.

[0044] Furthermore, according to the protection circuit 20A and the semiconductor device 10A, as can be understood from the above formulas (3) and (4), by adjusting the resistance values of the on-resistances of the NMOS transistors 21 and 22 to appropriate values, the voltage drop from the node N2 to the node N4 and the voltage drop from the node N3 to the node N4 can be adjusted individually. That is, according to the protection circuit 20A and the semiconductor device 10A, the degree of freedom in circuit design in the protection circuit 20A and the semiconductor device 10A can be increased. Note that the adjustment of the resistance values of the on-resistances of the NMOS transistors 21 and 22 may be appropriately selected from several methods such as changing the aspect ratios of the NMOS transistors 21 and 22.

[0045] [Second Embodiment] The protection circuit according to the second embodiment of the present invention and the semiconductor device including the protection circuit are different from the protection circuit according to the first embodiment and the semiconductor device including the protection circuit in that the drain of the formed protection transistor is connected to the substrate region and the partition region is not connected to any terminal, that is, it is floating, but there is no substantial difference in other respects. In other words, the protection circuit according to the second embodiment and the semiconductor device including the protection circuit have no substantial difference in circuit configuration from the protection circuit according to the first embodiment and the semiconductor device including the protection circuit, and the connection relationship between the protection transistor and the semiconductor substrate is different. Therefore, in the present embodiment, the description will be centered on the above-described differences, and redundant descriptions of points that are not substantially different will be omitted.

[0046] FIG. 4 is a cross-sectional view of a semiconductor device 10B including a protection circuit 20B, which is an example of a semiconductor device including the protection circuit according to the second embodiment.

[0047] The semiconductor device 10B is different from the semiconductor device 10A in that it includes a protection circuit 20B with respect to the protection circuit 20A, but is substantially the same in other respects. Also, the protection circuit 20B is different from the protection circuit 20A in that the connection destination of the drain D of the NMOS transistor 21 formed in the well region 541, the connection destination of the drain D of the NMOS transistor 22 formed in the well region 542, and the partition regions 531 and 532 are floating, but are substantially the same in other respects.

[0048] In the protection circuit 20B, the drain D of the NMOS transistor 21 is connected to a connection terminal 571 that is electrically connected to the substrate region 510. The drain D of the NMOS transistor 22 is connected to a connection terminal 572 that is electrically connected to the substrate region 510. The connection terminals 571 and 572 are regions formed in the substrate region 510 with a high impurity concentration (P+) with respect to the substrate region 510 and the well regions 541 and 542. On the other hand, the partition regions 531 and 532 are in a state of not being connected to any terminal, that is, floating.

[0049] Subsequently, the operations of the protection circuit 20B and the semiconductor device 10B will be described. In describing the operations of the protection circuit 20B and the semiconductor device 10B, it is assumed that there is no circuit that takes the voltage of the substrate region 510 as a reference, and the content that is substantially the same as the operations of the protection circuit 20A and the semiconductor device 10A will be omitted.

[0050] Assuming that there is no circuit in the semiconductor device 10B that takes the voltage of the substrate region 510 as a reference, in the protection circuit 20B and the semiconductor device 10B, the well regions 541 and 542 are connected to the GND terminal 2 via the NMOS transistors 21 and 22. Also, the substrate region 510 (more specifically, the connection terminals 571 and 572) is connected to the GND terminal 2, and the partition regions 531 and 532 are floating.

[0051] When the protection circuit 20B and the semiconductor device 10B are connected in this way, in the steady state, similar to the protection circuit 20A and the semiconductor device 10A, the NMOS transistors 21 and 22 can be turned on to secure a current path. On the other hand, when a power supply voltage with a polarity opposite to the steady state is applied, parasitic diodes (not shown) between the well regions 541 and 542 and the partition regions 531 and 532 or parasitic diodes (not shown) between the partition regions 531 and 532 and the substrate region 510 are reverse-biased. Therefore, similar to the protection circuit 20A and the semiconductor device 10A, the reverse-biased parasitic diodes block the reverse current.

[0052] As described above, according to the protection circuit 20B and the semiconductor device 10B, the same effects as those of the protection circuit 20A and the semiconductor device 10A can be obtained. That is, the analog circuit 11 and the digital circuit 12 can be protected from the application of a power supply voltage with a reverse polarity. The degree of freedom in circuit design in the protection circuit 20B and the semiconductor device 10B can be increased.

[0053] Furthermore, according to the protection circuit 20B and the semiconductor device 10B, since the substrate region 510 is connected to the GND terminal 2, the substrate region 510 can be used stably. Also, when an integrated circuit (IC) including the protection circuit 20B is encapsulated in a package with a soldered surface on the back, the workability of the electrical connection test between the package and the IC or between the package and the mounting substrate can be improved.

[0054] It should be noted that the present invention is not limited to the above-described embodiments as they are. At the implementation stage, it can be implemented in various forms other than the above-described examples, and various omissions, additions, replacements, or changes can be made without departing from the gist of the invention.

[0055] The protection circuit according to this embodiment and the semiconductor device including the protection circuit are, for example, in the protection circuit 20A and the semiconductor device 10A, the partition regions 531 and 532 are connected to the drain of the NMOS transistor 21 and the drain of the NMOS transistor 22, that is, the node N4, respectively, but are not limited thereto. One of the partition regions 531 and 532 in the protection circuit 20A and the semiconductor device 10A may be floating, and the other of the partition regions 531 and 532 may be connected to the node N4. In the protection circuit 20B and the semiconductor device 10B, it is not necessary for both of the connection terminals 571 and 572 to be formed, and at least one of them may be formed. That is, it is sufficient that one of the connection terminals 571 and 572 is connected to the GND terminal 2, and the other of the connection terminals 571 and 572 may be omitted. Also, as shown in FIGS. 5 to 11 described later, it may be modified.

[0056] FIGS. 5, 6, and 7 are cross-sectional views showing a semiconductor device 10C which is a first modification, a semiconductor device 10D which is a second modification, and a semiconductor device 10E which is a third modification of the semiconductor device according to the first embodiment, respectively. The X-axis, Y-axis, and Z-axis shown in FIG. 7 are three axes in a three-dimensional orthogonal coordinate system. In the present embodiment, the X-axis direction, Y-axis direction, and Z-axis direction correspond to the horizontal direction, vertical direction, and depth direction, respectively.

[0057] The protection circuit and the semiconductor device according to this embodiment may be, for example, a protection circuit 20C and a semiconductor device 10C in which the partition region 532 and the well region 542 are omitted (see FIG. 5) with respect to the protection circuit 20A and the semiconductor device 10A, or a protection circuit 20D and a semiconductor device 10D in which the partition region 531 and the well region 541 are omitted (see FIG. 6). Since the protection circuit 20C and the semiconductor device 10C and the protection circuit 20D and the semiconductor device 10D also act in the same manner as the protection circuit 20A and the semiconductor device 10A, the same effects as those of the protection circuit 20A and the semiconductor device 10A can be obtained.

[0058] Furthermore, the protection circuit and semiconductor device according to the present embodiment may omit the partition region 532 and well region 542, or the partition region 531 and well region 541, with respect to the protection circuit 20B and semiconductor device 10B described above. For the protection circuit and semiconductor device obtained by omitting the partition region 532 and well region 542, or the partition region 531 and well region 541, with respect to the protection circuit 20B and semiconductor device 10B, the same effects as those of the protection circuit 20B and semiconductor device 10B can be obtained.

[0059] The protection circuit and semiconductor device according to the present embodiment may be configured to include partition regions 561 and 562 instead of the partition regions 531 and 532, with respect to the protection circuit 20A and semiconductor device 10A described above, or with respect to the protection circuit 20B and semiconductor device 10B. The partition regions 561 and 562 are the same in that they each include Nwells 561a and 562a, respectively, with respect to the partition regions 531 and 532, but are different in that they partially include an insulator.

[0060] The partition region 561 includes, in part, a region composed of an N-type semiconductor, for example, in a direction along the horizontal direction, that is, at substantially the same depth, an NWell 561a having a predetermined width in the depth direction is formed. The NWell 561a is connected to a trench 561b and a trench 561c, which are insulators, at both ends thereof. The trench 561b and the trench 561c are formed of an oxide, which is an example of an insulator such as SiO2. The partition region 562 is configured in the same manner as the partition region 561.

[0061] Note that, in the example where the partition regions 561 and 562 shown in FIG. 7 have the NWell 561a uniformly formed at substantially the same depth, the position and size of the NWell 561a are not limited to the illustrated locations. In the partition regions 561 and 562, the NWells 561a and 562a may be included in at least a part of any one of a first part which is a region on the side where X is small, a second part which is a region on the side where X is large, and a third part which is a region extending in the direction along the lateral direction among the regions extending in the direction along the depth direction. That is, any one of the first region, the second region, and the third region may be formed to include the NWell 561a and an insulator.

[0062] Also, in the partition regions 561 and 562, for example, one of the first region and the second region may be formed of the NWells 561a and 562a, and the other of the first region and the second region and the third region may be formed of an insulator. Further, the insulator included in the partition regions 561 and 562 may be of any type of substance as long as it is an insulator applicable in the semiconductor manufacturing process. For example, the trench 561b or the trench 561c may be formed to include a portion of air which is an example of an insulator, that is, may be formed to include merely a groove. Furthermore, although the N-type semiconductor regions included in the partition regions 561 and 562 illustrated in FIG. 7 are floating, they may be connected to the node N4.

[0063] Also, the step-down circuit 15 described above has the current source 171 as an example of the load 17, but instead of the current source 171, it may be configured to have an I / V conversion circuit 173 (see FIGS. 8(A) to 8(C)) that converts current into voltage.

[0064] FIGS. 8(A) to 8(C) are circuit diagrams showing a second configuration example to a fourth configuration example of the load 17, respectively.

[0065] In the above-described embodiments, as an example of the I / V conversion circuit 17, a resistance element 173a may be applied as the load 17 (see the second configuration example: FIG. 8(A)), a Zener diode 173b may be applied (see the third configuration example: FIG. 8(B)), or a transistor circuit 173c including at least one diode-connected MOS transistor 173c_1 may be applied (see the fourth configuration example: FIG. 8(C)). Note that the transistor circuit 173c is not limited to the case including one diode-connected MOS transistor 173c_1, and a plurality of diode-connected MOS transistors including the MOS transistor 173c_1 may be connected in series.

[0066] The above-described semiconductor devices 10A to 10E include the step-down circuit 15, but may include a step-down circuit 25 (see FIGS. 9(A) and 9(B)) instead of the step-down circuit 15.

[0067] FIG. 9(A) is a circuit diagram of the step-down circuit 25 having a current source 251, and FIG. 9(B) is a partial circuit diagram of the step-down circuit 25 having a resistance element 252 instead of the current source 251. FIG. 10(A) is a circuit diagram showing a first configuration example of the current source 251, and FIG. 10(B) is a circuit diagram showing a second configuration example of the current source 251.

[0068] In the above-described embodiments, as illustrated in FIG. 9(A), the step-down circuit 25 has a current source 251 instead of the depletion-type NMOS transistor 16 with respect to the step-down circuit 15, has an I / V conversion circuit 250 instead of the load 17, and further has an output terminal 25o corresponding to the output terminal 15o. The step-down circuit 25 may have a resistance element 252 instead of the current source 251 as partially illustrated in FIG. 9(B).

[0069] The current source 251 is configured to include, for example, a depletion-type NMOS transistor 51 having its gate and source connected (see FIG. 10(A)), or may be configured to include a current source 53 that supplies a constant current I4 to the drain of a PMOS transistor 522 and a current mirror circuit 52 (see FIG. 10(B)).

[0070] The current mirror circuit 52 is configured to include, for example, a PMOS transistor 521 having a gate connected to its own drain, and a PMOS transistor 522 having a gate connected to the gate and drain of the PMOS transistor 521. The current mirror circuit 52 causes a constant current I3 (= kI4), which is a copy of the constant current I4 at a predetermined mirror ratio k (k is an arbitrary positive number), to flow through the drain of the PMOS transistor 521.

[0071] Similar to the I / V conversion circuit 173 described above, the I / V conversion circuit 250 may be configured by applying a transistor circuit formed by connecting in series a resistance element, a Zener diode, a diode-connected MOS transistor, or a plurality of diode-connected MOS transistors.

[0072] Although the protection circuits 20A to 20E described above are examples that do not include the step-down circuit 15 or the step-down circuit 25, the protection circuits 20A to 20E are not limited to this example. The protection circuits 20A to 20E and the protection circuit 20F (see FIG. 11) described later may be further configured to include the step-down circuits 15, 25 or the step-down circuit 35 (see FIG. 11) described later.

[0073] Although the protection circuits 20A to 20E described above are examples in which the NMOS transistor 21 and the NMOS transistor 22 include a common gate, the gates of the NMOS transistor 21 and the NMOS transistor 22 do not have to be common. That is, the gates of the NMOS transistor 21 and the NMOS transistor 22 may be independent. When the gates of the NMOS transistor 21 and the NMOS transistor 22 are independent, a step-down circuit may be formed by combining the step-down circuit 15 and the step-down circuit 25 so as to be able to supply independent gate voltages.

[0074] FIG. 11 is a partial circuit diagram of a protection circuit 20F and a semiconductor device 10F which is an example of the protection circuit and the semiconductor device according to this embodiment. In FIG. 11, for the sake of clarity and simplicity, the illustration of the analog circuit 11 and the digital circuit 12 which are connected in the same manner as in FIG. 1 is omitted.

[0075] The semiconductor device 10F is different from the semiconductor device 10A in that it includes a protection circuit 20F instead of the protection circuit 20A and a step-down circuit 35 instead of the step-down circuit 15, but other points are not substantially different. The protection circuit 20F is different from the protection circuit 20A in that the gates of the NMOS transistor 21 and the NMOS transistor 22 form different (independent) nodes N5 and N6 respectively, but other points are not substantially different. The step-down circuit 35 as a gate voltage control circuit is a step-down circuit capable of outputting two independent voltages and has one step-down circuit 15 and one step-down circuit 25 as illustrated in FIG. 11.

[0076] Note that the step-down circuit 35 shown in FIG. 11 is an example in which the step-down circuit 25 that supplies voltage to the gate of the NMOS transistor 22 is connected between the node N1 and the node N2, but it is not limited thereto. The step-down circuit 25 that supplies voltage to the gate of the NMOS transistor 22 may be connected to the node N3 instead of the node N2. Also, the step-down circuit 35 shown in FIG. 10 is an example having one step-down circuit 15 and one step-down circuit 25, but it is not limited thereto. The step-down circuit 35 may have two step-down circuits 15 or two step-down circuits 25.

[0077] Note that the above-described protection circuits 20A to 20F and semiconductor devices 10A to 10F have the first conductivity type and the second conductivity type as P-type and N-type respectively, and the case where VDD is a positive voltage in the steady state is taken as an example for explanation. However, the conductivity type (P-type and N-type) of the semiconductor substrate 50, the polarities of the elements having polarities such as the NMOS transistors 21 and 22, and the polarities of the power supply voltages (positive and negative) may be interchanged to be the protection circuit and the semiconductor device according to this embodiment.

[0078] These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0079] 1 VDD terminal 2 GND terminal 10A to 10F semiconductor device 11 Analog circuit (second circuit) 12 Digital circuit (first circuit) 15, 25, 35 Step-down circuit (gate voltage control circuit) 15o, 25o Output terminals (of the step-down circuit) 20A to 20E Protection circuit 21 NMOS transistor (first protection transistor) 22 NMOS transistor (second protection transistor) 50 Semiconductor substrate 510 Substrate region 531, 532 Partition region 541, 542 Well region N2 Node N3 Node

Claims

1. A protection circuit is formed in a semiconductor substrate having at least a portion thereof a triple well structure including a substrate region of a first conductivity type, a partition region formed in the substrate region and including at least a semiconductor region of a second conductivity type, and a well region of the first conductivity type formed inside the partition region, the protection circuit protecting a protected circuit from application of a power supply voltage of a polarity opposite to that in a steady state, the protected circuit includes a noise generating source, and has a first circuit between a first power supply terminal and a second power supply terminal and connected to the second power supply terminal via the protection circuit, and a second circuit between the first power supply terminal and the second power supply terminal and connected in parallel to the first circuit via the protection circuit, the protection circuit includes a first protection transistor including a drain connected to the second power supply terminal, a gate receiving a first control voltage, and a source and a back gate connected to the first circuit; a second protection transistor including a drain connected to the drain of the first protection transistor, a gate receiving a second control voltage, and a source and a back gate not connected to a connection point between the source and back gate of the first protection transistor and the first circuit and connected to the second circuit; At least one of the first protection transistor and the second protection transistor is formed in the well region; A protection circuit, comprising: a protection transistor formed in the well region, the drain of which is connected to either the semiconductor region or the substrate region included in the partition region surrounding the well region.

2. A drain of a protection transistor formed in the well region is connected to the substrate region and is further connected to the second power supply terminal; 2. The protection circuit according to claim 1, wherein the partition region surrounding the well region in which the protection transistor is formed is a floating region that is not connected to any terminal.

3. 2. The protection circuit according to claim 1, wherein a drain of the protection transistor formed in the well region is connected to the partition region surrounding the well region, and is further connected to the second power supply terminal.

4. 4. The protection circuit according to claim 1, further comprising a common node formed by connecting a gate of the second protection transistor and a gate of the first protection transistor.

5. 5. The protection circuit according to claim 4, further comprising a gate voltage control circuit having an output terminal that outputs the one predetermined voltage as the first control voltage and the second control voltage, the gate voltage control circuit being connected between the first power supply terminal and a connection point between the source and back gate of the second protection transistor and the second circuit.

6. a gate voltage control circuit connected between the first power supply terminal and a connection point between the source and back gate of the second protection transistor and the second circuit; 4. The protection circuit according to claim 1, wherein the gate voltage control circuit has a first output terminal for outputting the first control voltage and a second output terminal for outputting the second control voltage.

7. a gate voltage control circuit that outputs the first control voltage and the second control voltage; the gate voltage control circuit is provided between the first power supply terminal and a connection point between the source and back gate of the first protection transistor and the first circuit, and includes a first output terminal that outputs the first control voltage; a second output terminal that is provided between the first power supply terminal and a connection point between the source and back gate of the second protection transistor and the second circuit, and that outputs the second control voltage; 4. A protection circuit as claimed in claim 1, comprising:

8. a semiconductor integrated circuit formed on a semiconductor substrate having at least a portion thereof a triple well structure including a substrate region of a first conductivity type, a partition region formed in the substrate region and including at least a portion of a semiconductor region of a second conductivity type, and a well region of the first conductivity type formed inside the partition region, the semiconductor integrated circuit includes a protection circuit that protects a connected protected circuit from application of a power supply voltage of a polarity opposite to that of a steady state; the protected circuit includes a noise generating source, and has a first circuit between a first power supply terminal and a second power supply terminal and connected to the second power supply terminal via the protection circuit, and a second circuit between the first power supply terminal and the second power supply terminal and connected in parallel to the first circuit via the protection circuit, the protection circuit includes a first protection transistor including a drain connected to the second power supply terminal, a gate receiving a first control voltage, and a source and a back gate connected to the first circuit; a second protection transistor including a drain connected to the drain of the first protection transistor, a gate receiving a second control voltage, and a source and a back gate not connected to a connection point between the source and back gate of the first protection transistor and the first circuit and connected to the second circuit; At least one of the first protection transistor and the second protection transistor is formed in the well region; a drain of a protection transistor formed in the well region is connected to either the semiconductor region or the substrate region included in the partition region surrounding the well region, the drain of the protection transistor being connected to either the semiconductor region or the substrate region included in the partition region surrounding the well region.

9. the semiconductor integrated circuit further includes a gate voltage control circuit connected between the first power supply terminal and a connection point between the source and back gate of the second protection transistor and the second circuit, 9. The semiconductor device according to claim 8, wherein the gate voltage control circuit has an output terminal that outputs at least one of the first control voltage and the second control voltage.

10. the semiconductor integrated circuit further includes a gate voltage control circuit that outputs the first control voltage and the second control voltage; the gate voltage control circuit is provided between the first power supply terminal and a connection point between the source and back gate of the first protection transistor and the first circuit, and includes a first output terminal that outputs the first control voltage; a second output terminal that is provided between the first power supply terminal and a connection point between the source and back gate of the second protection transistor and the second circuit, and that outputs the second control voltage; The semiconductor device according to claim 8 , further comprising:

11. The semiconductor device according to claim 8 , wherein the semiconductor integrated circuit includes the circuit to be protected.

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