Control for secondary switch for achieving zero voltage switching

Abstract

To provide a method for using a secondary switch for enabling zero-voltage switching of the secondary switch in a flyback converter.SOLUTION: A method relates to zero-voltage switching (ZVS) of a secondary switch (e.g., a synchronous rectifier) in a flyback converter. The method causes a secondary control device to enable dynamic calculation of a secondary switch hold time required to achieve the ZVS of a primary switch during a switching cycle and thereby to determine the required secondary switch hold time without requiring communication from a primary side to a secondary side by measuring the charge time and discharge time during the switching cycle.SELECTED DRAWING: Figure 3A

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 607,960, filed on December 8, 2023, which is hereby incorporated by reference in its entirety.

[0002]

[0002] The present invention relates to zero - voltage switching with a secondary switch, and more particularly to the use of a secondary switch to enable zero - voltage switching in a flyback converter.

Background Art

[0003]

[0003] Many electronic devices, such as mobile phones, laptops, etc., are powered by direct - current (DC) power obtained from a power source. Conventional wall outlets generally supply high - voltage alternating - current (AC) power that needs to be converted to regulated DC power for use as a power source for consumer - oriented electronic devices. Switching - mode power converters, also known as switched - mode power supplies (SMPS), are commonly used because of their high efficiency, small size, and light weight.

[0004]

[0004] Many electronic devices have multiple loads and require more than one DC power source to operate. For example, an audio electronic device can have system components that operate at 5 volts and audio components that operate between 12 volts and 20 volts. In these applications, a multi - output power converter converts AC power into multiple DC power outputs and provides regulated DC power to each of the multiple loads, i.e., each of the system components and the audio components. In some applications, the regulated DC power output is a regulated constant - current (CC) output and / or a regulated constant - voltage (CV) output.

Summary of the Invention

[0005]

[0005] In power converters, power converter systems, multi-output power converters, and multi-output power converter systems, efficiency can be improved by reducing switching losses. For example, by switching a primary switch according to a zero voltage switching (ZVS) switching cycle, switching losses can be improved (i.e., reduced).

[0006]

[0006] Zero voltage switching (ZVS) can advantageously reduce the voltage of a primary switch during switching. Ideally, ZVS can control the voltage across the primary switch to be substantially zero (e.g., approach zero volts) when the primary switch turns on. For example, when the primary switch is implemented as a power field effect transistor (FET), ZVS may be implemented by controlling the drain-to-source voltage of the FET to be substantially zero when the FET turns on.

[0007]

[0007] Attempts to switch the primary side switch according to the ZVS cycle have been limited to systems assuming communication from the primary side to the secondary side. For example, a synchronous rectifier (SR) field effect transistor (FET) can be strategically switched at a second time during the switching cycle based on information about the primary switch (e.g., state conditions, primary voltage, primary current) to achieve ZVS of the primary switch. Unfortunately, in current state-of-the-art power converters and power converter systems, communication from the primary side to the secondary side may not be available.

[0008]

[0008] Therefore, it is necessary to utilize primary switch ZVS in power converters and power converter systems without the constraint of having communication from the primary side to the secondary side.

[0009] As described herein, a secondary switch (e.g., synchronous rectifier and / or SR FET) is controlled to achieve zero voltage switching of a primary switch. The method enables a secondary side controller to calculate a required secondary switch holding period (i.e., secondary switch on period). The required secondary switch holding period can be determined without the need for communication from the primary side to the secondary side, by measuring the forward pin voltage when the primary switch is conducting, or by measuring the ratio of the discharge period to the charge period of the switching cycle.

[0010] Non-limiting and non-exhaustive embodiments of controlling a secondary switch to achieve zero voltage switching are described with reference to the following figures, and like reference numerals refer to like parts throughout the various figures unless otherwise specified.

Brief Description of the Drawings

[0011]

Figure 1A

[0011] shows a power converter system according to one output embodiment of the present disclosure.

Figure 1B

[0012] FIG.

[0016] shows a power converter system according to another embodiment of the present disclosure.

Figure 1C

[0013] FIG.

[0020] shows a power converter system according to another embodiment of the present disclosure.

Figure 1D

[0014] FIG.

[0024] shows a power converter system according to another embodiment of the present disclosure.

Figure 1E

[0015] FIG.

[0028] shows a power converter system according to a multi-output embodiment of the present disclosure.

Figure 1F

[0016] FIG.

[0032] shows a power converter system according to another embodiment of the present disclosure.

Figure 1G

[0017] FIG.

[0036] shows a power converter system according to another embodiment of the present disclosure.

Figure 1H

[0018] A diagram showing a power converter system according to another embodiment of the present disclosure.

Figure 2A

[0019] A diagram showing waveforms during a switching cycle.

Figure 2B

[0020] A diagram showing waveforms during a switching cycle according to an embodiment of the present disclosure.

Figure 2C

[0021] A diagram showing waveforms during a switching cycle according to an embodiment of the present disclosure.

Figure 2D

[0022] A diagram showing waveforms during a switching cycle according to another embodiment of the present disclosure.

Figure 3A

[0023] A conceptual flowchart of zero-voltage switching in a power converter system according to an embodiment of the present disclosure is shown.

Figure 3B

[0024] A conceptual flowchart of zero-voltage switching in a power converter system according to another embodiment of the present disclosure is shown.

Figure 4

[0025] A diagram comparing two switching cycles of a primary switch according to an embodiment of the present disclosure.

Figure 5

[0026] A diagram showing a power converter system according to another embodiment of the present disclosure.

Figure 6

[0027] A conceptual flowchart of zero-voltage switching in a power converter system according to an embodiment of the present disclosure is shown.

Mode for Carrying Out the Invention

[0012]

[0028] Corresponding reference numerals indicate corresponding components throughout several views of the drawings. Those skilled in the art will appreciate that the elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale. For example, some dimensions of elements in the figures may be exaggerated relative to other elements to assist in improving the understanding of various embodiments of the teachings herein. Also, commonly understood elements that are useful or necessary in a commercially realizable embodiment are often not depicted so as not to obscure these various embodiments for achieving zero voltage switching to control the secondary switch.

[0013]

[0029] In the context of the present application, when a transistor is in an "off state" or "off", the transistor blocks current and / or does not substantially conduct current. Conversely, when a transistor is in an "on state" or "on", the transistor is capable of substantially conducting current. As an example, in one embodiment, a high voltage transistor comprises an N-channel metal-oxide-semiconductor (NMOS) field effect transistor (FET), and the high voltage is supported between a first terminal, i.e., the drain, and a second terminal, i.e., the source. In some embodiments, an integrated control device circuit can be used to drive a power switch when adjusting the energy supplied to a load. Also, for the purposes of the present disclosure, "ground" or "ground potential" refers to a reference voltage or potential with respect to which all other voltages or potentials in an electronic circuit or integrated circuit (IC) are defined or measured. Additionally, according to power electronics theory, "power" transfer can be implied by "energy" transfer. Conversely, "energy" transfer can be implied by "power" transfer (i.e., power is related to the rate of change of energy).

[0014]

[0030] An adjustable DC power can be provided to multiple loads using a multi-output power converter. The loads can be passive and / or active loads including discrete semiconductor devices, microprocessors, control devices, mixed signal circuit components, etc. When providing the adjustable DC power, the multi-output power converter can adjust the output current to a constant current (CC) output and / or adjust the output voltage to a constant voltage (CV) output. Additionally, the system voltage can be defined according to how the multi-output power converter provides power. For example, the multi-output power converter can provide a CC output operating at about 50 volts, a CV output adjusted to 12 volts, and a CV output adjusted to 5 volts.

[0015]

[0031] Power may be transferred from the primary side to the secondary side through an energy transfer element (e.g., a transformer) according to a switching cycle. For example, the primary switch can be switched according to a switching cycle, whereby the primary winding receives input power over a part of the switching cycle and one or more secondary windings provide power over another part of the switching cycle. If the power is transferred such that the current in the secondary side winding (i.e., the secondary current) substantially decreases to zero before the switching cycle is completed, the operating mode can be called the discontinuous conduction mode (DCM). Alternatively, if the power (i.e., energy) is transferred such that the current in the secondary side winding does not decrease to zero before the completion of the switching cycle, the operating mode can be called the continuous conduction mode (CCM).

[0016]

[0032] Additionally, during one switching cycle (i.e., one switching period), power (i.e., energy) can be transferred to a selected one of the multiple outputs.

[0017]

[0033] Figure 1A shows a power converter system 100 according to an embodiment with one output. The power converter system 100 includes an energy transfer element 102, a secondary switch block 104, a load circuit 106, a secondary control device 108, a primary control device 109, a clamp 110, and a primary switch 152. The energy transfer element 102 includes a primary winding 112 and a secondary winding 99. The secondary switch block 104 includes an N-channel field effect transistor (NFET) 126.

[0018]

[0034] The output power converter system 100 converts input power obtained from a rectified AC line voltage V IN and can provide output power having an output voltage V O1 and a secondary current I S1 . Alternatively, and additionally, the input power may be obtained from a high voltage power source. The load circuit 106 includes a feedback network 140, a filter capacitor C1, and a first load 142.

[0019]

[0035] As shown, the feedback network 140, the filter capacitor C1, and the first load 142 are electrically coupled. The feedback network 140 can provide a feedback signal FB to the secondary control device 108. In the steady state, the power converter system 100 of Figure 1A can be configured to regulate the power supplied to the first load 142 (e.g., the output voltage V O1 ). For example, the secondary control device 108 can regulate the output voltage V O1 based at least in part on the feedback signal FB1.

[0020]

[0036] The primary control device 109 provides a primary control signal V CS to the control terminal (e.g., gate) of the primary switch 152. In this way, the primary control device 109 controls a primary current I SW for supplying energy to the primary winding 112. The primary detection element 54 provides a detection signal SENS to the primary control device to detect the primary current I SWThe maximum value can be locally adjusted. Additionally, the clamp 110 can be connected in parallel with the primary winding 112 to limit (i.e., clamp) the switch voltage V SW . As shown, the primary control device 109 can be configured to operate with signals (e.g., the switch voltage V SW and the primary control signal V CS ) referenced to the primary ground GND.

[0021]

[0037] As discussed above, the secondary control device 108 can receive a feedback signal FB1 from the load circuit 106 (i.e., from the feedback network 140). Additionally, as shown, the secondary control device 108 can communicate with the primary control device 109 via the signal FL.

[0022]

[0038] The power converter system 100 can be configured as a flyback converter, whereby the primary switch 152 is switched according to a switching cycle. Thus, during the switching cycle, energy can be transferred via the secondary current I S1 on the circuit path 115. Although shown as a flyback converter in the example of FIG. 1A, other configurations of the power converter system 100 are possible. For example, the teachings of this specification may be applicable to forward converters and / or other converter topologies.

[0023]

[0039] According to the teachings of this specification, the secondary control device 108 can include a zero voltage switching (ZVS) on-time calculator 153. The secondary control device 108 can calculate a holding period (i.e., an on-time) for controlling a secondary switch (e.g., a synchronous rectifier (SR)) during a switching cycle (i.e., the switching cycle of the primary switch 152). This secondary holding period can be used to control the secondary switch to be on during the switching cycle in order to achieve ZVS operation of the primary switch 152.

[0024]

[0040] The operating theory and equations related to the ZVS on-period calculator 153 can be based at least in part on the oscillation (i.e., ringing) behavior at the primary node NSW where the primary switch 152 is electrically coupled to the primary winding 112. According to switching power supply theory, ringing (i.e., oscillation) may occur at the primary node NSW due at least in part to the primary capacitance Cpri and the primary inductance Lpri at the primary node NSW. The resonant oscillation period (i.e., ringing period) can often be referred to as the idle ring period TIR.

[0025]

[0041] The primary capacitance Cpri can include the capacitance of the primary switch 152. For example, when the primary switch 152 is implemented using an N-channel field effect transistor (NFET), the primary capacitance Cpri can include the capacitance associated with the NFET output capacitance.

[0026]

[0042] The primary inductance Lpri may include the inductance related to the primary winding 112. For example, the primary inductance Lpri can include the magnetizing inductance of the primary winding.

[0027]

[0043] According to circuit theory, a simple approximation relating the idle ringing period TIR to the primary capacitance Cpri and the primary inductance Lpri can be given by Equation 1.

Number

[0044] According to the teachings of this specification, the secondary switch holding period T CHR_ZVS can be determined from energy storage considerations. Alternatively, and additionally, the secondary switch holding period T CHR_ZVS can be the secondary switch on-period T CHR_ZVScan also be referred to as. In this regard, the synchronous rectifier (SR) and / or the secondary switch can operate in the "on state" during the secondary switch holding period T CHR_ZVS between.

[0028]

[0045] As understood by those skilled in the art, inductance energy can be mathematically expressed as E L = 0.5L Pri LI 2 pkZVS and capacitance energy can be expressed as E C = 0.5C Pri V 2 IN .

[0029]

[0046] Based at least in part on the principle of energy storage, the inductance energy can be considered equivalent to the capacitance energy, and the peak inductor current Ipk can be determined.

Equation

[0047] Next, based on Equation 2 and the inductor current formula (di / dt = V / I, I pk / T CHR_ZVS = V or / L pri ), an approximation of the secondary switch holding period T CHR_ZVS can be determined by Equation 3.

Equation

[0048] Here, Equation 3 introduces the turns ratio N of the winding and the output voltage Vout. In the case of a single-output flyback converter, as shown in Figure 1A, the output voltage Vout is the output voltage V O1 . The turns ratio N can be determined by the turns ratio of the primary winding 112 to the secondary winding 99.

[0030]

[0049] Equation 3 can be generalized by removing the dependence on the turns ratio N and introducing the concept of the reflected output voltage Vor. By introducing the reflected output voltage Vor and using Equation 1, Equation 3 can be recalculated as Equation 4.

Number

[0050] For comparison, the more accurate relationship of the secondary switch holding period T CHR_ZVS can be given by Equation 5.

Number

[0051] Referring to FIG. 1A, the forward pin voltage V at node 123 FWD can be related to the input voltage V IN , the output voltage Vout, and the turns ratio N of the winding.

Number

[0052] Next, the relationship of the ratio of the input voltage V IN to the reflected output voltage Vor can be determined by Equation 7 with respect to the forward pin voltage V at node 123 FWD .

Number

[0053] Additionally, as shown in FIG. 1A, the secondary winding 99 is electrically coupled to the resistor RW and the drain of the NFET 126 at node 123 (i.e., the forward pin node 123).

[0031]

[0054] According to the teachings of this specification, the ZVS on-period calculator 153 can calculate the secondary switch holding period T CHR_ZVS dynamically (e.g., dynamically within the switching cycle of the primary switch 152). According to Equation 7, the ZVS on-period calculator 153 can use an easily and dynamically measurable quantity, i.e., the forward pin voltage V at node 123 FWDand the output voltage Vout (e.g., output voltage V O1 ) can be used.

[0032]

[0055] Therefore, Equations 1 to 7 may be time-dependent equations in which the values (e.g., the value of the forward pin voltage V at node 123 FWD and the value of the output voltage Vout) are time-sampled values. For example, the forward pin voltage V at node 123 FWD can be sampled at discrete times during the switching cycle of the primary switch 152.

[0033]

[0056] Therefore, as can be understood by those skilled in the art, the ZVS on-period calculator 153 can be implemented using digital, analog, and / or algorithm-based techniques. For example, the calculation can be programmed into the control device 108.

[0034]

[0057] As shown, the NFET 126 may be configured to operate as a synchronous rectifier, and the secondary control device 108 can provide a control signal Vcr to gate (control) the NFET 126 (i.e., gate the SR). According to the teachings of this specification, the NFET 126 may also be configured to utilize zero voltage switching (ZVS) of the primary switch.

[0035]

[0058] The NFET 126 in FIG. 1A may be configured to operate as a synchronous rectifier, but other configurations are also possible. For example, FIGS. 1B and 1C show a power converter system 100 according to another embodiment of the present disclosure that uses a diode 126d in parallel with the secondary switch 127. The diode 126d may be configured to operate as a rectifier, and the secondary switch 127 may be configured to utilize ZVS.

[0036]

[0059] As shown in FIG. 1C, the secondary switch 127 may be implemented using an NFET 127c. Additionally, the diode 126d may be distinguished (e.g., separated) from the body diode of the NFET 127c. The diode 126d may be implemented to maintain a current similar to that of the NFET 126, while the NFET 127c may be implemented for a current rating much lower than the current rating of the diode 126d. For example, the diode 126d may be implemented as a separate high-current diode distinct from the NFET 127c.

[0037]

[0060] Accordingly, the NFET 127c may advantageously be implemented with a device area (e.g., a smaller semiconductor chip area) smaller than that of the NFET 126. Accordingly, without departing from the scope of the present disclosure, the NFET 127c may also be referred to as an auxiliary NFET 127c. For example, the auxiliary NFET 127c may be turned on only once during a switching cycle to utilize zero voltage switching (ZVS) of the primary switch 152.

[0038]

[0061] Also, according to the teachings of this specification, the secondary control device 108 can use information obtained from the forward pin voltage V at node 123 (i.e., the forward pin node 123). For example, the secondary control device 108 can receive a forward pin signal FW provided from a resistor RW coupled to node 123. The ZVS on-period calculator 153 can perform calculations based at least in part on the forward pin signal FW and / or the feedback signal FB1. FWD from.

[0039]

[0062] As disclosed herein, the ZVS on-period calculator 153 and the secondary control device 108 can include digital and / or analog circuitry configured to calculate a secondary switch holding period T CHR_ZVS to achieve ZVS. For example, FIG. 1D shows a power converter system 100 that uses a secondary control device 108 having both digital and analog functions.

[0040]

[0063] The secondary control device 108 in FIG. 1D includes a ZVS on-period calculator 153, an output control block 154, a comparator 155, an idle ringing period calculator 156, edge detection blocks 157 - 158, delay blocks 159 - 160, a sample and hold circuit 161, analog-to-digital converters 162 - 163, an AND gate 164, and an AND gate 165. The secondary control device 108 receives a forward pin signal FW and a feedback signal FB1. As shown, the feedback signal FB1 can be directly derived from (e.g., equal to) the output voltage V O1 In other embodiments (e.g., the embodiment of FIG. 1A), the feedback signal FB1 may be proportional to the output voltage V O1 (e.g., a scaled ratio of the output voltage).

[0041]

[0064] As shown, the comparator 155 can compare the feedback signal FB1 (i.e., the output voltage V O1 ) with the forward pin signal FW. In response, the comparator 155 can provide a comparator output signal L1, and as discussed herein with respect to FIGS. 2A - 2D, the idle ringing period TIR can be calculated in response to the transition of the comparator output signal L1.

[0042]

[0065] The edge detection block 157 receives the comparator output signal L1 and can trigger the delay block 159 when the comparator output signal L1 transitions from high to low. According to the teachings herein, the delay block 159 can provide a delayed output signal L2 after one-fourth of the idle ringing period TIR has elapsed.

[0043]

[0066] Similarly, the edge detection block 158 can receive the comparator output signal L1 and trigger the delay block 160 when the comparator output signal L1 transitions from low to high. According to the teachings of this specification, the delay block 160 can provide a delayed output signal L3 after one-fourth of the idle ringing period TIR has elapsed.

[0044]

[0067] The output control block 154 may provide a request signal REQ based on the feedback signal FB1 and the delayed output signal L2. For example, the output control block 154 can determine that there is a need to supply power to the load 142 based on the feedback signal FB1 (e.g., the value of the feedback signal FB1 decreases). Additionally, the output control block 154 may assert the request signal REQ in response to the demand and in response to the delayed output signal L2.

[0045]

[0068] The sample and hold circuit 161 can sample the forward pin signal FW and provide the sample to an analog-to-digital converter (ADC) 162. The ADC 162 can then provide a digital forward pin signal DFW (i.e., the digital representation of the forward pin signal FW).

[0046]

[0069] Similarly, the ADC 163 can convert the feedback signal FB1 and provide a digital output voltage signal DVO (i.e., the digital representation of the feedback signal FB1).

[0047]

[0070] As shown, the ZVS on-time calculator 153 can receive the digital output voltage signal DVO, the digital forward pin signal DFW, and the idle ringing period TIR. In response, the ZVS on-time calculator 153 may assert a ZVS calculator signal L4.

[0048]

[0071] According to the teachings of this specification, the ZVS on-time calculator 153 can perform calculations based at least in part on one or more of Equations 1-7. For example, the ZVS on-time calculator 153 calculates the secondary switch holding period T CHR_ZVS in accordance with Equation 8 derived from Equation 4 and Equation 7. [Number]

[0072] Also, as shown, the AND gate 164 receives the request signal REQ, the ZVS calculator signal L4, and the delayed output signal L2. As shown, the control signal V CR can be issued to drive the gate of the NFET 126 based on the logical AND function of the request signal REQ, the ZVS calculator signal L4, and the delayed output signal L2. As those skilled in the art can understand, additional components and / or buffer stages may exist between the output of the AND gate 164 and the gate of the NFET 127c. Alternatively, and additionally, the secondary control device 108 of FIG. 1D may be used in embodiments that use the NFET 126 (e.g., the embodiment of FIG. 1A).

[0049]

[0073] Additionally, the AND gate 165 receives the request signal REQ and the delayed output signal L3. As shown, the signal FL is issued to close the primary switch 152 based at least in part on the logical AND function of the request signal REQ and the delayed output signal L3 and may be coupled to the primary control device 109.

[0050]

[0074] FIGS. 1A-1D show a power converter system 100 according to a one-output embodiment, but other embodiments are possible.

[0051]

[0075] For example, FIG. 1E shows a power converter system 100 according to an embodiment of multiple output (i.e., multi-output). The power converter system 100 of FIG. 1E can be configured in the same manner as that of FIG. 1A, except that the power converter system 100 of FIG. 1E has multiple outputs, as will be described later.

[0052]

[0076] As shown in the figure, the power converter system 100 includes an energy transfer element 102, a secondary switch block 104, a load circuit 106, a secondary control device 108, a primary control device 109, a clamp 110, and a primary switch 152. The energy transfer element 102 includes a primary winding 112 and secondary windings 114, 116, 118. The secondary switch block 104 includes NFET 126 and secondary switches 119, 122, 125. In other examples, the power converter system 100 can include one secondary winding from which multiple outputs are derived.

[0053]

[0077] The multi-output power converter system 100 can convert the input power obtained from the rectified AC line voltage V IN into output power including multi-output voltages V O1 ~V O3 and secondary currents I S1 ~I S3 . Alternatively, and additionally, the input power may be obtained from a high voltage power source. The load circuit 106 includes a CC / CV3 port, a CC / CV2 port, a CC / CV1 port that can be a regulated DC power port, and a secondary ground return port SRTN.

[0054]

[0078] Additionally, the CC / CV3 port can be a constant current (CC) port (i.e., a secondary current I S3 constantly controlled) and / or a constant voltage (CV) port (i.e., an output voltage V O3It may also be. The CC / CV2 port may be a constant current (CC) port (i.e., a secondary current I S2 ) and / or a constant voltage (CV) port (i.e., a controlled output voltage V O2 ) according to the load state at the CC / CV2 port. The CC / CV1 port may be a constant current (CC) port (i.e., a secondary current I S1 ) and / or a constant voltage (CV) port (i.e., a controlled output voltage V O1 ) according to the load conditions at the CC / CV1 port.

[0055]

[0079] For example, in one embodiment, the CC / CV3 port may be a CC port, and the secondary current I S3 may be an adjusted load current, while the output voltage V O3 is at least partially determined by the load of the CC / CV3 port. Additionally, the CC / CV1 port and the CC / CV2 port may be CV ports where the output voltage V O1 and the output voltage V O2 are adjusted. The secondary ground return port SRTN can be electrically coupled to the secondary ground RTN.

[0056]

[0080] In one embodiment, the output voltages V O1 ~V O3 may be at least partially determined by the energy transfer element 102. For example, the turns ratio of the primary winding 112 and the secondary windings 114, 116, 118 having a transformer structure (e.g., stacked secondary windings) can be configured for the highest voltage CC / CV3 port (e.g., a voltage exceeding 40 volts). The CC / CV1 port and the CC / CV2 port can be adjusted to a lower voltage (e.g., a voltage of 3 to 40 volts). In one embodiment, the CC / CV2 port may be a CV port where the output voltage V O2 is adjusted to a lower voltage (e.g., 20 volts), and the CC / CV1 port may be a CV port where the output voltage V O1 is adjusted to the lowest voltage (e.g., 5 volts).

[0057]

[0081] Alternatively, and additionally, the output voltages V O1 ~V O3 may be determined by the operation of the secondary switches 119, 122, 125. For example, the secondary switch 119 may be controlled such that the output voltage V O3 becomes greater than the output voltage V O2 .

[0058]

[0082] As shown, the secondary windings 114, 116, and 118 are electrically coupled in a stacked (i.e., series) configuration according to the transformer “dot” notation. As shown, the secondary switch 119 is electrically coupled between the “dot” terminal of the secondary winding 118 and the CC / CV3 port on the circuit path 111. The secondary switch 122 is electrically coupled between the “dot” terminal of the secondary winding 116 and the CC / CV2 port on the circuit path 113, and the secondary switch 125 is electrically coupled between the “dot” terminal of the secondary winding 114 and the CC / CV1 port on the circuit path 115.

[0059]

[0083] As shown, an N-type FET (NFET) 126 is coupled between the secondary winding 114 and the secondary RTN in the circuit path 117. As discussed above with respect to FIG. 1A, the NFET 126 may operate as a synchronous rectifier and be configured to be switched on and off by a control signal Vcr. Additionally, as discussed above with respect to FIGS. 1B and 1C, the NFET 126 may be replaced by a diode 126d and a secondary switch 127 connected in parallel.

[0060]

[0084] Also, as shown, the primary winding 112 and the primary switch 152 may be connected between the input terminals 101, 103 to receive a rectified AC line voltage V IN with respect to the primary ground GND. During the switching cycle (i.e., the switching period), while the primary switch 152 is closed (i.e., conducting), the primary winding 112 has an increasing (i.e., ramping) primary current ISW It may be energized by

[0061]

[0085] The secondary control device 108 receives feedback signals FB1 to FB3 from the load circuit 106, communicates with the primary control device 109 via the signal FL, and provides control signals SEL1 to SEL3 to the secondary switch block 104. As shown in the figure, the secondary control device 108 is based on the secondary ground RTN (for example, feedback signals FB1 to FB3 and the multi-output voltage V O1 ~V O3 ). Thus, the signal FL may be an optically coupled, magnetically coupled, and / or capacitively coupled signal FL to enable communication with the primary control device 109 based on the primary ground GND.

[0062]

[0086] As described in this specification, the secondary control device 108 can provide one or more control signals SEL1 to SEL3 to selectively control (i.e., switch) the transmission of energy (i.e., power) to the load circuit 106 by selecting circuit paths (e.g., circuit paths 111, 113, and / or circuit path 115). As shown in the figure, the secondary control device 108 provides control signals SEL1, SEL2, SEL3 to the secondary switches 125, 122, 119 respectively. Next, the control signals SEL1, SEL2, SEL3 can gate the switches 125, 122, 119 to operate in the on state or the off state respectively.

[0063]

[0087] During the switching cycle, energy is transferred when the secondary switch 119 is closed (i.e., operating in the on state) while both secondary switches 125, 122 are open (i.e., both operating in the off state), and the secondary current I on the circuit path 111 S3It can be transmitted through. As shown in the figure, the circuit path 111 includes a secondary switch 119 and is a switching circuit path electrically coupled to the CC / CV3 port of the load circuit 106. Alternatively, when the secondary switch 122 is closed (i.e., operating in the on state) and the secondary switches 125, 119 are open (i.e., operating in the off state), the secondary current I on the circuit path 113 S2 can transmit energy through. As shown in the figure, the circuit path 113 includes a secondary switch 122 and is a switching circuit path electrically coupled to the CC / CV2 port of the load circuit 106. Alternatively, when the secondary switch 125 is closed (i.e., operating in the on state) and the secondary switches 122, 119 are open (i.e., operating in the off state), the secondary current I on the circuit path 115 S1 can transmit energy through. As shown in the figure, the circuit path 115 includes a secondary switch 125 and is a switching circuit path electrically coupled to the CC / CV1 port of the load circuit 106.

[0064]

[0088] As discussed above, the secondary control device 108 can include a zero-voltage switching (ZVS) on-period calculator 153. According to the teachings of this specification, the secondary control device 108, based at least in part on the forward pin signal FW and the selected output, determines a hold period (e.g., the secondary switch hold period T CHR_ZVS ) for controlling the synchronous rectifier (SR) during the switching cycle (i.e., the switching cycle of the primary switch 152).

[0065]

[0089] In the multi-output embodiment of FIG. 1E, the selected output can refer to the output that is active and / or selected during the switching cycle. For example, during the switching cycle, when the secondary switch 125 is closed, the selected output corresponds to the output voltage V O1 . Alternatively, when the secondary switch 122 is closed, the selected output corresponds to the output voltage V O2corresponds to. Therefore, Equation 7 can be reformulated by replacing the output voltage Vout with a selective output voltage Vo. For example, when the selective output corresponds to the output voltage V O2 when corresponding to, the selective output voltage Vo is the output voltage V O2 .

[0066]

[0090] Figure 1F shows a multiple output (i.e., multi-output) power converter system 100 according to the embodiment of Figure 1E. The primary switch 152 is implemented by an N-type field effect transistor (FET) 152b. The secondary switch 119 is replaced by a diode 120. As shown, the diode 120 is electrically coupled between the "dot" terminal of the secondary winding 118 and the CC / CV3 port on the circuit path 111. The output voltage V O3 is necessarily the multi-output voltage V O1 ~V O3 In an application having the highest voltage value among them, the secondary switch 119 can be replaced by a diode 120 to advantageously simplify the secondary switch block 104 and eliminate the need for the control signal SEL3.

[0067]

[0091] The secondary switch 122 is implemented by an N-type FET 122b. As shown, the secondary switch 122 is electrically coupled with a diode 121 between the "dot" terminal of the secondary winding 116 and the CC / CV2 port on the circuit path 113. The secondary switch 125 is implemented by an N-type FET 125b, and the secondary switch 125b is electrically coupled between the "dot" terminal of the secondary winding 114 and the CC / CV1 port on the circuit path 115.

[0068]

[0092] The N-type FETs 152b, 122b, 125b, 126 may be integrated and / or individual power FETs. In one embodiment, the N-type FETs 152b, 122b, 125b, 126 may be enhancement mode FETs.

[0069]

[0093] The load circuit 106 includes feedback networks 140, 136, 132 that can each provide feedback signals FB1, FB2, FB3 to the secondary control device 108. Additionally, the load circuit 106 includes filter capacitors C1 - C3 electrically coupled to a first load 142, a second load 138, and a third load 148, respectively. In a steady state, the multi - output power converter system 100 of FIG. 1F can be configured to regulate the power supplied to the first load 142, the second load 138, and the third load 148.

[0070]

[0094] For example, the feedback networks 140, 136, 132 can include a split network for providing feedback signals FB1, FB2, FB3 for respectively closed - loop regulating the output voltages V O1 , V O2 , V O3 . In a steady state, the feedback signals FB1, FB2, FB3 can be voltages derived or sampled from the output voltages V O1 , V O2 , V O3 , respectively. In this way, the power supplied to the first load 142 can be regulated as a CV output (i.e., the regulated output voltage V O1 ), the power supplied to the second load 138 can be regulated as a CV output (i.e., the regulated output voltage V O2 ), and the power supplied to the third load 148 can be regulated as a CV output (i.e., the regulated output voltage V O3 ).

[0071]

[0095] As described above, the secondary control device 108 may communicate with the primary control device 109 via a signal FL (e.g., a magnetically coupled signal FL). For example, using the signal FL, the primary control device 109 can send a handshake to the secondary control device 108 to indicate a power good state. Alternatively, and additionally, using the signal FL, the secondary control device 108 may send more energy transfer requests. In response to the request, the primary control device 109 closes the primary switch 152 and changes the primary control signal V CS to supply energy to the primary winding 112.

[0072]

[0096] As shown in the figure, the secondary control device 108 can receive a forward pin signal FW and feedback signals FB1 to FB3, and the secondary control device 108 can provide control signals SEL1, SEL2, and Vcr. As discussed herein, by using the control signals SEL1 and SEL2 to select circuit paths (e.g., circuit paths 111, 113, and / or 115), the transfer of energy (i.e., power) to the load circuit 106 can be selectively controlled (i.e., switched). Additionally, the control signal Vcr may be used to drive the gate of the N-type FET 126 to operate as a synchronous rectifier.

[0073]

[0097] As discussed above, the feedback signals FB1 to FB3 can be sampled (i.e., measured) signals used within the secondary control device 108 for closed-loop control of the CV output. However, as will be understood by those skilled in the art, other configurations are possible. For example, as discussed herein, the secondary control device 108 may also be configured to provide closed-loop control of the CC output.

[0074]

[0098] As shown in the figure, the forward pin voltage V FWD may be present at node 123, and an optional passive component (i.e., resistor R W) may be electrically coupled between the secondary windings 114 at node 123 to provide a forward pin signal FW to the secondary control device 108. In some embodiments, the forward pin signal FW may be equivalent to the forward pin voltage V FWD but in other embodiments, the forward pin signal FW may be attenuated with respect to the forward pin voltage V FWD .

[0075]

[0099] FIG. 1G shows a multi-output power converter system 100 according to another embodiment of FIG. 1E. The embodiment of FIG. 1G is similar to the embodiment of FIG. 1F except that the load 148 is replaced by LED strings 183-184 and the current sensing element 182 samples the load current I L3 to provide a feedback signal FB3. In the steady state, the multi-output power converter system 100 of FIG. 1G can be configured to regulate the power supplied to the LED strings 183-184 as a CC output (i.e., regulated load current I L3 ).

[0076]

[0100] Additionally, the load circuit 106 includes a plurality of parallel-connected light-emitting diode (LED) strings 183-184, a first load 142, and a second load 138. As shown, the LED strings 183-184 demand (i.e., receive) a load current I L3 and the feedback signal FB3 is shown as directly sampling the load current I L3 but other configurations are possible. For example, instead of directly sampling the load current I L3 , the load current I L3A can be regulated by sampling the LED string currents I L3B ~I L3 and the LED string currents I L3A ~I L3B are used by the secondary control device 108 to regulate the total load current I L3 .

[0077]

[0101] In one embodiment, the LED string currents I L3A ~I L3B are used by the secondary control device 108 to regulate the output voltage V L3 as a means of controlling the total load current I O3 . Additionally, although the load circuit 106 is shown as having two LED strings 183, 184, other configurations having more or fewer than two LED strings 183, 184 are possible.

[0078]

[0102] As discussed above, the NFET 126 may be replaced by a diode 126d and a secondary switch 127 connected in parallel. For example, FIG. 1H shows a multi-output power converter system 100 according to another embodiment of FIGS. 1G and 1D. The embodiment of FIG. 1H is similar to the embodiment of FIG. 1G, except that, as in FIG. 1D, the NFET 126 may be replaced by a diode 126d and a secondary switch 127 connected in parallel. As shown, the secondary switch 127 includes an auxiliary NFET 127c.

[0079]

[0103] Also, as would be understood by those skilled in the art, the embodiments of FIGS. 1A - 1H are non-limiting, and other configurations may be implemented using integrated and / or discrete semiconductor components including bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), and / or FETs of opposite polarity (e.g., P-channel FETs). Additionally, the active devices may be realized using material processes based on silicon, silicon germanium, gallium nitride, etc.

[0080]

[0104] The multi-output power converter system 100 has a plurality of selectable output voltages V O1 ~V O3 and secondary currents I S1 ~I S3Although a switching configuration (e.g., flyback configuration) is shown for providing, other configurations with more or fewer outputs are possible. For example, the teachings herein may also be applicable to forward converters and / or other converter topologies that use a transformer having multiple secondary outputs.

[0081]

[0105] In the description and the illustrative drawings, it is understood that the concept of multiple independently controlled CC / CV outputs is mainly shown by the series connection of secondary windings on an energy transfer element (e.g., a transformer). However, this should not be considered as a limitation, and in accordance with the teachings herein, based on the applications and load power requirements for each of the multiple outputs, independently adjustable CV / CC outputs may be arranged in any combination of connections of one or more series windings, parallel windings, or both series and parallel windings, with a common return line for all of the independently controlled and adjusted outputs.

[0082]

[0106] The proposed converter topology is an example of a single-stage multiple-output flyback converter targeted for applications having multiple independently adjustable constant voltage and / or constant current outputs. Exemplary targets for such products can include, for example, CC-controlled outputs of parallel strings (e.g., arrays) of backlight LEDs that require a regulated adjustable (e.g., dimmable) constant current output with a voltage drop of 40 - 50V, and one or more CV-controlled outputs for powering logic, universal serial bus (USB), and audio that must meet strict regulation accuracy requirements for each output, including monitor and television applications.

[0083]

[0107] FIG. 2A shows waveforms 202 - 205 during discontinuous mode (DCM) over the switching cycle of period T1 of an exemplary power converter, as shown, for example, in any one of FIGS. 1A - 1H. Waveform 202 is the forward pin voltage V as a function of time FWDand / or can correspond to the forward pin signal FW. Waveform 203 can correspond to the switch voltage V as a function of time SW can correspond to. Waveform 204 can correspond to the primary control signal V as a function of time CS and waveform 205 can correspond to the control signal Vcr as a function of time.

[0084]

[0108] As depicted by waveform 204, the primary control signal V that drives the primary switch (e.g., primary switch 152) CS can be periodic with a period T1. For example, as shown at time point 211, the primary control signal V CS can transition from high to low to turn off the primary switch 152. At time point 213, the primary control signal V CS can transition from low to high to turn on the primary switch 152, and at time point 214, the control signal can transition from high to low again to turn off the primary switch 152.

[0085]

[0109] As depicted by waveform 205, the signal Vcr that drives the SR (e.g., NFET126) gate can transition following the turn-off transition of the primary switch 152. For example, as shown at time point 211, the signal V CR can transition from low to high at time point 211 and remain high until time point 212. At time point 212, the signal Vcr can transition from high to low and remain low until a new cycle begins at time point 214.

[0086]

[0110] As depicted by waveform 202 in relation to waveforms 204 - 205, the forward pin voltage V at node 123 FWD can vary periodically according to the switching transitions of the primary switch 152 and the SR (e.g., NFET126). For example, from time point 211 to time point 212, the SR (NFET126) may be conducting and the forward pin voltage V FWDmay be less than and / or equal to zero volts (0V). Time point 212 can depict when the energy from the secondary windings 114, 116, 118 and / or winding 99 is depleted to an extent where ringing can occur at node 123. For example, as shown by waveform 202, there is ringing (i.e., oscillation) between time point 212 and time point 213.

[0087]

[0111] Also as shown, the ringing occurs with peaks above and below the output voltage V OUT (i.e., offsets). According to the teachings of this specification, the output voltage V OUT can correspond to the output V O1 of FIG. 1A and / or the output voltages V O1 to V O3 of FIGS. 1E - 1H.

[0088]

[0112] As depicted by waveform 203 in relation to waveforms 202, 204, 205, the switch voltage V SW can also vary periodically according to the switching transitions of the primary switch 152 and the SR (e.g., NFET 126). For example, from time point 211 to time point 212 when the forward pin voltage V FWD is forced to be less than and / or equal to zero volts (0V), the switch voltage V SW reaches a plateau and / or a clamp voltage exceeding the rectified AC line voltage V IN . Additionally, after time point 212 when the energy from the secondary windings 114, 116, 118 and / or winding 99 is depleted, the switch node voltage V SW can ring, at least in part, due to capacitance (e.g., the parasitic capacitance of the primary switch 152) and inductance (e.g., the inductance of the primary winding 112). According to the theory of the switching power converter, and as shown by waveforms 202 and 203, the ringing of waveforms 202 and 203 may be out of phase. At time point 213, the primary control signal V CSWhen the primary switch 152 is turned on, ringing can be terminated.

[0089]

[0113] According to the teachings of this specification, the information from the forward pin voltage V FWD can advantageously provide information regarding the state of the primary side of the power converter without requiring additional communication from the primary side to the secondary side.

[0090]

[0114] FIG. 2B shows waveforms 222-225 during the switching cycle of an exemplary power converter according to the teachings of this specification. Waveform 222 can correspond to the forward pin voltage V FWD and / or the forward pin signal FW as a function of time. Waveform 223 can correspond to the control signal Vcr as a function of time. Waveform 224 can correspond to the signal FL transmitted by the secondary control device 108 as an energy requirement, and waveform 225 can correspond to the primary control signal V CS as a function of time.

[0091]

[0115] In contrast to waveform 204, waveform 223 shows a transition of Vcr from low to high at time point 241 and a transition from high to low at time point 242. According to the teachings of this specification, by turning on the SR (e.g., NFET126) during the interval T2 (i.e., from time point 241 to time point 242), the primary switch 152 can receive ZVS, and as discussed in this specification, the duration of the interval T2, also referred to as the hold period (e.g., the secondary switch hold period T CHR_ZVS ) can be calculated using the information available to the secondary control device 108.

[0092]

[0116] As shown by waveforms 223-225, following the interval T2, the signal FL transitions from low to high at time point 244 and then from high to low at time point 245. Then, in response to the signal FL, the primary control signal V CSAt time 246, it can transition to high and turn on the primary switch 152. At time 247, the primary switch 152 turns off when the primary control signal V CS transitions from high to low.

[0093]

[0117] For waveforms 223 to 225, waveform 222 shows how the forward pin voltage V FWD changes according to the interval T2. For example, during the interval T3 from time 242 to time 243, the forward pin voltage V FWD transitions from zero volts (0V) to a value determined by the output voltage Vout and / or the selective output voltage Vo. During the interval T4 from time 243 to time 246, the forward pin voltage V FWD transitions from the value determined by the output voltage Vout and / or the selective output voltage Vo to the value V FON . As shown, the value V FON can correspond to the value of the forward pin voltage V FWD and / or the forward pin signal FW while the primary switch 152 is on.

[0094]

[0118] Waveform 222 is shown as changing the forward pin voltage V FWD to the value V FON , but other changes are possible. For example, as those skilled in the art can understand, in other configurations, the forward pin voltage V FWD may not reach the value V FON (i.e., may not ring or may not transition to the value V FON ).

[0095]

[0119] As discussed in this specification, the duration of the interval T2, also referred to as the holding period T2 (i.e., the secondary switch holding period T CHR_ZVS ), can be related to the value V FON as well as the output voltage V OUT and / or the selective output voltage Vo. Therefore, Equation 7 can be the sampled value of the forward pin voltage V FWD and can be the value VFON It can be recalculated by substituting

[0096]

[0120] FIG. 2C shows waveforms 252-255 during the switching cycle from time point 270 to time point 279 according to an embodiment of the present disclosure. Waveform 252 can correspond to the forward pin voltage V as a function of time FWD and / or the forward pin signal FW. Waveform 253 can correspond to the control signal Vcr as a function of time. Waveform 254 can correspond to the signal FL transmitted by the secondary control device 108 as the energy requirement at time point 276, and waveform 255 can correspond to the primary control signal V as a function of time CS can correspond to.

[0097]

[0121] Referring to waveform 255, the switching cycle can be measured from time point 270 when the primary control signal V CS transitions low to time point 279 when the control signal V CS transitions low again. Also, as shown by waveform 254, during the switching cycle from time point 270 to time point 279, the signal FL transmits an energy requirement between time point 276 and time point 277.

[0098]

[0122] As depicted by waveform 252 in relation to waveforms 253-255, the forward pin voltage V at node 123 FWD can vary periodically according to the switching transitions of the primary switch 152 and the SR switch (e.g., NFET126). For example, from time point 270 to time point 272, the SR (NFET126) may be conducting, and the forward pin voltage V FWD may be less than and / or equal to zero volts (0V). Time point 272 can depict when the energy from the secondary windings 114, 116, 118 and / or winding 99 is depleted to the extent that ringing can occur at node 123. For example, as shown by waveform 252, there can be an initial occurrence of ringing (i.e., oscillation) during interval T5 between time point 272 and time point 273.

[0099]

[0123] According to the teachings herein, the SR switch (NFET126) can be turned on at time point 273. Also, according to the teachings of this specification, the output voltage V OUT can correspond to the output V of FIG. 1A O1 and / or the output voltage V of FIGS. 1E to 1H O1 ~V O3 .

[0100]

[0124] As described herein, the control signal V CR can remain high during interval T6 (i.e., from time point 273 to time point 274). Interval T6 can also be referred to as the secondary switch hold period T CHR_ZVS . Referring to waveforms 252 to 255, the secondary switch hold period T CHR_ZVS can be determined (i.e., calculated) as a function of the forward pin voltage V FWD sampled at time point 269 (e.g., value V FON ).

[0101]

[0125] Additionally, as described above, the value V FON can correspond to the value of the forward pin voltage V FWD and / or the forward pin signal FW while the primary switch 152 is on.

[0102]

[0126] As discussed herein, interval T6 (e.g., the secondary switch hold period T CHR_ZVS ) can be further determined (i.e., calculated) as a function of the output voltage V OUT . According to the teachings of this specification, the output voltage V OUT can also be an optional output voltage V O readily available to the secondary controller 108. For example, referring to FIG. 1H, an optional output voltage V O from any one of the feedback signals FB1 to FB3 may be provided to the secondary controller 108.

[0103]

[0127] Referring to waveforms 253 - 255, waveform 252 also shows how the forward pin voltage V FWD changes according to interval T6. For example, during interval T7 from time point 274 to time point 275, the forward pin voltage V FWD transitions from zero volts (0V) to a value determined by the output voltage and / or the selectable output voltage Vo. Subsequently, during interval T8 from time point 275 to time point 278, the forward pin voltage V FWD transitions from the value determined by the output voltage and / or the selectable output voltage Vo to value V FON . According to the teachings of this specification, interval T8 may be one - quarter (i.e., 1 / 4) of the idle ringing period TIR given by Equation 9. [Number]

[0128] Also, according to the teachings of this specification, Equation 8 can also be reformulated as Equation 10 with respect to the sampling value V FON and the selectable output voltage Vo. [Number]

[0129] Figure 2D shows waveforms 252 - 255 during a switching cycle from time point 270 to time point 279 according to another embodiment of the present disclosure. The embodiment of Figure 2D may be similar to the embodiment of Figure 2C, except that waveform 253 does not transition high between time point 270 and time point 272 and does not transition high at time point 279. Instead, waveform 253 transitions high from time point 273 to time point 274 during interval T6.

[0104]

[0130] For example, waveform 253 in Figure 2D can correspond to the power converter system 100 of Figures 1C and / or 1H using NFET127c, while the embodiment of Figure 2C can correspond to the power converter system 100 of Figure 1A using NFET126.

[0105]

[0131] FIG. 3A shows a conceptual flowchart 300 of zero voltage switching in a power converter system 100 according to an embodiment of the present disclosure.

[0106]

[0132] Step 301 may correspond to closing (i.e., turning on) the primary switch 152 at time point 278.

[0107]

[0133] Step 302 may correspond to sampling the forward pin voltage V FWD at time point 269. Referring to waveform 252, the forward pin voltage V FWD at time point 269 may provide the value V FON of the forward pin signal when the primary switch 152 is on (i.e., conducting).

[0108]

[0134] Step 304 may correspond to opening (i.e., turning off) the primary switch at time point 270.

[0109]

[0135] Step 306 may correspond to closing the SR switch (e.g., NFET126) at time point 270, and step 308 may correspond to opening the SR switch (e.g., NFET126) at time point 272.

[0110]

[0136] Step 310 may correspond to calculating the SR hold duration T6 (e.g., calculating the interval T6). The SR hold duration T6 may be given by the secondary switch hold duration T CHR_ZVS derived herein.

[0111]

[0137] Step 312 may correspond to closing the synchronous rectifier over the hold duration T6. For example, step 312 may correspond to closing the SR switch (e.g., NFET126) over the interval T6 (i.e., the hold duration T6) from time point 273 to time point 274.

[0112]

[0138] Step 313 may correspond to turning on the synchronous rectifier after the holding duration T6 and before time point 278.

[0113]

[0139] FIG. 3B shows a conceptual flow diagram 350 of zero voltage switching in the power converter system 100 according to another embodiment of the present disclosure. The conceptual flow diagram 350 is similar to the conceptual flow diagram 300 except that steps 306-308 are excluded, and steps 312-313 are replaced by steps 352-353, respectively.

[0114]

[0140] Step 352 may correspond to closing the secondary switch (e.g., NFET127c) over the holding duration T6. Step 352 may correspond to opening the secondary switch (e.g., NFET127c) after the holding duration T6 and before time point 278.

[0115] Dynamic operation during the switching cycle

[0116]

[0141] FIG. 4 compares waveforms 403-407 between two switching cycles 401-402 of the primary switch 152. For the comparison during switching cycle 401, the control signal Vcr may be disabled, while during switching cycle 402, the control signal Vcr may be enabled.

[0117]

[0142] Waveform 405 can correspond to the forward pin voltage V FWD and / or the forward pin signal FW as a function of time. Waveform 407 can correspond to the switch voltage V SW as a function of time. Waveform 403 can correspond to the primary control signal V CS as a function of time, and waveform 404 can correspond to the control signal Vcr as a function of time. Additionally, waveform 406 can correspond to the output voltage V OUT (e.g., the output voltage V in FIG. 1D O1 ).

[0118]

[0143] The primary switch 152 can operate in an "on" state in response to the primary control signal V CS As shown in FIG. 4, the primary switch 152 closes (i.e., turns "on") at time points 410, 411, and 421. The switching cycle 401 (i.e., the switching period 401) is depicted from time point 410 to time point 411, while the switching cycle 402 is depicted from time point 411 to time point 421. As discussed above, the switching cycle 402 can correspond to the switching cycle of the primary switch 152 in the embodiment of FIG. 1D.

[0119]

[0144] At time point 412, the sample - hold circuit 161 can sample the forward pin signal FW and / or the forward pin voltage V FWD . For example, the sample - hold circuit 161 can sample the forward pin voltage V FWD at point 427 on waveform 405. Thus, the ADC 162 can then provide a digital forward pin signal DFW as the digital representation of waveform 405 at time point 412 (e.g., value V FON ).

[0120]

[0145] At time point 413, the primary switch 152 can open (i.e., turn "off"). From time point 413 to time point 414, the diode 126d can conduct according to the embodiment of FIG. 1D. Thus, the waveform 404 (i.e., the control signal Vcr) remains low from time point 413 to time point 414. However, as those skilled in the art can understand, in other embodiments (e.g., the embodiment of FIG. 1A), the waveform 404 (i.e., the control signal Vcr) can transition high at time point 413 to drive the gate of the NFET 126 and then transition low at time point 414.

[0121]

[0146] At time 414, the power converter system 100 can enter discontinuous conduction mode (DCM). Thus, waveforms 405 and 407 exhibit ringing. Using comparator 155, the points 432 - 436 where waveform 405 (i.e., forward pin voltage V FWD and / or forward pin signal FW) intersects (i.e., crosses) waveform 406 (i.e., output voltage V OUT ) can be distinguished. Thus, referring to FIG. 1D, the comparator output signal L1 can change (i.e., transition) according to the ringing of waveform 405, and then the idle ringing period calculator 156 can calculate the idle ringing period TIR according to the transition of the comparator output signal L1. Further, edge detection blocks 157 - 158 can be triggered according to the transition edges of the comparator output signal L1.

[0122]

[0147] During switching cycle 402, the ZVS on - period calculator 153 can dynamically calculate the hold - time (e.g., secondary switch hold - time T CHR_ZVS ) as a function of the idle ringing period TIR, the digital forward pin signal DFW, and the digital output voltage signal DVO. As shown in FIG. 1D, the hold - time may be provided via the ZVS calculator signal L4, and in response to AND gate 165, waveform 404 (i.e., control signal Vcr) transitions high at time 415 and transitions low at time 416. According to the teachings herein, the duration from time 415 to time 416 can be at least partially determined by the ZVS on - period calculator 153.

[0123]

[0148] Additionally, the comparator output signal L1 may also transition at point 437 where waveform 405 (i.e., forward pin voltage V FWD and / or forward pin signal FW) intersects (i.e., crosses) waveform 406 (i.e., output voltage V OUT ). Thereafter, delay block 159 causes the primary control signal V CS(I.e., waveform 403) may transition to turn on primary switch 152. The delay from point 437 to the time point 421 when primary switch 152 turns on may be referred to as the "on-ringing duration".

[0124]

[0149] According to the teachings of this specification, the on-ringing duration may be one-fourth of the idle ringing period TIR. For example, referring to FIG. 1D, delay block 160 can provide a delayed output signal L3 after one-fourth of the idle ringing period TIR has elapsed. This can then cause a delay of one-fourth of the idle ringing period TIR such that the duration from time point 416 to time point 421 is substantially equal to one-fourth of the idle ringing period TIR.

[0125]

[0150] When control signal Vcr is enabled during switching cycle 402, the switching is relatively "soft" (i.e., improved) at time point 421. As shown by waveform 407, at time point 421, the switch voltage V SW reaches approximately zero volts at point 438. In comparison, at time point 411 following switching cycle 401, the switch voltage V SW transitions from point 431 which has a relatively higher voltage than point 438.

[0126] Use of charge and discharge period intervals for calculating the hold period

[0127]

[0151] As described in this specification, the ZVS on-period calculator 153 can dynamically calculate the secondary switch hold period T FWD using the sampled values of the forward pin voltage V CHR_ZVS and the output voltage Vout. However, there may be applications (e.g., some single-output flyback converter applications) where the sampled voltage is undesirable due to bandwidth limitations. Therefore, other methods and ZVS on-period calculators are disclosed to meet these challenges.

[0128]

[0152] Charging period T CHG with respect to the discharge period T DCHG Based in part on the ratio of the secondary switch holding period T CHR_ZVS A ZVS on-period calculator for estimating is presented herein. The charging period T CHG and the discharge period T DCHG can be advantageously determined using a timer (e.g., a digital timer), thereby overcoming potential bandwidth limitations associated with voltage sampling. As shown in FIGS. 2C, 2D, and 4, the charging period T CHG can correspond to the time interval during which the primary switch 152 is on, and the discharge period T DCHG can correspond to the time interval during which the secondary switch (e.g., NFET 126) is on.

[0129]

[0153] In the steady state, the charging period T CHG can be given by Equation 11, and the discharge period T DCHG can be given by Equation 12.

Equation

Equation

[0154] FIG. 5 shows a power converter system 100 according to one embodiment of the present disclosure that includes a secondary control device 508. The secondary control device 508, unlike the secondary control device 108, includes a ZVS calculator 553, a charging timer 503, a discharging timer 504, a comparator 501, and a comparator 502. The charging timer 503 and the discharging timer 504 can be implemented as digital timers and / or analog timers.

[0130]

[0155] Additionally, unlike the ZVS calculator 153, the ZVS calculator 553 has a charging period TCHG the value (e.g., digital representation) and the discharge period T DCHG receives the value (e.g., digital representation) of. Thus, unlike the ZVS calculator 153, the ZVS calculator 553 can assert the ZVS calculator signal L4 based at least in part on Equation 13.

[0131]

[0156] As discussed above, Equation 13 can be predicted based on steady-state conditions. Thus, the ZVS calculator 553, over several switching cycles of the primary switch 152, the charge period T CHG and the discharge period T DCHG results may be filtered. This can advantageously reduce any errors due to transient conditions such as load step transitions and / or transitions from continuous conduction mode (CCM) to discontinuous mode (DCM).

[0132]

[0157] As shown, the ZVS calculator 553 receives the charge period T CHG from the charge timer 503 and may receive the discharge period T DCHG from the discharge timer 504. The charge timer 503 receives the signal FL at the start input and the comparator output signal L5 at the stop input. The comparator 501 can provide the comparator output signal L5 based on a comparison of the secondary winding voltage (i.e., the forward pin signal FW) with a low reference voltage REFL (e.g., zero volts with respect to the secondary ground RTN). Thus, the charge timer 503 can start timing in response to the signal FL issued by the AND gate 165 and stop timing when the forward pin signal FW transitions low.

[0133]

[0158] Thus, as shown by the waveform of Figure 2D, the charge timer 503 can start timing after time point 276 and stop timing at time point 279. The delay time T DE (e.g., 5 to 10 nanoseconds) is small relative to the total charge period T CHG , any errors introduced by starting the charge timer 503 simultaneously with the signal FL may be negligible.

[0134]

[0159] The discharge timer 504 receives the comparator output signal L5 at the start input and the comparator output signal L6 at the stop input. The comparator 502 can provide the comparator output signal L6 based on the comparison between the secondary winding voltage (i.e., the forward pin signal FW) and a high reference voltage REFH (e.g., 1 volt with respect to the secondary ground RTN). Therefore, the discharge timer 504 can start timing when the forward pin signal FW transitions from high to low, and stop timing when the forward pin signal FW transitions from low to high.

[0135]

[0160] Therefore, as shown by the waveforms in FIG. 4, the discharge timer 504 can start timing at time point 413 and stop timing at time point 414.

[0136]

[0161] FIG. 6 shows a conceptual flowchart 600 of zero voltage switching in the power converter system 100 according to the embodiment of FIG. 5.

[0137]

[0162] Step 601 can correspond to issuing a signal FL to turn on the primary switch 152.

[0138]

[0163] Step 602 can correspond to starting the charge timer 503. For example, the AND gate 165 can issue a signal FL to go high at the start input of the charge timer 503.

[0139]

[0164] Referring to FIG. 4, the decision step 603 can correspond to the operation of the charge timer 503 before the waveform 405 transitions low (e.g., before time point 413). As discussed above with respect to FIG. 5, the decision step 603 can be implemented using the comparator 501 that provides the comparator output signal L5 based on the comparison between the secondary winding voltage (i.e., the forward pin signal FW) and a low reference voltage REFL (e.g., zero volts with respect to the secondary ground RTN).

[0140]

[0165] Primary control signal V CS is issued so as to swing low, and when the primary switch turns off, the charging timer 503 can stop timing. Thus, the conceptual flow diagram 600 can proceed to the next step 604 corresponding to stopping the charging timer 503 with the comparator output signal L5.

[0141]

[0166] Step 605 can correspond to starting the discharge timer 504 with the comparator output signal L5.

[0142]

[0167] Referring to FIG. 4, the decision step 606 can correspond to the operation of the discharge timer 504 before the waveform 405 transitions high (e.g., before time point 414). As discussed above with respect to FIG. 5, the decision step 606 can be implemented using a comparator 502 that provides a comparator output signal L6 based on a comparison between the secondary winding voltage (i.e., the forward pin signal FW) and a high reference voltage REFH (e.g., 1 volt with respect to the secondary ground RTN).

[0143]

[0168] Thus, at time point 414, the conceptual flow diagram 600 can proceed to the next step 607 corresponding to stopping the discharge timer 504 with the comparator output signal L6.

[0144]

[0169] Step 608 can correspond to using the ZVS calculator 553 to estimate the secondary switch holding period T CHR_ZVS using Equation 13.

[0145]

[0170] Step 609 can correspond to closing the synchronous rectifier / secondary switch (e.g., NFET127c).

[0146]

[0171] Step 610 can correspond to turning on the synchronous rectifier / secondary switch (e.g., NFET127c) for a duration given by the secondary switch holding period T CHR_ZVS and then turning off the synchronous rectifier / secondary switch (e.g., NFET127c).

[0147]

[0172] The decision step 611 can then correspond to the operation before turning on the primary switch 152. When the secondary signal (i.e., the forward pin signal FW) reaches a value substantially equal to the output voltage V OUT , the conceptual flowchart 600 can proceed to step 612 corresponding to a standby for 1 / 4 of the idle ringing period TIR.

[0148] Conclusion

[0149]

[0173] In the above description, numerous specific details are set forth in order to provide a complete understanding of the control of the secondary switch to achieve zero voltage switching. However, it will be apparent to those skilled in the art that it is not necessary to use specific details to practice the teachings herein. In other instances, well-known materials or methods are not described in detail to avoid obscuring the present disclosure.

[0150]

[0174] Throughout this specification, references to "one embodiment", "an embodiment", "an example" or "an illustration" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the (multi-output) switching power converter system. Thus, the appearances of the phrases "in one embodiment", "in an embodiment", "an example" or "an illustration" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. The particular features, structures, or characteristics may be included in an integrated circuit, an electronic circuit, a logic circuit, or other suitable components that provide the described functionality. Additionally, the figures provided herein are for illustrative purposes for those skilled in the art, and it is understood that the drawings are not necessarily drawn to scale.

[0151]

[0175] The foregoing description of the above-exemplified examples of the present disclosure, including what is set forth in the abstract, is not intended to be exhaustive or to be limited to the precise forms disclosed. Specific embodiments and examples for controlling a secondary switch to achieve zero voltage switching are described herein for illustrative purposes, but various equivalent modifications are possible without departing from the broader spirit and scope of the present disclosure. In fact, it is understood that specific exemplary voltage, current, frequency, power range values, time, etc. are provided for illustrative purposes and that other values may be used in other embodiments and examples according to the teachings of this specification.

[0152]

[0176] The foregoing description may refer to elements or features as being "connected," "electrically connected," and / or "coupled" to each other. As used herein, unless otherwise specified, "connected" means that one element / feature is directly or indirectly connected to another element / feature and not necessarily mechanically connected. Similarly, unless otherwise specified, "coupled" means that one element / feature is directly or indirectly coupled to another element / feature and not necessarily mechanically coupled. Thus, the various schematic diagrams shown in the figures depict exemplary arrangements of elements and components, but in actual embodiments (assuming that the functionality of the depicted circuits is not adversely affected), additional intervening elements, devices, features, or components may be present.

[0153]

[0177] Furthermore, conditional language used herein, particularly in the English language, such as expressions corresponding to "can", "could", "might", "may", "e.g.", "for example", "such as", etc., unless otherwise specified or understood within the context in which it is used, generally is not intended to convey that a particular embodiment includes a particular feature, element, and / or state while other embodiments do not. Thus, such conditional language generally is not intended to suggest that a feature, element, and / or state is required in any way for one or more embodiments, or that one or more embodiments necessarily include logic for determining whether these features, elements, and / or states are included in or to be performed by any particular embodiment.

[0154]

[0178] While particular embodiments have been described, these embodiments are presented solely as examples and are not intended to limit the scope of the disclosure. Indeed, the novel devices, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given configuration, alternative embodiments may perform similar functions with different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and operations of the various embodiments described above may be combined to provide further embodiments. Accordingly, the scope of the invention is defined only by reference to the appended claims.

[0155]

[0179] The claims presented herein are in a form that is subordinate to one another for the purposes of filing in the USPTO, but it should be understood that any claim may be subordinate to any preceding claim of the same type, except where it is clearly technically infeasible.

[0156] Embodiment

[0157]

[0180] It should be understood that while the invention is defined in the appended claims, the invention can also (alternatively) be defined in accordance with the following embodiments.

[0158] Embodiment - Set 1:

[0159] 1. A method of dynamically switching during a switching cycle of a primary switch in a power converter, the method comprising: Closing the primary switch; Measuring a charging period while the primary switch is on; Opening the primary switch; Closing the secondary switch; Measuring a discharging period while the secondary switch is on; Opening the secondary switch; Determining an idle ringing period; Calculating a hold duration in relation to the charging period, the discharging period, and the idle ringing period; Closing the secondary switch over the hold duration; A method as described above.

[0160] 2. The method according to Embodiment 1, wherein the secondary switch is a synchronous rectifier.

[0161] 3. The method according to Embodiment 1, wherein the secondary switch is an auxiliary N-channel field effect transistor (NFET).

[0162] 4. The method according to Embodiment 1, wherein the secondary switch is an auxiliary bipolar junction transistor (BJT).

[0163] 5. The method according to Embodiment 1, wherein the power converter is a flyback converter.

[0164] 6. The method according to Embodiment 1, further comprising determining the idle ringing period using a comparator.

[0165] 7. Determining an open-ringing duration in relation to an idle-ringing period, completing a switching cycle after the open-ringing duration, The method according to Embodiment 1, further comprising:

[0166] 8. The method according to Embodiment 7, wherein the open-ringing duration is substantially equal to 1 / 4 of the idle-ringing period.

[0167] 9. Closing the primary switch The method according to Embodiment 1, comprising closing the primary switch in response to a signal transmitted from the secondary control device to the primary control device.

[0168] 10. Measuring a charging period while the primary switch is on Measuring the charging period using a charging timer, Starting the charging timer in response to a signal transmitted from the secondary control device to the primary control device, The method according to Embodiment 9, further comprising:

[0169] 11. Measuring a discharging period while the secondary switch is on The method according to Embodiment 1, comprising measuring the discharging period using a discharging timer.

[0170] 12. Calculating a holding duration in relation to the charging period, the discharging period, and the idle-ringing period The method according to Embodiment 1, further comprising calculating the holding duration in relation to a moving average of a ratio of the discharging period to the charging period.

[0171] 13. A method of dynamically switching during a switching cycle of a primary switch in a power converter, the method comprising: Closing the primary switch, Measuring a charging period while the primary switch is on, Opening the primary switch, Measuring a discharging period of a current flowing through the secondary winding, Determining an idle-ringing period, Calculating a hold duration in relation to a charging period, a discharging period, and an idle ringing cycle; Closing a secondary switch over the hold duration; A method comprising.

[0172] 14. The method according to embodiment 13, wherein the secondary switch is a synchronous rectifier.

[0173] 15. The method according to embodiment 13, wherein the secondary switch is an auxiliary N-channel field effect transistor (NFET).

[0174] 16. The method according to embodiment 13, wherein the secondary switch is an auxiliary bipolar junction transistor (BJT).

[0175] 17. The method according to embodiment 13, further comprising determining an idle ringing cycle using a comparator.

[0176] 18. Determining an on-ringing duration in relation to the idle ringing cycle; Completing a switching cycle after the on-ringing duration; The method according to embodiment 13, further comprising.

[0177] 19. The method according to embodiment 18, wherein the on-ringing duration is substantially equal to 1 / 4 of the idle ringing cycle.

[0178] 20. Closing the primary switch comprises: Closing the primary switch in response to a signal transmitted from a secondary control device to a primary control device, the method according to embodiment 13.

[0179] 21. Measuring a charging period while the primary switch is on comprises: Measuring the charging period using a charging timer; Starting the charging timer in response to a signal transmitted from a secondary control device to a primary control device; The method according to embodiment 20, comprising.

[0180] 22. Measuring the discharge period includes the method according to embodiment 13, which includes measuring the discharge period using a discharge timer.

[0181] 23. Calculating the hold duration in relation to the charge period, the discharge period, and the idle ringing period further includes calculating the hold duration in relation to the moving average of the ratio of the discharge period to the charge period, the method according to embodiment 13.

[0182] 24. A flyback converter, wherein the flyback converter comprises an energy transfer element including a primary winding configured to receive energy from a first power source and a secondary winding, a primary switch electrically coupled to the primary winding and configured to conduct during a charging period of a switching cycle, a secondary switch electrically coupled to the secondary winding, the secondary switch being configured to close over a discharge period of a switching cycle and subsequently over a hold duration, and a secondary control device comprising a zero voltage switching (ZVS) calculator configured to calculate the hold duration based at least in part on the idle ringing period, the charging period, and the discharging period. A flyback converter comprising the above.

[0183] 25. The flyback converter according to embodiment 24, wherein the idle ringing period depends at least in part on the primary capacitance and the primary inductance.

[0184] 26. The flyback converter according to embodiment 24, wherein the ZVS calculator is configured to calculate the hold duration based on the ratio of the discharge period to the charge period.

[0185] 27. The flyback converter according to embodiment 24, wherein the ZVS calculator is configured to calculate the hold duration based on the moving average of the ratio of the discharge period to the charge period.

[0186] 28. The secondary control device a charging timer configured to measure a charging period, a discharging timer configured to measure a discharging period, and a flyback converter according to Embodiment 24, comprising

[0187] 29. The charging timer of the flyback converter according to Embodiment 28, which is configured to start timing in response to a request for energy transmitted from the secondary control device to the primary control device.

[0188] 30. The charging timer of the flyback converter according to Embodiment 28, which is configured to stop timing in response to a charging stop signal, and the charging stop signal indicates a comparison between the secondary winding voltage and a low reference voltage.

[0189] 31. The flyback converter according to Embodiment 30, wherein the low reference voltage is substantially zero volts with respect to the secondary ground.

[0190] 32. The discharging timer of the flyback converter according to Embodiment 30, which is configured to start timing in response to a charging stop signal.

[0191] 33. The discharging timer of the flyback converter according to Embodiment 32, which is configured to stop timing in response to a discharging stop signal, and the discharging stop signal indicates a comparison between the secondary winding voltage and a high reference voltage having a value greater than the low reference voltage.

[0192] 34. A flyback converter, the flyback converter comprising an energy transfer element including a primary winding configured to receive energy from a first power source and a secondary winding, a primary switch electrically coupled to the primary winding and configured to conduct during a charging period of a switching cycle, The secondary winding is configured to be charged during the discharge period of the switching cycle, a primary switch, A secondary switch electrically coupled to the secondary winding, the secondary switch being configured to close over a hold duration, A secondary control device comprising a zero voltage switching (ZVS) calculator configured to calculate the hold duration based at least in part on an idle ringing period, a charge period, and a discharge period, A flyback converter comprising.

[0193] 35. The flyback converter according to embodiment 34, wherein the idle ringing period depends at least in part on a primary capacitance and a primary inductance.

[0194] 36. The flyback converter according to embodiment 34, wherein the ZVS calculator is configured to calculate the hold duration based on a ratio of the discharge period to the charge period.

[0195] 37. The flyback converter according to embodiment 34, wherein the ZVS calculator is configured to calculate the hold duration based on a moving average of a ratio of the discharge period to the charge period.

[0196] 38. The secondary control device A charge timer configured to measure the charge period, A discharge timer configured to measure the discharge period, The flyback converter according to embodiment 34 comprising.

[0197] 39. The charge timer is configured to stop timing in response to a charge stop signal, the charge stop signal indicating a comparison of a secondary winding voltage and a low reference voltage, the flyback converter according to embodiment 38.

[0198] 40. The discharge timer is configured to start timing in response to the charge stop signal, the flyback converter according to embodiment 39.

[0199] 41. The discharge timer is configured to stop timing in response to a discharge stop signal, and the discharge stop signal indicates a comparison between the secondary winding voltage and a high reference voltage having a value greater than the low reference voltage, in the flyback converter according to Embodiment 40.

[0200] Embodiment - Set 2:

[0201] 1. A method of dynamically switching during a switching cycle of a primary switch in a power converter, the method comprising: closing the primary switch; measuring a charging period while the primary switch is on; opening the primary switch; closing the secondary switch; measuring a discharge period while the secondary switch is on; opening the secondary switch; determining an idle ringing period; calculating a hold duration in relation to the charging period, the discharge period, and the idle ringing period; closing the secondary switch for the hold duration; The method as described above.

[0202] 2. The method according to Embodiment 1, wherein the secondary switch is a synchronous rectifier.

[0203] 3. The method according to Embodiment 1, wherein the secondary switch is an auxiliary N - channel field - effect transistor (NFET).

[0204] 4. The method according to Embodiment 1, wherein the secondary switch is an auxiliary bipolar junction transistor (BJT).

[0205] 5. The method according to Embodiment 1, wherein the power converter is a flyback converter.

[0206] 6. The method according to embodiment 1, further comprising determining an idle ringing period using a comparator.

[0207] 7. Determining an on-ringing duration in relation to the idle ringing period, and completing a switching cycle after the on-ringing duration, The method according to embodiment 1, further comprising.

[0208] 8. The method according to embodiment 7, wherein the on-ringing duration is substantially equal to 1 / 4 of the idle ringing period.

[0209] 9. Closing the primary switch The method according to embodiment 1, wherein closing the primary switch includes closing the primary switch by sending a signal from the secondary control device to the primary control device.

[0210] 10. Measuring a charging period while the primary switch is on Measuring the charging period using a charging timer, Starting the charging timer by a signal from the secondary control device to the primary control device, The method according to embodiment 9, including.

[0211] 11. Measuring a discharging period while the secondary switch is on The method according to embodiment 1, including measuring the discharging period using a discharging timer.

[0212] 12. Calculating a holding duration in relation to the charging period, the discharging period, and the idle ringing period The method according to embodiment 1, further including calculating the holding duration in relation to a moving average of the ratio of the discharging period to the charging period.

[0213] 13. A flyback converter, wherein the flyback converter An energy transfer element comprising a primary winding configured to receive energy from a first power source and a secondary winding A primary switch electrically coupled to the primary winding and configured to conduct during a charging period of a switching cycle A secondary switch electrically coupled to the secondary winding, the secondary switch being configured to close over a discharge period of a switching cycle and subsequently over a hold duration A secondary control device comprising a zero voltage switching (ZVS) calculator configured to calculate the hold duration based at least in part on an idle ringing period, a charging period, and a discharging period A flyback converter comprising

[0214] 14. The flyback converter according to embodiment 13, wherein the idle ringing period depends at least in part on a primary capacitance and a primary inductance

[0215] 15. The flyback converter according to embodiment 13, wherein the ZVS calculator is configured to calculate the hold duration based on a ratio of the discharge period to the charge period

[0216] 16. The flyback converter according to embodiment 13, wherein the ZVS calculator is configured to calculate the hold duration based on a moving average of a ratio of the discharge period to the charge period

[0217] 17. The secondary control device A charge timer configured to measure a charging period A discharge timer configured to measure a discharging period The flyback converter according to embodiment 13, comprising

[0218] 18. The flyback converter according to embodiment 17, wherein the charge timer is configured to start timing in response to a request for energy transmitted from the secondary control device

[0219] 19. The charging timer is configured to stop timing in response to a charging stop signal, and the charging stop signal is the flyback converter according to Embodiment 17, which indicates a comparison between the secondary winding voltage and a low reference voltage.

[0220] 20. The low reference voltage is substantially zero volts with respect to the secondary ground, and is the flyback converter according to Embodiment 19.

[0221] 21. The discharging timer is configured to start timing in response to a charging stop signal, and is the flyback converter according to Embodiment 19.

[0222] 22. The discharging timer is configured to stop timing in response to a discharging stop signal, and the discharging stop signal is the flyback converter according to Embodiment 21, which indicates a comparison between the secondary winding voltage and a high reference voltage having a value greater than the low reference voltage.

Claims

1. 1. A method for dynamically switching during a switching cycle of a primary switch in a power converter, the method comprising: closing the primary switch; measuring a charging period while the primary switch is on; opening the primary switch; Measuring a discharge period of a current through the secondary winding; determining an idle ringing period; calculating a hold duration in relation to said charge period, said discharge period, and said idle ringing period; closing the secondary switch for said hold duration; A method comprising:

2. To measure the discharge period while the secondary switch is on, the method includes: closing the secondary switch; opening the secondary switch; The method of claim 1 further comprising:

3. the secondary switch is a synchronous rectifier; or the secondary switch is an auxiliary N-channel field effect transistor (NFET) or an auxiliary bipolar junction transistor (BJT); The method according to claim 1 or 2.

4. The power converter is a flyback converter. The method according to claim 1 or 2.

5. determining the idle ringing period using a comparator. The method according to claim 1 or 2.

6. determining an open ringing duration relative to said idle ringing period; completing the switching cycle after the open ringing duration; The method of claim 1 or 2, further comprising:

7. the open ringing duration is substantially equal to 1 / 4 of the idle ringing period; The method according to claim 6.

8. Closing the primary switch closing the primary switch in response to a signal sent from a secondary controller to a primary controller. The method according to claim 1 or 2.

9. Measuring the charging period while the primary switch is on comprises: measuring said charging period using a charging timer; starting the charge timer in response to the signal sent from the secondary controller to the primary controller; The method of claim 8 , comprising:

10. Measuring the discharge duration while the secondary switch is on comprises: measuring said discharge period using a discharge timer; The method according to claim 1 or 2.

11. Calculating the hold duration in relation to the charge period, the discharge period, and the idle ringing period comprises: and calculating the hold duration in relation to a running average of a ratio of the discharge period to the charge period. The method according to claim 1 or 2.

12. A flyback converter, comprising: an energy transfer element comprising a primary winding configured to receive energy from a first power source and a secondary winding; a primary switch electrically coupled to the primary winding, the primary switch configured to conduct during a charging portion of a switching cycle; a secondary switch electrically coupled to the secondary winding, the secondary switch configured to close for a discharge period of the switching cycle followed by a hold duration; a secondary controller comprising a zero voltage switching (ZVS) calculator configured to calculate the hold duration based at least in part on an idle ringing period, the charge period, and the discharge period; A flyback converter comprising:

13. the idle ringing period being at least partially dependent on a primary capacitance and a primary inductance; 13. The flyback converter of claim 12.

14. The ZVS calculator may calculate the hold duration as: the ratio of the discharge period to the charge period; or A moving average of the ratio of the discharging period to the charging period; The calculation is configured based on 13. The flyback converter of claim 12.

15. The secondary control device includes: a charge timer configured to measure the charging period; a discharge timer configured to measure the discharge period; 13. The flyback converter of claim 12, comprising:

16. the charge timer is configured to begin timing in response to a request for energy transmitted from the secondary controller to the primary controller; 16. The flyback converter of claim 15.

17. the charge timer is configured to stop timing in response to a charge stop signal, the charge stop signal being indicative of a comparison of a secondary winding voltage to a low reference voltage; 16. The flyback converter of claim 15.

18. the low reference voltage being substantially zero volts with respect to a secondary ground; 18. The flyback converter of claim 17.

19. The discharge timer is configured to start timing in response to the charge stop signal.

18. The flyback converter of claim 17.

20. the discharge timer is configured to stop timing in response to a discharge stop signal, the discharge stop signal being indicative of a comparison between a secondary winding voltage and a high reference voltage having a value greater than the low reference voltage; 20. The flyback converter of claim 19.

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