Power stage controller

Abstract

To provide a controller that controls power stages having a plurality of phases.SOLUTION: The controller generates control signals, transmits the control signals to a plurality of phases via a first link, receives feedback signals from each phase via a second link, sums the plurality of feedback signals, and derives the average current for each phase.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to a controller for controlling a power stage having multiple phases. The present disclosure also relates to a power supply device including such a controller coupled to a power stage having multiple phases.

Background Art

[0002] By controlling an external power module via a single remote controller, the power supply plan of an application circuit board can be improved. The power converter module can be placed near the load, and the control circuit can be integrated as part of a larger power management integrated circuit (PMIC). This configuration increases the power handling capacity of the PMIC while not increasing the power loss of the circuit. Most of the power consumed by the power converter is consumed by the remote power module. This also reduces the constraints on the power envelope of the PMIC.

[0003] The driver MOSFET (DrMos) power stage introduces a standard interface for power modules intended to supply power to large digital systems. Figure 1 shows an example of DrMos implementation. By adopting the ISL69127 controller and the ISL99227 smart power module in a similar way, a high-performance current power conversion system as shown in Figure 1 can be realized (refer to the data sheet ISL69127 "Digital Dual Output 6+1-Phase VR13 PWM Controller" (January 2018, Renesas Electronics), and the data sheet ISL99227 "Smart Power Stage (SPS) Module with Integrated High Accuracy Current and Temperature Monitors" (November 2023, Renesas Electronics)). This type of power stage is mainly for high-power systems, but can also be adapted to low-power systems, liberating large PMICs from the power losses of multiple power conversion rails. Low-power modules such as UCD74106 and the related controller UCD9244 provide a scalable power management platform while using an interface similar to the DrMos interface (refer to the data sheet "Synchronous-Buck Power Stage" (December 2012, Texas Instruments), and the data sheet "Digital PWM System Controller with 4-bit, 6-bit, or 8-bit VID Support" (February 2011, Texas Instruments)).

[0004] In the case of a system as shown in FIG. 1, since the number of pins for the interface between the control and the power module is large, the circuit board design becomes complex, and the pin cost of the power module also increases. A dual single-wire interface as shown in FIG. 2 can be adopted. As shown in FIG. 2, P91E0APMIC can be connected to the P9148A power stage via a simplified interface that uses a switching control interface DIF and a general-purpose control interface DIO. However, the current DIF and DIO interfaces are troubled by bandwidth limitations and common communication delays that degrade the performance of the power supply. Therefore, there is a need for an improved interface between the control and the power stage that has a simplified protocol that reduces bus delay, improves the transient performance of the power supply, and realizes a simplified design.

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0005] An object of the present disclosure is to address one or more of the limitations described above.

MEANS FOR SOLVING THE PROBLEMS

[0006] According to a first aspect of the present disclosure, a controller for controlling a power stage having a plurality of phases is provided. Here, the controller is configured to generate a control signal, transmit the control signal to the plurality of phases via a first link, receive a feedback signal from each phase via a second link, sum the plurality of feedback signals, and derive an average current for each phase.

[0007] Optionally, the controller includes a first port connected to the first link, a second port connected to the second link, and a resistance circuit coupled to the second port. The resistance circuit has a plurality of resistors coupled in parallel. Each resistor is connected to ground via a corresponding switch. For example, the number of resistors may be the same as the number of phases or more than the number of phases.

[0008] Optionally, the resistance circuit includes an additional switch for performing a phase address reading function.

[0009] Optionally, the control signal includes one or more of a first pulse having a first pulse width for activating a first phase, a second pulse having a second pulse width for stepwise activating additional phases, a third pulse having a third pulse width for deactivating all phases, and a fourth pulse having a fourth pulse width for each phase to initiate reading of its own address.

[0010] Optionally, the first link and the second link are unidirectional links.

[0011] Optionally, the sum of the feedback signals is proportional to the output current generated by a plurality of phases.

[0012] Optionally, the controller is further configured to generate a configuration signal for configuring one or more phases. The configuration signal is transmissible via a third link. For example, the configuration signal may be configured to activate a turn-off during zero-crossing detection of the inductor, or may be configured to set a current limit of the phase.

[0013] According to a second aspect of the present disclosure, a power supply device is provided that includes a controller according to the first aspect coupled to a power stage having a plurality of phases.

[0014] Optionally, the controller is coupled to the power stage via a single-wire interface.

[0015] Optionally, each phase includes a decoder for decoding a control signal.

[0016] Optionally, the decoder includes a finite state machine coupled to a phase counter and logic circuitry. The finite state machine is configured to execute a decoding protocol.

[0017] Optionally, the logic circuit includes an arbiter coupled to one or more weight cells.

[0018] Optionally, each phase includes an address reader configured to read the address of the phase by passing a current through an address resistor.

[0019] Optionally, the address reader includes a logic circuit configured to initiate a read sequence.

[0020] Optionally, the address reader includes a compensator circuit configured to compensate for errors generated by the address resistor. For example, the compensator circuit may include a current-controlled voltage shifter using an operational amplifier.

[0021] Optionally, the decoder is configured to measure the pulse width of each pulse in the control signal and execute an associated protocol based on the measurement.

[0022] According to a third aspect of the present disclosure, a method of controlling a power stage according to the second aspect of the present disclosure having a plurality of phases is provided. The method includes generating a control signal including a series of pulses, transmitting the control signal to a plurality of phases via a first link, for each phase, decoding the control signal and activating or deactivating the phase based on the control signal, receiving a feedback signal from each phase via a second link, summing a plurality of feedback signals, and deriving an average current for each phase.

[0023] Optionally, the control signal includes one or more of a first pulse having a first pulse width for activating a first phase, a second pulse having a second pulse width for stepwise activating additional phases, a third pulse having a third pulse width for deactivating all phases, and a fourth pulse having a fourth pulse width for each phase to initiate reading its own address. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Hereinafter, the present disclosure will be described in more detail by way of example with reference to the accompanying drawings.

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DETAILED DESCRIPTION OF THE INVENTION

[0025] FIG. 1 is a diagram of a power circuit using a conventional power stage with multiple smart power phases (refer to the data sheet ISL99227 "Smart Power Stage (SPS) Module with Integrated High Accuracy Current and Temperature Monitors" (November 2023, Renesas Electronics)), and a controller (refer to the data sheet ISL69127 "Digital Dual Output 6+1-Phase VR13 PWM Controller" (January 2018, Renesas Electronics)). This circuit is a power stage solution that can be configured for a DC / DC power converter. This circuit includes a standard interface between the power and phases of a large-scale digital system.

[0026] FIG. 2 is a diagram of a known dual single-wire interface that can be used with the power supply device of FIG. 1. With this interface, a controller can be connected to the phases using a standard control interface such as a digital interface (DIF) and a general-purpose control interface such as digital input / output (DIO). Implementing the interface set of FIG. 2 in the circuit shown in FIG. 1 helps reduce the complexity of the circuit design, but the DIF and DIO interfaces implemented in FIG. 2 suffer from bandwidth limitations and general communication delays. As a result, the performance of the power circuit deteriorates.

[0027] FIG. 3 is a flowchart of a method for controlling a power stage having multiple phases according to the present disclosure. The method includes steps 310 to 350.

[0028] In step 310, the controller generates a control signal. The control signal includes a series of pulses. In step 320, the controller transmits the control signal to the multiple phases via a first link. The first link can be, for example, a unidirectional link.

[0029] In step 330, for each phase, the control signal is decoded, and the phase is made active or inactive based on the control signal. For example, the control signal may make the phase active or inactive according to the configuration of the pulses of the control signal.

[0030] In step 340, the controller receives feedback signals from each phase via the second link. The second link can be, for example, a unidirectional link. Finally, in step 350, the controller sums the plurality of feedback signals and derives the average current for each phase. This average current for each phase may be used to balance the currents across the plurality of phases in the power stage.

[0031] FIG. 4 is a diagram of a power supply device 400 according to the present disclosure. The power supply device includes a controller 410 and a power stage 420 having N phases 430, 431,... 43N-1. The controller 410 controls the power stage 420 using a method schematically shown in FIG. 3. The controller 410 includes a first port connected to a first link 440 and a second port connected to a second link 450. Each of the plurality of phases is connected to the controller via both the first link 440 and the second link 450. Both the first link and the second link can be, for example, unidirectional links. Also, the controller 410 and the power stage 420 can be coupled via a single-wire interface.

[0032] The controller 410 is configured to control a power stage 420 having a plurality of phases. The controller 410 generates control signals transmitted to the plurality of phases via the first link 440. Each phase receives the control signal and decodes the signal. Based on the decoded control signal, each phase is made active or inactive. Each phase has a unique address. In this example, the first phase 430 has address 0, the second phase 431 has address 1, and the Nth phase 43N-1 has address N-1. This address, which will be described in detail below, is assigned at the startup of the power supply device 400.

[0033] Each phase generates a feedback signal and an output current. For example, phase 430 generates an output current Iout(0), and phase 431 generates an output current Iout(1). The total output current Iout received by the load is the sum of the respective output currents from each of the plurality of phases. The controller 410 is configured to receive the feedback signals from each phase via the second link 450. Next, the controller 410 sums the plurality of feedback signals to derive the average current per phase. This average current per phase is proportional to the output current of each phase. Therefore, the controller 410 monitors the output currents of the plurality of phases 430 using the feedback signals received via the second link 450. The output current of each phase needs to be monitored to balance the current across all phases; otherwise, excessive power dissipation and power loss may occur across the power stage 420.

[0034] In certain embodiments, the first link 440 can be a digital interface (DIF), and the second link 450 can be an analog feedback link (IFB). In other embodiments, the controller 410 can be a distributed power unit (DPU) controller, and the plurality of phases 430 can be a plurality of DPUs.

[0035] The controller 410 can further include an optional third port connected to the third link 460. In this case, each phase is connected to the controller 410 via the third link. The third link can be, for example, a bidirectional link. In such an embodiment, the controller 410 is further configured to generate configuration signals transmissible to the plurality of phases via the third link 460. The third link 460 transmits operating configuration conditions to the phases, for example, to actively turn off during zero-crossing detection of the inductor or to set the current limit of the phase. In a specific embodiment, the third link can be a digital input / output (DIO). DIO enables the transmission of more complex control signals. For this purpose, a standard bidirectional multi-device bus can be used.

[0036] The first link 440 transmits a single unidirectional control signal. The control signal is unidirectional, driven by the controller 410, and received by all of the plurality of phases 430. The control signal can be a single-ended signal (one-wire) or a differential signal (two-wire).

[0037] FIG. 5 is a waveform diagram showing an exemplary control signal 510 that can be generated by the controller 410 of FIG. 4 to control a power stage 420 including N phases 430-43N-1.

[0038] The reset state of the control signal 510 is 0. The control signal 510 includes a series of commands for a plurality of phases encoded using pulse widths. The control signal is formed by a sequence of pulses. The pulse width of each pulse may be used to perform an active or inactive function of a particular phase. In FIG. 5, the control signal 510 is formed by a sequence of pulses 511-515.

[0039] The first pulse 511 has a first pulse width T1 and activates the first phase 430. The first pulse T1 triggers the phase with address 0 to become active and resets the phase counter phcount to zero. The pulse width T1 may be selected to have a duration as small as possible. The phcount corresponding to the exemplary control signal 510 is shown in the phase count 520 of FIG. 5.

[0040] The second pulse 512 has a second pulse width T2 and stepwise activates additional phases. The second pulse 512 is triggered to activate the phase at address phcount + 1. For example, if the current phcount is 0, the T2 pulse activates the phase with address 0 + 1 = 1, and if the current phcount is 2, the T2 pulse activates the phase with address 2 + 1 = 3. The pulse width T2 of 512 is selected to be greater than the pulse width T1 of 511, but still needs to be small enough to reduce the delay in the response of the plurality of phases 430.

[0041] In a general operating phase, as the load on the power supply device 400 increases, the number of phases that need to be activated considering the load increase also increases. Therefore, the control signal can have any configuration of pulses T1 and T2. The phase detects the rising edge of the control signal and reacts according to the detected pulse width. By setting the most critical controls T1 and T2 to the minimum pulse width, the critical delay is reduced. When triggered, the phase generates an on-time conduction pulse.

[0042] In FIG. 5, a three-phase duty cycle waveform is shown. The first phase 430 with address 0 is shown as 530, the second phase 431 with address 1 is shown as 531, and the third phase 432 with address 2 is shown as 532. An exemplary control signal 510 is formed by a sequence of pulses 511, 512, 513, 514. The pulse 511 of T1 activates the phase 430 with address 0. The pulse 512 (the first pulse width T2) activates the phase 431 with address 1 as shown by the on-time conduction pulse of the duty cycle 531. The pulse 513 (the second pulse width T2) corresponds to a phase count of 2. Therefore, the phase 432 with address 2 is activated by the third pulse 513.

[0043] Additional pulses (not shown) may be used to perform different functions.

[0044] For example, an inactive pulse having a third pulse width T3 may be used to make all phases inactive. The inactive pulse sets all power stages to the high impedance mode. This can be used, for example, when the load applied to the power supply device 400 suddenly drops and it is necessary to quickly make a plurality of phases 430 inactive. Also, this inactive pulse can be used when a large load drop transient requires the use of a freewheel diode instead of a switch to obtain a higher dI / dt.

[0045] Another pulse, called an address pulse having a fourth pulse width T4, may be used for each phase to start reading its own address. The pulse width T4 may be selected to be relatively long compared to T1, T2, and T3. The address pulse triggers an address reading sequence for all of the plurality of phases. In the normal operating mode of the power supply device 400, the address pulse is sent in a control signal generated by the controller 410 when the power supply device 400 is initialized for the first time. The address pulse is transmitted to the plurality of phases via the first link 440, thereby triggering a series of events that utilize the second link 450. A resistor connected via the first link for each phase can be used to read the phase address. Alternatively, the address resistor can be connected via the second or third input for each phase. This will be described later.

[0046] The control signal 510 in FIG. 5 is merely an example of how different pulses can be configured. In general, the control signal can include one or more of the pulses described above. In an alternative embodiment, more pulses having different pulse widths can be incorporated into the control signal to encode other instructions for the power stage 420.

[0047] For example, by using a unidirectional link as the first link 440 for transmitting the generated control signal, parasitic capacitance is reduced, power consumption is lowered, and generally a simplified input / output design with increased speed becomes possible.

[0048] FIG. 6 is a circuit diagram showing an example of the connection between the controller 410 and one of the plurality of phases in FIG. 4.

[0049] The controller 410 includes a resistance circuit 412 coupled to a second port that hosts a second link 450. The resistance circuit 412 has a plurality of resistors coupled in parallel, and each resistor is connected to ground via a corresponding switch called a sense switch (Ss1 - Ssn). The resistance circuit 412 further includes an additional address read switch Sr that is used to perform an address read function in FIG. 6. The number of resistors in the resistance circuit 412 may be the same as or greater than the number of N phases. The sense switches Ss1 - Ssn are used to pull the corresponding resistor Rs to ground in order to vary the equivalent sense resistance Rs / n as a function of the number of n active phases. The address read switch Sr is used to make a short for address reading, as will be described in more detail below with reference to FIGS. 7A and 7B.

[0050] Each of the plurality of N phases includes a decoder 432 coupled to the controller via a first link 440. Each phase further includes an address reader 434 coupled to the decoder 432. Also, the address reader 434 is coupled to an address resistor R addr (also called Ra) via a second link 450. Also, each phase includes a current monitoring module 438 that receives an input from the decoder 432 and a current balance module 436 that receives an input from the address reader 434. Also, a driver 433 is provided for driving the high - side and low - side power switches of each phase.

[0051] Each phase generates a feedback signal Ifb proportional to the output current of that phase. All the feedback signals are summed at the second link port of the controller 410. The resistor circuit 412 performs the summing process. By adjusting the number of active resistors in the resistor circuit 412 to match the number of active phases, the voltage of the feedback signal comes to represent the average current per phase. The number of active resistors can be selected by passing the signal nb_phases generated by the controller 410 through the resistor circuit 412 to turn on or off a plurality of switches within the circuit. For example, when the power supply device 400 operates with a single phase and output current Io, only one resistor is connected to ground. In this case, the feedback voltage is Io / R. Here, R represents the resistance value of the resistor circuit 412. When the power supply device 400 operates with four phases, the total load current is 4Io, and since four resistors are connected to ground, the feedback voltage is maintained at Io / R. This can be used for the purpose of current balancing among the phases. When triggered, the driver 433 drives the high-side switch for a duration called the on-time Ton, which is a function of the input voltage and pre-programmed parameters. The balance circuit 436 is used to adjust the on-time Ton. When the feedback current from a single phase is greater than the average output current Io of all phases, the current balance module 436 sends a signal to the driver 433 to shorten the on-time Ton of the high-side power switch. Conversely, when the feedback current from a single phase is less than the average output current of all phases, the current balance module 436 sends a signal to the driver 433 to increase the on-time Ton of the high-side power switch.

[0052] Each phase in a plurality of phases is assigned an individual address. Generally, the assigned address starts from 0 and is assigned continuously. The address reading for each phase is performed when the power supply device 400 is first connected to the power supply and starts when the decoder 432 receives and decodes the address pulse of pulse width T4. This starts the address reading sequence. The address reading switch Sr is turned on, and Raddr A current is passed through it to measure the voltage of that phase, and its own address is notified to that phase. Each phase has its own R arranged along a second link between the controller 410 and the phase. addr There is. Each resistor for address reading is arranged in front of the common node between the plurality of phases and the controller so that each phase reads its own resistor.

[0053] FIG. 7A is a circuit diagram showing an exemplary embodiment of the address reader 434. The same components as in the previous figures are labeled with the same reference numerals and have the same meaning. The address reader 434 includes a logic circuit 434a that receives a decoded control signal from a decoder 432 that starts the reading sequence of the phase 430. The logic circuit 434a is coupled to the address resistor Ra via an ADC. The address reader 434 also includes a current source for supplying the read current Iread. The logic circuit 434a is configured to supply an enable signal Isns_ena for turning on the current source.

[0054] Address reading is performed by passing the read current Iread through the address resistor Ra and measuring the voltage across it: V Ra =V sns-dpu -V sns . When Isns_ena = 1, Iread is passed through Ra, otherwise Iread = 0. Since the address reader 434 can only measure the phase voltage V sns-dpu with respect to ground, the resistance circuit 412 of the controller 410 turns on Sr to short-circuit the current sensing resistor R s / n and draws the control voltage V sns to ground. The read current I read having a preset known value is forced through the address resistor R a by the address reader 434, while V sns is drawn to ground. The phase voltage is obtained by the following formula: V sns-dpu =R a I read. To determine Ra and, ultimately, the phase address, the analog-to-digital converter ADC of the address reader 434 measures V sns-dpu and, since I read is known, the address can be determined (R a = V sns-dpu / I read ).

[0055] During the address reading operation, the phase does not supply power. Since the current i * is the measured value of the output current of the phase, i * = 0 during the address reading operation. Outside of the address reading, the current I read is deactivated, the current i * is proportional to the output current of the phase, and the voltage of the control circuit 412 is obtained by the following formula: V sns = R s i * . In the case of a power stage in which multiple phases are connected in parallel, the voltage is obtained by the following formula: V sns = R s / nx(i * 1 + i * 2 +... i * n ) = (Rs / n)i * total . Here, n represents the number of phases that make up the power stage. Each phase can compare its output current to the average load current by measuring V sns-dpu = R a i * + (R s / n)i * total . The error generated through the resistor R a during the operation mode that is not the address reading operation can be compensated via the compensator 434b. In this example, the compensator 434b is formed by a current-controlled voltage shifter that uses an operational amplifier. The operational amplifier outputs V sns-dpu - (R b Ki * ). Here, R b is an arbitrary resistance value, and K represents a multiplication factor that is a function of the address reading resistance R a . Therefore, the output of the compensator 434b is as follows: Ra i * +(R s / n)i * total -Ki * R b Therefore, K = R a / R b By setting it this way, the error caused by the address resistance R a can be removed.

[0056] Figure 7B is a waveform diagram showing the signals transmitted and received by the address leader circuit 434 of Figure 7A in the sequence of the address leader. The control signal 710 is received by the decoder 432 including the pulse T4. As shown by the waveform 720, the address read switch Sr is turned on at the start of the pulse T4. The decoder 432 supplies the signal 730 to the logic circuit 434a to start the address reading and asserts the enable signal Isns_ena 740. The read current I read passes through the address resistance and maintains a constant value, and the voltage 750 can be measured. This measurement can be performed by an analog-to-digital converter or several comparators that compare the voltage with several fixed reference voltages. The voltage measured across the address resistance gives the address of the target phase. The waveform 760 indicates that the phase has an unconfirmed ID until the address leader 434 finishes the voltage measurement. This point is shown by the waveform 770. At this point, the leader logic circuit 434a generates another pulse indicating that the address of the phase has been read, where the address read switch Sr is turned off. If the detection switch is turned off, it can be turned on again. Now the phase is ready to receive further commands through the control signal 710. In an alternative embodiment, the address reading sequence can be set to end after a predetermined time, and at the end, the address is in a read state, so the pulse 770 is not necessary.

[0057] When a resistor having a value readable by an address reader is connected to the first link, the delay increases and the pulse width decoding performance of the decoder 432 may deteriorate. Therefore, instead, the second link is used. This link is designed to operate at a low speed, and the input of the second link of the control circuit can be pulled down to a low level with a large transistor without degrading the interface.

[0058] Using R for address reading addr introduces additional errors into the phase balance system required to balance the loads of different power modules in the system. Therefore, the current balance module 436 is configured to take into account the additional voltage error introduced by R when balancing the feedback signals across all the plurality of phases 430. addr

[0059] The decoder 432 is configured to decode control signals. This measures the pulse width of each pulse in the control signal and executes the associated protocol based on this measurement.

[0060] FIG. 8A is an implementation example of a decoder 800 coupled to a driver 433 for driving the high-side and low-side power switches of a phase. The decoder 800 includes a decode asynchronous finite state machine (AFSM) 810 coupled to a counter or phase counter 820 and a logic circuit 830. The logic circuit 830 includes an arbiter WAITX and two wait cells WAIT1 and WAIT0. The logic circuit 830 is implemented as part of the decoder to mitigate the undesirable effects of glitches or non-persistent signals. The arbiter WAITX and the wait cells WAIT1, WAIT0 are used as a sanitization circuit. FIGS. 9A-9C show the circuits of the arbiter and the wait cells. An implementation example of the arbiter and the wait cells is described in the literature "WAITX: An Arbiter for Non-persistent Signals" by Khomenko, D. Sokolov, A. Mokhov, and A. Yakovlev (2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), San Diego, CA, USA (2017)). A brief explanation is given here. In the case of the cell WAIT1, the output is asserted when the input to the cell is 1. Also, the output has a value of 1 and remains this value even if the input becomes greater than 1. When WAIT1 is disabled, no output is generated. Similarly, the cell WAIT0 waits for the input to become 1 after being enabled. WAITX receives two inputs and waits for either input to become 1 after being enabled. However, the arbiter WAITX passes only one input of 1. After being enabled, WAITX holds the first input that becomes 1 and passes it through WAITX until WAITX is disabled.

[0061] In operation, decoder 800 receives a control signal from controller 410 at the input of logic circuit 830, and this control signal is sent to decode AFSM 810. AFSM 810 is configured to decode the control signal via a decode protocol. Decode AFSM 810 updates switch drive circuit 433 and counter 820. Since decoder 800 represents the implementation examples of decoder 432 in FIGS. 6 and 7a, it operates in the same manner as them.

[0062] FIG. 8B is a flowchart of a decode protocol executed by decode AFSM 810, also called a signal transition graph (STG). This flowchart provides instructions on how to execute any one of the pulses having pulse widths T1, T2, T3, or T4 of the control signal.

[0063] By the controller of the present disclosure, better control of the switching of N plural phases 430 to 43N-1 via the first link in combination with a simple but effective current balance and monitoring system via a shared feedback signal transmitted via the second link becomes possible. Optionally, the controller may include an overall configuration of the entire power supply system 400 via the third link. The combination of the first link and the second link can be used for power module / phase address reading without increasing the pin count. Reduction of the pin count reduces the cost associated with the pins of the power module and alleviates the pin congestion of the PMIC incorporating the control circuit.

[0064] FIG. 9A is a schematic diagram showing the operation of a first weight cell for use in the circuit of FIG. 8A.

[0065] FIG. 9B is a schematic diagram showing the operation of a second weight cell for use in the circuit of FIG. 8A.

[0066] FIG. 9C is a schematic diagram showing the operation of an arbiter for use in the circuit of FIG. 8A.

[0067] Those skilled in the art will understand that it is possible to make modifications to the disclosed arrangements without departing from the present disclosure. Accordingly, the foregoing description of specific embodiments is for purposes of illustration only and not for purposes of limitation. It will be apparent to those skilled in the art that minor modifications can be made without materially altering the operations described above.

Claims

1. 1. A controller for controlling a power stage having multiple phases, comprising: Generate a control signal; transmitting said control signals to a plurality of phases over a first link; receiving a feedback signal from each of the phases via a second link; summing a plurality of said feedback signals; configured to derive an average current for each phase; controller.

2. the controller has a first port connected to the first link, a second port connected to the second link, and a resistive circuit coupled to the second port; The resistor circuit includes a plurality of resistors coupled in parallel, each of the resistors being connected to ground via a corresponding switch. The controller of claim 1 .

3. The controller of claim 2 , wherein the resistor circuit includes an additional switch for performing a phase address read function.

4. The control signal is a first pulse having a first pulse width for activating a first phase; a second pulse having a second pulse width for incrementally activating an additional phase; a third pulse having a third pulse width to deactivate all of said phases; and each of the phases includes one or more fourth pulses having a fourth pulse width for initiating reading of its own address; The controller of claim 1 .

5. The controller of claim 1 , wherein the first link and the second link are unidirectional links.

6. The controller of claim 1 , wherein the sum of the feedback signals is proportional to an output current produced by a plurality of the phases.

7. The controller of claim 1 , wherein the controller is further configured to generate configuration signals for configuring one or more of the phases, the configuration signals being transmittable over a third link.

8. 10. A power supply comprising the controller of claim 1 coupled to a power stage having multiple phases.

9. 9. The power supply of claim 8, wherein the controller is coupled to the power stage via a single-wire interface.

10. 9. The power supply of claim 8, wherein each of the phases includes a decoder for decoding a control signal.

11. 11. The power supply of claim 10, wherein the decoder includes a finite state machine coupled to a phase counter and logic circuitry, the finite state machine configured to execute a decoding protocol.

12. 12. The power supply of claim 11, wherein the logic circuitry includes an arbiter coupled to one or more weight cells.

13. 9. The power supply of claim 8, wherein each of the phases includes an address reader configured to read the address of the phase by passing a current through an address resistor.

14. The power supply of claim 13 , wherein the address reader includes logic configured to initiate a read sequence.

15. 15. The power supply of claim 14, wherein the address reader includes a compensator circuit configured to compensate for errors caused by the address resistor.

16. 11. The power supply of claim 10, wherein the decoder is configured to measure a pulse width of each pulse in the control signal and execute an associated protocol based on the measurements.

17. 1. A method for controlling a power stage having multiple phases, comprising the steps of: generating a control signal comprising a series of pulses; transmitting said control signals over a first link to a plurality of said phases; for each of the phases, decoding the control signal and activating or deactivating the phase based on the control signal; receiving a feedback signal from each of the phases via a second link; summing a plurality of said feedback signals; deriving the average current for each phase; A method comprising:

18. The control signal is a first pulse having a first pulse width for activating a first phase; a second pulse having a second pulse width for incrementally activating an additional phase; a third pulse having a third pulse width to deactivate all of said phases; and each of the phases includes one or more fourth pulses having a fourth pulse width for initiating reading of its own address; 20. The method of claim 17.

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