Semiconductor device

Abstract

To provide a semiconductor device capable of improving breakdown resistance.SOLUTION: A semiconductor device 101 includes a wiring region RF1, a cell region RC, and a boundary region RB1. The semiconductor device also includes first and second electrodes 11, 12, a wiring 51, a semiconductor layer 20, a control electrode 31, and first and second contact regions 41a, 41b. The semiconductor layer includes first to sixth semiconductor regions. A first semiconductor region 21 is disposed in the cell region, the wiring region, and the boundary region. A second semiconductor region 22 includes a boundary semiconductor portion 22b disposed in the boundary region. Fifth and sixth semiconductor regions 25, 26 are disposed in the cell region and are located between the first semiconductor region and the second electrode. A first contact region is disposed in the boundary region and is in contact with a boundary semiconductor portion. The second contact region is disposed in the cell region and is in contact with the fifth semiconductor region. The impurity concentration of the second conductivity type in the boundary semiconductor portion is lower than the impurity concentration of the second conductivity type in the fifth semiconductor region.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] In semiconductor devices such as RC-IGBT (Reverse Conducting - Insulated Gate Bipolar Transistor), when an excessive current flows, the semiconductor device may be damaged.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a semiconductor device capable of improving the breakdown withstand voltage.

Means for Solving the Problems

[0005] According to an embodiment of the present invention, a semiconductor device includes a first wiring region, a cell region, and a first boundary region between the first wiring region and the cell region. The semiconductor device includes a first electrode, a second electrode, a first wiring, a semiconductor layer, a first control electrode, a first contact region, and a second contact region. At least a part of the second electrode is disposed in the first boundary region and the cell region. The direction from the first electrode to the second electrode is along a first direction. The direction from the first wiring region to the cell region is along a second direction intersecting the first direction. The first wiring is disposed in the first wiring region. The semiconductor layer includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, and a sixth semiconductor region of the first conductivity type. The first semiconductor region is disposed in the cell region, the first wiring region, and the first boundary region. The second semiconductor region includes a first boundary semiconductor portion disposed in the first boundary region. At least a part of the first boundary semiconductor portion is provided between the first semiconductor region and the second electrode. The third semiconductor region is disposed between the first electrode and the first semiconductor region. The fourth semiconductor region is disposed between the first electrode and the first semiconductor region. The impurity concentration of the first conductivity type in the fourth semiconductor region is higher than the impurity concentration of the first conductivity type in the first semiconductor region. The fifth semiconductor region is disposed in the cell region and is located between the first semiconductor region and the second electrode. The sixth semiconductor region is disposed in the cell region and is located between the first semiconductor region and the second electrode. The sixth semiconductor region is electrically connected to the second electrode. The first control electrode faces the first semiconductor region, the second semiconductor region, and the sixth semiconductor region with a first insulating portion therebetween. The first control electrode is electrically connected to the first wiring. The first contact region is disposed in the first boundary region and is in contact with the first boundary semiconductor portion. The first contact region electrically connects the first boundary semiconductor portion and the second electrode. The second contact region is disposed in the cell region and is in contact with the fifth semiconductor region. The second contact region electrically connects the fifth semiconductor region and the second electrode.The impurity concentration of the second conductivity type in the first boundary semiconductor portion is lower than the impurity concentration of the second conductivity type in the fifth semiconductor region.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In this specification and each figure, elements similar to those described above with respect to the previously shown figures are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate.

[0008] FIG. 1 is a schematic plan view illustrating a semiconductor device according to an embodiment. The semiconductor device 101 shown in FIG. 1 is, for example, an RC-IGBT. In the semiconductor device 101, a plurality of first wiring regions RF1, a plurality of cell regions RC, and a plurality of first boundary regions RB1 are set in the X-Y plane.

[0009] The cell region RC is, for example, a region where transistors are formed. The plurality of cell regions RC are arranged in the X direction. The cell region RC is provided with, for example, a second electrode 12. The second electrode 12 extends in the X-Y plane so as to cover substantially the entire cell region RC, for example.

[0010] In the first wiring region RF1, a first wiring 51 (gate wiring) is provided. The first wiring region RF1 corresponds to, for example, a gate finger portion. The gate finger portion is a region where the gate electrode is connected to the gate wiring. The first wiring 51 and the first wiring region RF1 extend in the Y direction. A plurality of first wiring regions RF1 (a plurality of first wirings 51) are arranged in the X direction. The direction from the first wiring region RF1 to the cell region RC follows the X direction. The first wiring region RF1 and the cell region RC are alternately arranged in the X direction. A cell region RC is located between two adjacent first wiring regions RF1 in the X direction, and a space between the first wiring regions RF1 is located between two adjacent cell regions RC in the X direction. A first boundary region RB1 is located between the first wiring region RF1 and the cell region RC adjacent to each other in the X direction. The plurality of first wirings 51 are electrically connected to a first electrode pad 51P.

[0011] Each first boundary region RB1 is a region located between each first wiring region RF1 and each cell region RC. The first boundary region RB1 extends in the Y direction along the first wiring region RF1. The first boundary region RB1 is continuous with the first wiring region RF1 and the cell region RC. The configuration of the first boundary region RB1 will be described later.

[0012] FIG. 2 is a schematic plan view illustrating a semiconductor device according to an embodiment. In FIG. 2, illustration of the first wiring 51, the second electrode 12, etc. is omitted, and the layout of the lower layer of the first wiring 51 and the second electrode 12 is schematically shown. The semiconductor device 101 includes a semiconductor layer 20. A plurality of trenches T1 are provided in the semiconductor layer 20. As will be described later, a first control electrode 31 (gate electrode) and a first insulating portion 71 are provided in each trench T1. In FIG. 2, for the sake of convenience, the trench T1, the first control electrode 31, and the first insulating portion 71 are collectively represented by a broken line.

[0013] The trench T1 (the first control electrode 31 and the first insulating portion 71) extends in the X direction. Each trench T1 (each first control electrode 31 and each first insulating portion 71) is disposed across the plurality of cell regions RC, the plurality of first boundary regions RB1, and the plurality of first wiring regions RF1 described with reference to FIG. 1. The plurality of trenches T1 (the plurality of first control electrodes 31 and the plurality of first insulating portions 71) are arranged in the Y direction.

[0014] Furthermore, a plurality of trenches T3 may be provided in the semiconductor layer 20. As will be described later, a conductive member 33 (for example, a dummy electrode) and an insulating portion 73 are provided in each trench T3. In FIG. 2, for the sake of convenience, the trench T3, the conductive member 33, and the insulating portion 73 are collectively represented by a broken line.

[0015] Similar to the trench T1, the trench T3 (the conductive member 33 and the insulating portion 73) extends in the X direction. Each trench T3 (each conductive member 33 and each insulating portion 73) is disposed across the plurality of cell regions RC, the plurality of first boundary regions RB1, and the plurality of first wiring regions RF1. The plurality of trenches T3 (the plurality of conductive members 33 and the plurality of insulating portions 73) are arranged in the Y direction. The trench T1 and the trench T3 are arranged in the Y direction.

[0016] In a plan view, the first wiring 51 shown in FIG. 1 intersects the plurality of trenches T1 and the plurality of trenches T3.

[0017] FIG. 3 is a schematic cross-sectional perspective view illustrating a semiconductor device according to an embodiment. FIGS. 4, 5, and 6 are schematic cross-sections illustrating a semiconductor device according to an embodiment. FIG. 3 shows the region R1 shown in FIG. 1. FIG. 4 shows a cross-section taken along line A-A shown in FIG. 3. FIG. 5 shows a cross-section taken along line B-B shown in FIG. 3. FIG. 6 shows a cross-section taken along line C-C shown in FIG. 3.

[0018] As shown in FIG. 3, the semiconductor device 101 includes a first wiring 51, a semiconductor layer 20, a first control electrode 31, and a contact portion 41 (a first contact region 41a and a second contact region 41b). As shown in FIGS. 4 to 6, the semiconductor device 101 includes a first electrode 11 and a second electrode 12.

[0019] The direction from the first electrode 11 to the second electrode 12 follows the Z direction (first direction). The Z direction is, for example, a direction perpendicular to the upper surface of the semiconductor layer 20 (for example, a semiconductor substrate). In the description of the embodiment, one direction intersecting the Z direction is defined as the X direction (second direction), and a direction intersecting the Z direction and the X direction is defined as the Y direction (third direction). The X direction and the Y direction may each be a direction perpendicular to the Z direction. The X direction and the Y direction may be perpendicular to each other. The direction from the first electrode 11 to the second electrode 12 may be referred to as "up", and the opposite direction may be referred to as "down". "Up" and "down" are based on the relative positional relationship between the first electrode 11 and the second electrode 12 and are independent of the direction of gravity.

[0020] In the following example, the first conductivity type is n-type and the second conductivity type is p-type. However, in the embodiment, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0021] The semiconductor layer 20 is located between the first electrode 11 and the second electrode 12 and between the first electrode 11 and the first wiring 51. As shown in FIG. 3, the semiconductor layer 20 includes a first semiconductor region 21, a second semiconductor region 22, a third semiconductor region 23, a fourth semiconductor region 24, a plurality of fifth semiconductor regions 25, and a plurality of sixth semiconductor regions 26.

[0022] The first wiring region RF1 is, for example, in a plan view seen from above (i.e., when viewed along the Z direction), the range where the first wiring 51 is provided. The first wiring region RF1 is a region where the first wiring 51 and the first control electrode 31 are connected. Elements overlapping the first wiring 51 in the Z direction are elements arranged in the first wiring region RF1. In the first wiring region RF1, the contact portion 41 (the first contact region 41a and the second contact region 41b) for electrically connecting the semiconductor layer 20 and the second electrode 12 may not be provided. The second electrode 12 may not be provided in the first wiring region RF1. In the first wiring region RF1, a semiconductor region (e.g., the sixth semiconductor region 26) serving as the emitter of the transistor may not be formed.

[0023] The cell region RC is a region including, in a plan view, the range where a semiconductor region (e.g., the sixth semiconductor region 26) serving as the emitter of the transistor is provided. For example, the cell region RC includes, in a plan view, the range where at least one of the fifth semiconductor region 25 and the sixth semiconductor region 26 is provided.

[0024] As shown in FIG. 3, in this example, the position of the end of the cell region RC (the position in contact with the first boundary region RB1) is the position of the end of the sixth semiconductor region 26 on the first boundary region RB1 side, or the position of the end of the fifth semiconductor region 25 on the first boundary region RB1 side. The position of the end of the cell region RC is the boundary between the second semiconductor region 22 and the fifth semiconductor region 25 in the X direction and the boundary between the second semiconductor region 22 and the sixth semiconductor region 26 in the X direction. In other words, the sixth semiconductor region 26 or the fifth semiconductor region 25 is in contact with the first boundary region RB1.

[0025] The first boundary region RB1 is, for example, a range in which an end portion (first contact region 41a) of the contact portion 41 in the X direction is arranged. The first boundary region RB1 does not include a range in which the first wiring 51 is provided in a plan view, and does not include a range in which the fifth semiconductor region 25 and the sixth semiconductor region 26 are provided. The first boundary region RB1 may not include a semiconductor region of a first conductivity type (for example, n-type) provided on the second semiconductor region 22. As an example, the first boundary region RB1 is a range within 50 micrometers (μm) in the X direction from the first wiring 51 in a plan view.

[0026] The first electrode 11 is arranged, for example, in the first wiring region RF1, the first boundary region RB1, and the cell region RC. As shown in FIGS. 4 and 5, at least a part of the second electrode 12 is arranged in the cell region RC and the first boundary region RB1.

[0027] The first semiconductor region 21 has a first conductivity type (for example, n-type). As shown in FIG. 3, the first semiconductor region 21 is arranged in the cell region RC, the first wiring region RF1, and the first boundary region RB1. That is, the first semiconductor region 21 includes a semiconductor portion 21a arranged in the first wiring region RF1, a semiconductor portion 21b arranged in the first boundary region RB1, and a semiconductor portion 21c arranged in the cell region RC. The semiconductor portion 21a is located, for example, between the first electrode 11 and the first wiring 51. At least a part of the semiconductor portion 21b is located, for example, between the first electrode 11 and the second electrode 12. The semiconductor portion 21c is located, for example, between the first electrode 11 and the second electrode 12.

[0028] The second semiconductor region 22 has a second conductivity type (e.g., p-type). As shown in FIG. 3, the first semiconductor region 21 is located between the second semiconductor region 22 and the first electrode 11. In this example, the second semiconductor region 22 is disposed in the cell region RC, the first wiring region RF1, and the first boundary region RB1. That is, for example, the second semiconductor region 22 includes a semiconductor portion (wiring semiconductor portion 22a) disposed in the first wiring region RF1, a semiconductor portion (boundary semiconductor portion 22b) disposed in the first boundary region RB1, and a semiconductor portion (cell semiconductor portion 22c) disposed in the cell region RC. The wiring semiconductor portion 22a (first wiring semiconductor portion) is located between the first semiconductor region 21 and the first wiring 51. At least a part of the boundary semiconductor portion 22b (first boundary semiconductor portion) is located between the first semiconductor region 21 and the second electrode 12. The cell semiconductor portion 22c is located between the first semiconductor region 21 and the second electrode 12. The second semiconductor region 22 (wiring semiconductor portion 22a, boundary semiconductor portion 22b, cell semiconductor portion 22c) may be composed of a plurality of regions separated by trenches.

[0029] The impurity concentration of the second conductivity type in the wiring semiconductor portion 22a may be the same as the impurity concentration of the second conductivity type in the boundary semiconductor portion 22b. The impurity concentration of the second conductivity type in the cell semiconductor portion 22c may be the same as the impurity concentration of the second conductivity type in the boundary semiconductor portion 22b.

[0030] The third semiconductor region 23 is between the first electrode 11 and the first semiconductor region 21. The third semiconductor region 23 is disposed in the first wiring region RF1, the first boundary region RB1, and the cell region RC. The third semiconductor region 23 has a second conductivity type. The third semiconductor region 23 is in contact with, for example, the first electrode 11 and is electrically connected to the first electrode 11.

[0031] The fourth semiconductor region 24 is between the first electrode 11 and the first semiconductor region 21. The fourth semiconductor region 24 is disposed in the first wiring region RF1, the first boundary region RB1, and the cell region RC. The fourth semiconductor region 24 has a first conductivity type. The impurity concentration of the first conductivity type in the fourth semiconductor region 24 is higher than the impurity concentration of the first conductivity type in the first semiconductor region 21. The fourth semiconductor region 24 is in contact with, for example, the first electrode 11 and is electrically connected to the first electrode 11. The fourth semiconductor region 24 is aligned with the third semiconductor region 23 in a direction (for example, the Y direction) in the X-Y plane. For example, a plurality of third semiconductor regions 23 and a plurality of fourth semiconductor regions 24 are alternately aligned in the Y direction. The direction in which the plurality of trenches T1 are aligned may be different from the direction in which the plurality of third semiconductor regions 23 and the plurality of fourth semiconductor regions 24 are aligned.

[0032] As shown in FIG. 3, the fifth semiconductor region 25 is disposed in the cell region RC. The fifth semiconductor region 25 has a second conductivity type. The fifth semiconductor region 25 is located between the first semiconductor region 21 and the second electrode 12. The fifth semiconductor region 25 is located between the cell semiconductor portion 22c and the second electrode 12.

[0033] The impurity concentration of the second conductivity type in the boundary semiconductor portion 22b of the second semiconductor region 22 is lower than the impurity concentration of the second conductivity type in the fifth semiconductor region. Also, the impurity concentration of the second conductivity type in the wiring semiconductor portion 22a may be lower than the impurity concentration of the second conductivity type in the fifth semiconductor region. The impurity concentration of the second conductivity type in the cell semiconductor portion 22c may be lower than the impurity concentration of the second conductivity type in the fifth semiconductor region. In other words, the impurity concentration of the second conductivity type in the fifth semiconductor region may be higher than the impurity concentration of the second conductivity type in the second semiconductor region 22.

[0034] As shown in FIG. 3, the sixth semiconductor region 26 is disposed in the cell region RC. The sixth semiconductor region 26 has a first conductivity type. The sixth semiconductor region 26 is located between the first semiconductor region 21 and the second electrode 12. The sixth semiconductor region 26 is located between the cell semiconductor portion 22c and the second electrode 12. The sixth semiconductor region 26 is adjacent to the fifth semiconductor region 25 in the X direction.

[0035] A semiconductor region 81 may be further provided in the semiconductor layer 20. The semiconductor region 81 is located between the first semiconductor region 21 and the fourth semiconductor region 24, and between the first semiconductor region 21 and the third semiconductor region 23. The semiconductor region 81 has a first conductivity type. The impurity concentration of the first conductivity type in the semiconductor region 81 is higher than the impurity concentration of the first conductivity type in the first semiconductor region 21 and lower than the impurity concentration of the first conductivity type in the fourth semiconductor region 24.

[0036] As shown in FIG. 3, a trench T1 is provided in the semiconductor layer 20. The trench T1 reaches from the upper surface 20f of the semiconductor layer 20 (the upper surfaces of the second semiconductor region 22, the fifth semiconductor region 25, and the sixth semiconductor region 26) to the first semiconductor region 21. A first insulating portion 71 is provided on the inner wall of the trench T1. A first control electrode 31 is provided inside the first insulating portion 71 in the trench T1. The first control electrode 31 is insulated from the semiconductor layer 20 by the first insulating portion 71.

[0037] For example, as shown in FIG. 4, the first control electrode 31 includes a portion (cell electrode portion 31c) disposed in the cell region RC. The first control electrode 31 faces the first semiconductor region 21, the second semiconductor region 22, and the sixth semiconductor region 26 in the cell region RC via the first insulating portion 71, respectively. More specifically, the direction from the cell electrode portion 31c to a part of the semiconductor portion 21c of the first semiconductor region 21 is along the Y direction. The direction from the cell electrode portion 31c to the cell semiconductor portion 22c of the second semiconductor region 22 is along the Y direction. The direction from the cell electrode portion 31c to one of the sixth semiconductor regions 26 is along the Y direction. The first insulating portion 71 is provided between the cell electrode portion 31c and the semiconductor portion 21c, between the cell electrode portion 31c and the cell semiconductor portion 22c, and between the cell electrode portion 31c and the sixth semiconductor region 26.

[0038] Also, the first control electrode 31 faces the fifth semiconductor region 25 in the cell region RC via the first insulating portion 71 (see FIG. 3). The direction from the first control electrode 31 (cell electrode portion 31c) to one of the fifth semiconductor regions 25 is along the Y direction. The first insulating portion 71 is provided between the cell electrode portion 31c and the fifth semiconductor region 25.

[0039] As shown in FIG. 3, the second contact region 41b is disposed in the cell region RC. For example, a plurality of second contact regions 41b are arranged in the Y direction. As shown in FIG. 3, the second contact region 41b is provided on the fifth semiconductor region 25 and is in contact with the fifth semiconductor region 25. The second contact region 41b electrically connects the fifth semiconductor region 25 and the second electrode 12. In other words, the fifth semiconductor region 25 is electrically connected to the second electrode 12 via the second contact region 41b. For example, each of the plurality of second contact regions 41b is in contact with each of the plurality of fifth semiconductor regions 25.

[0040] Also, as shown in FIGS. 3 and 4, some of the second contact regions 41b are provided on the sixth semiconductor region 26 and are in contact with the sixth semiconductor region 26. The second contact region 41b electrically connects the sixth semiconductor region 26 and the second electrode 12. In other words, the sixth semiconductor region 26 is electrically connected to the second electrode 12 via the second contact region 41b. For example, each of some of the second contact regions 41b is in contact with each of the plurality of sixth semiconductor regions 26.

[0041] For example, as shown in FIG. 4, an insulating portion 70A is provided on the semiconductor layer 20. The insulating portion 70A is disposed between the semiconductor layer 20 and the second electrode 12, between the first control electrode 31 and the second electrode 12, and between the conductive member 33 and the second electrode 12. The second electrode 12 is insulated from the first control electrode 31.

[0042] As shown in FIG. 5, the first control electrode 31 includes a portion (boundary electrode portion 31b) disposed in the first boundary region RB1. In the first boundary region RB1, the first control electrode 31 faces the first semiconductor region 21 and the second semiconductor region 22 respectively via the first insulating portion 71. More specifically, the direction from the boundary electrode portion 31b to a part of the semiconductor portion 21b of the first semiconductor region 21 is along the Y direction. The direction from the boundary electrode portion 31b to the boundary semiconductor portion 22b of the second semiconductor region 22 is along the Y direction. The first insulating portion 71 is provided between the boundary electrode portion 31b and the semiconductor portion 21b, and between the boundary electrode portion 31b and the boundary semiconductor portion 22b.

[0043] As shown in FIG. 3, the first contact region 41a is disposed in the first boundary region RB1. For example, a plurality of first contact regions 41a are arranged in the Y direction. As shown in FIGS. 3 and 5, the first contact region 41a is provided on the boundary semiconductor portion 22b of the second semiconductor region 22 and is in contact with the boundary semiconductor portion 22b. The first contact region 41a electrically connects the boundary semiconductor portion 22b and the second electrode 12. In other words, the boundary semiconductor portion 22b (the second semiconductor region 22) is electrically connected to the second electrode 12 via the first contact region 41a. For example, each of the plurality of first contact regions 41a is in contact with the boundary semiconductor portion 22b.

[0044] As shown in FIG. 3, in this example, the first contact region 41a and the second contact region 41b are included in the contact portion 41 extending in the X direction. In other words, the first contact region 41a and the second contact region 41b are each a part of the contact portion 41. The contact portion 41 is a conductive portion provided on the semiconductor layer 20 and electrically connects the semiconductor layer 20 and the second electrode 12. The contact portion 41 may be a conductive portion continuous with the second electrode 12 or may be provided integrally with the second electrode 12.

[0045] In the example of FIG. 3, a plurality of contact portions 41 are arranged in the Y direction. In a plan view, trenches (for example, trench T1 or trench T3) and the contact portion 41 are alternately arranged in the Y direction. The first contact region 41a and the second contact region 41b extend in the X direction. The first contact region 41a is continuous with the second contact region 41b.

[0046] For example, as shown in FIG. 6, the first control electrode 31 includes a portion (wiring electrode portion 31a) disposed in the first wiring region RF1. The first control electrode 31 faces the first semiconductor region 21 and the second semiconductor region 22 in the first wiring region RF1 via the first insulating portion 71. More specifically, the direction from the wiring electrode portion 31a to a part of the semiconductor portion 21a of the first semiconductor region 21 is along the Y direction. The direction from the wiring electrode portion 31a to the wiring semiconductor portion 22a of the second semiconductor region 22 is along the Y direction. The first insulating portion 71 is provided between the wiring electrode portion 31a and the semiconductor portion 21a, and between the wiring electrode portion 31a and the wiring semiconductor portion 22a.

[0047] For example, as shown in FIG. 6, the first wiring 51 is located above the wiring electrode portion 31a. In other words, the wiring electrode portion 31a is between the first wiring 51 and the first semiconductor region 21. The wiring electrode portion 31a is electrically connected to the first wiring 51 in the first wiring region RF1. Specifically, a conductive portion 61 (contact) for electrically connecting the wiring electrode portion 31a and the first wiring 51 is provided. The conductive portion 61 is provided between the wiring electrode portion 31a and the first wiring 51 and contacts the wiring electrode portion 31a and the first wiring 51.

[0048] For example, as shown in FIG. 6, an insulating portion 70B is provided on the semiconductor layer 20. The insulating portion 70B is disposed between the semiconductor layer 20 and the first wiring 51. The first wiring 51 is insulated from the semiconductor layer 20, the second electrode 12, and the conductive member 33.

[0049] Also, as already described, in this example, a trench T3 is provided. As shown in FIG. 3, the trench T3, similar to the trench T1, reaches from the upper surface 20f of the semiconductor layer 20 (the upper surfaces of the second semiconductor region 22, the fifth semiconductor region 25, and the sixth semiconductor region 26) to the first semiconductor region 21. An insulating portion 73 is provided on the inner wall of the trench T3. A conductive member 33 is provided inside the insulating portion 73 in the trench T3. The conductive member 33 is insulated from the semiconductor layer 20 by the insulating portion 73. The depth of the trench T3 may be the same as the depth of the trench T1.

[0050] For example, as shown in FIG. 4, in the cell region RC, the conductive member 33 faces each of the first semiconductor region 21, the second semiconductor region 22, and the fifth semiconductor region 25 via the insulating portion 73. The conductive member 33 is electrically connected to the second electrode 12 by the wiring W. For example, as shown in FIG. 5, in the first boundary region RB1, the conductive member 33 faces each of the first semiconductor region 21 and the second semiconductor region 22 via the insulating portion 73. For example, as shown in FIG. 6, in the first wiring region RF1, the conductive member 33 faces each of the first semiconductor region 21 and the second semiconductor region 22 via the insulating portion 73. The conductive member 33 is insulated from the first wiring 51 and the first control electrode 31. The conductive member 33 functions as a member that relaxes, for example, the concentration of the electric field.

[0051] An example of the material of each element of the semiconductor device 101 will be described. Each semiconductor region (such as the first to sixth semiconductor regions) of the semiconductor layer 20 contains silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. For example, a silicon substrate can be used for the semiconductor layer 20. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity. The first control electrode 31, the conductive member 33 (and the second control electrode 32 described later) contain a conductive material such as polysilicon. The insulating portion 70A, the insulating portion 70B, the first insulating portion 71, the insulating portion 73 (and the second insulating portion 72 described later) contain an insulating material such as silicon oxide. The contact portion 41 (the first contact region 41a, the second contact region 41b, and the third contact region 41c described later) contains a conductive material such as titanium or tungsten. The first wiring 51, the first electrode 11, the second electrode 12, the first electrode pad 51P, the second electrode pad 52P, the conductive portion 61 (and the second wiring 52, the second electrode pad 52P, the conductive portion 62 described later) contain a metal such as aluminum.

[0052] As described above, the semiconductor device 101 operates as an RC-IGBT. With a positive voltage applied to the first electrode 11 (e.g., collector electrode) with respect to the second electrode 12 (e.g., emitter electrode), a voltage equal to or higher than the threshold value is applied to the first control electrode 31 (e.g., gate electrode). As a result, an inversion layer (n-type inversion layer) is formed in the second semiconductor region 22 (e.g., p-type base region), and IGBT operation is started in the cell region RC. For example, a channel (inversion layer) is formed in the region of the second semiconductor region 22 facing the first control electrode 31. For example, electrons flow from the second electrode 12 through the sixth semiconductor region 26 (e.g., emitter region) and the channel to the first semiconductor region 21 (e.g., drift region). For example, holes flow from the first electrode 11 through the third semiconductor region 23 (e.g., collector region) to the first semiconductor region 21. Thereafter, when the voltage applied to the first control electrode 31 becomes lower than the threshold value, the inversion layer in the first semiconductor region 21 disappears, and the IGBT operation ends.

[0053] For example, a circuit is configured by a plurality of semiconductor devices 101. When the IGBT operation ends in one semiconductor device 101 in the circuit, an induced electromotive force is applied to the second electrode 12 of another semiconductor device 101 due to the inductance component of the circuit. When an induced electromotive force is applied to the second electrode 12, this other semiconductor device 100 operates as a diode. During diode operation, for example, holes flow from the second electrode 12 through the fifth semiconductor region 25 to the second semiconductor region 22 and the first semiconductor region 21. For example, electrons flow from the first electrode 11 through the fourth semiconductor region 24 (e.g., cathode region) to the first semiconductor region 21.

[0054] In the reverse recovery when the diode operation of the semiconductor device 101 ends, the holes accumulated in the first semiconductor region 21 are discharged to the second electrode 12 through the second semiconductor region 22, the fifth semiconductor region 25, and the contact (the first contact region 41a or the second contact region 41b). The electrons accumulated in the first semiconductor region 21 are discharged to the first electrode 11 through the fourth semiconductor region 24.

[0055] In a semiconductor device, holes accumulated in a finger portion and its vicinity (e.g., a first wiring region RF1 and a first boundary region RB1) flow to a first contact region 41a via, for example, a second semiconductor region 22 during reverse recovery. Therefore, the current flowing through the first contact region 41a may increase. For example, the current may concentrate at an end portion of the first contact region 41a on the side of a first wiring 51. When a large current flows, the semiconductor device may be damaged.

[0056] In contrast, in the embodiment, as described above, the impurity concentration of the second conductivity type in the boundary semiconductor portion 22b is lower than the impurity concentration of the second conductivity type in the fifth semiconductor region 25. Thereby, during diode operation, injection of holes from the first contact region 41a into the semiconductor layers of the first boundary region RB1 and the first wiring region RF1 is suppressed. The accumulated carriers in the semiconductor layers of the first boundary region RB1 and the first wiring region RF1 can be reduced. Also, for example, the flow of holes from the fifth semiconductor region 25 in a cell region RC to the first boundary region RB1 is suppressed. By reducing the carrier concentration, the current in the first contact region 41a can be reduced during reverse recovery of the diode. The breakdown withstand during reverse recovery can be improved. For example, concentration of the current in the first contact region 41a can be suppressed.

[0057] During reverse bias in which a positive voltage is applied to the first electrode 11 with respect to the second electrode 12, for example, holes can be discharged from the semiconductor layer 20 to the second electrode 12 via the first contact region 41a. Therefore, for example, at the turn-off of IGBT operation, holes can also be discharged from the first contact region 41a, so current concentration is suppressed. A decrease in the breakdown withstand at the turn-off of IGBT operation is suppressed.

[0058] For example, as shown in FIG. 1, a control unit CC may be provided. The control unit CC includes, for example, a control circuit such as a CPU. The control unit CC is electrically connected to the first control electrode 31 via the first electrode pad 51P and the first wiring 51. The control unit CC is electrically connected to, for example, the second electrode 12. The control unit CC applies a voltage V1 to the first control electrode 31. The voltage V1 and the voltage of the first electrode 11 are based on the potential of the second electrode 12 (reference potential V0). The reference potential V0 is, for example, a ground potential.

[0059] For example, the first contact region 41a may form a Schottky junction with the boundary semiconductor portion 22b. When the junction between the first contact region 41a and the boundary semiconductor portion 22b is a Schottky junction, in the diode operation, the injection of holes from the first contact region 41a can be more suppressed. The current in the first contact region 41a during reverse recovery can be further reduced.

[0060] For example, the second contact region 41b may form an ohmic junction with the fifth semiconductor region 25. Thereby, the contact resistance in the cell region RC can be reduced.

[0061] FIGS. 7(a) and 7(b) are schematic graph diagrams illustrating the impurity concentration distribution in the semiconductor layer. FIG. 7(a) illustrates the impurity concentration along the E-E line shown in FIG. 3, and FIG. 7(b) illustrates the impurity concentration along the D-D line shown in FIG. 3. The horizontal axis represents the depth Dp (μm). The origin of the horizontal axis is the position in the Z direction of the upper surface 20f of the semiconductor layer 20. The depth Dp corresponds to the distance along the Z direction from the upper surface 20f. The position D21 on the horizontal axis corresponds to the boundary position between the first semiconductor region 21 and the second semiconductor region 22. The vertical axis is the impurity concentration Cn (atoms / cm 3 )

[0062] In FIG. 7(a), the impurity concentration Cn in the range where the depth Dp is from 0 to the position D21 represents the distribution (first distribution) of the impurity concentration of the second conductivity type along the Z direction from the surface in contact with the first contact region 41a of the boundary semiconductor portion 22b to the first semiconductor region 21. The first distribution is, for example, a distribution with one peak. The first distribution has a first peak P1.

[0063] The first peak P1 is the peak of the impurity concentration distribution along the Z direction in the boundary semiconductor portion 22b. The value of the first peak P1 (the impurity concentration of the second conductivity type at the first peak P1) is the first concentration Cp1.

[0064] In FIG. 7(b), the impurity concentration Cn in the range where the depth Dp is from 0 to the position D21 represents the distribution (second distribution) of the impurity concentration of the second conductivity type along the Z direction from the surface in contact with the second contact region 41b of the fifth semiconductor region 25 to the first semiconductor region 21. The number of peaks of the second distribution is larger than the number of peaks of the first distribution. The second distribution is, for example, a distribution with two peaks. The second distribution has a second peak P2 and a third peak P3. The position of the third peak P3 is shallower than the position of the second peak P2. In other words, the position of the third peak P3 in the Z direction is between the position of the second peak P2 in the Z direction and the position of the upper surface 20f of the semiconductor layer 20 in the Z direction.

[0065] The second peak P2 is the peak of the impurity concentration distribution along the Z direction in the cell semiconductor portion 22c. The value of the second peak P2 (the impurity concentration of the second conductivity type at the second peak P2) is the second concentration Cp2.

[0066] The third peak P3 is the peak of the impurity concentration distribution along the Z direction in the fifth semiconductor region 25. The value of the third peak P3 (the impurity concentration of the second conductivity type at the third peak P3) is the third concentration Cp3.

[0067] The height of the third peak P3 is higher than the height of the first peak P1 and higher than the height of the second peak P2. That is, the third concentration Cp3 is higher than the first concentration Cp1 and higher than the second concentration Cp2. For example, the height of the first peak P1 (the first concentration Cp1) is 0.0000001 times or more and 0.01 times or less the height of the third peak P3 (the third concentration Cp3).

[0068] In FIGS. 7(a) and 7(b), the impurity concentration Cn in the range where the depth Dp is deeper than the position D21 corresponds to the impurity concentration of the first conductivity type along the Z direction in the first semiconductor region 21.

[0069] Thus, the first peak P1 having a low first distribution has a low impurity concentration in the boundary semiconductor portion 22b. As a result, during diode operation, the injection of holes from the first contact region 41a into the first boundary region RB1 and the first wiring region RF1 is suppressed. For example, the junction between the first contact region 41a and the boundary semiconductor portion 22b is likely to be a Schottky junction. Further, it has a third peak having a high second distribution, and the impurity concentration in the fifth semiconductor region 25 is high. As a result, for example, a good contact between the fifth semiconductor region 25 and the second contact region 41b can be obtained.

[0070] For example, the first concentration Cp1 is 1×10 14 atoms / cm 3 or more and 1×10 18 atoms / cm 3 or less. The depth of the first peak P1 (the distance along the Z direction from the upper surface 20f to the position of the first peak P1) is, for example, 0.5 μm or more and 5 μm or less. For example, the second concentration Cp2 is 1×10 14 atoms / cm 3 or more and 1×10 18 atoms / cm 3 or less. The depth of the second peak P2 (the distance along the Z direction from the upper surface 20f to the position of the second peak P2) is, for example, 0.5 μm or more and 5 μm or less. For example, the third concentration Cp3 is 1×10 18 atoms / cm 31 × 10 or less 21 atoms / cm 3 is as follows. The depth of the third peak P3 (the distance along the Z direction from the upper surface 20f to the position of the third peak P3) is, for example, 0.0 μm or more and 2 μm or less.

[0071] The impurity concentration distributions shown in FIGS. 7(a) and 7(b) can be formed, for example, by ion implantation. In this example, the depth of the second peak P2 is the same as the depth of the first peak P1. Also, in this example, the height of the second peak P2 is the same as the height of the first peak P1. In other words, the first concentration Cp1 is the same as the second concentration Cp2. Although not shown, the impurity concentration distribution (the height and depth of the peak) along the Z direction in the wiring semiconductor portion 22a may be the same as the impurity concentration distribution along the Z direction in the boundary semiconductor portion 22b. For example, the wiring semiconductor portion 22a, the boundary semiconductor portion 22b, and the cell semiconductor portion 22c can be formed by a common ion implantation process. For example, an increase in manufacturing cost can be suppressed.

[0072] FIG. 8 is a schematic cross-sectional perspective view illustrating a semiconductor device according to an embodiment. FIG. 8 represents a partial region of the semiconductor device 102 according to the embodiment, similar to FIG. 3. In the semiconductor device 102 shown in FIG. 8, the impurity concentration distribution of the second conductivity type in the boundary semiconductor portion 22b is different from the impurity concentration distribution of the second conductivity type in the cell semiconductor portion 22c. Other than this, the configuration of the semiconductor device 102 may be the same as that of the semiconductor device 101.

[0073] In the semiconductor device 102, for example, the impurity concentration of the second conductivity type in the boundary semiconductor portion 22b is lower than the impurity concentration of the second conductivity type in the cell semiconductor portion 22c. The impurity concentration of the second conductivity type in the boundary semiconductor portion 22b may be the same as the impurity concentration of the second conductivity type in the wiring semiconductor portion 22a.

[0074] FIGS. 9(a) and 9(b) are schematic graph diagrams illustrating the impurity concentration distribution in a semiconductor layer. FIG. 9(a) illustrates the impurity concentration along the G-G line shown in FIG. 8, and FIG. 9(b) illustrates the impurity concentration along the F-F line shown in FIG. 8. Similar to FIG. 7, the horizontal axis represents the depth Dp (μm), and the vertical axis represents the impurity concentration Cn (atoms / cm 3 ).

[0075] FIG. 9(a), similar to FIG. 7(a), represents the distribution of the impurity concentration of the second conductivity type (the first distribution) along the Z direction from the surface of the boundary semiconductor portion 22b to the first semiconductor region 21, and the distribution of the impurity concentration of the first conductivity type along the Z direction in the first semiconductor region 21. FIG. 9(b), similar to FIG. 7(b), represents the distribution of the impurity concentration of the second conductivity type (the second distribution) along the Z direction from the surface of the fifth semiconductor region 25 to the first semiconductor region 21, and the distribution of the impurity concentration of the first conductivity type along the Z direction in the first semiconductor region 21.

[0076] In this example, the height of the first peak P1 is lower than the height of the second peak P2. In other words, the first concentration Cp1 is lower than the second concentration Cp2. Thereby, during the diode operation, the injection of holes from the first contact region 41a to the first boundary region RB1 and the first wiring region RF1 is more suppressed. For example, the junction between the first contact region 41a and the boundary semiconductor portion 22b is more likely to be a Schottky junction.

[0077] FIG. 10 is a schematic cross-sectional perspective view illustrating a semiconductor device according to an embodiment. FIG. 10, similar to FIG. 3, represents a partial region of the semiconductor device 103 according to the embodiment. In the semiconductor device 103 shown in FIG. 10, the semiconductor layer 20 has a trench T4. The trench T3 (the conductive member 33 and the insulating portion 73) is divided in the X direction by the trench T4. The first contact region 41a and the second contact region 41b are not continuous. Other than this, the configuration of the semiconductor device 103 may be the same as that of the semiconductor device 101.

[0078] The trench T4 is provided in the first boundary region RB1 and extends in the Y direction. By means of the trench T4, the semiconductor layer of the first wiring region RF1 is separated from the semiconductor layer of the cell region RC. By separating the semiconductor layer of the first wiring region RF1, the injection of holes into the semiconductor layer of the first wiring region RF1 is more suppressed. In the reverse recovery of the diode, the increase in current in the first contact region 41a is more suppressed, and the breakdown voltage can be improved.

[0079] The boundary semiconductor portion 22b is divided by the trench T4 into a portion on the first wiring region RF1 side and a portion on the cell region RC side. The first contact region 41a is separated from the second contact region 41b in the X direction. The direction from the first contact region 41a to the second contact region 41b is along the X direction. In a plan view, the trench T4 is between the first contact region 41a and the second contact region. That is, the position of the trench T4 in the X direction is between the position of the first contact region 41a in the X direction and the position of the second contact region 41b in the X direction.

[0080] The trench T4 is provided between the portion of the boundary semiconductor portion 22b in contact with the first contact region 41a and the fifth semiconductor region 25. The portion of the boundary semiconductor portion 22b in contact with the first contact region 41a is separated by the trench T4 from the fifth semiconductor region 25 of the cell region RC and the cell semiconductor portion 22c. The injection of holes in the portion of the boundary semiconductor portion 22b in contact with the first contact region 41a is more suppressed. The increase in current in the first contact region 41a can be more suppressed.

[0081] The trench T4 extends from the upper surface 20f of the semiconductor layer 20 toward the first semiconductor region 21 and reaches the first semiconductor region 21. That is, the upper end of the trench T4 is located on the upper surface 20f of the semiconductor layer 20, and the lower end of the trench T4 is in contact with the first semiconductor region 21.

[0082] Trench T4 intersects with trench T1. An insulating portion 74 is provided inside trench T4. The insulating portion 74 is continuous with the first insulating portion 71 in trench T1. In trench T4, a conductive member may be provided inside the insulating portion 74. This conductive member is insulated from the semiconductor layer 20 by the insulating portion 74 and may be continuous from the first control electrode 31. The depth of trench T4 may be the same as the depth of trench T1. Trench T4 (insulating portion 74) is away from trench T3 (insulating portion 73).

[0083] FIG. 11 is a schematic cross-sectional perspective view illustrating a semiconductor device according to an embodiment. FIG. 12 is a schematic plan view illustrating a semiconductor device according to an embodiment. FIG. 11 shows a partial region of the semiconductor device 104 according to the embodiment. FIG. 12 shows a view of FIG. 11 seen from above. In the semiconductor device 104 shown in FIGS. 11 and 12, the arrangement of the fifth semiconductor region 25 and the sixth semiconductor region 26 is different from that of the semiconductor device 101 described above. Other than this, the configuration of the semiconductor device 104 may be the same as that of the semiconductor device 101.

[0084] As shown in FIG. 11, in the cell region RC, a plurality of sixth semiconductor regions 26 are arranged in the X direction. The fifth semiconductor region 25 and the sixth semiconductor region 26 are arranged alternately in the X direction.

[0085] As shown in FIG. 12, the distance D1 between two adjacent sixth semiconductor regions 26 among the plurality of sixth semiconductor regions 26 becomes shorter as it approaches the first boundary region RB1. More specifically, the distance D1a between the region 26a and the region 26b shown in FIG. 12 is shorter than the distance D1b between the region 26b and the region 26c. The distance D1b is shorter than the distance D1c between the region 26c and the region 26d. Note that the regions 26a, 26b, 26c, and 26d are each one of the sixth semiconductor regions 26. The regions 26a, 26b, 26c, and 26d are arranged in this order from the side of the first boundary region RB1. For example, the lengths of the sixth semiconductor regions 26 in the X direction are the same as each other.

[0086] Note that the distance D1 between two adjacent sixth semiconductor regions 26 corresponds to the length in the X direction of the fifth semiconductor region 25 located between the two sixth semiconductor regions. That is, the length of the fifth semiconductor region 25 in the X direction becomes shorter as it approaches the first boundary region RB1.

[0087] For example, in the cell region RC, the density of the sixth semiconductor regions 26 is higher the closer it is to the first boundary region RB1. More specifically, for example, as shown in FIG. 12, the cell region RC has a first region r1 and a second region r2. The second region r2 is between the first region r1 and the first boundary region RB1. In plan view, the area of the sixth semiconductor regions 26 per unit area in the second region r2 is larger than the area of the sixth semiconductor regions 26 per unit area in the first region r1. The distance (for example, the distance D1a between the regions 26a and 26b) between the sixth semiconductor regions 26 adjacent to each other in the second region r2 is shorter than the distance (for example, the distance D1c between the regions 26c and 26d) between the sixth semiconductor regions 26 adjacent to each other in the first region r1.

[0088] Thus, a large number of the sixth semiconductor regions 26 are provided on the first boundary region RB1 side of the cell region RC. In the diode operation, the injection of holes on the first boundary region RB1 side of the cell region RC is suppressed. The accumulated carriers in the first boundary region RB1 and the first wiring region RF1 can be reduced. The current in the first contact region 41a during reverse recovery can be further reduced. The breakdown voltage can be improved.

[0089] FIG. 13 is a schematic plan view illustrating a semiconductor device according to an embodiment. In the semiconductor device 105 shown in FIG. 13, a plurality of first wiring regions RF1, a plurality of cell regions RC, and a plurality of first boundary regions RB1 are set in the same manner as in the semiconductor device 101 described above. Further, a plurality of second wiring regions RF2 and a plurality of second boundary regions RB2 are set in the semiconductor device 105.

[0090] A second wiring 52 (gate wiring) is provided in the second wiring region RF2. The second wiring region RF2 corresponds to, for example, a gate finger portion. The second wiring 52 and the second wiring region RF2 extend in the Y direction. A plurality of second wiring regions RF2 (a plurality of second wirings 52) are arranged in the X direction. The direction from the cell region RC to the second wiring region RF2 is along the X direction. For example, the first wiring 51 (first wiring region RF1) and the second wiring 52 (second wiring region RF2) are alternately arranged in the X direction. A cell region RC is disposed between the first wiring region RF1 and the second wiring region RF2. For example, a second electrode 12 is disposed between the first wiring 51 and the second wiring 52. The plurality of second wirings 52 are electrically connected to a second electrode pad 52P. The first electrode pad 51P and the second electrode pad 52P are disposed on the diagonal line of a substantially rectangular semiconductor device in plan view.

[0091] Each second boundary region RB2 is a region located between each second wiring region RF2 and each cell region RC. The second boundary region RB2 extends in the Y direction along the second wiring region RF2. The second boundary region RB2 is continuous with the second wiring region RF2 and the cell region RC.

[0092] The control unit CC is electrically connected to a second control electrode 32, which will be described later, via a second electrode pad 52P and a second wiring 52. The control unit CC applies a voltage V2 to the second control electrode 32.

[0093] FIG. 14 is a schematic plan view illustrating a semiconductor device according to an embodiment. In FIG. 14, illustration of a first wiring 51, a second wiring 52, a second electrode 12, etc. is omitted, and a layout of a lower layer of the first wiring 51, the second wiring 52, and the second electrode 12 is schematically shown. Also in this example, a plurality of trenches T1 (a first control electrode 31, a first insulating portion 71) and a plurality of trenches T3 (a conductive member 33, an insulating portion 73) are provided in the semiconductor layer 20. Further, a plurality of trenches T2 are provided in the semiconductor layer 20. As will be described later, a second control electrode 32 (gate electrode) and a second insulating portion 72 are provided in each trench T2. In FIG. 14, for convenience, the trenches T2, the second control electrode 32, and the second insulating portion 72 are collectively represented by a broken line. Also, similar to FIG. 2, the trenches T1 and T3 are represented by a broken line.

[0094] The trench T2 (the second control electrode 32 and the second insulating portion 72) extends in the X direction. A plurality of trenches T2 (a plurality of second control electrodes 32 and a plurality of second insulating portions 72) are arranged in the Y direction. The trenches T1, the trench T2, and the trench T3 are arranged in the Y direction. In the example of FIG. 14, a trench T3 is arranged between the trench T1 and the trench T2. The trenches T1 (the first control electrode 31, the first insulating portion 71), the trenches T2 (the second control electrode 32, the second insulating portion 72), and the trenches T3 (the conductive member 33, the insulating portion 73) are arranged across a plurality of cell regions RC, a plurality of first boundary regions RB1, a plurality of first wiring regions RF1, a plurality of second boundary regions RB2, and a plurality of second wiring regions RF2.

[0095] In plan view, the first wiring 51 shown in FIG. 13 intersects a plurality of trenches T1, a plurality of trenches T2, and a plurality of trenches T3. In plan view, the second wiring 52 shown in FIG. 13 intersects a plurality of trenches T1, a plurality of trenches T2, and a plurality of trenches T3.

[0096] FIG. 15 is a schematic cross-sectional perspective view illustrating a semiconductor device according to an embodiment. FIG. 15 shows the region R2 shown in FIG. 13. A part of the semiconductor layer 20 is located between the first electrode 11 and the second wiring 52. For example, in plan view seen from above, the second wiring region RF2 is a range in which the second wiring 52 is provided. The second wiring region RF2 is a region where the second wiring 52 and the second control electrode 32 are connected. The contact portion 41 (the first contact region 41a, the second contact region 41b, the third contact region 41c) may not be provided in the second wiring region RF2. The second electrode 12 may not be provided in the second wiring region RF2. A semiconductor region (for example, the sixth semiconductor region 26) serving as an emitter of a transistor may not be formed in the second wiring region RF2.

[0097] In this example, the position of the end of the cell region RC (the position in contact with the second boundary region RB2) is the position of the end on the second boundary region RB2 side of the sixth semiconductor region 26, or the position of the end on the second boundary region RB2 side of the fifth semiconductor region 25. In other words, the sixth semiconductor region 26 or the fifth semiconductor region 25 is in contact with the second boundary region RB2.

[0098] The second boundary region RB2 is, for example, a range in which the end portion (the third contact region 41c) of the contact portion 41 in the X direction is arranged. The second boundary region RB2 does not include the range in which the second wiring 52 is provided in plan view, and does not include the range in which the fifth semiconductor region 25 and the sixth semiconductor region 26 are provided. The second boundary region RB2 may not include a semiconductor region of a first conductivity type (for example, n-type) provided on the second semiconductor region 22. As an example, the second boundary region RB2 is a range within 50 μm in the X direction from the second wiring 52 in plan view.

[0099] Also, a part of the second electrode 12 is disposed in the second boundary region RB2. Also, in the second wiring region RF2 and the second boundary region RB2, a part of the first electrode 11, a part of the first semiconductor region 21, a part of the second semiconductor region 22, a part of the third semiconductor region 23, a part of the fourth semiconductor region 24, and a part of the semiconductor region 81 are disposed.

[0100] For example, the first semiconductor region 21 includes a semiconductor portion 21d disposed in the second wiring region RF2 and a semiconductor portion 21e disposed in the second boundary region RB2. The semiconductor portion 21d is located, for example, between the first electrode 11 and the second wiring 52. At least a part of the semiconductor portion 21e is located, for example, between the first electrode 11 and the second electrode 12.

[0101] For example, the second semiconductor region 22 includes a semiconductor portion (second wiring semiconductor portion 22d) disposed in the second wiring region RF2 and a semiconductor portion (second boundary semiconductor portion 22e) disposed in the second boundary region RB2. The second wiring semiconductor portion 22d is located between the first semiconductor region 21 and the second wiring 52. At least a part of the second boundary semiconductor portion 22e is located between the first semiconductor region 21 and the second electrode 12. The second wiring semiconductor portion 22d and the second boundary semiconductor portion 22e may be composed of a plurality of regions separated by trenches.

[0102] The concentration and the distribution along the Z direction of the impurity of the second conductivity type in the second wiring semiconductor portion 22d may be the same as those of the wiring semiconductor portion 22a shown in FIG. 16. The concentration and the distribution along the Z direction of the impurity of the second conductivity type in the second boundary semiconductor portion 22e may be the same as those of the boundary semiconductor portion 22b shown in FIG. 16. For example, the impurity concentration of the second conductivity type in the second boundary semiconductor portion 22e is lower than the impurity concentration of the second conductivity type in the fifth semiconductor region 25. For example, the impurity concentration of the second conductivity type in the second boundary semiconductor portion 22e may be the same as the impurity concentration of the second conductivity type in the second wiring semiconductor portion 22d.

[0103] The trench T2 reaches from the upper surface 20f of the semiconductor layer 20 to the first semiconductor region 21. A second insulating portion 72 is provided on the inner wall of the trench T2. A second control electrode 32 is provided inside the second insulating portion 72 within the trench T2. The second control electrode 32 is insulated from the semiconductor layer 20 by the second insulating portion 72.

[0104] In the cell region RC, the second control electrode 32 faces the first semiconductor region 21, the second semiconductor region 22, and the fifth semiconductor region 25, respectively, with the second insulating portion 72 interposed therebetween. In the cell region RC, the direction from the second control electrode 32 toward the first semiconductor region 21, the second semiconductor region 22, and the fifth semiconductor region 25 is along the Y direction. The second insulating portion 72 is located between the first semiconductor region 21, the second semiconductor region 22, and the fifth semiconductor region 25, respectively, and the second control electrode 32. The second insulating portion 72 does not have to be in contact with the sixth semiconductor region 26. The second control electrode 32 is insulated from the second electrode 12, the conductive member 33, the first control electrode 31, and the first wiring 51.

[0105] In the second boundary region RB2 and the second wiring region RF2, the first control electrode 31 faces the first semiconductor region 21 and the second semiconductor region 22, respectively, with the first insulating portion 71 interposed therebetween. In the second boundary region RB2 and the second wiring region RF2, the second control electrode 32 faces the first semiconductor region 21 and the second semiconductor region 22, respectively, with the second insulating portion 72 interposed therebetween. In the second boundary region RB2 and the second wiring region RF2, the conductive member 33 faces the first semiconductor region 21 and the second semiconductor region 22, respectively, with an insulating portion 73 (third insulating portion) interposed therebetween.

[0106] The third contact region 41c is disposed in the second boundary region RB2. For example, a plurality of third contact regions 41c are arranged in the Y direction. The third contact region 41c is provided on the second boundary semiconductor portion 22e of the second semiconductor region 22 and is in contact with the second boundary semiconductor portion 22e. The third contact region 41c electrically connects the second boundary semiconductor portion 22e and the second electrode 12. In this example, the third contact region 41c is included in the contact portion 41. For example, the third contact region 41c extends in the X direction and is continuous with the second contact region 41b.

[0107] In the second wiring region RF2, a part of the first control electrode 31, a part of the second control electrode 32, and a part of the conductive member 33 are disposed between the second wiring 52 and the first semiconductor region 21. The second control electrode 32 is electrically connected to the second wiring 52 in the second wiring region RF2. Specifically, a conductive part 62 (contact) for electrically connecting the second control electrode 32 and the second wiring 52 is provided. The conductive part 62 is provided between the second control electrode 32 and the second wiring 52 and is in contact with the second control electrode 32 and the second wiring 52. The second wiring 52 is insulated from the semiconductor layer 20, the second electrode 12, the first control electrode 31, and the conductive member 33.

[0108] FIG. 16 is a schematic cross-sectional perspective view illustrating a semiconductor device according to an embodiment. FIG. 16 shows the region R3 shown in FIG. 13. The second control electrode 32 faces the first semiconductor region 21 and the second semiconductor region 22 via the second insulating portion 72 in the first boundary region RB1 and the first wiring region RF1.

[0109] As shown in FIG. 16, for example, the number of trenches T2 (the second control electrode 32, the second insulating portion 72) may be larger than the number of trenches T1 (the first control electrode 31, the first insulating portion 71).

[0110] FIGS. 17(a) to 17(c) are schematic diagrams illustrating the operation of a semiconductor device according to an embodiment. The horizontal axis in FIGS. 17(a) to 17(c) is the time tm. FIGS. 17(a) and 17(b) illustrate the voltage V1 and the voltage V2 in the IGBT operation of one semiconductor device 105 (for example, the first semiconductor device 105A described later). As described above, the voltage V1 is the voltage applied to the first control electrode 31, and the voltage V2 is the voltage applied to the second control electrode 32. For example, before the time tm1, the voltage V1 and the voltage V2 are positive (on state). At this time, for example, an n-type inversion layer is formed at the interface between the second semiconductor region 22 and the first insulating portion 71, and at the interface between the second semiconductor region 22 and the second insulating portion 72. For example, electrons flow from the second electrode 12 to the first semiconductor region 21 through the n-type inversion layer formed at the interface between the second semiconductor region 22 and the first insulating portion 71.

[0111] For example, at the time tm1, the voltage V2 changes from positive to negative (off state). As a result, for example, at the interface between the second semiconductor region 22 and the second insulating portion 72, the n-type inversion layer disappears and a p-type accumulation layer is formed. For example, at the time tm2 after the time tm1, the voltage V1 changes from positive to negative (off state). As a result, for example, at the interface between the second semiconductor region 22 and the first insulating portion 71, the n-type inversion layer disappears and a p-type accumulation layer is formed. The potential of the first control electrode 31 or the second control electrode 32 in the off state is lower than the potential of the first control electrode 31 or the second control electrode 32 in the on state. For example, the potential of the first control electrode 31 or the second control electrode 32 in the off state is lower than the potential of the second electrode 12 (reference potential V0). For example, at the time tm3 after the time tm2, the voltage V1 and the voltage V2 change from negative to positive.

[0112] Thus, in one example of the semiconductor device 105, before the first control electrode 31 turns off, the second control electrode 32 turns off. For example, the control unit CC turns off the second control electrode 32 before the first control electrode 31 turns off. By such an operation, for example, the loss when the semiconductor device 105 turns off can be reduced.

[0113] During the period TI between the times tm1 and tm2, for example, a p-type inversion layer is formed at the interface with the second insulating portion 72 of the first semiconductor region 21, and holes are discharged from the first semiconductor region 21 to the second electrode 12. By controlling the concentration of the stored carriers, for example, the loss when the first control electrode 31 is turned off can be reduced. As an example, the length of the period TI (the difference between the times tm1 and tm2) can be 10 microseconds or more and 100 microseconds or less.

[0114] Also, as described above, the number of the second control electrodes 32 may be larger than the number of the first control electrodes 31. For example, holes can be discharged from the first semiconductor region 21 to the second electrode 12 more. The loss can be reduced more.

[0115] FIG. 17(c) illustrates the voltages V1 and V2 in the diode operation. For example, FIG. 17(c) represents the voltages V1 and V2 in another semiconductor device 105 (for example, the second semiconductor device 105B described later) that constitutes a circuit with the first semiconductor device 105A. The operations shown in FIGS. 17(a) to 17(c) may be repeated.

[0116] For example, in the diode operation, between the times tm1, tm2 and tm4, the voltages V1 and V2 are negative (off state). When the voltages V1 and V2 are negative, for example, a p-type accumulation layer is formed at the interface with the first insulating portion 71 of the second semiconductor region 22 and at the interface with the second insulating portion 72 of the second semiconductor region 22. For example, holes flow from the second electrode 12 to the first semiconductor region 21.

[0117] At time tm4 after time tm2, voltages V1 and V2 change from negative to positive (on state). At time tm5 after time tm4, voltages V1 and V2 change from positive back to negative. Time tm5 is, for example, the time immediately before time tm3. A period Td is provided between time tm5 and time tm3. Thus, in the diode operation where current flows from the second electrode 12 to the first electrode 11, the first control electrode 31 and the second control electrode 32 are in the on state. Such an operation can reduce, for example, the recovery loss of the diode.

[0118] For example, during period TD from time tm4 to time tm5, at the interface between the second semiconductor region 22 and the first insulating portion 71 and at the interface between the second semiconductor region 22 and the second insulating portion 72, the p-type accumulation layer disappears and an n-type inversion layer is formed. Thereby, for example, electrons are extracted from the first semiconductor region 21 to the second electrode 12 through the n-type inversion layer at the interface between the second semiconductor region 22 and the first insulating portion 71. By controlling the concentration of the stored carriers, the loss at the end of the diode operation can be reduced, for example. As an example, the length of period TD (the duration of the on state of the first control electrode 31 and the second control electrode 32) can be set to be 10 microseconds or more and 100 microseconds or less.

[0119] During the reverse recovery when the diode operation of the semiconductor device 105 ends, a part of the holes accumulated in the first semiconductor region 21 is discharged to the second electrode 12 through, for example, the second semiconductor region 22 and the third contact region 41c.

[0120] As described above, the impurity concentration of the second conductivity type in the second boundary semiconductor portion 22e is lower than the impurity concentration of the second conductivity type in the fifth semiconductor region 25. During diode operation, the injection of holes from the third contact region 41c into the second boundary region RB2 and the second wiring region RF2 is suppressed. The accumulated carriers in the semiconductor layers of the second boundary region RB2 and the second wiring region RF2 can be reduced. In the reverse recovery of the diode, the current in the third contact region 41c can be reduced. The breakdown tolerance in reverse recovery can be further improved. For example, the third contact region 41c may form a Schottky junction with the second boundary semiconductor portion 22e. During diode operation, the injection of holes from the third contact region 41c can be more effectively suppressed.

[0121] As in the period TD of FIG. 17(c), by gate control that turns on the control electrode in the diode mode, the carriers in the cell region decrease, and the current in the cell region decreases. Accordingly, the current in the boundary region near the gate wiring may relatively increase. For example, the current may concentrate at the contact end. In contrast, in the embodiment, as already described, the impurity concentration of the second conductivity type in the boundary semiconductor portion 22b and the second boundary semiconductor portion 22e is low, and the injection of holes into the boundary region is suppressed. According to the embodiment, even when gate control is performed, an increase in the current at the contact end can be suppressed.

[0122] FIG. 18 is a schematic circuit diagram illustrating a circuit using the semiconductor device according to the embodiment. As shown in FIG. 18, for example, a voltage Vcc, a first semiconductor device 105A, and a second semiconductor device 105B are connected in series. The first electrode 11 of the first semiconductor device 105A and the second electrode 12 of the second semiconductor device 105B are electrically connected. An inductance L is connected in parallel with the second semiconductor device 105B.

[0123] The first semiconductor device 105A performs, for example, IGBT operation. In the first semiconductor device 105A, for example, the control described with reference to FIGS. 17(a) and 17(b) is performed. The second semiconductor device 105B performs, for example, diode operation. In the second semiconductor device 105B, for example, the control described with reference to FIG. 17(c) is performed.

[0124] Note that a semiconductor device without the second control electrode 32 may be used. Even in a semiconductor device without the second control electrode 32, gate control can be performed in the same manner as the voltage V1 shown in FIGS. 17(a) and 17(c).

[0125] The embodiment may include the following configuration (for example, a technical solution). (Configuration 1) A semiconductor device including a first wiring region, a cell region, and a first boundary region between the first wiring region and the cell region, a first electrode, a second electrode at least a part of which is disposed in the first boundary region and the cell region, wherein a direction from the first electrode to the second electrode is along a first direction, and a direction from the first wiring region to the cell region is along a second direction intersecting the first direction, a first wiring disposed in the first wiring region, a semiconductor layer, a first semiconductor region of a first conductivity type disposed in the cell region, the first wiring region, and the first boundary region, a second semiconductor region including a first boundary semiconductor portion disposed in the first boundary region, wherein at least a part of the first boundary semiconductor portion is a second semiconductor region of a second conductivity type provided between the first semiconductor region and the second electrode, a third semiconductor region of a second conductivity type disposed between the first electrode and the first semiconductor region, a fourth semiconductor region of a first conductivity type disposed between the first electrode and the first semiconductor region, wherein an impurity concentration of the first conductivity type in the fourth semiconductor region is higher than an impurity concentration of the first conductivity type in the first semiconductor region, A fifth semiconductor region of a second conductivity type, which is disposed in the cell region and is located between the first semiconductor region and the second electrode, and a sixth semiconductor region of a first conductivity type, which is disposed in the cell region, is located between the first semiconductor region and the second electrode, and is electrically connected to the second electrode, and a semiconductor layer including the same; a first control electrode, which faces the first semiconductor region, the second semiconductor region, and the sixth semiconductor region via a first insulating portion and is electrically connected to the first wiring; a first contact region, which is disposed in the first boundary region, contacts the first boundary semiconductor portion, and electrically connects the first boundary semiconductor portion and the second electrode; a second contact region, which is disposed in the cell region, contacts the fifth semiconductor region, and electrically connects the fifth semiconductor region and the second electrode; A semiconductor device comprising the same; In the semiconductor device, an impurity concentration of the second conductivity type in the first boundary semiconductor portion is lower than an impurity concentration of the second conductivity type in the fifth semiconductor region. (Configuration 2) A first distribution of an impurity concentration of the second conductivity type along the first direction from a surface of the first contact region of the first boundary semiconductor portion in contact with the first semiconductor region has a first peak, A second distribution of an impurity concentration of the second conductivity type along the first direction from a surface of the second contact region of the fifth semiconductor region in contact with the first semiconductor region has a second peak and a third peak that is higher than the second peak and higher than the first peak. The semiconductor device according to Configuration 1. (Configuration 3) In the semiconductor device according to Configuration 2, a height of the first peak is 0.01 times or less of a height of the third peak. (Configuration 4) In the semiconductor device according to Configuration 2 or 3, a height of the first peak is the same as a height of the second peak. (Configuration 5) In the semiconductor device according to Configuration 2 or 3, the first peak is lower than the second peak. (Configuration 6) The semiconductor device according to any one of Configurations 1 to 5, wherein the first contact region forms a Schottky junction with the first boundary semiconductor portion. (Configuration 7) The second semiconductor region includes a wiring semiconductor portion disposed in the first wiring region, The wiring semiconductor portion is located between the first wiring and the first semiconductor region, The semiconductor device according to any one of Configurations 1 to 6, wherein the impurity concentration of the second conductivity type in the wiring semiconductor portion is the same as the impurity concentration of the second conductivity type in the first boundary semiconductor portion. (Configuration 8) The semiconductor device according to any one of Configurations 1 to 7, wherein the semiconductor layer is provided in the first boundary region and has a trench extending in a third direction intersecting the first direction and the second direction. (Configuration 9) The semiconductor device according to Configuration 8, wherein the trench is provided between a portion of the first contact region of the first boundary semiconductor portion that is in contact with the fifth semiconductor region. (Configuration 10) The semiconductor device according to Configuration 8 or 9, wherein the trench extends from the surface of the semiconductor layer on the side of the second electrode toward the first semiconductor region and reaches the first semiconductor region. (Configuration 11) The first contact region is separated from the second contact region in the second direction, The semiconductor device according to any one of Configurations 8 to 10, wherein the position of the trench in the second direction is between the position of the first contact region in the second direction and the position of the second contact region in the second direction. (Configuration 12) A plurality of the sixth semiconductor regions are provided, The plurality of sixth semiconductor regions are arranged in the second direction, The cell region includes a first region and a second region located between the first region and the first boundary region. Of the plurality of the sixth semiconductor regions, the distance between two adjacent sixth semiconductor regions in the second region is shorter than the distance between two adjacent sixth semiconductor regions in the first region among the plurality of the sixth semiconductor regions. The semiconductor device according to any one of Configurations 1 to 11. (Configuration 13) A plurality of the fifth semiconductor regions are provided. The semiconductor device according to Configuration 12, wherein the fifth semiconductor region and the sixth semiconductor region are alternately arranged in the second direction. (Configuration 14) The first wiring extends in a third direction intersecting the first direction and the second direction. The semiconductor device according to any one of Configurations 1 to 13, wherein the first control electrode extends in the second direction and is disposed in the first wiring region, the first boundary region, and the cell region. (Configuration 15) A second wiring disposed in the second wiring region and insulated from the first control electrode; A second control electrode facing the first semiconductor region and the second semiconductor region via a second insulating portion, electrically connected to the second wiring, and insulated from the first wiring. The semiconductor device according to any one of Configurations 1 to 14, further comprising the second control electrode. (Configuration 16) The direction from the cell region to the second wiring region is along the second direction. The cell region is between the first wiring region and the second wiring region. The first wiring and the second wiring extend in a third direction intersecting the first direction and the second direction. The semiconductor device according to Configuration 15, wherein the first control electrode and the second control electrode extend in the second direction and are disposed in the first wiring region, the cell region, and the second wiring region. (Configuration 17) Further comprising a third contact region. The second semiconductor region includes a second boundary semiconductor portion disposed in a second boundary region between the cell region and the second wiring region. The third contact region is disposed in the second boundary region, contacts the second boundary semiconductor portion, and electrically connects the second boundary semiconductor portion and the second electrode. The semiconductor device according to Configuration 15 or 16, wherein the impurity concentration of the second conductivity type in the second boundary semiconductor portion is lower than the impurity concentration of the second conductivity type in the fifth semiconductor region. (Configuration 18) A plurality of the first control electrodes are provided. A plurality of the second control electrodes are provided. The semiconductor device according to any one of Configurations 15 to 17, wherein the number of the plurality of second control electrodes is larger than the number of the plurality of first control electrodes. (Configuration 19) The semiconductor device according to any one of Configurations 15 to 18, wherein the second control electrode is turned off before the first control electrode is turned off. (Configuration 20) The semiconductor device according to any one of Configurations 1 to 19, wherein the first control electrode is turned on when current flows from the second electrode to the first electrode. (Configuration 21) The semiconductor device according to any one of Configurations 1 to 20, further comprising a conductive member facing the first semiconductor region and the second semiconductor region via a third insulating portion and electrically connected to the second electrode.

[0126] In the embodiment, information regarding the shape of the semiconductor region and the like can be obtained by, for example, electron microscope observation. Information regarding the material and the impurity concentration in the semiconductor region can be obtained by, for example, EDX (Energy Dispersive X-ray Spectroscopy) or SIMS (Secondary Ion Mass Spectrometry). Information regarding the carrier concentration in the semiconductor region can be obtained by, for example, SCM (Scanning Capacitance Microscopy).

[0127] According to the embodiment, a semiconductor device capable of improving the breakdown withstand voltage can be provided.

[0128] In the present specification, "electrically connected" includes not only the case of being connected by direct contact but also the case of being connected via other conductive members or the like. In the present specification, "vertical" and "parallel" include not only strict verticality and strict parallelism but also, for example, variations in the manufacturing process, etc., and it suffices that they are substantially vertical and substantially parallel. That one direction follows the other direction means that the one direction and the other direction may be parallel.

[0129] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, regarding the specific configuration of each element included in the semiconductor device, the present invention can be similarly implemented by appropriately selecting from the range known to those skilled in the art, and as long as the same effects can be obtained, it is included in the scope of the present invention.

[0130] Combinations of any two or more elements of each specific example within a technically possible range are also included in the scope of the present invention as long as they encompass the gist of the present invention.

[0131] In addition, based on the semiconductor device described above as an embodiment of the present invention, all semiconductor devices that can be appropriately designed and modified by those skilled in the art also belong to the scope of the present invention as long as they encompass the gist of the present invention.

[0132] In addition, within the scope of the idea of the present invention, those skilled in the art can conceive of various modification examples and correction examples, and it is understood that those modification examples and correction examples also belong to the scope of the present invention.

[0133] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0134] 11: First electrode 12: Second electrode 20: Semiconductor layer 20f: Upper surface 21: First semiconductor region 21a, 21b, 21c, 21d, 21e: Semiconductor portions 22: Second semiconductor region 22a: Wiring semiconductor portion 22b: Boundary semiconductor portion 22c: Cell semiconductor portion 22d: Second wiring semiconductor portion 22e: Second boundary semiconductor portion 23: Third semiconductor region 24: Fourth semiconductor region 25: Fifth semiconductor region 26: Sixth semiconductor region 26a, 26b, 26c, 26d: Regions 31: First control electrode 31a: Wiring electrode portion 31b: Boundary electrode portion 31c: Cell electrode portion 32: Second control electrode 33: Conductive member 41: Contact portion 41a: First contact region 41b: Second contact region 41c: Third contact region 51: First wiring 51P: First electrode pad 52: Second wiring 52P: Second electrode pad 61, 62: Conductive part 70A, 70B: Insulating part 70B: Insulating part 71: First insulating part 72: Second insulating part 73, 74: Insulating part 81: Semiconductor region 100 - 105: Semiconductor device 105A: First semiconductor device 105B: Second semiconductor device CC: Control part Cn: Impurity concentration Cp1: First concentration Cp2: Second concentration Cp3: Third concentration D1, D1a, D1b, D1c: Distance D21: Position Dp: Depth L: Inductance P1: First peak P2: Second peak P3: Third peak R1 - R3: Region RB1: First boundary region RB2: Second boundary region RC: Cell region RF1: First wiring region RF2: Second wiring region T1 - T4: Trench TD, TI, Td: Period V0: Reference potential V1, V2, Vcc: Voltage W: Wiring r1: First region r2: Second region tm: Time tm1 - tm5: Time point

Claims

1. A semiconductor device including a first wiring region, a cell region, and a first boundary region between the first wiring region and the cell region, comprising: a first electrode; a second electrode at least a part of which is disposed in the first boundary region and the cell region, wherein a direction from the first electrode to the second electrode is along a first direction, and a direction from the first wiring region to the cell region is along a second direction intersecting the first direction; a first wiring disposed in the first wiring region; a semiconductor layer, comprising: a first semiconductor region of a first conductivity type disposed in the cell region, the first wiring region, and the first boundary region; a second semiconductor region including a first boundary semiconductor portion disposed in the first boundary region, wherein at least a part of the first boundary semiconductor portion is a second semiconductor region of a second conductivity type provided between the first semiconductor region and the second electrode; a third semiconductor region of a second conductivity type disposed between the first electrode and the first semiconductor region; a fourth semiconductor region of a first conductivity type disposed between the first electrode and the first semiconductor region, wherein an impurity concentration of the first conductivity type in the fourth semiconductor region is higher than an impurity concentration of the first conductivity type in the first semiconductor region; a fifth semiconductor region of a second conductivity type disposed in the cell region and located between the first semiconductor region and the second electrode; a sixth semiconductor region of a first conductivity type disposed in the cell region, located between the first semiconductor region and the second electrode, and electrically connected to the second electrode; a semiconductor layer including the above; a first control electrode facing the first semiconductor region, the second semiconductor region, and the sixth semiconductor region via a first insulating portion and electrically connected to the first wiring; a first contact region disposed in the first boundary region, in contact with the first boundary semiconductor portion, and electrically connecting the first boundary semiconductor portion and the second electrode; a second contact region disposed in the cell region, in contact with the fifth semiconductor region, and electrically connecting the fifth semiconductor region and the second electrode; wherein the semiconductor device further comprises: an impurity concentration of the second conductivity type in the first boundary semiconductor portion is lower than an impurity concentration of the second conductivity type in the fifth semiconductor region.

2. A first distribution of an impurity concentration of a second conductivity type along the first direction from a surface of the first boundary semiconductor portion in contact with the first contact region to the first semiconductor region has a first peak. The semiconductor device according to claim 1, wherein a second distribution of the impurity concentration of the second conductivity type along the first direction from the surface of the fifth semiconductor region in contact with the second contact region to the first semiconductor region has a second peak and a third peak that is higher than the second peak and higher than the first peak.

3. The semiconductor device according to claim 2, wherein the height of the first peak is 0.01 times or less the height of the third peak.

4. The semiconductor device according to claim 2 or 3, wherein the height of the first peak is the same as the height of the second peak.

5. The semiconductor device according to claim 2 or 3, wherein the first peak is lower than the second peak.

6. The semiconductor device according to any one of claims 1 to 3, wherein the first contact region forms a Schottky junction with the first boundary semiconductor portion.

7. The second semiconductor region includes a wiring semiconductor portion disposed in the first wiring region, The wiring semiconductor portion is located between the first wiring and the first semiconductor region, The semiconductor device according to any one of claims 1 to 3, wherein the impurity concentration of the second conductivity type in the wiring semiconductor portion is the same as the impurity concentration of the second conductivity type in the first boundary semiconductor portion.

8. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor layer is provided in the first boundary region and has a trench extending in a third direction intersecting the first direction and the second direction.

9. The semiconductor device according to claim 8, wherein the trench is provided between a portion of the first boundary semiconductor portion in contact with the first contact region and the fifth semiconductor region.

10. The semiconductor device according to claim 8, wherein the trench extends from the surface of the semiconductor layer on the side of the second electrode toward the first semiconductor region and reaches the first semiconductor region.

11. The first contact region is separated from the second contact region in the second direction, The semiconductor device according to claim 8, wherein the position of the trench in the second direction is between the position of the first contact region in the second direction and the position of the second contact region in the second direction.

12. A plurality of the sixth semiconductor regions are provided, The plurality of the sixth semiconductor regions are arranged in the second direction, The cell region includes a first region and a second region located between the first region and the first boundary region. In the semiconductor device according to any one of claims 1 to 3, the distance between two adjacent sixth semiconductor regions among the plurality of sixth semiconductor regions in the second region is shorter than the distance between two adjacent sixth semiconductor regions among the plurality of sixth semiconductor regions in the first region.

13. A plurality of the fifth semiconductor regions are provided. In the semiconductor device according to claim 12, the fifth semiconductor regions and the sixth semiconductor regions are alternately arranged in the second direction.

14. The first wiring extends in a third direction intersecting the first direction and the second direction. In the semiconductor device according to any one of claims 1 to 3, the first control electrode extends in the second direction and is disposed in the first wiring region, the first boundary region, and the cell region.

15. A second wiring disposed in the second wiring region and insulated from the first control electrode; A second control electrode facing the first semiconductor region and the second semiconductor region with a second insulating portion therebetween, electrically connected to the second wiring, and insulated from the first wiring. The semiconductor device according to any one of claims 1 to 3, further comprising:

16. The direction from the cell region to the second wiring region is along the second direction. The cell region is between the first wiring region and the second wiring region. The first wiring and the second wiring extend in a third direction intersecting the first direction and the second direction. In the semiconductor device according to claim 15, the first control electrode and the second control electrode extend in the second direction and are disposed in the first wiring region, the cell region, and the second wiring region.

17. Further comprising a third contact region; The second semiconductor region includes a second boundary semiconductor portion disposed in a second boundary region between the cell region and the second wiring region. The third contact region is disposed in the second boundary region, contacts the second boundary semiconductor portion, and electrically connects the second boundary semiconductor portion and the second electrode. In the semiconductor device according to claim 15, the impurity concentration of the second conductivity type in the second boundary semiconductor portion is lower than the impurity concentration of the second conductivity type in the fifth semiconductor region.

18. A plurality of the first control electrodes are provided. A plurality of the second control electrodes are provided. In the semiconductor device according to claim 15, the number of the plurality of second control electrodes is larger than the number of the plurality of first control electrodes.

19. The semiconductor device according to claim 15, wherein the second control electrode is in an off state before the first control electrode becomes an off state.

20. The semiconductor device according to any one of claims 1 to 3, wherein the first control electrode is in an on state when current flows from the second electrode to the first electrode.

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