Amplifier circuit

Abstract

To provide an amplifier circuit capable of setting the load impedance of a control amplifier to different values.SOLUTION: An amplifier circuit 100 comprises: a first splitter 14 which splits an input signal Si into a first signal S1 and a second signal S2; a control amplifier 10 which amplifies the first signal and outputs the amplified signal as a third signal S3; a second splitter 16 which splits the second signal into a fourth signal S4 and a fifth signal S5, which have different phases at the center frequency of the operating bandwidth; a first auxiliary amplifier 12a which amplifies the fourth signal and outputs the amplified signal as a sixth signal; a second auxiliary amplifier 12b which amplifies the fifth signal and outputs the amplified signal as a seventh signal; and a synthesizer 18 which outputs the synthesized signal as an output signal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an amplifier circuit.

Background Art

[0002] An LMBA (Load Modulated Balanced Amplifier) includes a control amplifier that amplifies one of the input signals that are distributed, and a balance amplifier that amplifies the other of the input signals that are distributed. The balance amplifier has two auxiliary amplifiers that are connected in parallel and balanced. It is known to make the two auxiliary amplifiers asymmetric. In order to make the two auxiliary amplifiers asymmetric, it is known to make the powers of the two auxiliary amplifiers different from each other, and as one of the means, to make the bias voltages supplied to the two auxiliary amplifiers different from each other (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By making the powers of the two auxiliary amplifiers different from each other, the load impedance of the control amplifier can be set to different values depending on the power of the input signal. However, when the bias voltages supplied to the two auxiliary amplifiers are made different from each other in order to make the powers of the two auxiliary amplifiers different from each other, the influence on the system becomes large because different bias voltages need to be prepared.

[0005] The present disclosure has been made in view of the above problems, and an object thereof is to set the load impedance of the control amplifier to different values without affecting the system.

Means for Solving the Problems

[0006] One embodiment of the present disclosure includes a first distributor that distributes an input signal into a first signal and a second signal, a control amplifier that amplifies the first signal and outputs the amplified signal as a third signal, a second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band, a first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal, a second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal, a first terminal into which the sixth signal is input, a second terminal into which the seventh signal is input, a third terminal into which the third signal is input, and a fourth terminal that outputs an output signal, and a synthesizer that delays the phase of the sixth signal by 90° with respect to the phase of the seventh signal, synthesizes the sixth signal, the seventh signal, and the third signal, and outputs the synthesized signal as the output signal. In the synthesizer, when a signal at the center frequency is input to the first terminal, a first distribution ratio of the amplitude of the power of the signal output to the fourth terminal and the third terminal is 0.5 dB or more, a second distribution ratio of the amplitude of the power of the signal distributed when a signal at the center frequency is input to the second distributor is 0.5 dB or more, and a phase difference at the center frequency between the sixth signal input to the first terminal and the seventh signal input to the second terminal is 85° or less or 95° or more. The amplification circuit satisfies at least one of the above conditions.

[0007] One embodiment of the present disclosure includes a first distributor that distributes an input signal into a first signal and a second signal, a control amplifier that operates in class AB or class B, amplifies the first signal, and outputs the amplified signal as a third signal, a second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band, a first auxiliary amplifier that operates in class C, amplifies the fourth signal, and outputs the amplified signal as a sixth signal, a second auxiliary amplifier that operates in class C, amplifies the fifth signal, and outputs the amplified signal as a seventh signal and has a saturation power equal to the saturation power of the first auxiliary amplifier, a bias circuit that supplies the same bias voltage to the first auxiliary amplifier and the second auxiliary amplifier, a first terminal to which the sixth signal is input, a second terminal to which the seventh signal is input, a third terminal to which the third signal is input, and a fourth terminal that outputs an output signal, a synthesizer that delays the phase of the sixth signal by 90° with respect to the phase of the seventh signal, synthesizes the sixth signal, the seventh signal, and the third signal, and outputs the synthesized signal as the output signal, and a matching circuit that matches the impedance at the center frequency seen from the third terminal by the matching circuit to the impedance at the center frequency seen from the control amplifier through the matching circuit. The absolute value of the first impedance at the center frequency seen from the third terminal by the matching circuit when the first auxiliary amplifier and the second auxiliary amplifier operate is 0.9 times or less or 1.1 times or more the absolute value of the second impedance at the center frequency seen from the third terminal by the matching circuit when the first auxiliary amplifier and the second auxiliary amplifier do not operate.

Advantages of the Invention

[0008] According to the present disclosure, the load impedance of the control amplifier can be set to different values without affecting the system.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] [Description of Embodiments of the Present Disclosure] First, the content of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a first distributor that distributes an input signal into a first signal and a second signal, a control amplifier that amplifies the first signal and outputs the amplified signal as a third signal, a second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band, a first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal, a second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal, a first terminal into which the sixth signal is input, a second terminal into which the seventh signal is input, a third terminal into which the third signal is input, and a fourth terminal that outputs an output signal. A synthesizer that delays the phase of the sixth signal by 90° with respect to the phase of the seventh signal, synthesizes the sixth signal, the seventh signal, and the third signal, and outputs the synthesized signal as the output signal. In the synthesizer, when a signal at the center frequency is input to the first terminal, the first distribution ratio of the power amplitudes of the signals output to the fourth terminal and the third terminal is 0.5 dB or more. In the second distributor, when a signal at the center frequency is input, the second distribution ratio of the power amplitudes of the distributed signals is 0.5 dB or more. And the phase difference at the center frequency between the sixth signal input to the first terminal and the seventh signal input to the second terminal is 85° or less or 95° or more. It is an amplifier circuit that satisfies at least one of these conditions. Thereby, the load impedance of the control amplifier can be set to different values. (2) In the above (1), the first distribution ratio may be 0.5 dB or more. Thereby, the load impedance of the control amplifier can be set to different values. (3) In the above (1), the first distribution ratio may be 2 dB or more. Thereby, the load impedance of the control amplifier can be set to different values. (4) In the above (1), the second distribution ratio may be 0.5 dB or more. Thereby, the load impedance of the control amplifier can be set to different values. (5) In the above (1), the second distribution ratio may be 3 dB or more. Thereby, the load impedance of the control amplifier can be set to different values. (6) In the above (1), the phase difference may be 85° or less or 95° or more. The load impedance of the control amplifier can be set to different values. (7) In the above (1), the phase difference may be 0° or more and 75° or less, or 105° or more and 180° or less. Thereby, the load impedance of the control amplifier can be set to different values. (8) In any one of the above (1) to (7), a bias circuit for supplying the same bias voltage to the first auxiliary amplifier and the second auxiliary amplifier is provided, and the saturation power of the first auxiliary amplifier and the saturation power of the second auxiliary amplifier may be equal. Thereby, the load impedance of the control amplifier can be set to different values. (9) In any one of the above (1) to (8), an impedance matching circuit for matching the impedance at the center frequency seen from the third terminal of the matching circuit with the impedance at the center frequency seen from the control amplifier to the matching circuit is provided, the control amplifier operates in class AB or class B, the first auxiliary amplifier and the second auxiliary amplifier operate in class C, and the absolute value of the first impedance at the center frequency seen from the third terminal of the matching circuit when the first auxiliary amplifier and the second auxiliary amplifier operate is 0.9 times or less or 1.1 times or more of the absolute value of the second impedance at the center frequency seen from the third terminal of the matching circuit when the first auxiliary amplifier and the second auxiliary amplifier do not operate. Thereby, the load impedance of the control amplifier can be set to different values. (10) One embodiment of the present disclosure includes a first distributor that distributes an input signal into a first signal and a second signal, a control amplifier that operates in class AB or class B, amplifies the first signal, and outputs the amplified signal as a third signal, a second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band, a first auxiliary amplifier that operates in class C, amplifies the fourth signal, and outputs the amplified signal as a sixth signal, a second auxiliary amplifier that operates in class C, amplifies the fifth signal, and outputs the amplified signal as a seventh signal, and has a saturation power equal to the saturation power of the first auxiliary amplifier, a bias circuit that supplies the same bias voltage to the first auxiliary amplifier and the second auxiliary amplifier, a first terminal to which the sixth signal is input, a second terminal to which the seventh signal is input, a third terminal to which the third signal is input, and a fourth terminal that outputs an output signal. The phase of the sixth signal is delayed by 90° with respect to the phase of the seventh signal, the sixth signal, the seventh signal, and the third signal are combined, and the combined signal is output as the output signal. A matching circuit that matches the impedance at the center frequency seen from the third terminal of the matching circuit to the impedance at the center frequency seen from the control amplifier to the matching circuit. When the first auxiliary amplifier and the second auxiliary amplifier operate, the absolute value of the first impedance at the center frequency seen from the third terminal of the matching circuit is 0.9 times or less or 1.1 times or more of the absolute value of the second impedance at the center frequency seen from the third terminal of the matching circuit when the first auxiliary amplifier and the second auxiliary amplifier do not operate. This is an amplifier circuit that can set the load impedance of the control amplifier to different values. (11) In the above (9) or (10), the absolute value of the first impedance may be 1.5 times or more of the absolute value of the second impedance. This can set the load impedance of the control amplifier to different values. [Details of Embodiments of the Present Disclosure] A specific example of an amplifier circuit according to an embodiment of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0011] [Example 1] FIG. 1 is a circuit diagram of an amplifier circuit according to Example 1. As shown in FIG. 1, in the amplifier circuit 100 of Example 1, a control amplifier 10 and a balance amplifier 11 are connected in parallel between an input terminal Tin and an output terminal Tout. A high-frequency signal is input as an input signal Si to the input terminal Tin. When the amplifier circuit 100 is used in a base station for mobile communication, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. A distributor 14 (first distributor) distributes the input signal Si input to the input terminal Tin into a signal S1 (first signal) and a signal S2 (second signal).

[0012] The signal S1 passes through a matching circuit (MN: Matching Network) 20 and is input to the control amplifier 10. The matching circuit 20 matches the impedance seen from the distributor 14 to the matching circuit 20 and the impedance seen from the matching circuit 20 to the control amplifier 10. A bias circuit (BC: Bias Circuit) 26 that supplies an input bias voltage VG1 to the control amplifier 10 is connected to a node in the line between the distributor 14 and the control amplifier 10. The bias circuit 26 supplies the input bias voltage VG1 to the control amplifier 10 and suppresses the signal S1 from leaking to the power supply that supplies the input bias voltage VG1.

[0013] The control amplifier 10 amplifies the signal S1 and outputs the amplified signal as a signal S3 (third signal). The signal S3 amplified by the control amplifier 10 passes through the matching circuit 24 and is input to the terminal T23 of the synthesizer 18. The matching circuit 24 matches the impedance seen from the control amplifier 10 to the matching circuit 24 and the impedance seen from the matching circuit 24 to the synthesizer 18. A bias circuit 27 that supplies the output bias voltage VD to the control amplifier 10 is connected to a node in the line between the control amplifier 10 and the synthesizer 18. The bias circuit 27 supplies the output bias voltage VD to the control amplifier 10 and suppresses the leakage of the signal S3 to the power supply that supplies the output bias voltage VD.

[0014] The signal S2 distributed by the distributor 14 is input to the balun 11. The balun 11 includes a distributor 16, auxiliary amplifiers 12a and 12b, and a synthesizer 18. The distributor 16 (second distributor) distributes the signal S2 input to the terminal T11 into a signal S4 (fourth signal) and a signal S5 (fifth signal), and outputs them from the terminals T13 and T14, respectively. The phase of the signal S5 lags behind the phase of the signal S4 by, for example, about 90°. The amplitudes of the signals S5 and S4 are, for example, substantially the same. The 90° does not have to be exactly 90°, and may be, for example, greater than 85° and less than 95°, or greater than or equal to 88° and less than or equal to 92°. The same applies to the synthesizer 18.

[0015] The signal S4 passes through the matching circuit 22a and is input to the auxiliary amplifier 12a. The matching circuit 22a matches the impedance seen from the distributor 16 to the matching circuit 22a and the impedance seen from the matching circuit 22a to the auxiliary amplifier 12a. A bias circuit 28a that supplies the input bias voltage VG2a to the auxiliary amplifier 12a is connected to a node in the line between the distributor 16 and the auxiliary amplifier 12a. The bias circuit 28a supplies the input bias voltage VG2a to the auxiliary amplifier 12a and suppresses the leakage of the signal S4 to the power supply that supplies the input bias voltage VG2a. The auxiliary amplifier 12a (the first auxiliary amplifier) amplifies the signal S4 and outputs the amplified signal as a signal S6 (the sixth signal). The signal S6 amplified by the auxiliary amplifier 12a is input to the terminal T21 of the synthesizer 18.

[0016] The signal S5 passes through the matching circuit 22b and is input to the auxiliary amplifier 12b. The matching circuit 22b matches the impedance seen from the distributor 16 to the matching circuit 22b and the impedance seen from the matching circuit 22b to the auxiliary amplifier 12b. A bias circuit 28b that supplies the input bias voltage VG2b to the auxiliary amplifier 12b is connected to a node in the line between the distributor 16 and the auxiliary amplifier 12b. The bias circuit 28b supplies the input bias voltage VG2b to the auxiliary amplifier 12b and suppresses the leakage of the signal S5 to the power supply that supplies the input bias voltage VG2b. The auxiliary amplifier 12b (the second auxiliary amplifier) amplifies the signal S5 and outputs the amplified signal as a signal S7 (the seventh signal). The signal S7 amplified by the auxiliary amplifier 12b is input to the terminal T22 of the synthesizer 18.

[0017] An impedance matching circuit for impedance matching may be connected between the auxiliary amplifiers 12a and 12b and the synthesizer 18. In the first embodiment, the synthesizer 18 adjusts the loads of the auxiliary amplifiers 12a and 12b. Therefore, an impedance matching circuit may not be provided between the auxiliary amplifiers 12a and 12b and the synthesizer 18. A harmonic processing circuit that reflects harmonic signals in the signals S6 and S7 may be connected between the auxiliary amplifiers 12a and 12b and the synthesizer 18. The harmonic signal is, for example, a second harmonic or a third harmonic when the operating frequency of the amplifier circuit is taken as the fundamental wave. A bias circuit that supplies an output bias voltage to the auxiliary amplifiers 12a and 12b may be provided between the auxiliary amplifiers 12a and 12b and the synthesizer 18. In the first embodiment, the output bias voltages of the auxiliary amplifiers 12a and 12b are supplied from the bias circuit 27 through the synthesizer 18 to the auxiliary amplifiers 12a and 12b.

[0018] The synthesizer 18 is, for example, a branch line coupler. The terminals T21 to T24 are the terminals of the branch line coupler. The terminals T21 and T24 are located diagonally, and the terminals T22 and T23 are located diagonally. The signal S6 is input to the terminal T21 (the first terminal). The signal S7 is input to the terminal T22 (the second terminal). The signal S3 is input to the terminal T23 (the third terminal). The output signal So is output from the terminal T24 (the fourth terminal). The synthesizer 18 synthesizes the signals S3, S6, and S7 and outputs the synthesized signal as the output signal So.

[0019] The control amplifier 10, auxiliary amplifiers 12a and 12b are transistors such as FETs (Field Effect Transistors), for example. The source is grounded, a high-frequency signal is input to the gate, and a high-frequency signal is output from the drain. The FET is, for example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or an LDMOS (Laterally Diffused Metal Oxide Semiconductor). The control amplifier 10, auxiliary amplifiers 12a and 12b may each be provided with a multi-stage FET. When the control amplifier 10, auxiliary amplifiers 12a and 12b are FETs, the input bias voltages VG1, VG2a and VG2b are gate bias voltages, and the output bias voltage VD is a drain bias voltage.

[0020] The control amplifier 10 corresponds to the main amplifier of the Doherty amplifier circuit, and the auxiliary amplifiers 12a and 12b correspond to the peak amplifiers of the Doherty amplifier circuit. The control amplifier 10 operates in class AB or class B, and the auxiliary amplifiers 12a and 12b operate in class C. When the input power of the input signal Si is small, the control amplifier 10 mainly amplifies the input signal Si. When the input power increases, in addition to the control amplifier 10, the auxiliary amplifiers 12a and 12b amplify the peak of the input signal Si. Thereby, the control amplifier 10 and the auxiliary amplifiers 12a and 12b amplify the input signal Si.

[0021] [Example of the splitter 16] FIG. 2 and FIG. 3 are circuit diagrams showing Example 1 and Example 2 of the distributor 16 in Embodiment 1. As shown in FIG. 2, in Example 1, the distributor 16 uses a distributed constant type branch line coupler. Transmission lines TL11, TL12, TL13, and TL14 are respectively connected between node N11 and N12, between node N11 and N13, between node N13 and N14, and between node N12 and N14. Transmission lines TL11 to TL14 are λ / 4 transmission lines. The electrical length of the λ / 4 transmission line is, for example, approximately λ / 4. Here, λ is the wavelength of the center frequency fo of the operating band of the amplifier circuit 100. The electrical length of the λ / 4 transmission line does not have to be exactly λ / 4, and may be, for example, 3λ / 16 or more and 5λ / 16 or less, or 7λ / 32 or more and 9λ / 32 or less. The same applies to other λ / 4 transmission lines. Between end T11 and node N11, between end T12 and node N12, between end T13 and node N13, and between end T14 and node N14 are connected by transmission line 32. The signal S2 input to end T11 is distributed to signals S4 and S5 and output from ends T13 and T14, respectively. The phase of the signal S5 at the center frequency fo is approximately 90° later than the phase of the signal S4 at the center frequency fo. End T12 is connected to the reference potential via resistor R1. The resistance value of resistor R1 is, for example, the reference impedance (for example, 50Ω).

[0022] As shown in FIG. 3, in Example 2, the distributor 16 uses a Wilkinson type distributor 16a. The Wilkinson type distributor 16a includes transmission lines TL15, TL16, and resistor R2. Transmission line TL15 is connected between end T11 and end T13, and transmission line TL16 is connected between end T11 and end T14a. Transmission lines TL15 and TL16 are, for example, λ / 4 transmission lines. The resistance value of resistor R2 is, for example, twice the reference impedance. A transmission line TL17 is connected between end T14a and end T14. Transmission line TL17 is a λ / 4 transmission line. The Wilkinson type distributor 16a distributes the signal S2 input to end T11 to signals S4 and S5 with substantially the same amplitude. Transmission line TL17 delays the phase of signal S5 by approximately 90° from the phase of signal S4.

[0023] As the distributor 16, a concentrated multiplier type branch line coupler using an inductor and a capacitor, a distributed coupling type coupler in which two transmission lines are electromagnetically coupled, or a closely wound coil coupler in which two inductors are electromagnetically coupled may be used.

[0024] [Example of synthesizer 18] FIG. 4 is a circuit diagram showing an example of the synthesizer 18 in the first embodiment. As shown in FIG. 4, the synthesizer 18 is a distributed constant type branch line coupler. Transmission lines TL21, TL22, TL23, and TL24 are connected between nodes N21 and N22, between nodes N21 and N23, between nodes N23 and N24, and between nodes N22 and N24, respectively. The transmission lines TL21 to TL24 are λ / 4 transmission lines. Between the end T21 and the node N21, between the end T22 and the node N22, between the end T23 and the node N23, and between the end T24 and the node N24 are connected by transmission lines 32. The signals S6 input to the end T21, the signal S7 input to the end T22, and the signal S3 input to the end T23 are synthesized, and the synthesized signal is output as the output signal So from the end T24.

[0025] As the synthesizer 18, a concentrated multiplier type branch line coupler using an inductor and a capacitor, a distributed coupling type coupler in which two transmission lines are electromagnetically coupled, or a closely wound coil coupler in which two inductors are electromagnetically coupled may be used.

[0026] FIG. 5 is a plan view of the branch line coupler in Example 1. As shown in FIG. 5, in the distributed constant type branch line coupler 34 used for the distributor 16 and the combiner 18, the transmission lines TL11 to TL14, TL21 to TL24, and 32 are formed by the conductor pattern 31 provided on the dielectric substrate 30. A metal layer to which a reference potential is supplied is provided on the lower surface of the dielectric substrate 30. The transmission lines TL21 to TL24 and 32 are microstrip lines. The characteristic impedance of the transmission line 32 is the reference impedance Zo (for example, 50 Ω). The widths of the transmission lines TL11, TL13, TL21, and TL23 are width W1, the widths of the transmission lines TL12, TL14, TL22, and TL24 are width W2, and the width of the transmission line 32 is width W3. When the distributed constant type branch line coupler 34 is a 3 dB coupler (that is, a coupler with a distribution ratio and a combination ratio of 1), the characteristic impedance Zc1 of the transmission lines TL11, TL21, TL13, and TL23 is the reference impedance Zo, and the characteristic impedance Zc2 of the transmission lines TL12, TL22, TL14, and TL24 is 1 / √2 times the reference impedance Zo.

[0027] When the dielectric substrate 30 is a mounting substrate, the dielectric substrate 30 is, for example, a glass epoxy resin substrate or a ceramic substrate. When the distributor 16 and the combiner 18 are monolithically integrated with the control amplifier 10, the auxiliary amplifiers 12a and 12b, the dielectric substrate 30 is, for example, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, or a silicon substrate. The conductor pattern 31 is a metal layer such as a gold layer, a copper layer, or an aluminum layer.

[0028] The matching circuits 20, 22a, 22b, and 24 are passive circuits including inductors and capacitors, and are, for example, inductors connected in series, a π-type circuit having a CLC configuration, a T-type circuit having an LCL configuration, an L-type circuit having an LC configuration, or a circuit combining these circuits.

[0029] [Comparative Example 1] As Comparative Example 1, a Doherty amplifier circuit will be described. FIG. 6 is a circuit diagram of the amplifier circuit according to Comparative Example 1. As shown in FIG. 6, in the amplifier circuit 110 of Comparative Example 1, a main amplifier 10a and a peak amplifier 12 are provided in parallel between an input terminal Tin and an output terminal Tout. A distributor 14 distributes an input signal Si into signals S1 and S2. The main amplifier 10a amplifies the signal S1 that has passed through the matching circuit 20, and outputs the amplified signal as a signal S3 to a synthesizer 18a via a matching circuit 24. The peak amplifier 12 amplifies the signal S2 that has passed through the matching circuit 22, and outputs the amplified signal as a signal S9 to the synthesizer 18a via a matching circuit 24a.

[0030] The synthesizer 18a includes λ / 4 transmission lines TL51 and TL52 as impedance converters. The impedance seen from the matching circuit 24 to the synthesizer 18a and the load impedance of the peak amplifier 12 are modulated using the λ / 4 transmission lines TL51 and TL52.

[0031] In Comparative Example 1, when the frequency changes, it is difficult to broaden the operating bandwidth because the electrical length of the λ / 4 transmission line deviates from λ / 4. In one example, the ratio bandwidth of the synthesizer using the λ / 4 transmission lines TL51 and TL52 is about 8%. In the LMBA as in Example 1, since a branch-line coupler is used to modulate the load impedance of the auxiliary amplifiers 12a and 12b, it is possible to broaden the operating bandwidth. The ratio bandwidth of the branch-line coupler is up to 120% in, for example, a commercially available hybrid coupler. Thus, in the LMBA, the synthesizer 18 can be broadened in bandwidth.

[0032] [Comparative Example 2] FIG. 7 is a circuit diagram showing a part of the amplifier circuits in Comparative Example 2 and Example 1. FIG. 8 is a circuit diagram showing a part of the amplifier circuit in Comparative Example 2. In FIGS. 7 and 8, the circuits after the control amplifier 10 and the balance amplifier are illustrated. In Comparative Example 2, all of the following three conditions are satisfied. Condition 1: The power distribution ratio at which the distributor 16 distributes the signal S2 into signals S4 and S5 is 1:1. Condition 2: The power combining ratio of the signals S6 and S7 combined by the combiner 18 is 1:1. Condition 3: The phase of the signal S7 input to the combiner 18 lags behind the phase of the signal S6 by 90°.

[0033] Using FIG. 7, an explanation will be given when the power of the input signal Si is small and the auxiliary amplifiers 12a and 12b are not operating. As shown in FIG. 7, in the amplifier circuit 112 of Comparative Example 2, the signal S3 input to the combiner 18 from the terminal T23 is divided into signals S3a and S3b at the terminals T21 and T22. The ratio of the power amplitudes of the signals S3a and S3b is 1:1 according to Condition 2. The phase of the signal S3b at the terminal T22 lags behind the phase of the signal S3a at the terminal T21 by 90°. The signals S3a and S3b are reflected at the terminals T21 and T22, respectively. The reflected signals S3a and S3b are combined at the terminal T24. The phase of the signal S3a reflected at the terminal T21 lags behind the phase of the signal S3b reflected at the terminal T22 by 90°. As a result, at the terminal T24, the phases of the signals S3a and S3b are aligned and the signal S3 is combined. The combined signal S3 is output as the output signal So to the output terminal Tout. At this time, the reflection coefficients (i.e., the absolute values of the impedances Z3a and Z3b) seen from the auxiliary amplifiers 12a and 12b to the combiner 18 are greater than 1, and the impedances Z3a and Z3b that are the loads of the auxiliary amplifiers 12a and 12b are substantially high. On the other hand, the impedance Z2 seen from the matching circuit 24 to the terminal T23 is the reference impedance (e.g., 50 Ω) that is the input impedance of the terminal T23.

[0034] Next, with reference to FIG. 8, an explanation will be given when the power of the input signal Si is large and the auxiliary amplifiers 12a and 12b are operating. As shown in FIG. 8, in the amplifier circuit 112 of Comparative Example 2, the phase of the signal S7 lags behind the phase of the signal S6 by 90°. The phase of the signal S3b at the terminal T22 lags behind the phase of the signal S3a at the terminal T21 by 90°. Thus, by appropriately adjusting the phase difference between the signals S1 and S2 in FIG. 1, the phases of the signals S6 and S3a at the terminal T21 are optimized (for example, the phases of the signals S6 and S3a are aligned), and the phases of the signals S7 and S3b at the terminal T22 are optimized (for example, the phases of the signals S7 and S3b are aligned). The signal S6 + S3a synthesized at the terminal T21 and the signal S7 + S3b synthesized at the terminal T22 are synthesized at the terminal T24. The synthesized signal S3 + S6 + S7 is output as the output signal So to the output terminal Tout.

[0035] At this time, the signals incident from the auxiliary amplifiers 12a and 12b to the terminals T21 and T22 are substantially S6 + S3a and S7 + S3b, respectively, and the signals reflected at the terminals T21 and T22 are substantially S3a and S3b, respectively. For this reason, the reflection coefficients (i.e., the absolute values of the impedances Z3a and Z3b) seen from the auxiliary amplifiers 12a and 12b to the terminals T21 and T22 are less than 1, and become smaller as the power amplitudes of the signals S6 and S7 are larger. The impedances Z3a and Z3b that are the loads of the auxiliary amplifiers 12a and 12b become substantially lower as the power amplitudes of the signals S6 and S7 are larger. In this way, the synthesizer 18 modulates the impedances Z3a and Z3b that are the loads seen from the auxiliary amplifiers 12a and 12b to the synthesizer 18 depending on the amplitudes of the signals S6 and S7. On the other hand, the impedance Z2 seen from the matching circuit 24 to the terminal T23 is a reference impedance (for example, 50 Ω) regardless of the magnitudes of the amplitudes of the signals S6 and S7.

[0036] When the power of the output signal So is at the maximum value within the operating range of the amplifier circuit, the output power of the output signal So is defined as the saturation power Psat. At the saturation power Psat, in Comparative Example 1, the output powers of the main amplifier 10a and the peak amplifier 12, and in Comparative Example 2, the output powers of the control amplifier 10, the auxiliary amplifiers 12a and 12b are saturated. Here, the saturation of the output power includes a state that is 1 dB or less or 2 dB or less lower than the complete saturation state. When the power of the output signal So is at the minimum value within the operating range of the amplifier circuit, it is defined as the back-off power Pbo. At the back-off power Pbo, in Comparative Example 1, the main amplifier 10a has started to saturate, and in Comparative Example 2, the output power of the control amplifier 10 is saturated. Let the impedance seen from the main amplifier 10a or the control amplifier 10 to the matching circuit 24 be Z1, and the impedance seen from the matching circuit 24 to the synthesizer 18a or 18 be Z2.

[0037] Figure 9 is a Smith chart showing the impedance Z1 in Comparative Examples 1 and 2 and Example 1. The center of the circle corresponds to the reference impedance Zo, and the circumference corresponds to the absolute value of the impedance Z1 / Zo being 1. The impedance Z1e is the load impedance at which the efficiency of the main amplifier 10a and the control amplifier 10 is optimal. The impedance Z1p is the impedance Z1 of the load at which the output power of the main amplifier 10a and the control amplifier 10 is optimal. Note that the impedances Z1e and Z1p in Figure 9 are schematic examples.

[0038] In Comparative Example 1, the impedance Z2 seen from the matching circuit 24 to the synthesizer 18a is different when the output power Pout of the output signal So is at the saturation power Psat and when it is at the back-off power Pbo. Therefore, by appropriately designing the matching circuit 24, it can be set such that the impedance Z1 becomes Z1p when the output power Pout is at the saturation power Psat and the impedance Z1 becomes Z1e when the output power Pout is at the back-off power Pbo. Note that the matching circuit 24 is designed such that the efficiency and the output power are compatible when the output power Pout at which the peak amplifier 12 saturates is the power Pbo.

[0039] FIG. 10 is a diagram showing the drain efficiency with respect to the output power in Comparative Examples 1 and 2 and Example 1. The drain efficiency is maximized when the output power Pout is the back-off power Pbo and the saturation power Psat. In Comparative Example 1, due to the impedance Z1p such that the output power of the main amplifier 10a is optimized when the output power Pout is the saturation power Psat, the output power Pout becomes a large Psat1.

[0040] On the other hand, in Comparative Example 2, the impedance Z2 seen from the synthesizer 18 to the matching circuit 24 is the same when the output power Pout is the saturation power Psat and when it is the back-off power Pbo. For this reason, the impedance Z1 is the same regardless of whether the output power Pout is the saturation power Psat or the back-off power Pbo. Emphasizing the efficiency at the saturation power Psat, the matching circuit 24 is designed such that the impedance Z1 becomes Z1e in FIG. 9.

[0041] In FIG. 10, in Comparative Example 2, since the impedance Z1 of the control amplifier 10 is Z1e at which the efficiency is optimized when the output power Pout is the back-off power Pbo, the drain efficiency is about the same as that in Comparative Example 1. When the output power Pout is the saturation power Psat, the impedance Z1 of the control amplifier 10 is in the state of Z1e at which the efficiency is optimized, and the output power Pout becomes Psat2 which is smaller than Psat1 in Comparative Example 1. Thus, in Comparative Example 2, the saturation power Psat becomes smaller than that in Comparative Example 1. For this reason, in Comparative Example 2, the back-off amount becomes smaller and the dynamic range becomes smaller.

[0042] In Comparative Example 2, if the matching circuit 24 is designed such that the impedance Z1 of the control amplifier 10 is in the state of Z1p at which the power is optimized when the output power Pout is the saturation power Psat, the saturation power Psat can be made about the same as that in Comparative Example 1, but the drain efficiency at the saturation power Psat becomes lower than that in Comparative Example 1. As described above, in Comparative Example 2, the characteristics deteriorate compared to Comparative Example 1.

[0043] [Description of Example 1] In Example 1, at least one of Conditions 1 to 3 is not satisfied. When the power of the input signal Si is small and the auxiliary amplifiers 12a and 12b are not operating, as described with reference to FIG. 7, the impedance seen from terminal T23 of the matching circuit 24 is the reference impedance (for example, 50 Ω) which is the input impedance of terminal T23.

[0044] FIG. 11 is a circuit diagram showing a part of the amplifier circuit in Example 1. With reference to FIG. 11, the case where the power of the input signal Si is large and the auxiliary amplifiers 12a and 12b are operating will be described. In Example 1, at least one of the following Conditions A to C is satisfied. Condition A: The power distribution ratio at which the distributor 16 distributes the signal S2 into the signals S4 and S5 is not 1:1. Condition B: The power combination ratio at which the combiner 18 combines the signals S6 and S7 is not 1:1. Condition C: The phase difference between the signal S7 and the signal S6 input to the combiner 18 is not 90°.

[0045] When Condition A is satisfied and Conditions B and C are not satisfied, the amplitudes of the powers of the signals S6 and S7 are not 1:1. Therefore, the power of the signal output from terminal T23 of the combiner 18 does not become zero, and a signal ΔS is output from terminal T23. The signal ΔS output from terminal T23 is reflected by the control amplifier 10 and returns to terminal T23. For this reason, the signal output from terminal T24 becomes S3 + S6 + S7.

[0046] When Condition B is satisfied and Conditions A and C are not satisfied, the amplitudes of the powers of the signals S6 and S7 are 1:1, but the power of the signal output from terminal T23 of the combiner 18 does not become zero, and a signal ΔS is output from terminal T23. The signal output from terminal T24 becomes S3 + S6 + S7.

[0047] When Condition C is satisfied and Conditions A and B are not satisfied, the amplitudes of the powers of the signals S6 and S7 are 1:1, but the power of the signal output from terminal T23 of the combiner 18 does not become zero, and a signal ΔS is output from terminal T23. The signal output from terminal T24 becomes S3 + S6 + S7.

[0048] The signal incident on terminal T23 from the matching circuit 24 is S3, and the signal output from (i.e., reflected by) terminal T23 is ΔS. Therefore, the impedance Z2 of the matching circuit 24 as seen from terminal T23 is higher than the reference impedance.

[0049] As described above, the impedance Z2 of the matching circuit 24 as seen from the synthesizer 18 is different when the output power Pout of the output signal So is at the saturation power Psat and when it is at the back-off power Pbo. Therefore, as shown in FIG. 9, by appropriately designing the matching circuit 24, the impedance Z1 can be set to Z1p when the output power Pout is at the saturation power Psat, and the impedance Z1 can be set to Z1e when the output power Pout is at the back-off power Pbo.

[0050] As shown in FIG. 10, in the first embodiment, the drain efficiency of the control amplifier 10 is maximized when the output power Pout is at the back-off power Pbo and the saturation power Psat. Since the impedance Z1p is such that the output power of the control amplifier 10 is optimized when the output power Pout is at the saturation power Psat, the output power Pout becomes a large Psat1. Thus, in the first embodiment, the saturation power Psat is larger than that in Comparative Example 2 and can be made about the same as in Comparative Example 1. Therefore, compared with Comparative Example 2, the back-off amount becomes larger, and the dynamic range can be increased. Since a branch coupler is used for the synthesizer 18, the bandwidth of the synthesizer 18 can be increased compared with Comparative Example 1.

[0051] [Simulation] In the first embodiment, simulations were performed to determine to what extent the impedance Z2 can be modulated under conditions A, B, and C. The control amplifier 10, auxiliary amplifiers 12a and 12b were made of GaN HEMT. The frequency of the signal was 3.5 GHz.

[0052] [Simulation 1] First, it was verified that the output power of the control amplifier 10 does not change when the impedance Z2 changes. With the impedance Z2 at the back-off power Pbo as the reference impedance Zo (50 Ω), when the output power Pout reaches the saturation power Psat, the impedance Z2 was changed and the output power Pout@CA of the control amplifier 10 at saturation was simulated.

[0053] Figure 12 is a diagram showing the output power Pout@CA with respect to Z2 / Zo in Simulation 1. The horizontal axis is the impedance Z2 normalized by the reference impedance Zo. The vertical axis is the output power Pout@CA of the control amplifier 10. The dots indicate the simulated points, and the straight line is the line connecting the dots. The same applies to the following figures. As shown in Figure 12, even when Z2 / Zo is changed between 1 and 5, the output power Pout@CA is 42 dBm or more. Thus, even when the impedance Z2 is changed, the change in the output power Pout@CA is small, and the simulation of the impedance Z2 under Conditions A, B, and C is possible.

[0054] [Simulation 2] The impedance Z2 was simulated when Condition A was satisfied and Conditions B and C were not satisfied. As Condition A, it was assumed that the power amplitude ratio of signals S4 and S5 is the same as the power amplitude ratio of signals S6 and S7, and the impedance Z2 was simulated by changing the power amplitude ratio of signals S6 and S7. The output power of the auxiliary amplifier 12a was set to the saturation power, which is approximately 43 dBm.

[0055] Figure 13 is a diagram showing Z2 / Zo with respect to PS6 - PS7 in Simulation 2. PS6 and PS7 are the power amplitudes of signals S6 and S7, respectively. The horizontal axis shows PS6 - PS7 in dB. The vertical axis is Z2 / Zo.

[0056] As shown in Fig. 13, when PS6 - PS7 is 0 dB, Z2 / Zo is 1, and the impedance Z2 is the reference impedance Zo. As PS6 - PS7 increases, Z2 / Zo increases. That is, the impedance Z2 becomes larger than the reference impedance Zo. Thus, when the output power Pout is the saturation power Psat, the impedance Z2 can be made larger than the back-off power Pbo. In a symmetric Doherty amplifier circuit, the ratio of the impedance Z2 between the saturation power Psat and the back-off power Pbo is 2 times. Therefore, in order to modulate the impedance Z2 similar to that of a Doherty amplifier circuit, PS6 - PS7 should be about 4 dB or more. If the ratio of the impedance Z2 between the saturation power Psat and the back-off power Pbo is 1.5 times, and the impedance Z1 can be set to Z1e and Z1p in Fig. 9, then PS6 - PS7 should be about 2 dB or more. Assuming that the ratio of the amplitudes of the powers of signals S4 and S5 is the same as PS6 - PS7, it is 2 dB or more and 4 dB or more.

[0057] [Simulation 3] The impedance Z2 was simulated when condition B was satisfied and conditions A and C were not satisfied. The ratio of the signal S6 input to terminal T21 distributed to terminals T23 and T24 was displayed in dB and used as the distribution ratio. The distribution ratio was positive when the signal output to terminal T23 was large, and negative when the signal output to terminal T24 was large.

[0058] Fig. 14 is a diagram showing Z2 / Zo with respect to the distribution ratio in Simulation 3. The distribution ratio is shown in dB. As shown in Fig. 14, when the distribution ratio is 0 dB, Z2 / Zo is 1, and the impedance Z2 is the reference impedance Zo. As the distribution ratio becomes larger positively and negatively, Z2 / Zo increases. To make Z2 / Zo 1.5 or more, the distribution ratio should be 3 dB or more or -3 dB or less. To make Z2 / Zo 2 or more, the distribution ratio should be 5 dB or more or -5 dB or less.

[0059] [Simulation 4] The impedance Z2 was simulated when condition C was satisfied and conditions A and B were not satisfied. When condition C was not satisfied, the phase of the signal S7 input to the terminal T22 was 90° later than the phase of the signal S6 input to the terminal T21. Therefore, the deviation of 90° from the phase difference between the signals S6 and S7 was defined as the Δ phase difference.

[0060] FIG. 15 is a diagram showing Z2 / Zo with respect to the Δ phase difference in Simulation 4. As shown in FIG. 15, when the Δ phase difference is 0° and 360°, Z2 / Zo is 1, and the impedance Z2 is the reference impedance. As the Δ phase difference increases from 0° and decreases from 360°, Z2 / Zo increases. In order to make Z2 / Zo 1.5 or more, the Δ phase difference is 15° or more or 345° or less (i.e., -15° or less), and in order to make Z2 / Zo 2 or more, the Δ phase difference is 30° or more or 330° or less (i.e., -30° or less). When the upper limit of Z2 / Zo is 8 or 10, the Δ phase difference is 90° or less or 80° or less.

[0061] [Simulation 5] As in Simulations 2 to 4, Z2 / Zo can be changed most by changing the Δ phase difference. Therefore, when condition C is satisfied and conditions A and B are not satisfied, each impedance was simulated. The Δ phase difference was set to 45°, and the power of the input signal Si was changed so that the output power Pout changed from 25 dBm to 48 dBm.

[0062] FIG. 16 is a Smith chart of the impedances Z1, Z2, Z3a, and Z3b in Simulation 5. As shown in FIG. 16, when the output power Pout is small, the impedances Z3a and Z3b are located near the outer periphery of the Smith chart, and the reflection coefficients seen from the auxiliary amplifiers 12a and 12b to the terminals T21 and T22 are 1 or more. As the output power Pout increases, the absolute values of the impedances Z3a and Z3b decrease and are located inside the circle of the Smith chart. Since the phase difference between the signals S6 and S7 is not 90°, the trajectories of the impedances Z3a and Z3b on the Smith chart are not the same.

[0063] When the output power Pout is small, the impedance Z2 is the reference impedance and is 50 Ω. When the output power Pout increases, the impedance Z2 changes and the absolute value of the impedance Z2 increases. Since the impedance Z2 changes according to the output power Pout, the impedance Z1 also changes according to the output power Pout.

[0064] In Simulation 5, since the matching circuit 24 is not properly designed, the locus of the impedance Z2 is not on the real axis of the Smith chart. However, if the matching circuit 24 is properly designed, the locus of the impedance Z2 will be closer to the real axis. Also, by properly designing the matching circuit 24, when the output power Pout is the back-off power Pbo, the impedance Z2 can be at the position of Z1p in FIG. 9, and when the output power Pout is the saturation power Psat, the impedance Z2 can be at the position of Z1e in FIG. 9.

[0065] In Simulations 2 to 5 above, the cases where any one of the conditions A, B, and C is satisfied have been described. It is sufficient to satisfy either condition A or B and not necessarily condition C. It is sufficient to satisfy either condition B or C and not necessarily condition A. It is sufficient to satisfy either condition A or C and not necessarily condition B. It is also possible to satisfy conditions A, B, and C.

[0066] When the power distribution ratio is different from 1:1, the dB-represented distribution ratio is different from 0 dB. Considering manufacturing errors and measurement errors, the distribution ratio is 0.5 dB or more. If the distribution ratio is defined as the amplitude ratio of the power of the larger signal to the smaller signal among the distributed signals, in dB representation, the distribution ratio is 0 dB or more. When the phase difference is different from 90°, considering manufacturing errors and measurement errors, the phase difference is 85° or less or 95° or more.

[0067] Therefore, in Example 1, at least one of the following three conditions A to C is satisfied. Condition A: When a signal at the center frequency fo of the operating band is input to terminal T21 in synthesizer 18, the first power amplitude distribution ratio of the signals output to terminals T23 and T24 is 0.5 dB or more. Condition B: When a signal at the center frequency fo is input to divider 16, the second power amplitude distribution ratio of the divided signals is 0.5 dB or more. Condition C: The phase difference at the center frequency fo between signal S6 input to terminal T21 of synthesizer 18 and signal S7 input to terminal T22 is 85° or less or 95° or more.

[0068] Thus, impedance Z2 changes depending on output power Pout. Therefore, impedance Z1 can be set to different values for different output powers Pout. For example, matching circuit 24 is designed such that impedance Z1 becomes Z1p at saturation power Psat and impedance Z1 becomes Z1e at back-off power Pbo. Thereby, as shown in FIG. 10, the characteristics of amplifier circuit 100 can be improved compared to Comparative Example 2. Also, by using a branch-line coupler in synthesizer 18, the bandwidth of synthesizer 18 can be broadened, and the bandwidth of amplifier circuit 100 can be broadened compared to Comparative Example 1.

[0069] Furthermore, as in Patent Document 1, when the bias voltages supplied to the two auxiliary amplifiers are made different from each other, the influence on the system (for example, a base station) becomes large because different bias voltages need to be prepared. In Example 1, the bias voltages supplied to the two auxiliary amplifiers may be the same. Thereby, the influence on the system can be reduced.

[0070] As shown in FIG. 13 of Simulation 2, in order to increase impedance Z2 at saturation power Psat, the first distribution ratio can be 2 dB or more, 3 dB or more, and 4 dB or more. If the first distribution ratio is too large, the design of the matching circuit becomes difficult. From this viewpoint, the first distribution ratio can be 10 dB or less.

[0071] As shown in FIG. 14 of Simulation 3, in order to increase the impedance Z2 at the saturation power Psat, the second distribution ratio can be 3 dB or more, can be 4 dB or more, and can be 5 dB or more. If the second distribution ratio is too large, it will be difficult to design the matching circuit. From this perspective, the second distribution ratio can be 10 dB or less.

[0072] As shown in FIG. 15 of Simulation 4, in order to increase the impedance Z2 at the saturation power Psat, the phase difference between the signals S6 and S7 can be 75° or less or 105° or more, can be 60° or less or 120° or more, and can be 45° or less or 135° or more. If the phase difference is too large, the power of the signal S6 + S7 output to the terminal T24 will become small. From this perspective, the phase difference can be 0° or more and 75° or less or 105° or more and 180° or less.

[0073] The bias circuits 28a and 28b in FIG. 1 supply the same input bias voltages VG2a and VG2b to the auxiliary amplifiers 12a and 12b. The bias circuit 27 supplies the same output bias voltage VD to the auxiliary amplifiers 12a and 12b. Thereby, it is not necessary to supply different bias voltages to the auxiliary amplifiers 12a and 12b. Therefore, the influence on the system can be reduced. The same bias voltage (or substantially the same bias voltage) allows for a difference in the bias voltage due to voltage drop in the wiring or the like. For example, the difference in the bias voltages between the auxiliary amplifiers 12a and 12b is 0.1 times or less of the total bias voltage, and 0.05 times or less.

[0074] The physical size of auxiliary amplifier 12a is the same as that of auxiliary amplifier 12b. For example, when auxiliary amplifiers 12a and 12b are FETs, the gate width of auxiliary amplifier 12a is the same as the gate width of auxiliary amplifier 12b. At this time, the saturation power of auxiliary amplifier 12a and the saturation power of auxiliary amplifier 12b at the same bias voltage are equal. Thereby, since the configurations of matching circuits 22a and 22b can be made the same, the design of amplifier circuit 100 becomes easy. That the saturation powers are equal (or approximately equal) allows for a difference in saturation power due to manufacturing errors or the like. For example, the difference in saturation power between auxiliary amplifiers 12a and 12b is 1 dB or less, and 0.5 dB or less.

[0075] When auxiliary amplifiers 12a and 12b are operating (at saturation power Psat), the absolute value of the first impedance Z2a seen from terminal T23 of matching circuit 24 is different from the absolute value of the second impedance Z2b seen from terminal T24 of matching circuit 24 when auxiliary amplifiers 12a and 12b are not operating (for example, at back-off power Pbo). Considering manufacturing errors and measurement errors, the absolute value of the first impedance Z2a is 0.9 times or less or 1.1 times or more the second impedance Z2b, and 0.8 times or less or 1.2 times or more. Thereby, by appropriately setting matching circuit 24, impedance Z1 can be set to different values for different output powers Pout.

[0076] In a Doherty amplifier circuit, the absolute value of the first impedance Z2a at saturation power Psat is about twice the absolute value of the second impedance Z2b at back-off power Pbo. Therefore, if the absolute value of the first impedance Z2a is 1.5 times or more the absolute value of the second impedance Z2b, impedance Z1 can be set to different values. The absolute value of the first impedance Z2a can be made 2 times or more, and 3 times or more the absolute value of the second impedance Z2b. If the difference between the first impedance Z2a and the second impedance Z2b is too large, the design of matching circuit 24 becomes difficult. From this perspective, the absolute value of the first impedance Z2a can be made 10 times or less the absolute value of the second impedance Z2b.

[0077] [Method for Satisfying Conditions A and B] A method for satisfying Condition A and Condition B will be described. As shown in FIGS. 2 and 4, the case where a distributed constant type branch line coupler is used for the distributor 16 and the synthesizer 18 will be described. In FIGS. 2 and 4, when the distribution ratio at which the signals input from the terminals T11 and T21 are distributed to the terminals T13 and T23 and the terminals T14 and T24 is 0 dB, the characteristic impedance Zc1 of the transmission lines TL11, TL13, TL21, and TL23 is set as the reference impedance Zo, and the characteristic impedance Zc2 of the transmission lines TL12, TL14, TL22, and TL24 is set as the reference impedance / √2. For example, when the reference impedance Zo is 50 Ω, the characteristic impedance Zc1 is 50 Ω and the characteristic impedance Zc2 is 35.35 Ω.

[0078] FIGS. 17 and 18 are plan views showing the branch line coupler in Example 1. The signal S6 input to the terminals T11 and T21 is distributed to the terminals T13 and T23 and the terminals T14 and T24 as signals S6a and S6b, respectively. The signal S7 input to the terminals T12 and T22 is distributed to the terminals T13 and T23 and the terminals T14 and T24 as signals S7a and S7b, respectively.

[0079] The case where the amplitude of the power of signal S6a is made larger than the amplitude of the power of signal S6b and the amplitude of the power of signal S7b is made larger than the amplitude of the power of signal S7a will be described. As shown in FIG. 17, the characteristic impedance Zc1 of transmission lines TL11, TL13, TL21, and TL23 is made larger than the reference impedance Zo. Therefore, the width W1 of transmission lines TL11, TL13, TL21, and TL23 becomes smaller than the width W3 of transmission line 32. The characteristic impedance Zc2 of transmission lines TL12, TL14, TL22, and TL24 is made lower than Zc1 / √2 and lower than the reference impedance Zo. Therefore, the width W2 of transmission lines TL12, TL14, TL22, and TL24 becomes larger than the width W3 of transmission line 32. For example, when the amplitude of the power of signal S6a is made 3 dB larger than the amplitude of the power of signal S6b and the amplitude of the power of signal S7b is made 3 dB larger than the amplitude of the power of signal S7a, the characteristic impedance Zc1 is set to 70.6 Ω and the characteristic impedance Zc2 is set to 40.80 Ω.

[0080] The case where the amplitude of the power of signal S6b is made larger than the amplitude of the power of signal S6a and the amplitude of the power of signal S7a is made larger than the amplitude of the power of signal S7b will be described. As shown in FIG. 18, the characteristic impedance Zc1 of transmission lines TL11, TL13, TL21, and TL23 is made smaller than the reference impedance Zo. Therefore, the width W1 of transmission lines TL11, TL13, TL21, and TL23 becomes larger than the width W3 of transmission line 32. The characteristic impedance Zc2 of transmission lines TL12, TL14, TL22, and TL24 is made higher than Zc1 / √2. Therefore, the width W2 of transmission lines TL12, TL14, TL22, and TL24 becomes larger than the width W1 of transmission line 32. For example, when the amplitude of the power of signal S6b is made 3 dB larger than the amplitude of the power of signal S6a and the amplitude of the power of signal S7a is made 3 dB larger than the amplitude of the power of signal S7b, the characteristic impedance Zc1 is set to 35.4 Ω and the characteristic impedance Zc2 is set to 28.89 Ω.

[0081] From the above, from the perspective of increasing the first distribution ratio or the second distribution ratio, the characteristic impedance Zc1 can be set to 1.01 times or more, 1.2 times or more, 1.4 times or more, or 1.7 times or more of the transmission line TL32 of the reference impedance Zo. Alternatively, the characteristic impedance Zc1 can be set to 0.99 times or less, 0.85 times or less, 0.7 times or less, or 0.6 times or less of the reference impedance Zo. From the perspective of not increasing the first distribution ratio or the second distribution ratio too much, the characteristic impedance Zc1 can be set to 3 times or less and 0.5 times or more of the reference impedance Zo.

[0082] When the characteristic impedance Zc1 is greater than the reference impedance Zo, the characteristic impedance Zc2 can be set to 0.99 times or less, 0.95 times or less, or 0.9 times or less of Zc1 / √2. When the characteristic impedance Zc1 is less than the reference impedance Zo, the characteristic impedance Zc2 can be set to 1.01 times or more, 1.05 times or more, or 1.1 times or more of Zc1 / √2. From the perspective of not increasing the first distribution ratio or the second distribution ratio too much, Zc2 can be set to 0.3 times or more and 3 times or less of Zc1 / √2o.

[0083] The width W1 can be set to 1.01 times or more, 1.4 times or more, or 1.7 times or more of the width W3. Alternatively, the width W1 can be set to 0.99 times or less, 0.7 times or less, or 0.5 times or less of the width W3. The width W2 can be set to 1.01 times or more or 1.1 times or more of the width W3, and 10 times or less. The width W2 can be set to 1.01 times or more or 1.1 times or more of the width W1, and 10 times or less.

[0084] As described above, by appropriately setting the characteristic impedances Zc1 and Zc2, the distribution ratio can be set to a desired value. Even when the distributor 16 and the synthesizer 18 use circuits other than the distributed constant branch line coupler, the distribution ratio can be set to a desired value by using a known method.

[0085] [Method for satisfying condition C] A method for satisfying condition C will be described. When using a Wilkinson-type distributor 16a as shown in FIG. 3 as the distributor 16, the phase difference between signals S4 and S5 can be set to a desired value by changing the electrical length of the transmission line TL17 from λ / 4. Also, by making the designs of the matching circuits 22a and 22b different, the phase difference between signals S4 and S5 passing through the matching circuits 22a and 22b can be set to a desired value.

[0086] FIG. 19 shows another example of the amplifier circuit according to Embodiment 1. As shown in FIG. 19, in the amplifier circuit 102, a phase adjustment circuit 29a is provided between the distributor 16 and the auxiliary amplifier 12a, and a phase adjustment circuit 29b is provided between the distributor 16 and the auxiliary amplifier 12b. The phase adjustment circuits 29a and 29b are, for example, transmission lines, and the phase difference between signals S4 and S5 can be set to a desired value by changing the electrical length. It is sufficient that at least one of the phase adjustment circuits 29a and 29b is provided.

[0087] It should be considered that all the disclosed embodiments are illustrative in all respects and not restrictive. The scope of the present disclosure is indicated not by the above description but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Description of Reference Numerals

[0088] 10 Control amplifier 10a Main amplifier 11 Balanced amplifier 12 Peak amplifier 12a (First auxiliary amplifier), 12b (Second auxiliary amplifier) Auxiliary amplifier 14 (First distributor), 16 (Second distributor) Distributor 16a Wilkinson-type distributor 18, 18a Combiner 20, 22, 22a, 22b, 24, 24a Matching circuit 26, 27, 28a, 28b Bias circuit 29a, 29b Phase adjustment circuit 30 Dielectric substrate 31 Conductor pattern 32 Transmission line 34 Distributed constant type branch line coupler 100, 102, 110, 112 Amplifier circuit S1 (first signal), S2 (second signal), S3 (third signal), S4 (fourth signal), S5 (fifth signal), S6 (sixth signal), S7 (seventh signal) Signal Si Input signal So Output signal

Claims

1. A first distributor that distributes an input signal into a first signal and a second signal, a control amplifier that amplifies the first signal and outputs the amplified signal as a third signal, a second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band, a first auxiliary amplifier that amplifies the fourth signal and outputs the amplified signal as a sixth signal, a second auxiliary amplifier that amplifies the fifth signal and outputs the amplified signal as a seventh signal, a synthesizer comprising a first terminal into which the sixth signal is input, a second terminal into which the seventh signal is input, a third terminal into which the third signal is input, and a fourth terminal that outputs an output signal, the synthesizer delaying the phase of the sixth signal by 90° with respect to the phase of the seventh signal, synthesizing the sixth signal, the seventh signal, and the third signal, and outputting the synthesized signal as the output signal, and in the synthesizer, when a signal at the center frequency is input to the first terminal, a first distribution ratio of the power amplitudes of the signals output to the fourth terminal and the third terminal is 0.5 dB or more, in the second distributor, when a signal at the center frequency is input, a second distribution ratio of the power amplitudes of the distributed signals is 0.5 dB or more, and a phase difference at the center frequency between the sixth signal input to the first terminal and the seventh signal input to the second terminal is 85° or less or 95° or more, an amplifier circuit satisfying at least one of the above.

2. The amplifier circuit according to claim 1, wherein the first distribution ratio is 0.5 dB or more.

3. The amplifier circuit according to claim 1, wherein the first distribution ratio is 2 dB or more.

4. The amplifier circuit according to claim 1, wherein the second distribution ratio is 0.5 dB or more.

5. The amplifier circuit according to claim 1, wherein the second distribution ratio is 3 dB or more.

6. The amplifier circuit according to claim 1, wherein the phase difference is 85° or less or 95° or more.

7. The amplifier circuit according to claim 1, wherein the phase difference is 0° or more and 75° or less, or 105° or more and 180° or less.

8. comprising a bias circuit that supplies the same bias voltage to the first auxiliary amplifier and the second auxiliary amplifier, The amplifier circuit according to any one of claims 1 to 7, wherein the saturation power of the first auxiliary amplifier is equal to the saturation power of the second auxiliary amplifier.

9. A matching circuit that matches the impedance at the center frequency as seen from the third terminal of the integrated circuit to the impedance at the center frequency as seen from the control amplifier to the integrated circuit, The control amplifier operates in class AB or class B, and the first auxiliary amplifier and the second auxiliary amplifier operate in class C, When the first auxiliary amplifier and the second auxiliary amplifier operate, the absolute value of the first impedance at the center frequency as seen from the third terminal of the matching circuit is 0.9 times or less or 1.1 times or more of the absolute value of the second impedance at the center frequency as seen from the third terminal of the matching circuit when the first auxiliary amplifier and the second auxiliary amplifier do not operate. The amplifier circuit according to any one of claims 1 to 7.

10. A first distributor that distributes an input signal into a first signal and a second signal, A control amplifier that operates in class AB or class B, amplifies the first signal, and outputs the amplified signal as a third signal, A second distributor that distributes the second signal into a fourth signal and a fifth signal having different phases at the center frequency of the operating band, A first auxiliary amplifier that operates in class C, amplifies the fourth signal, and outputs the amplified signal as a sixth signal, A second auxiliary amplifier that operates in class C, amplifies the fifth signal, outputs the amplified signal as a seventh signal, and has a saturation power equal to the saturation power of the first auxiliary amplifier, A bias circuit that supplies the same bias voltage to the first auxiliary amplifier and the second auxiliary amplifier, A first terminal into which the sixth signal is input, a second terminal into which the seventh signal is input, a third terminal into which the third signal is input, and a fourth terminal that outputs an output signal. A synthesizer that delays the phase of the sixth signal by 90° with respect to the phase of the seventh signal, synthesizes the sixth signal, the seventh signal, and the third signal, and outputs the synthesized signal as the output signal, A matching circuit that matches the impedance at the center frequency as seen from the third terminal of the matching circuit to the impedance at the center frequency as seen from the control amplifier to the matching circuit, Comprising The absolute value of the first impedance at the center frequency seen from the third terminal of the matching circuit when the first auxiliary amplifier and the second auxiliary amplifier are operating is 0.9 times or less or 1.1 times or more the absolute value of the second impedance at the center frequency seen from the third terminal of the matching circuit when the first auxiliary amplifier and the second auxiliary amplifier are not operating. An amplifier circuit.

11. The amplifier circuit according to claim 10, wherein the absolute value of the first impedance is 1.5 times or more the absolute value of the second impedance.

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