Capacitive element and manufacturing method thereof

Abstract

To increase the capacity of a capacitive element.SOLUTION: A capacitive element includes a substrate 2 having a first surface 21 and a second surface 22 facing opposite each other in a thickness direction and in which a plurality of communication holes 20 are formed connecting the first surface 21 and the second surface 22, and a plurality of electrodes 31, 32 respectively formed in a cylindrical shape covering the inner circumferential surfaces of the plurality of communication holes 2. The plurality of electrodes 31, 32 constitute a capacitance.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a capacitive element and a method for manufacturing the same.

Background Art

[0002] A capacitive element has been proposed in Patent Document 1 and the like, in which an electrode material is filled in a large number of holes drilled in the thickness direction of a substrate, and the thus formed electrodes are appropriately connected to wiring patterns routed to one surface and the other surface of the substrate, etc., so as to form a capacitance between the paired electrodes. Such a capacitive element can be manufactured by a manufacturing method for semiconductors, MEMS elements, etc. Therefore, such a capacitive element is easier to manufacture than a conventional capacitive element in which a dielectric is sandwiched between electrodes and laminated in multiple layers or wound multiple times.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] The capacitance formed by a capacitive element is roughly proportional to the area of the electrodes, and the area of the electrodes is determined by the hole diameter and the depth of the holes in the case of a capacitive element having the above-described structure. Therefore, in a capacitive element having the above-described structure, since the hole diameter is also determined by the strength required for the substrate, etc., when trying to obtain a large capacitance, it is necessary to thicken the substrate and form deep holes. That is, in a capacitive element having the above-described structure, when trying to obtain a large capacitance, it is necessary to increase the aspect ratio, which is the ratio of the depth of the holes to the hole diameter.

[0005] However, when the aspect ratio is increased, that is, the holes are made deeper, it becomes particularly difficult to form electrodes during drilling, and in some cases, voids may occur. Further, even if an electrode can be formed, due to the difference in CTE (coefficient of thermal expansion) between the substrate material such as SiO2 and the electrode material such as Ni and Cu, thermal stress is generated, which may cause cracks in the substrate or the cracks may progress to cause element failure. In particular, in the case of a capacitive element used in relation to a switching power element, heat resistance of 200 ° C may be required.

[0006] An object of the present disclosure is to provide a capacitive element capable of increasing the capacitance and a method for manufacturing the same.

[0007] In order to solve the above-described problems, the capacitive element and the manufacturing method thereof according to the present disclosure include a substrate having a first surface and a second surface facing opposite sides in the thickness direction, and a plurality of communication holes formed to communicate the first surface and the second surface, and a plurality of electrodes formed in a cylindrical shape covering the inner peripheral surface of each of the plurality of communication holes, and the plurality of electrodes constitute capacitance.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2A

Figure 2B

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Figure 3B

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Figure 3D

Figure 3E

Figure 3F

Figure 4

Figure 5

Figure 6

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Figure 8A

Figure 8B

Figure 8C

Figure 9

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Figure 11

[0009] [Detailed Description] Next, this embodiment will be described with reference to the drawings. In the description of the drawings below, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and different from the actual ones. Therefore, specific structures, dimensions, etc. should be appropriately determined in consideration of the following description.

[0010] Further, the embodiments described below exemplify devices and methods for embodying the technical idea, and do not specify the materials, shapes, structures, arrangements, etc. of each component. Various modifications can be made to the present embodiment within the scope of the claims.

[0011] (Embodiment 1) FIG. 1 is a schematic cross-sectional view of a capacitive element 1 according to a first embodiment, FIG. 2A is a plan view of the capacitive element 1 shown in FIG. 1, and FIG. 2B is a schematic cross-sectional view of the capacitive element 1 shown in FIG. 1. FIG. 1 shows a cross-section taken along the cutting line I-I of FIGS. 2A and 2B, and FIG. 2B shows a cross-section taken along the cutting line IIB-IIB of FIG. 1.

[0012] The capacitive element 1 of the present disclosure includes a substrate 2, electrodes 31 and 32, wiring patterns 41 and 42, insulating films 51 and 52, and a resin 6. The substrate 2 is made of, for example, SiO2. The substrate 2 has a first surface 21 and a second surface 22 facing opposite sides in the thickness direction, and a plurality of communication holes 20 are formed along the thickness direction so as to communicate the first surface 21 and the second surface 22, that is, perpendicular to the first surface 21 and the second surface 22. A large number of communication holes 20 are formed in a predetermined arrangement such as a matrix in the plane direction of the substrate 2. In the example of FIG. 2A, they are shown as holes having a polygonal shape (a rectangle in FIG. 2A) when viewed in the thickness direction in which the electrode area can be widened. The polygonal communication holes 20 are formed such that the sides of the polygons forming a pair adjacent to each other are parallel to each other when viewed in the thickness direction. Cylindrical electrodes 31 and 32 are formed on the inner peripheral surfaces of the respective communication holes 20 by a conductive thin film so as to cover the inner peripheral surfaces.

[0013] The electrodes 31 and 32 are made of, for example, a single layer or a composite layer of Ni, Cu, or TiN. Insulating films 51 and 52 are formed on each surface 21 and 22 of the substrate 2, and wiring patterns 41 and 42 are formed after the insulating films 51 and 52 are appropriately removed. For example, the insulating films 51 and 52 are made of PI (polyimide), SiN, or SiO2, and the wiring patterns 41 and 42 are made of Ni, Cu, or Al. In the example of FIG. 1, the wiring patterns 41 and 42 are either positive or negative wirings that also serve as electrode pads, and the electrodes 31 and 32 become either positive or negative electrodes by being selectively connected to the wiring patterns 41 and 42. The positive and negative electrodes 31 and 32 adjacent to each other form a pair, and these electrodes 31 and 32 cooperate with each other and with the dielectric (substrate 2 of SiO2) interposed between them to form the capacitive element 1.

[0014] In the rectangular substrate 2 shown in FIG. 2A, for example, the width (longitudinal direction) is 10 mm, the depth (lateral direction) is 5 mm, and the width (lateral direction) of the rectangular through-hole 20 is 10 μm. In FIGS. 1, 2A, and 2B, the number of through-holes 20 is thinned out for easier understanding. Also, in the present disclosure, round holes are also possible as shown in FIG. 11 described later. For example, in the case of a 10-μm round hole, with Ni plating, a depth of 20 μm or more is possible. Therefore, the depth of the through-hole 20, that is, the thickness of the substrate 2, may be 20 μm or more and 100 μm or more, although it also depends on the width (lateral direction) and length (longitudinal direction) of the through-hole 20, that is, the opening area. The product of the width (lateral direction) or length (longitudinal direction) of the through-hole 20 and the depth becomes the electrode area as described above (in the case of this embodiment, since the sides in the length (longitudinal) direction of the electrodes 31 and 32 are adjacent to each other, it is the product of that length and the depth). Therefore, the width and length of the through-hole 20, that is, the opening area, are preferably formed as large as possible within the range allowable in terms of strength. The electrodes 31 and 32 can be formed as a thin film of about 1 μm when formed by Ni plating in the above-mentioned 10-μm round hole. And in the capacitive element 1 of the present disclosure, a resin 6, which is an insulator, is embedded in the cylindrical electrodes 31 and 32.

[0015] Figs. 3A to 3F are schematic cross-sectional views showing the manufacturing process of the capacitive element 1 shown in Figs. 1 and 2A and 2B. As shown in Fig. 3A, a through-hole 20 is formed by etching in the Si substrate 2a which is a base material. As shown in Fig. 3B, the entire Si substrate 2a is thermally oxidized to become a SiO2 substrate 2. As shown in Fig. 3C, thin-film cylindrical electrodes 31 and 32 are formed on the inner peripheral surface of the through-hole 20 by Ni plating or the like. As shown in Fig. 3D, the resin 6 is filled in the electrodes 31 and 32. As shown in Fig. 3E, the first surface 21 and the second surface 22 of the substrate 2 are polished, and the electrodes 31 and 32 on the first surface 21 and the second surface 22 are removed. As shown in Fig. 3F, insulating films 51 and 52 are formed on the first surface 21 and the second surface 22 of the substrate 2. After the insulating films 51 and 52 are appropriately patterned by etching, wiring patterns 41 and 42 are formed on the insulating films 51 and 52 from the portions where the insulating films 51 and 52 are removed. Then, the wiring pattern 41 on the first surface 21 of the substrate 2 is electrically connected to the electrode 31, and the wiring pattern 42 on the second surface 22 is electrically connected to the electrode 32, so that the capacitive element 1 is formed between the paired electrodes 31 and 32. In the cross-section of Fig. 1, the capacitive element 1 of two parallel elements is formed by two electrodes 31 and one electrode 32.

[0016] Therefore, according to the capacitive element 1 of the present disclosure as described above, for a conventional capacitive element in which a dielectric is sandwiched between electrodes and laminated in multiple layers or wound multiple times, an element with a desired capacitance can be easily created by a manufacturing method such as a semiconductor or a MEMS element. Further, in the capacitive element 1 of the present disclosure, since the electrodes 31 and 32 are in the form of thin-film cylinders, unevenness can be formed with less variation even in deep holes (holes with a large aspect ratio, which is the ratio of depth to hole diameter), and the aspect ratio can be increased, that is, the substrate 2 can be made thicker to increase the capacitance. Furthermore, if the entire inside of the communication hole 20 is filled with an electrode (solidified), there is a possibility that voids may occur in the electrode or the substrate may crack due to the difference in CTE (linear thermal expansion coefficient) between the electrode and the substrate. In contrast, in the present disclosure, since the electrodes 31 and 32 are in the form of thin-film cylinders, such problems do not occur. In addition, even if an unfilled film portion occurs during the formation of the thin films of the electrodes 31 and 32, that is, even if the necessary electrode area cannot be formed, it is possible to distinguish whether such a defective product or a non-defective product with correct film formation from the capacitance after completion.

[0017] In addition to the above-mentioned Ni, Cu, and TiN, the electrodes 31 and 32 may be any one of Co, W, poly-Si, Ag, Au, or a combination of these electrode materials. These electrode materials are suitable because they cause less contamination to SiO2, which is the material of the substrate 2, and have high conductivity. In particular, poly-Si and TiN are suitable.

[0018] Further, since the entire inside of the communication hole 20 is not filled with the electrodes 31 and 32 themselves in the capacitive element 1 of the present disclosure (the electrodes 31 and 32 are cylindrical), the current, that is, the capacitance to be formed, is slightly reduced and the resistance component is increased compared to the case of filling (solidifying). Therefore, by using the capacitive element 1 of the present disclosure as the capacitive element of the snubber circuit, the resistance can be eliminated, which is suitable.

[0019] Furthermore, in the capacitive element 1 of the present disclosure, the substrate 2 is realized by a fully oxidized silicon substrate. Here, a partially oxidized silicon substrate that oxidizes only the through holes in the silicon substrate is relatively easy to fabricate. However, if silicon remains, it will act as a conductor. Therefore, for example, by increasing the density of the through holes 20 within the range of the allowable strength for the substrate 2 to make it easier to fully oxidize and using such a fully oxidized silicon substrate, the capacitance that can be accumulated can be increased, which is preferable.

[0020] FIG. 4 is a schematic cross-sectional view of a capacitive element 1a, which is a modified example of the capacitive element 1 of the first embodiment, and FIG. 5 is a plan view of the capacitive element 1a shown in FIG. 4. FIG. 4 shows a cross-section taken along the cutting line IV-IV in FIG. 5. These FIGS. 4 and 5 correspond to FIGS. 1 and 2A described above, and the corresponding parts are denoted by the same reference numerals. In this capacitive element 1a, wiring patterns 41 and 42 are formed only on the first surface 21 of the substrate 2, and no wiring patterns 41 and 42 are formed on the second surface 22. Therefore, the fabrication of this capacitive element 1a is the same as that of the capacitive element 1 in the steps from FIGS. 3A to 3F, except that the insulating film 52 formed on the second surface 22 of the substrate 2 is not patterned, and only the insulating film 51 on the first surface 21 is patterned.

[0021] The patterning of the insulating film 51 is such that the electrode 31 is electrically connected from the wiring pattern 41 to the electrode pad 71, and the electrode 32 is electrically connected from the wiring pattern 42 to the electrode pad 72, and they can be performed in the same process. By configuring in this way, the extraction electrode pads 71 and 72 and the wiring patterns 41 and 42 can be formed by concentrating them only on the first surface 21 of the substrate 2.

[0022] (Embodiment 2) FIG. 6 is a schematic cross-sectional view of the capacitive element 11 according to the second embodiment, and FIG. 7 is a plan view of the capacitive element 11 shown in FIG. 6. FIG. 6 shows a cross-section taken along the cutting line VI-VI of FIG. 7. These FIGS. 6 and 7 correspond to FIGS. 1 and 2A described above, and the corresponding parts are denoted by the same reference numerals. In the capacitive element 1 described above, the electrodes 31 and 32 are filled with the resin 6, whereas in this capacitive element 11, the inside of the electrodes 31 and 32 is a hollow space 16, which is different.

[0023] FIGS. 8A to 8C are schematic cross-sectional views showing the manufacturing process of the capacitive element 11 shown in FIGS. 6 and 7. In the process of manufacturing this capacitive element 11, the processes up to FIGS. 3A to 3C are the same as those of the capacitive element 1. After the thin-film cylindrical electrodes 31 and 32 are formed on the inner peripheral surface of the communication hole 20 of the substrate 2, as shown in FIG. 8A, the first surface 21 and the second surface 22 of the substrate 2 are polished, and the electrodes 31 and 32 on the first surface 21 and the second surface 22 are removed. Cleaning inside the electrodes 31 and 32 may be performed. Subsequently, as shown in FIG. 8B, dry film resists 151 and 152 are attached to the first surface 21 and the second surface 22 of the substrate 2. In the capacitive element 1 described above, since the electrodes 31 and 32 are filled with the resin 6, thereafter, the insulating films 51 and 52 can be formed and patterned. On the other hand, the inside of the electrodes 31 and 32 of this capacitive element 11 needs to be a hollow space 16. Therefore, self-supporting dry film resists 151 and 152 are used to block the openings of the electrodes 31 and 32 and form the hollow space 16. Thereafter, as shown in FIG. 8C, the dry film resists 151 and 152 are selectively patterned as appropriate, and openings 153 and 154 are formed in portions to be connected to the electrodes 31 and 32. Subsequently, while leaving the patterned dry film resists 151 and 152, as shown in FIG. 6, the wiring patterns 141 and 142 are formed, so that the wiring patterns 141 and 142 are electrically connected to the electrodes 31 and 32 through the openings 153 and 154.

[0024] Therefore, wiring patterns 141 and 142 can be electrically connected to the inner peripheral surfaces of the hollow electrodes 31 and 32 formed in a thin film tubular shape on the inner peripheral surfaces of the through holes 20 drilled in the thickness direction of the substrate 2 on at least one surface of the substrate 2 as appropriate, and a desired capacitive element can be created.

[0025] FIG. 9 is a schematic cross-sectional view of a capacitive element 11a which is a modification of the capacitive element 11 of the second embodiment, and FIG. 10 is a plan view of the capacitive element 11a shown in FIG. 9. These FIGS. 9 and 10 correspond to FIGS. 6 and 7 described above, and the corresponding parts are denoted by the same reference numerals. The relationship between the above-described capacitive element 11 and this capacitive element 11a which is a modification thereof is the same as the relationship between the capacitive element 1 of the first embodiment and the capacitive element 1a which is a modification thereof. That is, also in this capacitive element 11a, the wiring patterns 141 and 142 are formed only on the first surface 21 of the substrate 2, and the wiring patterns 141 and 142 are not formed on the second surface 22. Therefore, in the creation of this capacitive element 11a, the steps up to FIGS. 8A to 8B are the same as those of the capacitive element 11, but in FIG. 8C, the dry film resist 152 formed on the second surface 22 of the substrate 2 is not patterned, and only the dry film resist 151 on the first surface 21 is patterned.

[0026] The patterning of the dry film resist 151 is such that the electrode 31 is electrically connected from the wiring pattern 141 to the electrode pad 71, and the electrode 32 is electrically connected from the wiring pattern 142 to the electrode pad 72, and they can be performed in the same process. By configuring in this way, the extraction electrode pads 71 and 72 and the wiring patterns 41 and 42 can be formed by aggregating them only on the first surface 21 of the substrate 2.

[0027] (Embodiment 3) FIG. 11 is a schematic cross-sectional view of the capacitive element 1b according to the third embodiment. The configuration of FIG. 11 corresponds to the configuration of FIG. 1 described above, and the corresponding parts are appended with the same reference numerals with the suffix b. When viewed in the thickness direction of the substrate 2b, in the capacitive element 1 described above, the communication hole 20 was polygonal (rectangular in the example of FIG. 2A), but in the capacitive element 1b of the present embodiment, the communication hole 20b is circular. The rectangular communication hole 20 has a long parallel portion between the electrodes 31 and 32, and the capacitance can be increased slightly. On the other hand, the round communication hole 20b has a slightly smaller capacitance, but since there are no corners, stress does not concentrate on a part of the communication hole 20b.

[0028] The technical idea that can be grasped from the present disclosure is described in the following supplementary notes. Note that, for the purpose of assisting understanding rather than limiting, the corresponding components in the embodiments are appended with the reference numerals of the corresponding components in the supplementary notes. The reference numerals are shown as examples for assisting understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0029] <Supplementary Note 1> The capacitive elements 1, 1a, 1b, 11, 11a described in Supplementary Note 1 have a first surface 21 and a second surface 22 facing opposite sides in the thickness direction, and a plurality of communication holes 20, 20b formed to communicate the first surface 21 and the second surface 22 are formed on the substrate 2, 2b, and a plurality of electrodes 31, 31b, 32, 32b formed in a cylindrical shape covering the inner peripheral surfaces of the plurality of communication holes 20, 20b, and the plurality of electrodes 31, 31b, 32, 32b constitute capacitance. Since the electrodes 31, 31b, 32, 32b are in the form of thin film cylinders, unevenness can be formed with less unevenness even in holes with a large aspect ratio, which is the ratio of depth to hole diameter, and the aspect ratio can be increased, that is, the substrate 2, 2b can be made thicker to increase the capacitance.

[0030] <Supplementary Note 2> The capacitive elements 1, 1a, 1b, 11, 11a described in Supplementary Note 2 are the capacitive elements 1, 1a, 1b, 11, 11a described in Supplementary Note 1, and each of the plurality of communication holes 20, 20b is formed along the thickness direction.

[0031] <Appendix 3> In the capacitive element 1b described in Appendix 3, in the capacitive element 1b described in Appendix 1, each of the plurality of communication holes 20b is formed in a circular shape when viewed in the thickness direction. Thereby, stress concentration on a part of the communication hole 20b can be avoided.

[0032] <Appendix 4> In the capacitive elements 1, 1a, 11, 11a described in Appendix 4, in the capacitive elements 1, 1a, 11, 11a described in Appendix 1, each of the plurality of communication holes 20 is formed in a polygonal shape when viewed in the thickness direction. Thereby, the parallel portion between the electrodes 31 and 32 becomes long, and the element capacitance can be increased.

[0033] <Appendix 5> In the capacitive elements 1, 1a, 11, 11a described in Appendix 5, in the capacitive elements 1, 1a, 11, 11a described in Appendix 4, a pair of adjacent communication holes among the plurality of communication holes 20 are arranged such that the sides of the polygon are parallel to each other when viewed in the thickness direction. Thereby, the element capacitance can be increased.

[0034] <Appendix 6> In the capacitive elements 1, 1a, 1b, 11, 11a described in Appendix 6, in the capacitive elements 1, 1a, 1b, 11, 11a described in any one of Appendices 1 to 5, each of the plurality of electrodes 31, 31b, 32, 32b is constituted by a conductive film formed on the inner peripheral surface.

[0035] <Appendix 7> In the capacitive elements 1, 1a, 1b, 11, 11a described in Appendix 7, in the capacitive elements 1, 1a, 1b, 11, 11a described in Appendix 6, each of the plurality of electrodes 31, 31b, 32, 32b is formed in a hollow shape. Thereby, generation of voids that easily occurs when the entire inside of the communication hole 20 is filled with the electrode itself is suppressed, and cracking of the substrate due to a difference in CTE (linear thermal expansion coefficient) between the electrode and the substrate is also suppressed.

[0036] <Appendix 8> The capacitive elements 1, 1a, and 1b described in Supplementary Note 8 are the capacitive elements 1, 1a, and 1b described in Supplementary Note 7, and each include an insulator (6, 6b) filled inside each of a plurality of electrodes 31, 31b, 32, and 32b formed in a cylindrical shape.

[0037] <Supplementary Note 9> The capacitive elements 1, 1a, and 1b described in Supplementary Note 9 are the capacitive elements 1, 1a, and 1b described in Supplementary Note 8, and the insulators (6, 6b) are resins 6 and 6b.

[0038] <Supplementary Note 10> The capacitive elements 1, 1a, 1b, 11, and 11a described in Supplementary Note 10 include substrates 2 and 2b in which a plurality of holes (20, 20b) are formed in the thickness direction, and electrodes 31, 31b, 32, and 32b formed in a cylindrical shape covering the inner peripheral surfaces of the holes (20, 20b), and form capacitance between the paired electrodes 31, 31b and 32, 32b.

[0039] According to the above configuration, electrodes 31, 31b, 32, and 32b are formed in a large number of holes (20, 20b) formed in the thickness direction of the substrates 2 and 2b, and one end (the first surface 21 of the substrate 2, 2b) side and the other end (the second surface 22 of the substrate 2) side of the holes (20, 20b), or on the substrate surface on one end (the first surface 21 of the substrate 2) side where the region is divided (corresponding to FIGS. 5 and 10), by appropriately connecting the electrodes 31, 31b, 32, and 32b to the wiring patterns 41, 42, 141, and 142 routed thereon, capacitance is formed between the paired electrodes 31, 31b and 32, 32b. In creating such capacitive elements 1, 1a, 1b, 11, and 11a, in the present disclosure, after perforating in the thickness direction of the substrates 2 and 2b, the electrodes 31, 31b, 32, and 32b are formed as a thin film, that is, in a cylindrical shape, on the inner peripheral surfaces of the holes (20, 20b).

[0040] Therefore, for a conventional capacitive element in which a dielectric is sandwiched between electrodes and laminated in multiple layers or wound multiple times, and a manufacturing method thereof, an element with a desired capacitance can be easily created by a manufacturing method for semiconductors, MEMS elements, etc. Further, the electrodes 31, 31b, 32, 32b are in the form of thin-film cylinders, and unevenness can be formed with less variation even in deep holes (holes with a large aspect ratio, which is the ratio of depth to hole diameter), and the aspect ratio can be increased, that is, the substrates 2, 2b can be made thicker to increase the capacitance. Furthermore, if the entire inside of the holes (20, 20b) is filled (solidified) with electrodes, there is a possibility that voids may occur in the electrodes or the substrates may crack due to differences in CTE (linear thermal expansion coefficient) between the electrodes and the substrates. On the other hand, by forming the electrodes 31, 31b, 32, 32b in the form of thin-film cylinders and making them hollow, such problems do not occur.

[0041] <Appendix 11> The capacitive elements 1, 1a, 1b described in Appendix 11 include resins 6, 6b filled in the electrodes 31, 31b, 32, 32b in the capacitive elements 1, 1a, 1b described in Appendix 1.

[0042] According to the above configuration, each of the electrodes 31, 31b, 32, 32b needs to be connected to the wiring patterns 41, 42 routed on the surface of the substrate on one end side (the first surface 21 of the substrates 2, 2b) and the other end side (the second surface 22 of the substrate 2) of the holes (20, 20b), or on the surface of the substrate on one end side (the first surface 21 of the substrate 2) where the region is divided. However, as described above, when the electrodes 31, 31b, 32, 32b are in the form of thin-film cylinders and not solid, there is a possibility that they may also be connected to the opposite electrodes when forming the wiring (41, 42). Specifically, for example, when positive and negative wirings (41, 42) are formed on each of the surfaces 21, 22 of the substrate, both sides of the electrodes 31, 31b, 32, 32b may be connected to the positive and negative wirings (41, 42) together, and the material of the wiring (41, 42) formed in a later process may undesirably come into contact with the electrodes 31, 31b, 32, 32b formed in a previous process.

[0043] Therefore, by filling the resin 6 and 6b into the cylindrical electrodes 31, 31b, 32, and 32b of the thin film, the insulating films 51 and 52 formed on the respective surfaces 21 and 22 of the substrates 2 and 2b can be arbitrarily etched to form the wiring patterns 41 and 42, and such problems can be eliminated. In addition, the decrease in the strength of the capacitive element due to making the electrodes 31, 31b, 32, and 32b into a thin film cylindrical shape, that is, not solid, can be compensated by the filled resin 6 and 6b. Furthermore, by filling the resin 6 and 6b, which has a relatively low Young's modulus and a low coefficient of linear expansion compared to the metal that becomes the electrode material when the entire inside of the holes (20, 20b) is filled with the electrode (made solid), the problems such as cracking of the substrates 2 and 2b are also reduced.

[0044] <Appendix 12> The capacitive elements 11 and 11a described in Appendix 12 are the capacitive elements 11 and 11a described in Appendix 1, and include dry film resists 151 and 152 that selectively block the ends of the cylindrical electrodes 31 and 32, and wiring patterns 141 and 142 that are electrically connected to the exposed ends of the electrodes 31 and 32 by patterning the dry film resists 151 and 152.

[0045] According to the above configuration, since the thin films of the cylindrical electrodes 31 and 32 are formed in the holes (20) drilled in the substrate 2, the electrodes 31 and 32 are hollow. Therefore, when trying to form the wiring patterns 141 and 142 and using a normal photoresist for patterning, since the normal photoresist is a liquid, it enters the electrodes 31 and 32. Therefore, instead of the liquid normal photoresist, dry film resists 151 and 152 are used, these dry film resists 151 and 152 are attached, and the portions of the electrodes 31 and 32 to be connected are etched. The wiring patterns 141 and 142 are selectively connected to the exposed ends of the thin films of the electrodes 31 and 32 by the etching.

[0046] Therefore, wiring patterns 141 and 142 are electrically connected as appropriate to the inner peripheral surfaces of the holes (20) drilled in the thickness direction of the substrate 2 to the hollow electrodes 31 and 32 formed in a thin film tubular shape on at least one surface (21) of the substrate 2, and a desired capacitive element can be created.

[0047] <Appendix 13> The capacitive elements 1, 1a, 1b, 11, and 11a described in Appendix 13 are the capacitive elements 1, 1a, 1b, 11, and 11a described in any one of Appendices 10 to 12, and the electrodes 31, 31b, 32, and 32b are made of any one of Ni, Co, W, Cu, poly-Si, TiN, Ag, Au, or a combination thereof.

[0048] According to the above configuration, the above electrode materials are suitable because they cause little contamination to SiO2, which is the material of the substrates 2 and 2b, and have a high conductivity. In particular, poly-Si and TiN are suitable.

[0049] <Appendix 14> The capacitive elements 1, 1a, 1b, 11, and 11a described in Appendix 14 are the capacitive elements 1, 1a, 1b, 11, and 11a described in any one of Appendices 10 to 13, and are used as the capacitive elements of the snubber circuit.

[0050] According to the above configuration, when the entire inside of the holes (20 and 20b) is filled (solidified) with the electrodes 31, 31b, 32, and 32b, compared with the case of not filling (hollowing) as described above, the current, that is, the capacitance to be formed, is slightly reduced, and the resistance component also increases. Therefore, by using the capacitive elements 1, 1a, 1b, 11, and 11a of the present disclosure as the capacitive elements of the snubber circuit, the resistance can be made unnecessary, which is suitable.

[0051] <Appendix 15> The capacitive elements 1, 1a, 1b, 11, and 11a described in Appendix 15 are the capacitive elements 1, 1a, 1b, 11, and 11a described in any one of Appendices 10 to 14, and the substrates 2 and 2b are fully oxidized silicon substrates.

[0052] According to the above configuration, a partially oxidized silicon substrate that oxidizes only inside the holes of the silicon substrate is relatively easy to fabricate. However, if silicon portions remain, they will act as conductors. Therefore, for example, by increasing the density of the holes (20, 20b) within the range of allowable strength, it becomes easier to achieve full oxidation, and by using such a fully oxidized silicon substrate, the capacitance that can be accumulated can be increased.

[0053] <Appendix 16> The manufacturing method of the capacitive elements 1, 1a, 11, 11a described in Appendix 16 includes a step of drilling in the thickness direction of the substrates 2, 2b, a step of forming cylindrical thin films that will become the electrodes 31, 31b, 32, 32b on the inner peripheral surfaces of the holes (20, 20b) drilled by the drilling, and a step of performing wiring on the surfaces of the substrates 2, 2b with respect to the pairs of electrodes 31, 31b and 32, 32b, and forming a capacitance between these electrodes 31, 31b and 32, 32b.

[0054] <Appendix 17> The manufacturing method of the capacitive elements 1, 1a, 1b described in Appendix 17 has a step of filling the resins 6, 6b into the electrodes 31, 31b, 32, 32b in the manufacturing method of the capacitive elements described in Appendix 16 before performing the wiring.

[0055] <Appendix 18> The manufacturing method of the capacitive elements 11, 11a described in Appendix 18, in the manufacturing method of the capacitive elements described in Appendix 16, after performing the wiring and forming the capacitance, further includes a step of attaching dry film resists 151, 152 to at least one surface (21, 22) of the substrate 2, a step of patterning the dry film resists 151, 152 so that the ends of the cylindrical electrodes 31, 32 are selectively exposed, and a step of forming wiring patterns 141, 142 that are electrically connected to the ends of the electrodes 31, 32 exposed by the patterning.

Explanation of Reference Numerals

[0056] 1, 1a, 1b, 11, 11a Capacitive elements 2, 2b Substrates Holes 20 and 20b First surface 21 Second surface 22 Electrodes 31, 31b, 32, and 32b Wiring patterns 41 and 42 Insulating films 51 and 52 Resins 6 and 6b Electrode pads 71 and 72 Wiring patterns 141 and 142 Dry film resists 151 and 152 Openings 153 and 154

Claims

1. A substrate having a first surface and a second surface facing opposite sides in the thickness direction, and a plurality of communication holes formed to communicate the first surface and the second surface; A plurality of electrodes formed in a cylindrical shape covering the inner peripheral surfaces of the plurality of communication holes; The plurality of electrodes constitute a capacitive element that forms a capacitance.

2. The capacitive element according to claim 1, wherein each of the plurality of communication holes is formed along the thickness direction.

3. The capacitive element according to claim 2, wherein each of the plurality of communication holes is formed in a circular shape when viewed in the thickness direction.

4. The capacitive element according to claim 2, wherein each of the plurality of communication holes is formed in a polygonal shape when viewed in the thickness direction.

5. The capacitive element according to claim 4, wherein a pair of adjacent communication holes among the plurality of communication holes are arranged such that sides of the polygon are parallel to each other when viewed in the thickness direction.

6. The capacitive element according to any one of claims 1 to 5, wherein each of the plurality of electrodes is constituted by a conductive film formed on the inner peripheral surface.

7. The capacitive element according to claim 6, wherein each of the plurality of electrodes is formed hollow.

8. The capacitive element according to claim 6, further comprising an insulator filled inside each of the plurality of electrodes formed in a cylindrical shape.

9. The capacitive element according to claim 8, wherein the insulator is a resin.

10. A dry film resist that selectively closes the ends of the plurality of electrodes; A wiring pattern electrically connected to the exposed ends of the electrodes by patterning the dry film resist.

11. The capacitive element according to claim 1, wherein the electrode is made of any one or a combination of Ni, Co, W, Cu, poly-Si, TiN, Ag, and Au.

12. The capacitive element according to claim 1, which is used as a capacitive element of a snubber circuit.

13. The capacitive element according to claim 1, wherein the substrate is a fully oxidized silicon substrate.

14. A substrate having a plurality of holes drilled in the thickness direction; An electrode formed in a cylindrical shape covering the inner peripheral surface of the hole; A capacitive element that forms a capacitance between a pair of electrodes.

15. A step of drilling holes in the thickness direction of the substrate; A step of forming a cylindrical thin film serving as an electrode on the inner peripheral surface of the holes drilled by the drilling. A method for manufacturing a capacitive element, including a step of wiring between paired electrodes on the surface of the substrate to form a capacitance therebetween.

16. The method for manufacturing a capacitive element according to claim 15, further comprising a step of filling the electrodes with resin before performing the wiring.

17. The step of performing the wiring and forming the capacitance includes: after forming the electrodes, a step of attaching a dry film resist to at least one surface of the substrate; a step of patterning the dry film resist so that the ends of the cylindrical electrodes are selectively exposed; and a step of forming a wiring pattern electrically connected to the ends of the electrodes exposed by the patterning. The method for manufacturing a capacitive element according to claim 15.

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