Memory device and operating method thereof

Abstract

To provide a memory device and an operating method thereof capable of shortening rising time of a read voltage corresponding to a relatively high program state, thereby improving speed of a read operation.SOLUTION: The present technology relates to a memory device and an operating method thereof. A memory device 1100 includes: a memory block 110 including a plurality of memory cells; a peripheral circuit 200 for executing a plurality of read voltage applying operations and a plurality of word line setting operations for the memory block 110; and a control logic 300 controls the peripheral circuit 200 to set at least one word line setting operation among the plurality of word line setting operations to a word line potential higher than that of the remaining word line setting operations, and has a word line potential to which the word line of the memory block 110 is set.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly, to a memory device and an operation method thereof.

Background Art

[0002] Recently, the paradigm for the computer environment has been shifted to ubiquitous computing that enables the use of computer systems anytime and anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has increased rapidly. Such portable electronic devices generally use a memory system that utilizes a memory device, that is, a data storage device. The data storage device is used as the main memory device or auxiliary memory device of the portable electronic device.

[0003] A data storage device that utilizes a memory device has no mechanical driving part, is excellent in stability and durability, has a very high information access speed, and consumes less power. Examples of data storage devices as such a memory system include a USB (Universal Serial Bus) memory device, a memory card having various interfaces, a solid state drive (SSD), and the like.

[0004] Memory devices are broadly classified into volatile memory devices and nonvolatile memory devices.

[0005] Non-volatile memory devices have relatively slow write and read speeds, but retain stored data even when the power supply is cut off. Therefore, non-volatile memory devices are used to store data that should be retained regardless of the presence or absence of a power supply. Examples of non-volatile memory devices include ROM (Read Only Memory), MROM (Mask ROM), PROM (Programmable ROM), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory, PRAM (Phase change Random Access Memory), MRAM (Magnetic RAM), RRAM (Resistive RAM), FRAM (registered trademark) (Ferroelectric RAM), and the like. Flash memory is classified into NOR type and NAND type.

Summary of the Invention

Problems to be Solved by the Invention

[0006] Embodiments of the present invention provide a memory device and an operation method thereof that can shorten the rising time of a read voltage corresponding to a relatively high program state and improve the speed of a read operation.

Means for Solving the Problems

[0007] A memory device according to an embodiment of the present invention includes a memory block including a plurality of memory cells, a peripheral circuit for performing a plurality of read voltage application operations and a plurality of word line setting operations on the memory block, and at least one word line setting operation among the plurality of word line setting operations is set to a higher word line potential than the remaining word line setting operations, and control logic for controlling the peripheral circuit so that the word lines of the memory block have the set word line potential.

[0008] The memory device according to an embodiment of the present invention includes a memory block including a plurality of memory cells, a peripheral circuit for alternately executing a plurality of read voltage application operations and a plurality of word line setting operations for the memory block, and a first specific word line setting operation among the plurality of word line setting operations executed immediately before a first specific read voltage application operation using the highest read voltage among the plurality of read voltage application operations sets a word line potential higher than that of the remaining word line setting operations, and control logic for controlling the peripheral circuit so that the word lines of the memory block have the set word line potential.

[0009] The operation method of the memory device according to an embodiment of the present invention includes a step of executing a first word line setting operation for adjusting a plurality of word lines of a memory block to a first voltage level, a step of executing a first read voltage application operation to the selected word line, a step of executing a second word line setting operation for adjusting the selected word line to a second voltage level after executing the first read voltage application operation, a step of executing a second read voltage application operation to the selected word line, a step of executing a third word line setting operation for adjusting the selected word line to a third voltage level after executing the second read voltage application operation, and a step of executing a third read voltage application operation to the selected word line, and the third voltage level of the third word line setting operation executed immediately before executing the third read voltage application operation using the highest read voltage among the first read voltage application operation, the second read voltage application operation, and the third read voltage application operation is higher than the first voltage level and the second voltage level.

Advantages of the Invention

[0010] This technology can shorten the rising time of the read voltage by setting the word line potential to a positive voltage level before applying a read voltage corresponding to a relatively high program state during a read operation. As a result, the speed of the read operation can be improved, and power consumption can be reduced.

Brief Description of the Drawings

[0011]

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DETAILED DESCRIPTION OF THE INVENTION

[0012] The specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in this specification or application are merely exemplified for the purpose of explaining the embodiments according to the concept of the present invention. The embodiments according to the concept of the present invention can be implemented in various forms and should not be construed as being limited to the embodiments described in this specification or application.

[0013] Hereinafter, for the purpose of explaining in detail to the extent that those having ordinary knowledge in the technical field to which the present invention pertains can easily implement the technical idea of the present invention, embodiments of the present invention will be described with reference to the accompanying drawings.

[0014] FIG. 1 is a diagram for explaining a memory system according to an embodiment of the present invention.

[0015] Referring to FIG. 1, a memory system 1000 may include a memory device 1100 in which data is stored, and a memory controller 1200 that controls the memory device 1100 according to the control of a host 2000.

[0016] The host 2000 can communicate with the memory system 1000 using an interface protocol such as PCI-E (Peripheral Component Interconnect-Express), ATA (Advanced Technology Attachment), SATA (Serial ATA), PATA (Parallel ATA), or SAS (serial attached SCSI). Also, the interface protocol between the host 2000 and the memory system 1000 is not limited to the above examples and may be one of other interface protocols such as USB (Universal Serial Bus), MMC (Multi-Media Card), ESDI (Enhanced Small Disk Interface), or IDE (Integrated Drive Electronics).

[0017] The memory controller 1200 can overall control the operation of the memory system 1000 and control the data exchange between the host 2000 and the memory device 1100. For example, the memory controller 1200 can control the memory device 1100 to program or read data in response to a request from the host 2000. During a program operation, the memory controller 1200 transfers a command CMD, an address ADD, and data DATA to be programmed to the memory device 1100. Also, during a read operation, the memory controller 1200 can receive and temporarily store the data DATA read from the memory device 1100 and transfer the temporarily stored data DATA to the host 2000.

[0018] The memory device 1100 can execute program, read, or erase operations according to the control of the memory controller 1200.

[0019] According to an embodiment, the memory device 1100 may include a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), an LPDDR4 (Low Power Double Data Rate4) SDRAM, a GDDR (Graphics Double Data Rate) SDRAM, an LPDDR (Low Power DDR), an RDRAM (Rambus Dynamic Random Access Memory), or a flash memory (FLASH Memory).

[0020] FIG. 2 is a diagram for explaining the memory device of FIG. 1.

[0021] Referring to FIG. 2, the memory device 1100 may include a memory cell array 100 in which data is stored. The memory device 1100 may include a peripheral circuit 200 configured to execute a program operation for storing data in the memory cell array 100, a read operation for outputting the stored data, and an erase operation for erasing the stored data. The memory device 1100 may include a control logic 300 for controlling the peripheral circuit 200 according to the control of a memory controller (1200 in FIG. 1).

[0022] The memory device 1100 according to an embodiment of the present invention executes a plurality of read voltage application operations respectively corresponding to a plurality of program states during a read operation, but the potential of the word line can be adjusted to a positive voltage level higher than 0V immediately before the read voltage application operation corresponding to the highest program state.

[0023] The memory cell array 100 can include a number of memory blocks MB1 to MBk (110; k is a positive integer). Each of the memory blocks MB1 to MBk (110) can be connected to local lines LL and bit lines BL1 to BLm (m is a positive integer). For example, the local lines LL can include a first select line, a second select line, and a number of word lines arranged between the first and second select lines. Also, the local lines LL can include dummy lines arranged between the first select line and the word lines, and between the second select line and the word lines. Here, the first select line can be a source select line, and the second select line can be a drain select line. For example, the local lines LL can include word lines, drain and source select lines, and source lines SL. For example, the local lines LL may further include dummy lines. For example, the local lines LL may further include pipe lines. The local lines LL can be respectively connected to the memory blocks MB1 to MBk (110), and the bit lines BL1 to BLm can be commonly connected to the memory blocks MB1 to MBk (110). The memory blocks MB1 to MBk (110) can be realized in a two-dimensional or three-dimensional structure. For example, in the two-dimensional memory block 110, the memory cells can be arranged in a direction parallel to the substrate. For example, in the three-dimensional memory block 110, the memory cells can be stacked in a direction perpendicular to the substrate.

[0024] The peripheral circuit 200 can be configured to execute program, read, and erase operations of the memory block 110 selected according to the control of the control logic 300. For example, the peripheral circuit 200 can include a voltage generating circuit 210, a row decoder 220, a page buffer group 230, a column decoder 240, an input / output circuit 250, a pass / fail check circuit 260, and a source line driver 270.

[0025] The voltage generating circuit 210 can generate various operation voltages Vop used for program, read, and erase operations in response to the operation signal OP_CMD. Also, the voltage generating circuit 210 can selectively discharge the local line LL in response to the operation signal OP_CMD. For example, the voltage generating circuit 210 can generate a program voltage, a verification voltage, a read voltage, a pass voltage, a number of setting voltages, etc. according to the control of the control logic 300. The voltage generating circuit 210 can adjust the potential of the word line after the read voltage application operation to a set value according to the control of the word line voltage setting unit 310 of the control logic 300.

[0026] The row decoder 220 can transmit the operating voltage Vop to the local line LL connected to the selected memory block 110 in response to the row decoder control signal AD_signals. For example, during a program operation, the row decoder 220 can apply the program voltage generated by the voltage generation circuit 210 to the selected word line among the local lines LL in response to the row decoder control signal AD_signals, and apply the pass voltage generated by the voltage generation circuit 210 to the non-selected word lines. Also, during a read operation, the row decoder 220 can sequentially apply a number of read voltages generated by the voltage generation circuit 210 to the selected word line among the local lines LL in response to the row decoder control signal AD_signals, and apply the pass voltage generated by the voltage generation circuit 210 to the non-selected word lines.

[0027] The page buffer group 230 can include a number of page buffers PB1 to PBm (231) connected to the bit lines BL1 to BLm. The page buffers PB1 to PBm (231) can operate in response to the page buffer control signal PBSIGNALS. For example, during a program operation, the page buffers PB1 to PBm (231) can temporarily store the data to be programmed and adjust the potential levels of the bit lines BL1 to BLm based on the temporarily stored data to be programmed. Also, during a read or program verification operation, the page buffers PB1 to PBm (231) can sense the voltage or current of the bit lines BL1 to BLm.

[0028] The column decoder 240 can transfer data between the input / output circuit 250 and the page buffer group 230 in response to the column address CADD. For example, the column decoder 240 can exchange data with the page buffer 231 via the data line DL, or exchange data with the input / output circuit 250 via the column line CL.

[0029] The input / output circuit 250 can transmit the command CMD and the address ADD transmitted from the memory controller (1200 in FIG. 1) to the control logic 300, or can communicate with the column decoder 240 with the data DATA.

[0030] During a read operation or a program verify operation, the pass / fail determination unit 260 can generate a reference current in response to the tolerance bit VRY_BIT<#>, and compare the sensing voltage VPB received from the page buffer group 230 with the reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL. The sensing voltage VPB can be a voltage controlled based on the number of memory cells determined to be passed during a program verify operation.

[0031] The source line driver 270 is connected to the memory cells included in the memory cell array 100 via the source line SL, and can control the voltage applied to the source line SL. The source line driver 270 can receive a source line control signal CTRL_SL from the control logic 300, and can control the voltage applied to the source line SL based on the source line control signal CTRL_SL.

[0032] The control logic 300 can output an operation signal OP_CMD, a row decoder control signal AD_signals, a page buffer control signal PBSIGNALS, and a tolerance bit VRY_BIT<#> in response to the command CMD and the address ADD to control the peripheral circuit 200.

[0033] The control logic 300 can control the peripheral circuit 200 to perform a read operation on the selected memory block. For example, during a read operation on the selected memory block, the control logic 300 can control the peripheral circuit 200 to perform a read voltage application operation of applying a plurality of read voltages corresponding to each of the plurality of program states. Also, when one read voltage application operation is completed, the control logic 300 can control the peripheral circuit 200 to perform a word line setting operation of controlling the word line of the selected memory block to a set level before performing the next read voltage application operation. When performing the word line setting operation immediately before performing a read voltage application operation including the read voltage corresponding to the highest program state among the plurality of read voltages, the control logic 300 can control the peripheral circuit 200 so that the potential of the word line has a positive voltage level higher than 0V.

[0034] The control logic 300 can include a word line voltage setting unit 310. The word line voltage setting unit 310 can set the potential of the word line during the word line setting operation between the plurality of read voltage application operations. When performing the word line setting operation immediately before performing a specific read voltage application operation including the read voltage corresponding to the highest program state among the plurality of read voltages, the word line voltage setting unit 310 can control the peripheral circuit 200 so that the potential of the word line has a positive voltage level higher than 0V. Also, when performing the word line setting operation immediately before performing the remaining read voltage application operations except for the specific read voltage application operation, the word line voltage setting unit 310 can control the peripheral circuit 200 so that the potential of the word line becomes 0V.

[0035] FIG. 3 is a diagram for explaining the memory block of FIG. 2.

[0036] Referring to FIG. 3, a memory block 110 can have a number of word lines arranged parallel to each other connected between a first selection line and a second selection line. Here, the first selection line can be a source selection line SSL, and the second selection line can be a drain selection line DSL. More specifically described, the memory block 110 can include a number of strings ST connected between bit lines BL1 to BLm and a source line SL. The bit lines BL1 to BLm can be respectively connected to the string ST, and the source line SL can be commonly connected to the string ST. Since the strings ST can be identically configured to each other, the string ST connected to the first bit line BL1 will be specifically described as an example.

[0037] The string ST can include a source selection transistor SST, a number of memory cells F1 to F16, and a drain selection transistor DST connected in series to each other between the source line SL and the first bit line BL1. One string ST may include at least one or more source selection transistors SST and drain selection transistors DST, and the memory cells F1 to F16 may also include more than the number shown in the figure.

[0038] The source of the source selection transistor SST can be connected to the source line SL, and the drain of the drain selection transistor DST can be connected to the first bit line BL1. The memory cells F1 to F16 can be connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the source selection transistors SST included in different strings ST can be connected to the source selection line SSL, the gates of the drain selection transistors DST can be connected to the drain selection line DSL, and the gates of the memory cells F1 to F16 can be connected to a number of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings ST can be referred to as a physical page PPG. Therefore, the memory block 110 can include as many physical pages PPG as the number of word lines WL1 to WL16.

[0039] FIG. 4 is a diagram for explaining an embodiment of a three-dimensionally configured memory block.

[0040] Referring to FIG. 4, the memory cell array 100 can include a number of memory blocks MB1 to MBk (110). The memory block 110 can include a number of strings ST11 to ST1m, ST21 to ST2m. As an example, each of the number of strings ST11 to ST1m, ST21 to ST2m can be formed in an "I" shape or a "U" shape. In the first memory block MB1, m strings can be arranged in the row direction (X direction). In FIG. 4, although two strings are shown arranged in the column direction (Y direction) for the sake of illustration, this is for convenience of explanation, and three or more strings may be arranged in the column direction (Y direction).

[0041] Each of a plurality of strings ST11 to ST1m, ST21 to ST2m can include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST.

[0042] The source selection transistor SST of each string can be connected between the source line SL and the memory cells MC1 to MCn. The source selection transistors of the strings arranged in the same row can be connected to the same source selection line. The source selection transistors of the strings ST11 to ST1m arranged in the first column can be connected to the first source selection line SSL1. The source selection transistors of the strings ST21 to ST2m arranged in the second row can be connected to the second source selection line SSL2. As another example, the source selection transistors of the strings ST11 to ST1m, ST21 to ST2m may be commonly connected to one source selection line.

[0043] The first to nth memory cells MC1 to MCn of each string can be connected in series with each other between the source selection transistor SST and the drain selection transistor DST. The gates of the first to nth memory cells MC1 to MCn can be respectively connected to the first to nth word lines WL1 to WLn.

[0044] As an example, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. When a dummy memory cell is provided, the voltage or current of the corresponding string can be stably controlled. Thereby, the reliability of the data stored in the memory block 110 can be improved.

[0045] The drain selection transistor DST of each string can be connected between the bit line and the memory cells MC1 to MCn. The drain selection transistors DST of the strings arranged in the row direction can be connected to a drain selection line extending in the row direction. The drain selection transistors DST of the strings ST11 to ST1m in the first row can be connected to the first drain selection line DSL1. The drain selection transistors DST of the strings ST21 to ST2m in the second row can be connected to the second drain selection line DSL2.

[0046] FIG. 5 is a diagram showing the threshold voltage distribution of a triple-level cell according to an embodiment of the present invention and the bits per page corresponding thereto.

[0047] Referring to FIG. 5, referring to the graph of the triple-level cell TLC, the horizontal axis represents the threshold voltage (for example, the level of the threshold voltage), and the vertical axis represents the number of memory cells. The triple-level cell TLC can have an erase state E in which the threshold voltage distribution gradually increases and one of the first to seventh program states P1, P2, P3, P4, P5, P6, P7.

[0048] In a triple-level cell (TLC), the first read voltage VR1 can be a voltage for distinguishing an erase state E and a first program state P1. The second read voltage VR2 can be a voltage for distinguishing the first program state P1 and a second program state P2. The third read voltage VR3 can be a voltage for distinguishing the second program state P2 and a third program state P3. The fourth read voltage VR4 can be a voltage for distinguishing the third program state P3 and a fourth program state P4. The fifth read voltage VR5 can be a voltage for distinguishing the fourth program state P4 and a fifth program state P5. The sixth read voltage VR6 can be a voltage for distinguishing the fifth program state P5 and a sixth program state P6. The seventh read voltage VR7 can be a voltage for distinguishing the sixth program state P6 and a seventh program state P7.

[0049] Referring to the table of the triple-level cell (TLC), a first logical page bit 1st Page, a second logical page bit 2nd Page, and a third logical page bit 3rd Page corresponding to the cell state are shown. The first logical page bit 1st Page, the second logical page bit 2nd Page, and the third logical page bit 3rd Page can be a least significant bit (LSB), a center significant bit (CSB), and a most significant bit (MSB), respectively.

[0050] During the read operation of a memory block including the above-described triple-level cell TLC, a read voltage application operation can be performed for each logical page bit. For example, to read the first logical page bit 1st Page, a first read voltage application operation of applying the first read voltage VR1 and the fifth read voltage VR5 is performed. To read the second logical page bit 2nd Page, a second read voltage application operation of applying the second read voltage VR2, the fourth read voltage VR4, and the sixth read voltage VR6 is performed. To read the third logical page bit 3rd Page, a third read voltage application operation of applying the third read voltage VR3 and the seventh read voltage VR7 can be performed.

[0051] The first read voltage application operation, the second read voltage application operation, and the third read voltage application operation can be sequentially performed.

[0052] FIG. 6 is a diagram for explaining the read operation of a memory device according to an embodiment of the present invention.

[0053] FIG. 7 is a diagram for explaining the voltage applied to a word line during the read operation of a memory device according to an embodiment of the present invention.

[0054] Referring to FIGS. 2 to 7, the read operation of a memory device according to an embodiment of the present invention will be described as follows.

[0055] In an embodiment of the present invention, the read operation for one selected word line of a selected memory block (e.g., MB1) including the triple-level cell TLC will be described as an example.

[0056] In step S610, the word line voltage setting unit 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of the first voltage V1. The first voltage V1 can be 0V or a positive voltage higher than 0V.

[0057] The voltage generation circuit 210 generates a first voltage V1 according to the control of the word line voltage setting unit 310, and the row decoder 220 applies the first voltage V1 to the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to perform a word line setting operation. That is, in the t1 period, the first voltage V1 is applied to the selected word line Sel WL and the unselected word lines Unsel WLs.

[0058] In step S620, the control logic 300 controls the peripheral circuit 200 to perform a first read voltage application operation for reading a first logic page bit 1st page among a plurality of logic page bits stored in the memory cells connected to the selected word line Sel WL.

[0059] The first read voltage application operation can be an operation of applying a first read voltage VR1 and a fifth read voltage VR5 that can distinguish the data value of the first logic page bit 1st page into 0 or 1 to the selected word line Sel WL. During the first read voltage application operation, after first applying the fifth read voltage VR5 with a higher potential level among the first read voltage VR1 and the fifth read voltage VR5 to the selected word line Sel WL, the first read voltage VR1 can be applied to the selected word line Sel WL.

[0060] For example, the voltage generation circuit 210 can sequentially generate the fifth read voltage VR5 and the first read voltage VR1 according to the control of the control logic 300. The row decoder 220 applies the fifth read voltage VR5 to the selected word line Sel WL of the selected memory block MB1 for a certain period of time, and then applies the first read voltage VR1 to the selected word line Sel WL of the selected memory block MB1 for a certain period of time. Also, the voltage generation circuit 210 generates a pass voltage Vpass. The row decoder 220 applies the pass voltage Vpass to the unselected word lines Unsel WLs while the fifth read voltage VR5 and the first read voltage VR1 are applied to the selected word line Sel WL. That is, in the t2 interval, the fifth read voltage VR5 and the first read voltage VR1 are sequentially applied to the selected word line Sel WL, and the pass voltage Vpass is applied to the unselected word lines Unsel WLs.

[0061] Thereafter, the page buffer group 230 senses the voltage or current of the bit lines BL1 to BLm and stores the data value of the first logic page bit 1st page of the memory cell connected to the selected word line Sel WL.

[0062] In step S630, the word line voltage setting unit 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of the second voltage V2. The second voltage V2 can have the same potential as the first voltage V1. For example, the second voltage V2 can be 0V or a positive voltage higher than 0V.

[0063] The voltage generation circuit 210 generates a second voltage V2 according to the control of the word line voltage setting unit 310, and the row decoder 220 applies the second voltage V2 to the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to perform a word line setting operation. That is, in the t3 period, the second voltage V2 is applied to the selected word line Sel WL and the unselected word lines Unsel WLs.

[0064] As another example, when the potential of the selected word line Sel WL is higher than the potential of the second voltage V2, without the voltage generation operation of the voltage generation circuit 210, the row decoder 220 can discharge the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs to the second voltage V2 level.

[0065] In step S640, the control logic 300 controls the peripheral circuit 200 to perform a second read voltage application operation for reading a second logic page bit 2nd page among a plurality of logic page bits stored in the memory cell connected to the selected word line Sel WL.

[0066] The second read voltage application operation can be an operation of applying a second read voltage VR2, a fourth read voltage VR4, and a sixth read voltage VR6, which can distinguish the data value of the second logic page bit 2nd page into 0 or 1, to the selected word line Sel WL. During the second read voltage application operation, the sixth read voltage VR6, the fourth read voltage VR4, and the second read voltage VR2 can be sequentially applied to the selected word line Sel WL in descending order of potential level among the second read voltage VR2, the fourth read voltage VR4, and the sixth read voltage VR6.

[0067] For example, the voltage generation circuit 210 can sequentially generate a sixth lead voltage VR6, a fourth lead voltage VR4, and a second lead voltage VR2 according to the control of the control logic 300. The row decoder 220 applies the sixth lead voltage VR6 to the selected word line Sel WL of the selected memory block MB1 for a certain period of time, and then applies the fourth lead voltage VR4 to the selected word line Sel WL of the selected memory block MB1 for a certain period of time. Thereafter, the row decoder 220 applies the second lead voltage VR2 to the selected word line Sel WL of the selected memory block MB1 for a certain period of time.

[0068] Also, the voltage generation circuit 210 generates a pass voltage Vpass. The row decoder 220 applies the pass voltage Vpass to the unselected word lines Unsel WLs while the sixth lead voltage VR6, the fourth lead voltage VR4, and the second lead voltage VR2 are applied to the selected word line Sel WL. That is, in the t4 period, the sixth lead voltage VR6, the fourth lead voltage VR4, and the second lead voltage VR2 are sequentially applied to the selected word line Sel WL, and the pass voltage Vpass is applied to the unselected word lines Unsel WLs.

[0069] Thereafter, the page buffer group 230 senses the voltage or current of the bit lines BL1 to BLm and stores the data value of the second logical page bit 2nd page of the memory cell connected to the selected word line Sel WL.

[0070] In step S650, the word line voltage setting unit 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of the third voltage V3. The third voltage V3 can have a potential higher than the first voltage V1 and the second voltage V2. For example, the third voltage V3 can be a positive voltage higher than 0V. In an embodiment, the word line voltage setting unit 310 sets the potential of the word line to a positive voltage level higher than 0V immediately before the read voltage application operation that utilizes the seventh read voltage VR7 corresponding to the seventh program state P7, which has a relatively high threshold voltage distribution among the plurality of program states P1 to P7. That is, the peripheral circuit 200 can be controlled to adjust the potential of the word line to a positive voltage level higher than 0V immediately before applying the seventh read voltage, which has the highest potential level among the plurality of read voltages VR1 to VR7 corresponding to the plurality of program states P1 to P7, to the selected word line Sel WL.

[0071] The voltage generation circuit 210 generates the third voltage V3 according to the control of the word line voltage setting unit 310, and the row decoder 220 applies the third voltage V3 to the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to perform a word line setting operation. That is, in the t5 interval, the third voltage V3 is applied to the selected word line Sel WL and the unselected word lines Unsel WLs.

[0072] As another embodiment, when the potential of the selected word line Sel WL is higher than the potential of the third voltage V3, without the voltage generation operation of the voltage generation circuit 210, the row decoder 220 can discharge the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs to the third voltage V3 level.

[0073] In step S660, the control logic 300 controls the peripheral circuit 200 to execute a third read voltage application operation for reading a third logic page bit 3rd page among a plurality of logic page bits stored in the memory cell connected to the selected word line Sel WL.

[0074] The third read voltage application operation can be an operation of applying a third read voltage VR3 and a seventh read voltage VR7 that can distinguish the data value of the third logic page bit 3rd page into 0 or 1 to the selected word line Sel WL. During the third read voltage application operation, after first applying the seventh read voltage VR7 with a higher potential level among the third read voltage VR3 and the seventh read voltage VR7 to the selected word line Sel WL, the third read voltage VR3 can be applied to the selected word line Sel WL.

[0075] For example, the voltage generation circuit 210 can sequentially generate the seventh read voltage VR7 and the third read voltage VR3 according to the control of the control logic 300. The row decoder 220 applies the seventh read voltage VR7 to the selected word line Sel WL of the selected memory block MB1 for a certain period of time, and then applies the third read voltage VR3 to the selected word line Sel WL of the selected memory block MB1 for a certain period of time. Also, the voltage generation circuit 210 generates a pass voltage Vpass. The row decoder 220 applies the pass voltage Vpass to the unselected word lines Unsel WLs while the seventh read voltage VR7 and the third read voltage VR3 are applied to the selected word line Sel WL. That is, in the t6 interval, the seventh read voltage VR7 and the third read voltage VR1 are sequentially applied to the selected word line Sel WL, and the pass voltage Vpass is applied to the unselected word lines Unsel WLs.

[0076] Thereafter, the page buffer group 230 senses the voltages or currents of bit lines BL1 to BLm and stores the data value of the third logical page bit 3rd page of the memory cell connected to the selected word line Sel WL.

[0077] The voltage generation circuit 210 raises the potential of the word line controlled to the positive voltage level in the t5 section to the seventh read voltage VR7 level in the t6 section. Compared with the operation of raising the word line from 0V to the seventh read voltage VR7 level, the operation of raising the potential from the third read voltage V3 level having a positive potential to the seventh read voltage VR7 level reduces the operation time and also reduces the power consumption of the voltage generation circuit 210.

[0078] In step S670, the word line voltage setting unit 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of the fourth voltage V4. The fourth voltage V4 can have the same potential as the first voltage V1 and the second voltage V2. For example, the fourth voltage V4 can be 0V or a positive voltage higher than 0V.

[0079] The row decoder 220 can execute a word line setting operation by discharging the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs to the fourth voltage V4 level.

[0080] In the above-described embodiment of the present invention, it has been described that the potential of the word line is set to a positive voltage level immediately before applying the seventh lead voltage VR7, which has the relatively highest potential among the plurality of lead voltages, to the selected word line Sel WL. As another example, the potential of the word line can be set to a positive voltage level immediately before applying at least one or more lead voltages, which have relatively high potentials among the plurality of lead voltages, to the selected word line Sel WL. For example, immediately before the third lead voltage application operation using the seventh lead voltage VR7, the potential of the word line is set to the third voltage V3, and immediately before the second lead voltage application operation using the sixth lead voltage VR6, the potential of the word line can be set to a level lower than the third voltage V3 and higher than the first voltage V1, which is the third voltage V3 or lower.

[0081] FIG. 8 is a diagram showing the threshold voltage distribution of a triple-level cell according to another embodiment of the present invention and the bits per page corresponding thereto.

[0082] Referring to FIG. 8, referring to the graph of the triple-level cell TLC, the horizontal axis represents the threshold voltage (for example, the level of the threshold voltage), and the vertical axis represents the number of memory cells. The triple-level cell TLC can have an erase state E in which the threshold voltage distribution gradually increases and one of the states from the first program state to the seventh program state P1, P2, P3, P4, P5, P6, P7.

[0083] In a triple-level cell (TLC), the first read voltage VR1 can be a voltage for distinguishing an erase state E and a first program state P1. The second read voltage VR2 can be a voltage for distinguishing the first program state P1 and a second program state P2. The third read voltage VR3 can be a voltage for distinguishing the second program state P2 and a third program state P3. The fourth read voltage VR4 can be a voltage for distinguishing the third program state P3 and a fourth program state P4. The fifth read voltage VR5 can be a voltage for distinguishing the fourth program state P4 and a fifth program state P5. The sixth read voltage VR6 can be a voltage for distinguishing the fifth program state P5 and a sixth program state P6. The seventh read voltage VR7 can be a voltage for distinguishing the sixth program state P6 and a seventh program state P7.

[0084] Referring to the table of the triple-level cell (TLC), a first logical page bit 1st Page, a second logical page bit 2nd Page, and a third logical page bit 3rd Page corresponding to the cell state are shown. The first logical page bit 1st Page, the second logical page bit 2nd Page, and the third logical page bit 3rd Page can be a least significant bit (LSB), a middle significant bit (CSB), and a most significant bit (MSB).

[0085] During the read operation of a memory block including the above-described triple-level cell (TLC), a read voltage application operation can be performed for each logical page bit. For example, in order to read the third logical page bit 3rd Page, a first read voltage application operation of applying the fourth read voltage VR4 can be performed. In order to read the second logical page bit 2nd Page, a second read voltage application operation of applying the first read voltage VR1, the third read voltage VR3, and the sixth read voltage VR6 can be performed. Also, in order to read the first logical page bit 1st Page, a third read voltage application operation of applying the second read voltage VR2 and the fifth read voltage VR5 can be performed.

[0086] The first lead voltage application operation, the second lead voltage application operation, and the third lead voltage application operation can be sequentially executed.

[0087] FIG. 9 is a diagram for explaining a read operation of a memory device according to another embodiment of the present invention.

[0088] FIG. 10 is a diagram for explaining a voltage applied to a word line during a read operation of a memory device according to another embodiment of the present invention.

[0089] Referring to FIGS. 2 to 4 and FIGS. 8 to 10, the read operation of the memory device according to an embodiment of the present invention will be described as follows.

[0090] In one embodiment of the present invention, a read operation for one selected word line of a selected memory block (for example, MB1) including a triple-level cell TLC will be described as an example.

[0091] In step S910, the word line voltage setting unit 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of the first voltage V1. The first voltage V1 can be 0V or a positive voltage higher than 0V.

[0092] The voltage generation circuit 210 generates the first voltage V1 according to the control of the word line voltage setting unit 310, and the row decoder 220 applies the first voltage V1 to the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to execute a word line setting operation. That is, in the period t11, the first voltage V1 is applied to the selected word line Sel WL and the unselected word lines Unsel WLs.

[0093] In step S920, the control logic 300 controls the peripheral circuit 200 to perform a first read voltage application operation for reading the third logical page bit 3rd page among a plurality of logical page bits stored in the memory cells connected to the selected word line Sel WL.

[0094] The first read voltage application operation can be an operation of applying a fourth read voltage VR4 that can distinguish the data value of the third logical page bit 3rd page into 0 or 1 to the selected word line Sel WL.

[0095] For example, the voltage generation circuit 210 can generate the fourth read voltage VR4 according to the control of the control logic 300. The row decoder 220 applies the fourth read voltage VR4 to the selected word line Sel WL of the selected memory block MB1 for a certain period of time. Also, the voltage generation circuit 210 generates a pass voltage Vpass. The row decoder 220 applies the pass voltage Vpass to the unselected word lines Unsel WLs while the fourth read voltage VR4 is applied to the selected word line Sel WL. That is, in the t12 period, the fourth read voltage VR4 is applied to the selected word line Sel WL, and the pass voltage Vpass is applied to the unselected word lines Unsel WLs.

[0096] Thereafter, the page buffer group 230 senses the voltage or current of the bit lines BL1~BLm and stores the data value of the third logical page bit 3rd page of the memory cells connected to the selected word line Sel WL.

[0097] In step S930, the word line voltage setting unit 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of the second voltage V2. The second voltage V2 can have the same potential as the first voltage V1. For example, the second voltage V2 can be 0V or a positive voltage higher than 0V.

[0098] The voltage generation circuit 210 generates a second voltage V2 according to the control of the word line voltage setting unit 310, and the row decoder 220 applies the second voltage V2 to the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to execute a word line setting operation. That is, in the period t13, the second voltage V2 is applied to the selected word line Sel WL and the unselected word lines Unsel WLs.

[0099] As another example, when the potential of the selected word line Sel WL is higher than the potential of the second voltage V2, without the voltage generation operation of the voltage generation circuit 210, the row decoder 220 can discharge the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs to the second voltage V2 level.

[0100] In step S940, the control logic 300 controls the peripheral circuit 200 to perform a second read voltage application operation for reading a second logic page bit 2nd page among a plurality of logic page bits stored in the memory cell connected to the selected word line Sel WL.

[0101] The second read voltage application operation can be an operation of applying a first read voltage VR1, a third read voltage VR3, and a sixth read voltage VR6, which can distinguish the data value of the second logic page bit 2nd page into 0 or 1, to the selected word line Sel WL. During the second read voltage application operation, the sixth read voltage VR6, the third read voltage VR3, and the first read voltage VR1 can be sequentially applied to the selected word line Sel WL in the order of decreasing potential levels among the first read voltage VR1, the third read voltage VR3, and the sixth read voltage VR6.

[0102] For example, the voltage generation circuit 210 can sequentially generate a sixth lead voltage VR6, a third lead voltage VR3, and a first lead voltage VR1 according to the control of the control logic 300. The row decoder 220 applies the sixth lead voltage VR6 to the selected word line Sel WL of the selected memory block MB1 for a certain period of time, and then applies the third lead voltage VR3 to the selected word line Sel WL of the selected memory block MB1 for a certain period of time. Thereafter, the row decoder 220 applies the first lead voltage VR1 to the selected word line Sel WL of the selected memory block MB1 for a certain period of time.

[0103] Also, the voltage generation circuit 210 generates a pass voltage Vpass. The row decoder 220 applies the pass voltage Vpass to the unselected word lines Unsel WLs while the sixth lead voltage VR6, the third lead voltage VR3, and the first lead voltage VR1 are applied to the selected word line Sel WL. That is, in the t14 period, the sixth lead voltage VR6, the third lead voltage VR3, and the first lead voltage VR1 are sequentially applied to the selected word line Sel WL, and the pass voltage Vpass is applied to the unselected word lines Unsel WLs.

[0104] Thereafter, the page buffer group 230 senses the voltage or current of the bit lines BL1 to BLm and stores the data value of the second logical page bit 2nd page of the memory cell connected to the selected word line Sel WL.

[0105] In step S950, the word line voltage setting unit 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of the third voltage V3. The third voltage V3 can have a potential higher than the first voltage V1 and the second voltage V2. For example, the third voltage V3 can be a positive voltage higher than 0V. In an embodiment, the word line voltage setting unit 310 adjusts the potential of the word line to a positive voltage level higher than 0V immediately before the read voltage application operation that utilizes the seventh read voltage VR7 corresponding to the seventh program state P7, which has a relatively high threshold voltage distribution among the plurality of program states P1 to P7. That is, the peripheral circuit 200 can be controlled to adjust the potential of the word line to a positive voltage level higher than 0V immediately before applying the seventh read voltage, which has the highest potential level among the plurality of read voltages VR1 to VR7 corresponding to the plurality of program states P1 to P7, to the selected word line Sel WL.

[0106] The voltage generation circuit 210 generates the third voltage V3 according to the control of the word line voltage setting unit 310, and the row decoder 220 applies the third voltage V3 to the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to perform a word line setting operation. That is, in the t15 interval, the third voltage V3 is applied to the selected word line Sel WL and the unselected word lines Unsel WLs.

[0107] As another embodiment, when the potential of the selected word line Sel WL is higher than the potential of the third voltage V3, the row decoder 220 can discharge the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs to the third voltage V3 level without the voltage generation operation of the voltage generation circuit 210.

[0108] In step S960, the control logic 300 controls the peripheral circuit 200 to perform a third read voltage application operation for reading the first logic page bit 1st page among a plurality of logic page bits stored in the memory cell connected to the selected word line Sel WL.

[0109] The third read voltage application operation can be an operation of applying the second read voltage VR2, the fifth read voltage VR5, and the seventh read voltage VR7 that can distinguish the data value of the first logic page bit 1st page into 0 or 1 to the selected word line Sel WL. During the third read voltage application operation, after first applying the seventh read voltage VR7 with a higher potential level among the second read voltage VR2, the fifth read voltage VR5, and the seventh read voltage VR7 to the selected word line Sel WL, the fifth read voltage VR5 can be applied to the selected word line Sel WL. After applying the fifth read voltage VR5 to the selected word line Sel WL, the second read voltage VR2 can be applied to the selected word line Sel WL.

[0110] For example, the voltage generation circuit 210 can sequentially generate the seventh read voltage VR7, the fifth read voltage VR5, and the second read voltage VR2 according to the control of the control logic 300. The row decoder 220 applies the seventh read voltage VR7 to the selected word line Sel WL of the selected memory block MB1 for a certain period of time, and then applies the fifth read voltage VR5 to the selected word line Sel WL of the selected memory block MB1 for a certain period of time. Thereafter, the row decoder 220 applies the second read voltage VR2 to the selected word line Sel WL of the selected memory block MB1 for a certain period of time.

[0111] Also, the voltage generation circuit 210 generates a pass voltage Vpass. The row decoder 220 applies the pass voltage Vpass to the unselected word lines Unsel WLs while the seventh read voltage VR7, the fifth read voltage VR5, and the second read voltage VR2 are applied to the selected word line Sel WL. That is, in the t16 period, the seventh read voltage VR7, the fifth read voltage VR5, and the second read voltage VR2 are sequentially applied to the selected word line Sel WL, and the pass voltage Vpass is applied to the unselected word lines Unsel WLs.

[0112] Thereafter, the page buffer group 230 senses the voltages or currents of the bit lines BL1 to BLm and stores the data value of the first logical page bit 1st page of the memory cell connected to the selected word line Sel WL.

[0113] The voltage generation circuit 210 raises the potential of the word line controlled to the positive voltage level in the t15 period to the seventh read voltage VR7 level in the t16 period. Compared with the operation of raising the word line from 0V to the seventh read voltage VR7 level, the operation of raising the potential from the third read voltage V3 level having a positive potential to the seventh read voltage VR7 level reduces the operation time and also reduces the power consumption of the voltage generation circuit 210.

[0114] In step S970, the word line voltage setting unit 310 of the control logic 300 sets the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs of the selected memory block MB1 to the potential of the fourth voltage V4. The fourth voltage V4 can have the same potential as the first voltage V1 and the second voltage V2. For example, the fourth voltage V4 can be 0V or a positive voltage higher than 0V.

[0115] The row decoder 220 can execute a word line setting operation by discharging the potentials of the selected word line Sel WL and the unselected word lines Unsel WLs to the fourth voltage V4 level.

[0116] In the above-described embodiments of the present invention, it was described that immediately before applying the seventh lead voltage VR7, which has the relatively highest potential among the plurality of lead voltages, to the selected word line Sel WL, the potential of the word line is set to a positive voltage level. As another example, immediately before applying at least one or more lead voltages, which have relatively high potentials among the plurality of lead voltages, to the selected word line Sel WL, the potential of the word line can be set to a positive voltage level. For example, immediately before the third lead voltage application operation using the seventh lead voltage VR7, the potential of the word line is set to the third voltage V3, and immediately before the second lead voltage application operation using the sixth lead voltage VR6, the potential of the word line can be set to a level lower than the third voltage V3 and higher than the first voltage V1, or to the third voltage V3.

[0117] FIG. 11 is a diagram for explaining another embodiment of the memory system.

[0118] Referring to FIG. 11, the memory system 30000 can be implemented by a cellular phone, a smart phone, a tablet PC, a PDA (personal digital assistant), or a wireless communication device. The memory system 30000 can include a memory device 1100 and a memory controller 1200 capable of controlling the operation of the memory device 1100. The memory controller 1200 can control data access operations of the memory device 1100, such as program operations, erase operations, or read operations, according to the control of the processor 3100.

[0119] The data programmed in the memory device 1100 can be output via the display 3200 under the control of the memory controller 1200.

[0120] The radio transceiver 3300 can exchange wireless signals via the antenna ANT. For example, the radio transceiver 3300 can change the wireless signal received via the antenna ANT into a signal that can be processed by the processor 3100. Therefore, the processor 3100 can process the signal output from the radio transceiver 3300 and transmit the processed signal to the memory controller 1200 or the display 3200. The memory controller 1200 can program the signal processed by the processor 3100 into the memory device 1100. Also, the radio transceiver 3300 can change the signal output from the processor 3100 into a wireless signal and output the changed wireless signal to an external device via the antenna ANT. The input device 3400 is a device that can input a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100, and can be realized by a pointing device such as a touch pad and a computer mouse, a keypad, or a keyboard. The processor 3100 can control the operation of the display 3200 so that the data output from the memory controller 1200, the data output from the radio transceiver 3300, or the data output from the input device 3400 is output via the display 3200.

[0121] According to an embodiment, the memory controller 1200 that can control the operation of the memory device 1100 can be realized as a part of the processor 3100, or can also be realized by a chip separate from the processor 3100. Note that the memory controller 1200 can be realized according to the example of the memory controller 1200 shown in FIG. 1, and the memory device 1100 can be realized according to the example of the memory device 1100 shown in FIG. 2.

[0122] FIG. 12 is a diagram for explaining another embodiment of the memory system.

[0123] Referring to FIG. 12, the memory system 40000 can be implemented by a personal computer (PC), a tablet PC, a net-book, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

[0124] The memory system 40000 can include a memory device 1100 and a memory controller 1200 that can control the data processing operations of the memory device 1100.

[0125] The processor 4100 can output the data stored in the memory device 1100 via the display 4300 according to the data input via the input device 4200. For example, the input device 4200 can be implemented by a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

[0126] The processor 4100 can control the overall operation of the memory system 40000 and can control the operation of the memory controller 1200. According to an embodiment, the memory controller 1200 that can control the operation of the memory device 1100 can be implemented as a part of the processor 4100 or can be implemented on a separate chip from the processor 4100. Also, the memory controller 1200 can be implemented by the example of the memory controller 1200 shown in FIG. 1, and the memory device 1100 can be implemented by the example of the memory device 1100 shown in FIG. 2.

[0127] FIG. 13 is a diagram for explaining another embodiment of the memory system.

[0128] Referring to FIG. 13, the memory system 50000 can be implemented in an image processing device, such as a digital camera, a mobile phone with a digital camera, a smartphone with a digital camera, or a tablet PC with a digital camera.

[0129] The memory system 50000 includes a memory device 1100 and a memory controller 1200 that can control data processing operations of the memory device 1100, such as program operations, erase operations, or read operations.

[0130] The image sensor 5200 of the memory system 50000 can convert an optical image into a digital signal, and the converted digital signal can be transmitted to a processor 5100 or the memory controller 1200. According to the control of the processor 5100, the converted digital signal can be output via a display 5300 or stored in the memory device 1100 via the memory controller 1200. Also, the data stored in the memory device 1100 can be output via the display 5300 according to the control of the processor 5100 or the memory controller 1200.

[0131] The memory controller 1200 that can control the operation of the memory device 1100 according to the embodiment can be implemented as part of the processor 5100 or as a separate chip from the processor 5100. Also, the memory controller 1200 can be implemented according to the example of the memory controller 1200 shown in FIG. 1, and the memory device 1100 can be implemented according to the example of the memory device 1100 shown in FIG. 2.

[0132] FIG. 14 is a diagram for explaining another embodiment of the memory system.

[0133] Referring to FIG. 14, the Memory System 70000 can be implemented by a memory card or a smart card. The Memory System 70000 can include a Memory Device 1100, a Memory Controller 1200, and a Card Interface 7100.

[0134] The Memory Controller 1200 can control the exchange of data between the Memory Device 1100 and the Card Interface 7100. According to an embodiment, the Card Interface 7100 can be, but is not limited to, an SD (secure digital) card interface or an MMC (multi-media card) interface. Also, the Memory Controller 1200 can be implemented by the example of the Memory Controller 1200 shown in FIG. 1, and the Memory Device 1100 can be implemented by the example of the Memory Device 1100 shown in FIG. 2.

[0135] The Card Interface 7100 can interface data exchange between the HOST 60000 and the Memory Controller 1200 according to the protocol of the HOST 60000. According to an embodiment, the Card Interface 7100 can support a USB (Universal Serial Bus) protocol, an IC (InterChip)-USB protocol. Here, the card interface can mean hardware that can support the protocol used by the HOST 60000, software or a signal transmission method installed on the hardware.

[0136] When the memory system 70000 is connected to a host interface 6200 of a host 60000 such as a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, console video game hardware, or a digital set-top box, the host interface 6200 can communicate data with the memory device 1100 via the card interface 7100 and the memory controller 1200 under the control of the microprocessor 6100.

[0137] In the above embodiments, all steps may be selectively executed or omitted. Also, the steps in each embodiment do not necessarily have to be performed in the order shown and may be reversed. On the other hand, the embodiments of the present specification disclosed in the present specification and the drawings are merely specific examples presented to easily explain the technical content of the present specification and assist in understanding the present specification, and do not limit the scope of the present specification. That is, it is obvious to those of ordinary skill in the technical field to which the present specification belongs that other variations based on the technical idea of the present specification are possible.

Explanation of Reference Numerals

[0138] 1000 Memory system 1100 Memory device 1200 Memory controller 100 Memory cell array 200 Peripheral circuit 300 Control logic 310 Word line voltage setting unit

Claims

1. a memory block including a plurality of memory cells; a peripheral circuit for performing a plurality of read voltage application operations and a plurality of word line setting operations for the memory block; and control logic for setting at least one of the plurality of word line setting operations to a word line potential higher than the remaining word line setting operations and controlling the peripheral circuitry so that the word lines of the memory block have the set word line potential.

2. 2. The memory device of claim 1, wherein the memory cells have an erased state and a plurality of programmed states, and the peripheral circuit applies at least one of a plurality of read voltages for distinguishing the erased state and the plurality of programmed states to a selected one of the word lines in each of the plurality of read voltage application operations.

3. the peripheral circuit performs one of the word line setting operations between the read voltage application operations; 3. The memory device of claim 2, wherein the at least one word line setting operation is performed immediately before performing a specific read voltage application operation using at least one highest read voltage among the plurality of read voltage application operations.

4. 3. The memory device of claim 2, wherein the plurality of read voltage application operations correspond to a least significant bit, a middle bit, and a most significant bit of the memory cell.

5. the peripheral circuit adjusts the word lines to have a first voltage level in the at least one word line setting operation and adjusts the word lines to have a second voltage level in the remaining word line setting operations; 2. The memory device of claim 1, wherein the first voltage level is a positive voltage level greater than 0V.

6. 6. The memory device of claim 5, wherein the peripheral circuitry adjusts the word line to the second voltage level before performing a first read voltage application operation of the plurality of read voltage application operations.

7. 6. The memory device of claim 5, wherein the peripheral circuitry adjusts the word line to the second voltage level after performing a last read voltage application operation of the plurality of read voltage application operations.

8. the control logic includes a word line setting unit; 2. The memory device of claim 1, wherein the word line setting unit sets a word line potential in each of the plurality of word line setting operations.

9. a memory block including a plurality of memory cells; a peripheral circuit for alternately performing a plurality of read voltage application operations and a plurality of word line setting operations for the memory block; a first specific word line setting operation among a plurality of word line setting operations performed immediately before a first specific read voltage application operation using the highest read voltage among the plurality of read voltage application operations, the first specific word line setting operation being set to a word line potential higher than the remaining word line setting operations, and control logic for controlling the peripheral circuitry so that the word lines of the memory block have the set word line potential.

10. 10. The memory device of claim 9, wherein the control logic sets a second specific word line setting operation among the plurality of word line setting operations performed immediately before a second specific read voltage application operation using the second highest read voltage among the plurality of read voltage application operations to a word line potential lower than the first specific word line setting operation and higher than the remaining word line setting operations excluding the first specific word line setting operation and the second specific word line setting operation.

11. the peripheral circuit adjusts the word lines to have a first voltage level in the first specific word line setting operation, and adjusts the word lines to have a second voltage level in remaining word line setting operations other than the first specific word line setting operation and the second specific word line setting operation; 11. The memory device of claim 10, wherein the first voltage level is a positive voltage level greater than 0V.

12. the peripheral circuit controls the word line to have a third voltage level in the second specific word line setting operation; 12. The memory device of claim 11, wherein the third voltage level is a positive voltage level greater than 0V.

13. 12. The memory device of claim 11, wherein the peripheral circuitry adjusts the word line to the second voltage level before performing a first read voltage application operation of the plurality of read voltage application operations.

14. 12. The memory device of claim 11, wherein the peripheral circuitry controls the word line to the second voltage level after performing a last read voltage application operation of the plurality of read voltage application operations.

15. performing a first word line setting operation to adjust a plurality of word lines of the memory block to a first voltage level; performing a first read voltage application operation on a selected word line; performing a second word line setting operation to adjust the selected word line to a second voltage level after performing the first read voltage application operation; performing a second read voltage application operation on the selected word line; performing a third word line setting operation to adjust the selected word line to a third voltage level after performing the second read voltage application operation; performing a third read voltage application operation on the selected word line; A method for operating a memory device, wherein the third voltage level of the third word line setting operation performed immediately before performing the third read voltage application operation using the highest read voltage among the first read voltage application operation, the second read voltage application operation, and the third read voltage application operation is higher than the first voltage level and the second voltage level.

16. 16. The method of claim 15, wherein the third voltage level is greater than 0V.

17. 16. The method of claim 15, wherein the second voltage level of the second word line setting operation performed immediately before performing the second read voltage application operation using the second highest read voltage among the first read voltage application operation, the second read voltage application operation, and the third read voltage application operation is higher than the first voltage level and lower than the third voltage level.

18. 20. The method of claim 17, wherein the second voltage level is greater than 0V.

19. the first read voltage application operation is an operation for reading the least significant bit of a memory cell connected to the selected word line, the second read voltage application operation is an operation for reading an intermediate bit of the memory cell, 16. The method of claim 15, wherein the third read voltage application operation is an operation for reading a most significant bit of the memory cell.

20. the first read voltage application operation is an operation for reading a most significant bit of a memory cell connected to the selected word line, the second read voltage application operation is an operation for reading an intermediate bit of the memory cell, 16. The method of claim 15, wherein the third read voltage application operation is an operation for reading a least significant bit of the memory cell.

21. after performing the third read voltage application operation on the selected word line, performing a fourth word line setting operation to adjust the selected word line to a fourth voltage level; 16. The method of claim 15, wherein the fourth voltage level is lower than the third voltage level.

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