Information processor

Abstract

To provide an information processor capable of flexible accommodation by a mounting shape and a shape change.SOLUTION: An information processor includes a plurality of chips. The plurality of chips are accumulated in a horizontal direction. Each of the plurality of chips is formed with a transmission coil and a reception coil as one pair. Each of the plurality of chips executes radio communication between the chips using inductive coupling in the horizontal direction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an information processing apparatus.

Background Art

[0002] A SoC (System-on-a-Chip) in which different blocks are mounted on a single chip is known. FIG. 2 of Patent Document 1 discloses a processor SoC.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the conventional SoC, there has been a problem that the mounting shape and the change in the shape are restricted.

[0005] The present invention has been made in view of such circumstances, and an object thereof is to provide an information processing apparatus that can flexibly respond to changes in the mounting shape and the shape.

Means for Solving the Problems

[0006] According to one aspect of the present invention, there is provided an information processing apparatus including a plurality of chips, the plurality of chips being integrated in a horizontal direction, and a pair of transmission coils and reception coils being formed in each of the plurality of chips, and each of the plurality of chips performing wireless connection between chips using horizontal inductive coupling.

Effects of the Invention

[0007] According to one aspect of the present invention, there is an advantageous effect that an information processing apparatus that can flexibly respond to changes in the mounting shape and the shape can be provided.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Various characteristic matters shown in the following embodiments can be combined with each other.

[0010] As used herein, the term "section" may include, for example, hardware resources implemented by a circuit in a broad sense and information processing of software that can be specifically realized by these hardware resources. Also, in this embodiment, various types of information are handled. These types of information are represented by the high and low levels of signal values as a set of binary bits composed of 0 or 1, and communication and operations can be executed on a circuit in a broad sense.

[0011] Also, a circuit in a broad sense is a circuit realized by appropriately combining at least a circuit (cIRCUIT), circuitry (cIRCUITRY), a processor (pROCESSOR), a memory (mEMORY), etc. That is, it includes an application specific integrated circuit (aPPLICATION sPECIFIC iNTEGRATED cIRCUIT: asic), programmable logic devices (for example, a simple programmable logic device (sIMPLE pROGRAMMABLE lOGIC dEVICE: spld), a complex programmable logic device (cOMPLEX pROGRAMMABLE lOGIC dEVICE: cpld), and a field programmable gate array (fIELD pROGRAMMABLE gATE aRRAY: fpga)), etc.

[0012] <Embodiment 1> 1. Horizontal inter-chip wireless bus FIG. 1 is a diagram (part 1) showing an example of a wireless bus between chips in the horizontal direction. Also, FIG. 2 is a diagram (part 2) showing an example of a wireless bus between chips in the horizontal direction. The information processing apparatus 100 includes a plurality of chips 110 A ~110 E and has. The plurality of chips 110 A ~110 E are integrated in the horizontal direction. A pair of transmission coils and reception coils are formed in each of the plurality of chips. Each of the plurality of chips 110 A ~110 E performs wireless connection between chips using horizontal inductive coupling. As shown in FIG. 1, an on-chip coil is formed using internal wiring of the chip. Also, as shown in FIGS. 1 and 2, wireless connection between chips is made using horizontal inductive coupling. With such a configuration, it is not necessary to set up and manufacture a silicon interposer, and the information processing apparatus 100 can be inexpensively constructed by flexibly combining the chiplets.

[0013] FIG. 3 is a diagram (part 3) showing an example of a wireless bus between chips in the horizontal direction. As shown in FIG. 3, the information processing apparatus 100 can be mounted in a free form. For example, it is possible to mount the chips in a long and narrow shape like a fiber itself, mount the chips with an oblique relative angle between the chips, and mount a system whose shape deforms during operation. One of the plurality of chips constituting the information processing apparatus 100 is a CPU (Central Processing Unit). Also, one of the plurality of chips constituting the information processing apparatus 100 is a memory. The information processing apparatus 100 is not limited thereto. The hardware constituting the information processing apparatus 100 may be composed of one or a plurality of chips. For example, among the plurality of chips constituting the information processing apparatus 100, the CPU may be constituted by at least two or more chips. In other words, the chips constituting the information processing apparatus 100 can be flexibly separated. Note that the information processing apparatus 100 does not necessarily have to include a CPU and a memory.

[0014] FIG. 4 is a diagram showing an example when combined with a wireless power supply technology. In the information processing apparatus 100, by combining a wireless bus between chips in the horizontal direction and a wireless power supply technology, chips can be mounted on various substrates 400. Also, the chips can be easily replaced even after mounting. As shown in FIG. 4, a plurality of chips are horizontally integrated on the substrate 400. Here, the substrate 400 is a variable shape member. A variable shape member is a member whose shape can be deformed, and examples thereof include a flexible substrate, plastic, and fiber. By simply fixing and arranging the chips on such a variable shape member using something like a DAF tape, etc., the information processing apparatus 100 can be constructed. In the case of a failure or system update data, a new information processing apparatus 100 can be realized by simply replacing the chips and arranging them again.

[0015] 2. Horizontal inductive coupling between coils First, the horizontal inductive coupling between on-chip coils will be described. The coupling degree between coils is mainly determined by the length of one adjacent side and the distance between two coils. Therefore, the larger the coil and the shorter the distance between adjacent sides, the stronger the coupling. Through this inductive coupling, a signal can be transmitted from the transmitting coil to the receiving coil. For example, as shown in FIG. 5, when a transmission current Itx flows toward the back side of the screen, a corresponding received voltage Vrx is induced on the receiving side. The characteristics of this coil can be represented by an equivalent circuit as shown in FIG. 6. The received voltage is the product of the first-order differential waveform of the transmission current Itx multiplied by the second-order low-pass filter characteristics on the transmitting side and the receiving side. Also, the amplitude of the received voltage Vrx is proportional to the transmission current and the coupling coefficient. If the threshold for normally restoring data on the receiving side is fixed, when the coupling coefficient becomes half, it is necessary to flow twice the current, which determines the power consumption of the transmission circuit.

[0016] 3. Transceiver core circuit Next, the transmission / reception core circuit will be described with reference to FIGS. 7 and 8. FIGS. 7 and 8 are diagrams for explaining the transmission / reception core circuit configured on the chip. Here, two inverters are used to drive the coil. A transmission current Itx in the direction corresponding to the input Txdata flows through the coil. As a result, on the reception side, a pulse voltage corresponding to the data transition is generated as shown in FIG. 8. At this time, the polarity of the pulse depends on whether the data transition is from LOW to HIGH or from HIGH to LOW. The reception-side hysteresis comparator restores this pulse voltage to the original NRZ data, and the final Rxdata is obtained as shown in FIG. 8.

[0017] 4. Transmission / Reception Circuit FIG. 9 is a diagram showing an example of the transmission / reception circuit configured on the chip. A method of serializing the parallel signal sent from the core and performing burst transfer is adopted. As shown in FIG. 9, the transmission / reception circuit is equipped with a SerDes (Serializer / Deserializer) and a CDR circuit for connection to the digital circuit. In addition, the transmission / reception circuit is equipped with a collision detection circuit. When a collision of transmission data occurs between chips, the collision detection circuit retransmits the data according to the procedure defined by the upper protocol. Note that the transmission coil 801 is a transmission coil. The reception coil 802 is a reception coil. FIG. 10 is a diagram showing an example of the transmission coil 801 and the reception coil 802. In the present embodiment, since a coil with a size of several mm square is used, the area of the entire interface becomes extremely large. However, since the influence of the magnetic field generated by the on-chip coil on the internal circuit is small, as shown in FIG. 10, the coil can be formed along the peripheral part with abundant wiring resources rather than inside the core, and the core circuit, network interface, and transmission / reception circuit can be formed inside it. Considering the communication characteristics and a design example of a typical square chip, each side of the transmission coil 801 and the reception coil 802 is at least about 90% of the length of each side of the chip. The opening area of the transmission coil and the opening area of the reception coil are preferably 80% or more of the area of the chip.

[0018] Note that the transmitting coil 801 and the receiving coil 802 may be formed on different layers of the chip. Also, the transmitting coil 801 and the receiving coil 802 may be formed at substantially the same positions of a plurality of chips.

[0019] 5. Electromagnetic field simulation environment FIG. 11 is a diagram showing an example of an electromagnetic field simulation environment. A simulation model of the coil and the substrate was created based on the parameters of the manufacturing process, and the coupling coefficient between the coils was investigated by using EmPro, a three-dimensional electromagnetic field simulator manufactured by Keysight. The S-parameters obtained from the electromagnetic field simulation were fitted to an equivalent circuit, and the resulting coupling coefficient and mutual inductance were adopted as the simulation results.

[0020] 6. Mutual inductance of rectangular coils FIGS. 12 and 13 are diagrams showing an example of the mutual inductance of rectangular coils. FIG. 12 shows the change in the mutual inductance when the side Dw perpendicular to the side closest to the adjacent coil of the transmitting-side coil is shortened. It can be seen from the results that even when Dw is halved, the mutual inductance is 85% of that in the case of a square, and it can be seen that the mutual inductance decreases relatively gently.

[0021] On the other hand, FIG. 13 shows the change in the mutual inductance when the side closest to the adjacent coil is shortened. The mutual inductance decreases linearly as the side becomes shorter, and the mutual inductance when the side is halved is 49% compared to the case of a square.

[0022] From the results, it became clear that the coils are also coupled in the case of a rectangle, and the change in mutual inductance according to the shape was revealed. Since the side closest to the adjacent coil contributes strongly to the coupling, when this side becomes shorter, the mutual inductance decreases linearly. For example, based on the case of a square coil, when keeping the mutual inductance at a value of 90% or more, the side (Dw) orthogonal to the side closest to the adjacent coil needs to be 60% or more in length, and in the case of the side (Dh) closest to the adjacent coil, it needs to be 90% or more in length.

[0023] 7. Relationship between relative angle and coupling coefficient Figure 14 is a diagram showing the simulation results when the relative angle between the coils changes. As shown in Figure 14, it was confirmed by simulation that when the coils are diagonal, as the relative angle decreases, the coupling coefficient increases monotonically. From the results, it was found that although diagonal coils are also coupled, their coupling coefficient changes according to the relative angle. Considering the hysteresis comparator of the receiving circuit here, its input voltage is required to be in a range that is equal to or higher than the threshold value of the comparator and does not exceed the power supply voltage. For example, assuming that the amplitude in the case of a relative angle of 180 degrees with the lowest signal amplitude is 100 mV, the received signal amplitude when the relative angle is 0 degrees is 760 mV. Assuming a process with a core power supply voltage of about 1 V, it can be considered a typical design example if a sufficient amplitude can be ensured that does not exceed the power supply voltage even at the maximum voltage amplitude and is not buried in the noise floor even at the minimum.

[0024] 8. Circuit simulation The performance of the transceiver circuit and the influence on the communication characteristics of the ring-shaped wiring were investigated by circuit simulation. Assuming a 45nm CMOS process as the manufacturing process, the coil diameter was investigated in the range of 100 μm to 5 mm in a square. At this time, the communication distance is set to 1 / 10 of the coil diameter. Figure 15 is a diagram for explaining the coil diameter and the communication distance. For the coil and the ring-shaped wiring parts, a model is created based on the results of electromagnetic field simulation and incorporated into the circuit simulation.

[0025] 9. Simulation Waveforms of Transceiver Core Circuit Figure 16 is a diagram showing an example of simulation waveforms of the transceiver core circuit. When simulating the transfer of a PRBS31 signal under the condition of a coil diameter of 300 μm, a maximum transfer speed of 14.3 Gb / s and a power consumption of 7.91 mW were achieved.

[0026] 10. Relationship between Coil Diameter and Maximum Transfer Speed Figure 17 is a diagram showing the relationship between the coil diameter and the maximum transfer speed. As the coil diameter decreases, the parasitic capacitance decreases, so the maximum transfer speed improves. In the process of this embodiment, since the communication speed is limited by the transceiver circuit, the transfer speed does not improve for coils with a diameter of 300 μm or less, but further performance improvement is expected when using advanced processes. That is, with the progress of process miniaturization, finer granularity of each chiplet, and mounting technology, performance improvement of wireless bus technology can be expected.

[0027] 11. Performance Comparison Figure 18 is a diagram showing a performance comparison between conventional wired communication technology and wireless bus technology. The three on the left are all high-speed communication technologies using silicon interposers. It can be seen that the wireless bus technology can obtain results comparable to those of the wired communication technology using silicon interposers in terms of both data transfer efficiency per unit area of the interface and power efficiency.

[0028] 12. Influence of Ring-shaped Wiring Figure 19 is a diagram showing the influence of ring-shaped wiring. As shown in Figure 19, when there is ring-shaped wiring of the same size as the coil on the chip, eddy currents in the opposite direction may flow through these ring-shaped wirings when the transmission current flows, which may have an adverse effect on the communication characteristics. Examples of such ring-shaped wirings include a power ring for power distribution and a seal ring for chip protection.

[0029] 13. Influence of the power supply ring Figure 20 is a diagram showing the influence of the power supply ring. When there is a power supply ring on the chip, the received signal amplitude decreases due to the influence of eddy currents. This influence can be alleviated to some extent by making the power supply ring thinner and increasing the distance between the coil and the power supply ring. For example, when the thickness of the power supply ring is 20 μm and we want to obtain an amplitude of about 80% of the case without the ring, when the coil diameter is 1 mm, the distance d from the ring needs to be 150 μm or more.

[0030] 14. Influence of the seal ring Figure 21 is a diagram showing the influence of the seal ring. Even when there is a seal ring on the chip, the received signal amplitude decreases due to the influence of eddy currents. This influence can be alleviated to some extent by making the seal ring thinner. For example, to obtain an amplitude of about 50% of the case without the ring, the thickness of the seal ring needs to be 2 μm or less. On the other hand, even if a part of the seal ring is cut, as long as the length of the cut part is short enough, it can function as a seal ring and can prevent moisture penetration and crack propagation without problems. When simulations were performed using a partially cut seal ring, no influence on the received signal amplitude was observed. Therefore, if it is possible in the process, using a segmented seal ring is also considered as an option.

[0031] 15. Prototype substrate Figure 22 is a diagram showing an example of a prototype substrate. To evaluate the wireless bus technology through actual measurement, a prototype substrate was designed, prototyped, and measured. As the receiving circuit, a high-speed hysteresis comparator IC was used to restore the pulse waveform transmitted through the coil to the NRZ waveform.

[0032] 16. Measurement results FIG. 23 is a diagram showing an example of a measured eye pattern and a bathtub curve. When a PRBS7 signal was applied, the maximum transfer speed of 2.6 Gbps was achieved under the condition that the BER was 10-12 or less. At that time, a sufficiently wide timing margin of 0.71 UI was obtained.

[0033] 17. Effects of Embodiment 1 According to Embodiment 1, it is possible to provide an information processing apparatus that can flexibly cope with changes in the mounting shape and shape.

[0034] <Modification 1> 1. Electromagnetic field simulation environment FIG. 24 is a diagram showing an example of an electromagnetic field simulation environment. A simulation model of the coil and the substrate was created based on the parameters of the manufacturing process, and the coupling coefficient between the coils was investigated using Momentum, a 3D planar electromagnetic field simulator manufactured by Keysight.

[0035] 2. Relationship between communication distance and coupling coefficient FIG. 25 is a diagram showing the relationship between the communication distance and the coupling coefficient. As shown in FIG. 25, the coupling coefficient k monotonically decreases as the communication distance X increases. In the case of horizontal inductive coupling, when the coil diameter D is three times the communication distance X, the coupling coefficient is 0.023, which is 1 / 4 or less. Here, considering the case where the coil diameter is 5 mm and the communication distance is 800 μm, the coupling coefficient is 0.042. That is, about 3.6 times the transmission current is required compared to conventional inductive coupling communication.

[0036] 3. Relationship between coil misalignment and coupling coefficient FIG. 26 is a diagram showing the relationship between the coil misalignment and the coupling coefficient. Under the condition that the coil diameter D is 12 times the communication distance X, the change in the coupling coefficient k according to the misalignment dY is shown. Even when the position is misaligned by about 10% of the coil diameter, the coupling coefficient only changes by 3%. For example, when the coil diameter is 5 mm, even if the position of the coil is misaligned by 500 μm, the transmission current only needs to be increased by 3%.

[0037] 4. Coupling Coefficient When Multiple Coils are Arranged FIG. 27 is a diagram showing the coupling coefficient when multiple coils are arranged. As shown in FIG. 27, the coupling coefficient between coils adjacent in the diagonal direction is about 20% of the coupling coefficient between coils adjacent in the vertical, horizontal, left, and right directions.

[0038] 5. Circuit Simulation A simulation of the transceiver core circuit was created and the power consumption etc. was investigated. As the manufacturing process, a 45nm CMOS process was assumed, and the coil diameter was investigated at 5 mm. The communication distance is set to 0.8 mm. FIG. 28 is a diagram for explaining the communication distance.

[0039] 6. Simulation Waveform of Transceiver Core Circuit FIG. 29 is a diagram showing an example of the simulation waveform of the transceiver core circuit. A voltage is generated in the receiving coil in response to the transition of the input transmission data, and is restored to the original data by the receiving circuit.

[0040] 7. Performance of Transceiver Core Circuit FIG. 30 shows the eye pattern and bathtub curve when a 1.0 Gb / s PRBS-31 signal is input. The timing margin of the designed transceiver core circuit at BER = 10 -12 is 0.68 UI, and it was confirmed that it operates while maintaining a sufficient margin. Also, the power consumption of the transceiver core circuit was 11.1 mW when the communication distance was 0.8 mm and 6.41 mW when it was 0.5 mm.

[0041] It may be provided in each of the following aspects. The information processing apparatus, wherein the plurality of chips are horizontally integrated on a base material, and the base material is a deformable member. The information processing apparatus, wherein the deformable member is a flexible substrate. The information processing apparatus, wherein the deformable member is plastic. The information processing apparatus, wherein the deformable member is a fiber. The information processing apparatus, wherein the transmission coil and the reception coil are formed at substantially the same position of each of the plurality of chips. The information processing apparatus, wherein the transmission coil and the reception coil are formed in different layers of the chip. The information processing apparatus, wherein the opening area of the transmission coil and the opening area of the reception coil are 80% or more of the area of the chip. The information processing apparatus, wherein a seal ring is formed on each of the plurality of chips, and a part of the seal ring is disconnected. The information processing apparatus, wherein the thickness of the seal ring is 2 μm or less. The information processing apparatus, wherein a power supply ring is formed on each of the plurality of chips, and when the coil diameters of the transmission coil and the reception coil are approximately 1 mm, the distance between the transmission coil, the reception coil and the power supply ring is 150 μm or more. The information processing apparatus, wherein one of the plurality of chips is a CPU (Central Processing Unit). The information processing apparatus, wherein one of the plurality of chips is a memory. The information processing apparatus, wherein the hardware constituting the information processing apparatus is composed of one or a plurality of chips among the plurality of chips. The information processing apparatus, wherein the hardware is a CPU (Central Processing Unit). Of course, this is not the limit. Also, the above-described embodiments and modified examples may be arbitrarily combined and implemented.

[0042] Finally, although various embodiments of the present invention have been described, these are presented as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. The embodiments and their modifications are included in the scope and gist of the invention and are also included in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0043] 100: Information processing apparatus 110A: Chip 110B: Chip 110C: Chip 110D: Chip 110E: Chip 400: Base material 801: Transmission coil 802: Reception coil

Claims

1. An information processing device, A plurality of chips are included. The plurality of chips are integrated horizontally, Each of the plurality of chips is formed with a pair of a transmitting coil and a receiving coil, Each of the plurality of chips uses horizontal inductive coupling to perform wireless connection between the chips. Information processing device.

2. 2. The information processing device according to claim 1, The plurality of chips are horizontally integrated on a substrate; The substrate is a variable shape member. Information processing device.

3. 3. The information processing device according to claim 2, The variable shape member is a flexible substrate. Information processing device.

4. 3. The information processing device according to claim 2, The variable shape member is plastic. Information processing device.

5. 3. The information processing device according to claim 2, The variable shape member is a fiber. Information processing device.

6. The information processing device according to any one of claims 1 to 5, The transmitting coil and the receiving coil are formed at approximately the same positions on each of the plurality of chips. Information processing device.

7. 7. The information processing device according to claim 6, The transmitter coil and the receiver coil are formed on different layers of the chip. Information processing device.

8. The information processing device according to any one of claims 1 to 7, The area of ​​the opening of the transmitter coil and the area of ​​the opening of the receiver coil are 80% or more of the area of ​​the chip. Information processing device.

9. The information processing device according to any one of claims 1 to 8, A seal ring is formed on each of the plurality of chips, A portion of the seal ring is separated. Information processing device.

10. The information processing device according to claim 9, The thickness of the seal ring is 2 μm or less. Information processing device.

11. The information processing device according to any one of claims 1 to 10, A power supply ring is formed on each of the plurality of chips; When the coil diameter of the transmitting coil and the receiving coil is approximately 1 mm, the distance between the transmitting coil and the receiving coil and the power ring is 150 μm or more. Information processing device.

12. The information processing device according to any one of claims 1 to 11, One of the plurality of chips is a CPU (Central Processing Unit), Information processing device.

13. The information processing device according to any one of claims 1 to 12, one of the plurality of chips is a memory; Information processing device.

14. The information processing device according to any one of claims 1 to 11, The hardware constituting the information processing device is composed of one or more of the plurality of chips. Information processing device.

15. The information processing device according to claim 14, The hardware is a CPU (Central Processing Unit), Information processing device.

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