Printed wiring board

Abstract

To provide a high quality printed wiring board.SOLUTION: A printed wiring board according to an embodiment includes: an uppermost conductor layer having an electrode that mounts an electronic component; a first build-up part disposed below the uppermost conductor layer; and a third build-up part disposed below the first build-up part. The first build-up part includes a plurality of first conductor layers and a plurality of first resin insulating layers, the first conductor layers and the first resin insulating layers being alternately laminated. The third build-up part includes a plurality of third conductor layers and a plurality of third resin insulating layers, the third conductor layers and the third resin insulating layers being alternately laminated. The first conductor layers each are formed of a first seed layer formed by sputtering and a first electrolytic plating layer formed below the first seed layer. The third conductor layers each are formed of a third seed layer formed by electroless plating and a third electrolytic plating layer formed below the third seed layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technology disclosed by this specification relates to printed wiring boards.

Background Art

[0002] Patent Document 1 discloses a method for manufacturing a printed wiring board including forming an opening for via hole formation in an interlayer resin insulating layer and forming an alloy layer by sputtering on the surface of the interlayer insulating layer having the opening for via hole formation.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] [Problems of Patent Document 1] Sputtering is performed in a vacuum. When a printed wiring board including a plurality of conductor layers is formed, it is considered that forming the seed layers of all the conductor layers by sputtering affects productivity. It is considered that the production cost increases.

Means for Solving the Problems

[0005] The printed wiring board of the present invention has a top conductor layer having electrodes for mounting electronic components, a first build-up portion disposed under the top conductor layer, and a third build-up portion disposed under the first build-up portion. The first build-up portion has a plurality of first conductor layers and a plurality of first resin insulating layers, and the first conductor layers and the first resin insulating layers are alternately laminated. The third build-up portion has a plurality of third conductor layers and a plurality of third resin insulating layers, and the third conductor layers and the third resin insulating layers are alternately laminated. The first conductor layer is formed of a first seed layer formed using sputtering and a first electrolytic plating layer formed under the first seed layer. The third conductor layer is formed of a third seed layer formed using electroless plating and a third electrolytic plating layer formed under the third seed layer.

[0006] The printed wiring board according to an embodiment of the present invention has a first conductor layer including a first seed layer formed using sputtering and a third conductor layer including a third seed layer formed using electroless plating. Therefore, the seed layers of all conductor layers are not formed by sputtering. It is difficult for the productivity of the printed wiring board to decrease. The embodiment can suppress the production cost.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0008] [Embodiment] FIG. 1 is a cross-sectional view showing the printed wiring board 2 of the embodiment. FIGS. 2 and 3 are enlarged cross-sectional views showing a part of the printed wiring board 2 of the embodiment. As shown in FIG. 1, the printed wiring board 2 has an upper surface 2a and a lower surface 2b opposite to the upper surface 2a. The upper surface 2a has a first mounting area A1 for mounting the first electronic component E1 and a second mounting area A2 for mounting the second electronic component E2. The first mounting area A1 is located directly below the first electronic component E1. The second mounting area A2 is located directly below the second electronic component E2. Examples of the first electronic component E1 and the second electronic component E2 are electronic components such as logic ICs and memories. Examples of the logic IC are microprocessors, digital signal processors (DSPs), etc.

[0009] The printed wiring board 2 has a third build-up portion 60, a second build-up portion 40, a first build-up portion 20, the uppermost conductor layer 10, a solder resist layer 80, and bumps 90a to 90f. The printed wiring board 2 does not have a core substrate. The printed wiring board 2 is an asymmetric substrate. The first build-up portion 20 is disposed under the uppermost conductor layer 10. The first build-up portion 20 is disposed directly under the uppermost conductor layer 10. The second build-up portion 40 is disposed under the first build-up portion 20. The third build-up portion 60 is disposed under the second build-up portion 40. The solder resist layer 80 is disposed on the uppermost conductor layer 10 and the first build-up portion 20. The bumps 90a to 90f are formed in the openings 82 penetrating the solder resist layer 80 and on the solder resist layer 80. The first electronic component E1 and the second electronic component E2 are mounted on the printed wiring board 2 via the bumps 90a to 90f. In the embodiment, the second build-up portion 40 can be deleted. In that case, the printed wiring board is formed by the third build-up portion 60, the first build-up portion 20 on the third build-up portion 60, the uppermost conductor layer 10 on the first build-up portion 20, the first build-up portion 20, the solder resist layer 80 on the uppermost conductor layer 10, and the bumps 90a to 90f.

[0010] The uppermost conductor layer 10 includes electrodes 12a to 12f for mounting electronic components E1 and E2. Electrodes 12a to 12c are electrically connected to the first electronic component E1. Electrodes 12d to 12f are electrically connected to the second electronic component E2. The uppermost conductor layer 10 is mainly formed of copper. Bumps 90a to 90f are formed on each of the electrodes 12a to 12f. Bumps 90a to 90f are formed by solder or plating. The first electronic component E1 and the second electronic component E2 are mounted on the bumps 90a to 90f. The first electronic component E1 and the second electronic component E2 are mounted on the electrodes 12a to 12f via the bumps 90a to 90f.

[0011] The third build-up portion 60 has a plurality of third conductor layers 62, a plurality of third resin insulating layers 64, and a plurality of third via conductors 70. The third conductor layers 62 and the third resin insulating layers 64 are alternately laminated. The third via conductors 70 are formed in third openings 66 that penetrate each of the third resin insulating layers 64. Adjacent third conductor layers 62 are connected by the third via conductors 70. In FIG. 1, the number of the third conductor layers 62 and the number of the third resin insulating layers 64 are 2. The number of the third conductor layers 62 and the number of the third resin insulating layers 64 may be 3 or more.

[0012] The third conductor layer 62 is mainly formed of copper. The third conductor layer 62 is formed of a third seed layer 160 and a third electrolytic plating layer 162 below the third seed layer 160. The third seed layer 160 is formed by electroless plating. An example of electroless plating is electroless copper plating. The third conductor layer 62 includes an upper third conductor layer 62a and a lower third conductor layer 62b. The upper third conductor layer 62a and the lower third conductor layer 62b sandwich one third resin insulating layer 64. The upper third conductor layer 62a is closer to the uppermost conductor layer 10 than the lower third conductor layer 62b. The upper third conductor layer 62a has a pad 63a. The lower third conductor layer 62b has a pad 63b.

[0013] The third resin insulating layer 64 is formed using a thermosetting resin. An example of the thermosetting resin is an epoxy resin. The third resin insulating layer 64 may contain inorganic particles such as silica. The third resin insulating layer 64 includes an upper third resin insulating layer 64a and a lower third resin insulating layer 64b. The lower third resin insulating layer 64b is the lowermost resin insulating layer. The third resin insulating layer 64 includes a reinforcing material 67 made of fibers. An example of the reinforcing material 67 made of fibers is a glass cloth or the like.

[0014] As shown in FIGS. 1 and 2, the third via conductor 70 is formed in the third opening 66. FIG. 2 is an enlarged view of the portion indicated by II in FIG. 1. The third via conductor 70 includes an upper third via conductor 70a and a lower third via conductor 70b. The lower third via conductor 70b connects the upper third conductor layer 62a and the lower third conductor layer 62b. The upper third via conductor 70a connects the upper third conductor layer 62a and the second conductor layer 42 (lower second conductor layer 42b) in the second build-up portion 40. The third via conductor 70 is formed of a third seed layer 160 and a third electrolytic plating layer 162 below the third seed layer 160. The third seed layer 160 forming the third via conductor 70 and the third seed layer 160 forming the third conductor layer 62 are common. The third seed layer 160 forming the third via conductor 70 and the third seed layer 160 forming the third conductor layer 62 are formed simultaneously. The third electrolytic plating layer 162 forming the third via conductor 70 and the third electrolytic plating layer 162 forming the third conductor layer 62 are common. The third electrolytic plating layer 162 forming the third via conductor 70 and the third electrolytic plating layer 162 forming the third conductor layer 62 are formed simultaneously.

[0015] FIG. 2 shows two third conductor layers 62 within the third build-up portion 60, one third opening 66 that exposes one of the third conductor layers 62 (62a) within the two third conductor layers 62, and one third via conductor 70 (70b) formed within the one third opening 66. The third opening 66 in FIG. 2 penetrates through one third resin insulation layer 64 (64b) and reaches the third conductor layer 62a. FIG. 3 is an enlarged view of a part of FIG. 2. FIG. 3 shows the connection portion CT between the third via conductor 70b and the third conductor layer 62a. Through the connection portion CT, the third conductor layer 62 exposed by the third opening 66 and the third via conductor 70 filling the third opening 66 are connected. In FIGS. 2 and 3, as a representative example of the third via conductor 70, the lower third via conductor 70b is depicted, and as representative examples of the third conductor layer 62, the upper third conductor layer 62a and the lower third conductor layer 62b are depicted. As shown in FIGS. 2 and 3, the third conductor layer 62 and the third via conductor 70 have voids B. The voids B exist in at least one of a first location, a second location, and a third location. The first location is located within a seed layer made of an electroless plating layer. An example of the seed layer made of an electroless plating layer is the third seed layer 160. The second location is the boundary portion between the seed layer made of an electroless plating layer and the electroplating layer. An example of the second location is the boundary portion between the third seed layer 160 and the third electroplating layer 162. The second location can include a second location within the conductor layer and a second location within the via conductor. The second location within the conductor layer is formed at the interface between the electroplating layer forming the conductor layer and the seed layer made of an electroless plating layer forming the conductor layer. The interface between the electroplating layer and the seed layer made of an electroless plating layer within one conductor layer is an example of the second location within the conductor layer. An example of the second location within the conductor layer is the interface between the third electroplating layer 162 forming the third conductor layer 62 and the third seed layer 160 forming the third conductor layer 62. The second location within the via conductor is formed at the interface between the electroplating layer forming the via conductor and the seed layer made of an electroless plating layer forming the via conductor. The interface between the electroplating layer and the seed layer made of an electroless plating layer within one via conductor layer is an example of the second location within the via conductor layer. An example of the second location within the via conductor layer is the interface between the third electroplating layer 162 forming the third via conductor 70 and the third seed layer 160 forming the third via conductor 70.The third location includes a connection portion CT between a via conductor including a seed layer composed of a conductor layer and an electroless plating layer. The connection portion CT is shown in FIGS. 2 and 3. The third location includes an interface between a conductor layer exposed by an opening (an opening for a via conductor) and a via conductor formed in the opening (the opening for the via conductor). The third location includes a boundary portion between a pad included in the conductor layer and a via conductor including a seed layer composed of an electroless plating layer. The third location includes a boundary portion between a pad included in the conductor layer and a seed layer composed of an electroless plating layer forming the via conductor. A boundary portion between a third seed layer 160 forming the third via conductor 70 and a pad 63a is an example of the third location. There is a void B at the first location. In this case, it is preferable that there is no void B at the second and third locations. Alternatively, there is a void B at the second location. In this case, it is preferable that there is no void B at the first and third locations. Alternatively, there is a void B at the third location. In this case, it is preferable that there is no void B at the first and second locations. Alternatively, there are voids B at the first and second locations. In this case, it is preferable that there is no void B at the third location. Alternatively, there are voids B at the first and third locations. In this case, it is preferable that there is no void B at the second location. Alternatively, there are voids B at the second and third locations. In this case, it is preferable that there is no void B at the first location. Alternatively, there are voids B at the first, second, and third locations.

[0016] The upper third conductor layer 62a, the upper third via conductor 70a, the lower third conductor layer 62b, and the lower third via conductor 70b preferably have voids B.

[0017] As shown in FIG. 1, the second build-up portion 40 has a plurality of second conductor layers 42, a plurality of second resin insulating layers 44, and a plurality of second via conductors 50. The second conductor layers 42 and the second resin insulating layers 44 are alternately laminated. The second via conductors 50 are formed in second openings 46 penetrating each second resin insulating layer 44. Adjacent second conductor layers 42 are connected by the second via conductors 50. In FIG. 1, the number of the second conductor layers 42 and the number of the second resin insulating layers 44 are 2. The number of the second conductor layers 42 and the number of the second resin insulating layers 44 may be 3 or more.

[0018] The second conductor layer 42 is mainly formed of copper. The second conductor layer 42 is formed by the second seed layer 140 and the second electrolytic plating layer 142 under the second seed layer 140. The second seed layer 140 is formed using electroless plating. The second conductor layer 42 includes an upper second conductor layer 42a and a lower second conductor layer 42b. The upper second conductor layer 42a has a pad 43a. The lower second conductor layer 42b has a pad 43b. The lower second conductor layer 42b can also serve as the lowermost second conductor layer within the second build-up portion 40.

[0019] The second resin insulating layer 44 is formed using a thermosetting resin. An example of the thermosetting resin is an epoxy resin. The second resin insulating layer 44 may contain inorganic particles such as silica. The second resin insulating layer 44 includes an upper second resin insulating layer 44a and a lower second resin insulating layer 44b. The second resin insulating layer 44 does not contain a reinforcing material made of fibers. The lower second resin insulating layer 44b can also serve as the lowermost second resin insulating layer within the second build-up portion 40.

[0020] The second via conductor 50 is formed within the second opening 46. The second via conductor 50 includes an upper second via conductor 50a and a lower second via conductor 50b. The lower second via conductor 50b connects the upper second conductor layer 42a and the lower second conductor layer 42b. The upper second via conductor 50a connects the upper second conductor layer 42a and the first conductor layer 22 (lower first conductor layer 22b) within the first build-up portion 20. The second via conductor 50 is formed by the second seed layer 140 and the second electrolytic plating layer 142 under the second seed layer 140. The second seed layer 140 for forming the second via conductor 50 and the second seed layer 140 for forming the second conductor layer 42 are common. The second seed layer 140 for forming the second via conductor 50 and the second seed layer 140 for forming the second conductor layer 42 are formed simultaneously. The second electrolytic plating layer 142 for forming the second via conductor 50 and the second electrolytic plating layer 142 for forming the second conductor layer 42 are common. The second electrolytic plating layer 142 for forming the second via conductor 50 and the second electrolytic plating layer 142 for forming the second conductor layer 42 are formed simultaneously.

[0021] The second conductor layer 42 has voids B similar to those in the third conductor layer 62. The second conductor layer 42 has voids B at the same locations as the third conductor layer 62. The second via conductor 50 has voids B similar to those in the third via conductor 70. The second via conductor 50 has voids B at the same locations as the third via conductor 70.

[0022] The first build-up portion 20 has a plurality of first conductor layers 22, a plurality of first resin insulating layers 24, and a plurality of first via conductors 30. The first conductor layers 22 and the first resin insulating layers 24 are alternately laminated. The first via conductors 30 are formed in first openings 26 that penetrate each of the first resin insulating layers 24. Adjacent first conductor layers 22 are connected by the first via conductors 30. In FIG. 1, the number of the first conductor layers 22 and the number of the first resin insulating layers 24 are two. The number of the first conductor layers 22 and the number of the first resin insulating layers 24 may be three or more.

[0023] The first conductor layer 22 is mainly formed of copper. The first conductor layer 22 is formed of a first seed layer 120 and a first electrolytic plating layer 122 under the first seed layer 120. The first seed layer 120 is formed using sputtering. The first conductor layer 22 includes an upper first conductor layer 22a and a lower first conductor layer 22b. The upper first conductor layer 22a has pads 23a and connection wirings 25a. The lower first conductor layer 22b has pads 23b and connection wirings 25b.

[0024] The first resin insulating layer 24 is formed using a thermosetting resin. An example of the thermosetting resin is an epoxy resin. The first resin insulating layer 24 may contain inorganic particles such as silica. The first resin insulating layer 24 includes an upper first resin insulating layer 24a and a lower first resin insulating layer 24b. The upper first resin insulating layer 24a is the uppermost resin insulating layer that contacts the uppermost conductor layer 10. The first resin insulating layer 24 does not contain a reinforcing material made of fibers.

[0025] The first via conductor 30 is formed in the first opening 26. The first via conductor 30 includes an upper first via conductor 30a and a lower first via conductor 30b. The lower first via conductor 30b connects the upper first conductor layer 22a and the lower first conductor layer 22b. The upper first via conductor 30a connects the upper first conductor layer 22a and the electrodes 12a - 12f in the uppermost conductor layer 10. The first via conductor 30 is formed of a first seed layer 120 and a first electroless plating layer 122 below the first seed layer 120. The first seed layer 120 for forming the first via conductor 30 and the first seed layer 120 for forming the conductor layer 22 are common. The first seed layer 120 for forming the first via conductor 30 and the first seed layer 120 for forming the conductor layer 22 are formed simultaneously. The first electroless plating layer 122 for forming the first via conductor 30 and the first electroless plating layer 122 for forming the conductor layer 22 are common. The first electroless plating layer 122 for forming the first via conductor 30 and the first electroless plating layer 122 for forming the conductor layer 22 are formed simultaneously.

[0026] The first conductor layer 22 and the first via conductor 30 have no voids. The first conductor layer 22 is formed of a first seed layer 120 and a first electrolytic plating layer 122 under the first seed layer 120. The first seed layer 120 is formed by sputtering, and the first electrolytic plating layer 122 is formed by electrolytic plating. There are no voids at the boundary between the first seed layer (the first layer) 120 forming the first conductor layer 22 and the first electrolytic plating layer (the second layer) 122 forming the first conductor layer 22. The first layer and the second layer are in contact. There are no voids in the first seed layer 120 formed by sputtering. There are no voids at the boundary between the first via conductor 30 and the pad 23a. There are no voids at the boundary between the first seed layer 120 forming the first via conductor 30 and the pad 23a. The pad 23a is one of the conductor circuits forming the first conductor layer 22. The first opening 26 penetrates the first resin insulating layer 24 and reaches the pad 23a. There are no voids at the boundary between the first seed layer 120 forming the first via conductor 30 and the uppermost conductor layer 10. There are no voids at the boundary between the first seed layer 120 forming the first via conductor 30 and the electrodes 12a - 12f. The first opening 26 penetrates the uppermost resin insulating layer 24a and reaches the uppermost conductor layer 10 including the electrodes 12a - 12f. The first via conductor 30 fills the first opening 26. There are no voids at the boundary between the first seed layer (the third layer) 120 forming the first via conductor 30 and the first electrolytic plating layer (the fourth layer) 122 forming the first via conductor 30. The third layer and the fourth layer are in contact.

[0027] The first build-up portion 20 has a plurality of first conductor layers 22. Among the plurality of first conductor layers 22, some of the first conductor layers 22 have connection wirings 25a, 25b. Among the plurality of first conductor layers 22, more than half of the first conductor layers 22 can have connection wirings 25a, 25b. For example, the number of the first conductor layers 22 having the connection wirings 25a, 25b is 3 or more and 7 or less. As shown in FIG. 1, all the first conductor layers 22 may have the connection wirings 25a, 25b. Data is transmitted from the first electronic component E1 to the second electronic component E2 via the connection wirings 25a, 25b. The connection wirings 25a, 25b are part of a path for sending data from the first electronic component E1 to the second electronic component E2. The path includes first via conductors 30 in addition to the connection wirings 25a, 25b. Since the connection wirings 25a, 25b and the first via conductors 30 forming the path do not include voids B, the path can transmit high-speed data. Also, when data is transmitted via the path, the printed wiring board 2 of the embodiment can reduce transmission loss.

[0028] In the embodiment, the first seed layer 120 of the first conductor layer 22 having the connection wirings 25a, 25b is formed using sputtering. The second seed layer 140 of the second conductor layer 42 having no connection wiring is formed using electroless plating. The third seed layer 160 of the third conductor layer 62 having no connection wiring is formed using electroless plating.

[0029] The first build-up portion 20 has a resin insulating layer that does not include a reinforcing material made of fiber and includes connection wirings with a seed layer formed by sputtering. The second build-up portion 40 has a resin insulating layer that does not include a reinforcing material made of fiber and includes a conductor layer with a seed layer formed by electroless plating. The second build-up portion 40 has no connection wiring. The third build-up portion 60 has a resin insulating layer that includes a reinforcing material made of fiber and includes a conductor layer with a seed layer formed by electroless plating. The third build-up portion 60 has no connection wiring.

[0030] The thickness of the third resin insulating layer 64 is greater than the thickness of the second resin insulating layer 44. The thickness of the second resin insulating layer 44 is greater than the thickness of the first resin insulating layer 24. The thickness of the third resin insulating layer 64 is, for example, 90 μm or more and 110 μm or less. The thickness of the second resin insulating layer 44 is, for example, 20 μm or more and 25 μm or less. The thickness of the first resin insulating layer 24 is, for example, 8 μm or more and 12 μm or less. The thickness of the third resin insulating layer 64 substantially coincides with the distance between the third conductor layers 62 sandwiching one third resin insulating layer 64. The thickness of the second resin insulating layer 44 substantially coincides with the distance between the second conductor layers 42 sandwiching one second resin insulating layer 44. The thickness of the first resin insulating layer 24 substantially coincides with the distance between the first conductor layers 22 sandwiching one first resin insulating layer 24.

[0031] The thickness of the third conductor layer 62 is greater than the thickness of the second conductor layer 42. The thickness of the second conductor layer 42 is greater than the thickness of the first conductor layer 22. The thickness of the third conductor layer 62 is, for example, 10 μm or more and 30 μm or less. The thickness of the second conductor layer 42 is, for example, 13 μm or more and 17 μm or less. The thickness of the first conductor layer 22 is, for example, 3 μm or more and 7 μm or less. The thickness of the third conductor layer 62 is measured using the third conductor layer 62 sandwiched by the third resin insulating layer 64. The thickness of the second conductor layer 42 is measured using the second conductor layer 42 sandwiched by the second resin insulating layer 44. The thickness of the first conductor layer 22 is measured using the first conductor layer 22 sandwiched by the first resin insulating layer 24.

[0032] The thickness of the printed wiring board 2 is 0.5 mm or more and 0.7 mm or less. The length of the short side of the printed wiring board 2 is 70 mm or more, and the length of the long side is 250 mm or less.

[0033] The seed layer for forming the conductor layer having the connection wiring is formed using sputtering. The seed layer for forming the conductor layer without the connection wiring is formed using electroless plating. The seed layer of the conductor layer having the connection wiring is a sputtering-made seed layer, and the seed layer of the conductor layer without the connection wiring is an electroless plating-made seed layer. An example of the seed layer (electroless plating-made seed layer) formed using electroless plating is a seed layer made of electroless copper plating.

[0034] For example, the seed layer in contact with the resin insulation layer without a reinforcing material made of fiber is formed using sputtering. The seed layer formed using sputtering (sputtering-made seed layer) preferably contains copper and aluminum. The sputtering-made seed layer may contain copper, aluminum, and silicon. For example, the seed layer in contact with the resin insulation layer having a reinforcing material made of fiber is formed using electroless plating. An example of electroless plating is electroless copper plating. For example, the seed layer in contact with the resin insulation layer without a reinforcing material made of fiber is a sputtering-made seed layer, and the seed layer in contact with the resin insulation layer having a reinforcing material made of fiber is an electroless plating-made seed layer.

[0035] It is preferable that voids exist in the electroless plating-made seed layer. The conductor layer (electroless plating-made conductor layer) including the electroless plating-made seed layer preferably has voids at the boundary between the electroless plating-made seed layer forming the electroless plating-made conductor layer and the electrolytic plating layer forming the electroless plating-made conductor layer. The via conductor (electroless plating-made via conductor) including the electroless plating-made seed layer preferably has voids at the boundary between the electroless plating-made seed layer forming the electroless plating-made via conductor and the electrolytic plating layer forming the electroless plating-made via conductor. It is preferable that voids exist at the boundary between the electroless plating-made seed layer of the electroless plating-made via conductor and the pad. As shown in FIG. 4, the boundary between the electroless plating-made seed layer 302 and the electrolytic plating layer 304 in the electroless plating-made conductor layer 300 is the first boundary portion 501. The boundary between the electroless plating-made seed layer 302 and the electrolytic plating layer 304 in the electroless plating-made via conductor 310 is the first boundary portion 501. The boundary between the electroless plating-made seed layer 302 of the electroless plating-made via conductor 310 and the pad 320 is the second boundary portion 502.

[0036] The first boundary portion 501 is included in the second location. The first boundary portion 501 can include the second location within the conductor layer and the second location within the via conductor. An example of the second location within the conductor layer is the second location within the third conductor layer. An example of the second location within the via conductor is the second location within the third via conductor. The conductor layer having the second location within the conductor layer includes an electroless plating seed layer. The via conductor having the second location within the via conductor includes an electroless plating seed layer. The second boundary portion 502 is included in the third location. The via conductor forming the second boundary portion 502 includes an electroless plating seed layer.

[0037] It is preferable that there are no voids in the sputtering seed layer. The conductor layer including the sputtering seed layer (sputtering conductor layer) preferably has no voids at the boundary portion between the sputtering seed layer forming the sputtering conductor layer and the electroplating layer forming the sputtering conductor layer. The via conductor including the sputtering seed layer (sputtering via conductor) preferably has no voids at the boundary portion between the sputtering seed layer forming the sputtering via conductor and the electroplating layer forming the sputtering via conductor. It is preferable that there are no voids at the boundary portion between the sputtering seed of the sputtering via conductor and the pad. It is preferable that there are no voids at the boundary portion between the sputtering seed of the sputtering via conductor and the electrode. As shown in FIG. 5, the boundary portion between the sputtering seed layer 402 and the electroplating layer 404 in the sputtering conductor layer 400 is the third boundary portion 503. The boundary portion between the sputtering seed layer 402 and the electroplating layer 404 in the sputtering via conductor 410 is the third boundary portion 503. The boundary portion between the sputtering seed layer 402 of the sputtering via conductor 410 and the pad 420 is the fourth boundary portion 504. The boundary portion between the sputtering seed layer 402 of the sputtering via conductor 410 and the electrodes 12a to 12f is the fourth boundary portion 504.

[0038] The printed wiring board 2 of the embodiment is formed of a lowermost build-up portion having a lowermost conductor layer, an uppermost build-up portion formed on the lowermost build-up portion, and an uppermost conductor layer formed on the uppermost build-up portion. The conductor layer forming the lowermost build-up portion includes an electroless plating seed layer and does not include connection wirings. The conductor layer forming the uppermost build-up portion includes a sputtering seed layer and includes connection wirings. The resin insulating layer forming the lowermost build-up portion includes a reinforcing material made of fibers, and the resin insulating layer forming the uppermost build-up portion does not include a reinforcing material made of fibers. An example of the uppermost build-up portion is the first build-up portion 20, and an example of the lowermost build-up portion is the third build-up portion 60.

[0039] [Method for manufacturing the printed wiring board 2 of the embodiment] The uppermost conductor layer 10 is formed on the support plate. A first build-up portion 20 is formed on the support plate and the uppermost conductor layer 10. The first seed layer 120 of the first conductor layer 22 is formed using sputtering. The first conductor layer 22 and the first via conductor 30 have no voids. A second build-up portion 40 is formed on the first build-up portion 20. The second seed layer 140 of the second conductor layer 42 is formed using electroless plating. When the second seed layer 140 is formed by electroless plating, for example, gas (e.g., hydrogen gas) generated during the electroless plating process is taken into the substrate in the middle. After the formation of the second seed layer 140, heat is applied to the substrate in the middle. By adjusting the heating conditions, a void B is formed in at least one of a first location, a second location, and a third location in the second build-up portion 40. A third build-up portion 60 is formed on the second build-up portion 40. The third seed layer 160 of the third conductor layer 62 is formed using electroless plating. The third seed layer 160 is formed in the same manner as the second seed layer 140. A void B is formed in at least one of a first location, a second location, and a third location in the third build-up portion 60. The support plate is removed. The uppermost resin insulating layer 24a belongs to the first resin insulating layer 24 and is located directly below the uppermost conductor layer 10. The uppermost resin insulating layer 24a is in contact with the uppermost conductor layer 10. The substrate in the middle is arranged such that the uppermost conductor layer 10 and the uppermost resin insulating layer 24a face upward. A solder resist layer 80 and bumps 90a to 90f are formed on the uppermost conductor layer 10 and the uppermost resin insulating layer 24a. A printed wiring board 2 is obtained. An example of electroplating is electrocopper plating, and an example of an electroplated layer is an electrocopper plating layer. An example of electroless plating is electroless copper plating.

[0040] In the embodiment, the seed layers of all the conductor layers are not formed by sputtering. Therefore, even if the production process includes sputtering, the embodiment can improve productivity. The embodiment can suppress production costs.

[0041] The principle of electroless plating is different from that of sputtering. Therefore, it is difficult to make the adhesion force (the first adhesion force) between the electroless plating-made seed layer and the electroplating layer on the electroless plating layer-made seed the same as the adhesion force (the second adhesion force) between the sputtering-made seed layer and the electroplating layer on the sputtering-made seed layer. It is difficult to make the adhesion force (the third adhesion force) between the pad and the electroless plating-made seed layer on the pad the same as the adhesion force (the fourth adhesion force) between the pad and the sputtering-made seed layer on the pad. When a printed wiring board is used, the printed wiring board is subjected to stress many times. If the second adhesion force is lower than the first adhesion force, stress is likely to concentrate at the boundary between the sputtering-made seed layer and the electroplating layer. Or, stress is likely to concentrate on the sputtering-made seed layer. If the fourth adhesion force is lower than the third adhesion force, stress is likely to concentrate at the boundary between the pad and the sputtering-made seed layer. Stress is likely to concentrate at the boundary between the electrode and the sputtering-made seed layer. Therefore, due to stress, the following problems are likely to occur. For example, peeling occurs between the sputtering-made seed layer and the electroplating layer. Or, peeling occurs between the pad and the sputtering-made seed layer. Or, the connection resistance between via conductors including the pad and the sputtering-made seed layer increases. Or, the connection resistance between via conductors including the electrode and the sputtering-made seed layer increases. Or, cracks occur in the sputtering-made seed layer.

[0042] The electroless plating seed layer is formed in a liquid. Therefore, even if the surface to be plated has irregularities, the electroless plating seed layer easily follows the irregularities. Also, even if the surface to be plated has a large recess, the electroless plating layer is easily formed within the large recess. On the other hand, in sputtering, particles fly out from the target. And those particles tend to travel straight. Therefore, if the surface to be sputtered has irregularities, it is considered that the thickness variation of the sputtered seed layer is large. Also, if the surface to be sputtered has a large recess, it is difficult for the sputtered seed layer to grow on the wall or bottom of the large recess. The sputtered seed layer is formed on the surface to be sputtered. However, in the embodiment, the conductor layer including the seed layer (for example, the third seed layer 160) formed by electroless plating has a void B at at least one of the first location and the second location. The via conductor including the seed layer formed by electroless plating has a void B at at least one of the first location, the second location, and the third location. On the other hand, the conductor layer including the sputtered seed layer (for example, the first seed layer 120) does not have a void B at either the first location or the second location. The via conductor including the sputtered seed layer does not have a void B at any of the first location, the second location, and the third location. Therefore, substantially equal stress is likely to act on the first boundary portion 501 and the third boundary portion 503. Substantially equal stress is likely to act on the second boundary portion 502 and the fourth boundary portion 504. Substantially equal stress is likely to act on the first boundary portion 501, the second boundary portion 502, the third boundary portion 503, and the fourth boundary portion 504. Even if the printed wiring board 2 of the embodiment is repeatedly stressed, peeling is unlikely to occur between the seed layer and the electrolytic plating layer. Peeling is unlikely to occur between the pad and the via conductor. Peeling is unlikely to occur between the electrode and the via conductor. Cracks are unlikely to occur in the seed layer. The connection resistance between the pad and the via conductor is stable for a long time. The connection resistance between the electrode and the via conductor is stable for a long time. A printed wiring board 2 having high connection reliability is provided.

[0043] The resin insulation layer 64 that forms the third build-up portion 60 has a reinforcing material 67 made of fibers, and the resin insulation layer 24 that forms the first build-up portion 20 does not have a reinforcing material 67 made of fibers. The printed wiring board 2 of the embodiment is an asymmetric wiring board. Therefore, the printed wiring board 2 of the embodiment is likely to have a large warp. Electronic components E1 and E2 are mounted on the first build-up portion 20. When the electronic components E1 and E2 are mounted on the first build-up portion 20, a semiconductor device is formed by the printed wiring board 2 of the embodiment and the electronic components E1 and E2. When the semiconductor device undergoes a heat cycle, the third build-up portion 60 is more likely to have a larger warp than the first build-up portion 20. Since the third build-up portion 60 is farther from the electronic components E1 and E2 than the first build-up portion 20, it is considered that the third build-up portion 60 is likely to have a large warp. However, at least one of the conductor layer (third conductor layer) 62 and the via conductor (third via conductor) 70 in the third build-up portion 60 has a void B at at least one of a first location, a second location, and a third location. The stress is relaxed by the void B. Therefore, even when the semiconductor device undergoes a heat cycle, the embodiment can provide a printed wiring board 2 having high connection reliability. If the conductor layer (first conductor layer) 22 and the via conductor (first via conductor) 30 in the first build-up portion 20 have a void B, since the first build-up portion 20 is close to the electronic components E1 and E2, the void B in the first build-up portion 20 expands due to the heat generated by the electronic components E1 and E2. In that case, the connection reliability through the wiring in the first build-up portion 20 decreases. The wiring in the first build-up portion 20 includes the first conductor layer 22 and the first via conductor 30. Since the conductor layer 22 and the via conductor 30 in the first build-up portion 20 that forms the printed wiring board 2 of the embodiment do not have a void B, such a problem is unlikely to occur.

[0044] [Another Example 1 of the Embodiment] In Another Example 1, the second conductor layer 42 and the second via conductor 50 do not contain voids. The second seed layer 140 is formed using sputtering. There are no voids B at the boundary between the second seed layer 140 formed by sputtering and the second electrolytic plating layer 142 formed by electrolytic plating. The second conductor layer 42 is formed by the second seed layer 140 formed by sputtering and the second electrolytic plating layer 142 formed by electrolytic plating. The second via conductor 50 is formed by the second seed layer 140 formed by sputtering and the second electrolytic plating layer 142 formed by electrolytic plating. There are no voids in the second seed layer 140 formed by sputtering. There are no voids at the boundary between the second via conductor 50b and the pad 43a.

[0045] Top and bottom are used based on FIG. 1. The conductor layers formed by the seed layer and the electrolytic plating layer on the seed layer, the seed layer, and the conductor layer formed by the electrolytic plating layer under the seed layer are similar conductor layers. The via conductors formed by the seed layer and the electrolytic plating layer on the seed layer, the seed layer, and the via conductor formed by the electrolytic plating layer under the seed layer are similar via conductors.

Description of Reference Numerals

[0046] 2: Printed Wiring Board 10: Top Conductor Layer 12a~12f: Electrodes 20: First Build-Up Portion 22: First Conductor Layer 24: First Resin Insulating Layer 40: Second Build-Up Portion 42: Second Conductor Layer 44: Second Resin Insulating Layer 60: Third Build-Up Portion 62: Third Conductor Layer 64: Third Resin Insulating Layer 67: Reinforcing Material 70: Third Via Conductor 90a~90f: Bumps 120: First Seed Layer 122: First Electrolytic Plating Layer 140: Second Seed Layer 142: Second Electrolytic Plating Layer 160: Third seed layer 162: Third electrolytic plating layer B: Void E1: First electronic component E2: Second electronic component

Claims

1. a top conductor layer having electrodes for mounting electronic components, a first build-up portion disposed under the top conductor layer, a third build-up portion disposed under the first build-up portion, wherein the first build-up portion has a plurality of first conductor layers and a plurality of first resin insulating layers, and the first conductor layers and the first resin insulating layers are alternately laminated, wherein the third build-up portion has a plurality of third conductor layers and a plurality of third resin insulating layers, and the third conductor layers and the third resin insulating layers are alternately laminated, wherein the first conductor layer is formed of a first seed layer formed using sputtering and a first electrolytic plating layer formed under the first seed layer, wherein the third conductor layer is formed of a third seed layer formed using electroless plating and a third electrolytic plating layer formed under the third seed layer.

2. The printed wiring board according to claim 1, wherein the third conductor layer has voids in the third seed layer (first location) or at a boundary portion between the third seed layer and the third electrolytic plating layer (second location), and the first conductor layer has no voids in the first seed layer and at a boundary portion between the first seed layer and the first electrolytic plating layer.

3. The printed wiring board according to claim 2, wherein the voids are present in both the first location and the second location.

4. The printed wiring board according to claim 1, wherein the third conductor layer includes an upper third conductor layer and a lower third conductor layer sandwiching one of the third resin insulating layers, and the third build-up portion has an opening penetrating the third resin insulating layer sandwiched between the upper third conductor layer and the lower third conductor layer and reaching a pad included in the upper third conductor layer, and a third via conductor formed in the opening and connecting the pad and the lower third conductor layer, and the third via conductor is formed of the third seed layer and the third electrolytic plating layer connected to the pad, and a connection portion between the pad and the third via conductor has voids, and the voids are present in the third seed layer (first location), or at a boundary portion between the third seed layer and the third electrolytic plating layer (second location), or at a boundary portion between the third seed layer and the pad (third location), and the first conductor layer has no voids in the first seed layer and at a boundary portion between the first seed layer and the first electrolytic plating layer.

5. The printed wiring board according to claim 4, wherein the void is present in both the second location and the third location, or in all of the first location, the second location, and the third location.

6. The printed wiring board according to claim 1, further comprising a second build-up portion disposed between the first build-up portion and the third build-up portion, the second build-up portion having a plurality of second conductor layers and a plurality of second resin insulating layers, the second conductor layers and the second resin insulating layers being alternately laminated, the second conductor layer being formed of a second seed layer formed using electroless plating and a second electrolytic plating layer formed under the second seed layer, the second conductor layer having voids in the second seed layer or at a boundary portion between the second seed layer and the second electrolytic plating layer.

7. The printed wiring board according to claim 1, wherein the third resin insulating layer contains a reinforcing material, and the first resin insulating layer does not contain the reinforcing material.

8. The printed wiring board according to claim 1, wherein the thickness of the third resin insulating layer is greater than the thickness of the first resin insulating layer, and the thickness of the third conductor layer is greater than the thickness of the first conductor layer.

9. The printed wiring board according to claim 1, wherein the first resin insulating layer includes the uppermost resin insulating layer in contact with the uppermost conductor layer, and the third resin insulating layer includes the lowermost resin insulating layer.

10. The printed wiring board according to claim 1, further comprising bumps formed on the electrodes.

11. The printed wiring board according to claim 10, wherein the bumps are formed of solder or plating.

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