Memory system and semiconductor memory

Abstract

To provide a satisfactorily operable memory system.SOLUTION: A memory system comprises plural memory chips. Each of the plural memory chips comprises: a memory array; a first pad electrode to which write data are inputted and which outputs read data; a second pad electrode to which a timing signal is inputted and which outputs the timing signal; a phase adjustment circuit which adjusts a phase of the timing signal inputted from the second pad electrode; and a control circuit which is connected to the phase adjustment circuit. The control circuit of a first memory chip executes the output of the read data in accordance with the input of a first command set and the input of a second command set, the control circuit of a second memory chip inputs the read data output from the first memory chip in parallel with the output of the read data to the second memory chip, and one or both of the phase adjustment circuit of the first memory chip and the phase adjustment circuit of the second memory chip adjust a phase of a signal of the read data or the timing signal.SELECTED DRAWING: Figure 18

Description

Technical Field

[0001] This embodiment relates to a memory system and a semiconductor memory device.

Background Art

[0002] A memory system having a plurality of memory chips is known. Each memory chip includes a memory cell array.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a memory system that can operate preferably.

Means for Solving the Problems

[0005] A memory system according to an embodiment includes a plurality of memory chips. Each of the plurality of memory chips includes a memory cell array, a first pad electrode that receives write data written to the memory cell array and outputs read data read from the memory cell array, a second pad electrode that receives a first timing signal when the write data is input and outputs the first timing signal when the read data is output, a phase adjustment circuit that adjusts the phase of the first timing signal input from the second pad electrode, and a control circuit connected to the phase adjustment circuit. In response to an input of a first command set for instructing output of read data to a first memory chip among the plurality of memory chips and an input of a second command set for instructing input of write data to a second memory chip among the plurality of memory chips, the control circuit of the first memory chip executes output of the read data from the first memory chip. Also, the control circuit of the second memory chip executes input of write data that inputs the read data output from the first memory chip as write data to the second memory chip in parallel with the output of the read data from the first memory chip. Further, one or both of the phase adjustment circuit of the first memory chip and the phase adjustment circuit of the second memory chip adjust the phase of the read data signal or the first timing signal.

Brief Description of the Drawings

[0006]

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Mode for Carrying Out the Invention

[0007] Hereinafter, a memory system and a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. For convenience of explanation, some configurations may be omitted. Also, the same reference numerals are given to common parts in a plurality of embodiments, and the description may be omitted.

[0008] Also, when the term "memory system" is used in this specification, it means a system including a plurality of memory dies (memory chips) and a controller die. The memory system may mean, for example, a memory card, an SSD (Solid State Drive), etc., or may mean a configuration including a host computer such as a smartphone, a tablet terminal, or a personal computer.

[0009] Also, in this specification, when referring to a "semiconductor memory device", it may mean a memory die (memory chip), or it may mean a memory system including a controller die such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may also mean a configuration including a host computer such as a smartphone, a tablet terminal, or a personal computer.

[0010] Also, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, or the like. For example, when three transistors are connected in series, even if the second transistor is in an OFF state, the first transistor is "electrically connected" to the third transistor.

[0011] Also, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and the second configuration is connected to the third configuration via the first configuration.

[0012] Also, in this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0013] [First Embodiment] [Memory System 10] FIG. 1 is a schematic block diagram showing the configuration of a memory system 10 according to the first embodiment.

[0014] Memory system 10 reads, writes, erases, etc. user data in response to signals transmitted from host computer 20. Memory system 10 is, for example, a memory card, SSD, or other system capable of storing user data. Memory system 10 includes a plurality of packages PKG and a controller die CD connected to these plurality of packages PKG and host computer 20. Each package PKG includes a plurality of memory dies MD. Each memory die MD is capable of storing user data. Controller die CD includes, for example, a processor, RAM, etc., and performs processes such as conversion between logical addresses and physical addresses, bit error detection / correction, garbage collection (compaction), wear leveling, etc.

[0015] FIG. 2 and FIG. 3 are diagrams showing a configuration example of package PKG included in memory system 10 according to the present embodiment. More specifically, FIG. 2 is a schematic side view showing a configuration example of package PKG, and FIG. 3 is a schematic plan view showing a configuration example of package PKG. Also, FIG. 4 is a schematic side view showing a configuration example of memory system 10. For convenience of explanation, some configurations are omitted in FIGS. 2 to 4.

[0016] As shown in FIG. 2, the package PKG according to this embodiment includes a memory die mounting substrate MSB and a plurality of memory dies MD stacked on the memory die mounting substrate MSB. Among the upper surface of the memory die mounting substrate MSB, pad electrodes P are provided in the regions at the ends in the Y direction, and some other regions are adhered to the lower surface of the memory die MD via an adhesive or the like. Among the upper surface of the memory die MD, pad electrodes P are provided in the regions at the ends in the Y direction, and the other regions are adhered to the lower surface of another memory die MD via an adhesive or the like. The corresponding pad electrodes P among the plurality of memory dies MD are commonly connected by bonding wires B. Electrode terminals T are provided on the lower surface of the memory die mounting substrate MSB. The pad electrodes P on the upper surface of the memory die mounting substrate MSB are respectively connected to the electrode terminals T on the lower surface. The memory die mounting substrate MSB may be, for example, a grid array substrate. On the upper surface of the memory die mounting substrate MSB, the plurality of memory dies MD and the bonding wires B are covered with, for example, a sealing resin (not shown).

[0017] Also, as shown in FIG. 3, the memory die mounting substrate MSB and the plurality of memory dies MD each include a plurality of pad electrodes P arranged in the X direction. The plurality of pad electrodes P of each memory die MD respectively correspond to the control terminals / CE, CA1(CLE), CA0(ALE), CA_clk( / WE), / RE, RE, / WP, the data signal input / output terminals DQ0~DQ7, the data strobe signal input / output terminals DQS, / DQS, and the terminal RY / / BY, which will be described later with reference to FIG. 5 and the like.

[0018] The plurality of pad electrodes P provided on the memory die mounting substrate MSB and the plurality of memory dies MD are respectively connected to each other via bonding wires B. For example, the pad electrodes P corresponding to the control terminal CA1(CLE) among the plurality of memory dies MD are connected to each other, and the pad electrodes P corresponding to the control terminal CA0(ALE) are connected to each other. The same applies to the other terminals. Also, the pad electrodes P of each memory die MD inside the package PKG are connected to the outside of the package PKG via the electrode terminals T on the lower surface of the memory die mounting substrate MSB.

[0019] In the example of FIG. 4, the memory system 10 includes a system implementation substrate SSB, a plurality of packages PKG arranged on the system implementation substrate SSB, and a controller die CD. On the upper surface of the system implementation substrate SSB, the controller die CD and some of the packages PKG are arranged. On the lower surface of the system implementation substrate SSB, the other packages PKG are arranged.

[0020] The controller die CD is provided with a plurality of pad electrodes P. The pad electrodes P of the controller die CD are connected to the system implementation substrate SSB via bonding wires B. The electrode terminals T of the plurality of packages PKG are connected to the system implementation substrate SSB via solder balls SB. The pad electrodes P of the controller die CD and the electrode terminals T of the plurality of packages PKG are connected by wirings (not shown) formed on the upper surface and the lower surface of the system implementation substrate SSB. The upper surface and the lower surface of the system implementation substrate SSB are connected by through electrodes TV.

[0021] A part of the electrode terminals T of the packages PKG arranged on the upper surface of the system implementation substrate SSB and a part of the electrode terminals T of the packages PKG arranged on the lower surface of the system implementation substrate SSB may be connected by through electrodes TV. More specifically, the electrode terminals T corresponding to the data signal input / output terminals DQ0 to DQ7 in the packages PKG arranged on the upper surface of the system implementation substrate SSB and the electrode terminals T corresponding to the data signal input / output terminals DQ0 to DQ7 in the packages PKG arranged on the lower surface of the system implementation substrate SSB may be respectively connected via through electrodes TV.

[0022] When packages PKG have the same configuration, for example, the electrode terminal T corresponding to the data signal input / output terminal DQ0 in one package PKG is connected to the electrode terminal T corresponding to the data signal input / output terminal DQ7 in the other package PKG (Figure 4). Here, one package PKG is called the forward connection package PKGa, and the other package PKG is called the reverse connection package PKGb. The electrode terminals T corresponding to the data signal input / output terminals DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7 in the forward connection package PKGa are respectively connected to the electrode terminals T corresponding to the data signal input / output terminals DQ6, DQ5, DQ4, DQ3, DQ2, DQ1, DQ0 in the reverse connection package PKGb. Such a connection method is called mirror connection.

[0023] In addition, the electrode terminals T corresponding to other control terminals are individually connected to the pad electrodes P of the controller die CD. For example, the electrode terminal T corresponding to the control terminal CA1 (CLE) in one package PKG (forward connection package PKGa) and the electrode terminal T corresponding to the control terminal CA1 (CLE) in the other package PKG (reverse connection package PKGb) are respectively connected to the pad electrode P of the controller die CD by different wirings. Also, the electrode terminal T corresponding to the control terminal CA0 (ALE) in one package PKG (forward connection package PKGa) and the electrode terminal T corresponding to the control terminal CA0 (ALE) in the other package PKG (reverse connection package PKGb) are respectively connected to the pad electrode P of the controller die CD by different wirings.

[0024] Furthermore, the configurations shown in FIGS. 2 to 4 are merely examples, and the specific configuration can be adjusted as appropriate. For example, in the examples shown in FIGS. 2 and 3, a plurality of memory dies MD are stacked, and these configurations are connected by bonding wires B. However, the plurality of memory dies MD may be connected to each other via through electrodes or the like instead of the bonding wires B. Also, in the example shown in FIG. 4, an example is shown in which the electrode terminals T (data signal input / output terminals DQ0 to DQ7) of the packages PKG arranged above and below the system implementation substrate SSB are mirror-connected by the through electrodes TV. However, the electrode terminals T (data signal input / output terminals DQ0 to DQ7) of the package PKG may not be mirror-connected.

[0025] [Configuration of Memory Die MD] FIG. 5 is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. FIG. 6 is a schematic circuit diagram showing a part of the configuration of the memory die MD. FIG. 7 is a schematic perspective view showing a part of the configuration of the memory die MD. FIGS. 8 and 9 are schematic circuit diagrams showing a part of the configuration of the memory die MD. For convenience of explanation, some configurations are omitted in FIGS. 5 to 9.

[0026] Furthermore, FIG. 5 shows a plurality of control terminals and the like. These plurality of control terminals are represented as control terminals corresponding to high-active signals (positive logic signals), control terminals corresponding to low-active signals (negative logic signals), and control terminals corresponding to both high-active signals and low-active signals. In FIG. 5, the symbols of the control terminals corresponding to the low-active signals include an overline (upper line). In this specification, the symbols of the control terminals corresponding to the low-active signals include a slash (" / "). Note that the description in FIG. 5 is an example, and the specific aspect can be adjusted as appropriate. For example, it is also possible to use some or all of the high-active signals as low-active signals, or some or all of the low-active signals as high-active signals.

[0027] In addition, arrows indicating the input / output direction are shown beside the plurality of control terminals shown in FIG. 5. In FIG. 5, the control terminals with arrows from left to right can be used for the input of data or other signals from the controller die CD to the memory die MD. In FIG. 5, the control terminals with arrows from right to left can be used for the output of data or other signals from the memory die MD to the controller die CD. In FIG. 5, the control terminals with arrows in both left and right directions can be used for both the input of data or other signals from the controller die CD to the memory die MD and the output of data or other signals from the memory die MD to the controller die CD.

[0028] As shown in FIG. 5, the memory die MD includes a memory cell array MCA0, MCA1 for storing user data and a peripheral circuit PC connected to the memory cell arrays MCA0, MCA1. In the following description, the memory cell arrays MCA0, MCA1 may be referred to as the memory cell array MCA. Also, the memory cell arrays MCA0, MCA1 may be referred to as planes PLN0, PLN1.

[0029] [Configuration of Memory Cell Array MCA] As shown in FIG. 6, the memory cell array MCA includes a plurality of memory blocks BLK. Each of these plurality of memory blocks BLK includes a plurality of string units SU. Each of these plurality of string units SU includes a plurality of memory strings MS. One end of each of these plurality of memory strings MS is connected to the peripheral circuit PC via a bit line BL. Also, the other end of each of these plurality of memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0030] The memory string MS includes a drain-side selection transistor STD, a plurality of memory cells MC (memory cell transistors), and a source-side selection transistor STS, which are connected in series between a bit line BL and a source line SL. Hereinafter, the drain-side selection transistor STD and the source-side selection transistor STS may be simply referred to as selection transistors (STD, STS).

[0031] The memory cell MC is a field-effect transistor including a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC changes according to the amount of charge in the charge storage film. The memory cell MC stores one-bit or multiple-bit user data. Note that word lines WL are respectively connected to the gate electrodes of the plurality of memory cells MC corresponding to one memory string MS. These word lines WL are commonly connected to all the memory strings MS in one memory block BLK.

[0032] The selection transistors (STD, STS) are field-effect transistors including a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. Selection gate lines (SGD, SGS) are respectively connected to the gate electrodes of the selection transistors (STD, STS). The drain-side selection gate line SGD is provided corresponding to a string unit SU and is commonly connected to all the memory strings MS in one string unit SU. The source-side selection gate line SGS is commonly connected to all the memory strings MS in a memory block BLK.

[0033] The memory cell array MCA is provided above a semiconductor substrate 100, for example, as shown in FIG. 7. In the example of FIG. 7, a plurality of transistors Tr constituting a peripheral circuit PC are provided between the semiconductor substrate 100 and the memory cell array MCA.

[0034] The memory cell array MCA includes a plurality of memory blocks BLK arranged in the Y direction. Further, an inter-block insulating layer ST made of silicon oxide (SiO2) or the like is provided between two adjacent memory blocks BLK in the Y direction.

[0035] The memory block BLK includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor pillars 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively provided between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120.

[0036] The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Further, the conductive layer 110 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 made of silicon oxide (SiO2) or the like is provided between the plurality of conductive layers 110 arranged in the Z direction.

[0037] Among the plurality of conductive layers 110, one or more conductive layers 110 located at the lowermost layer function as a source-side selection gate line SGS (FIG. 6) and gate electrodes of a plurality of source-side selection transistors STS connected thereto. These plurality of conductive layers 110 are electrically independent for each memory block BLK.

[0038] Further, the plurality of conductive layers 110 located above this function as word lines WL (FIG. 6) and gate electrodes of a plurality of memory cells MC (FIG. 6) connected thereto. These plurality of conductive layers 110 are electrically independent for each memory block BLK respectively.

[0039] Further, one or more conductive layers 110 located above this function as a drain-side selection gate line SGD and gate electrodes of a plurality of drain-side selection transistors STD (FIG. 6) connected thereto. These plurality of conductive layers 110 have a smaller width in the Y direction than the other conductive layers 110.

[0040] Below the conductive layer 110, a semiconductor layer 112 is provided. The semiconductor layer 112 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Also, an insulating layer 101 such as silicon oxide (SiO2) is provided between the semiconductor layer 112 and the conductive layer 110.

[0041] The semiconductor layer 112 functions as a source line SL (FIG. 6). The source line SL is provided in common for all memory blocks BLK included in the memory cell array MCA, for example.

[0042] The semiconductor pillars 120 are arranged in a predetermined pattern in the X direction and the Y direction as shown in FIG. 7, for example. The semiconductor pillars 120 function as the channel regions of a plurality of memory cells MC and selection transistors (STD, STS) included in one memory string MS (FIG. 6). The semiconductor pillars 120 are, for example, semiconductor layers such as polycrystalline silicon (Si). The semiconductor pillars 120 have a substantially bottomed cylindrical shape as shown in FIG. 7, for example, and an insulating layer 125 such as silicon oxide is provided in the central portion. Also, the outer peripheral surfaces of the semiconductor pillars 120 are each surrounded by the conductive layer 110 and face the conductive layer 110.

[0043] An impurity region 121 containing an N-type impurity such as phosphorus (P) is provided at the upper end portion of the semiconductor pillar 120. The impurity region 121 is connected to the bit line BL via the contacts Ch and Cb.

[0044] The gate insulating film 130 has a substantially bottomed cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. The gate insulating film 130 includes, for example, a tunnel insulating film, a charge storage film, and a block insulating film laminated between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film and the block insulating film are insulating films such as silicon oxide (SiO2), for example. The charge storage film is a film capable of storing charges such as silicon nitride (Si3N4), for example. The tunnel insulating film, the charge storage film, and the block insulating film have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120 except for the contact portion between the semiconductor pillar 120 and the semiconductor layer 112.

[0045] Further, the gate insulating film 130 may include a floating gate such as polycrystalline silicon containing N-type or P-type impurities, for example.

[0046] A plurality of contacts CC are provided at the ends of the plurality of conductive layers 110 in the X direction. The plurality of conductive layers 110 are connected to the peripheral circuit PC via these plurality of contacts CC. As shown in FIG. 7, these plurality of contacts CC extend in the Z direction and are connected to the conductive layer 110 at the lower end. The contact CC may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0047] [Configuration of Peripheral Circuit PC] The peripheral circuit PC includes, for example, as shown in FIG. 5, row decoders RD0 and RD1 respectively connected to memory cell arrays MCA0 and MCA1, and sense amplifiers SA0 and SA1. Further, the peripheral circuit PC includes, for example, as shown in FIG. 8, a plurality of column decoders COLD respectively connected to the plurality of sense amplifiers SA0 and SA1, and a multiplexer MPX connected to these plurality of column decoders COLD. Further, the peripheral circuit PC includes, for example, as shown in FIG. 5, a voltage generation circuit VG and a sequencer SQC. Further, the peripheral circuit PC includes an input / output control circuit I / O, a logic circuit CTR, a register circuit RG, and a data output timing adjustment unit TCT. In the following description, the row decoders RD0 and RD1 may be referred to as row decoder RD, and the sense amplifiers SA0 and SA1 may be referred to as sense amplifier SA.

[0048] [Configuration of Row Decoder RD] The row decoder RD (FIG. 5) includes, for example, as shown in FIG. 6, an address decoder 22 that decodes a row address RA (FIG. 5), and a block selection circuit 23 and a voltage selection circuit 24 that transfer an operating voltage to the memory cell array MCA according to the output signal of the address decoder 22.

[0049] The address decoder 22 includes, for example, as shown in FIG. 6, a plurality of block selection lines BLKSEL and a plurality of voltage selection lines 33. The address decoder 22 sequentially refers to the row address RA of the address register ADR (FIG. 5) according to a control signal from, for example, the sequencer SQC, decodes this row address RA, turns on a predetermined block selection transistor 35 and voltage selection transistor 37 corresponding to the row address RA, and turns off the other block selection transistors 35 and voltage selection transistors 37. For example, the voltages of the predetermined block selection line BLKSEL and the voltage selection line 33 are set to the "H" state, and the other voltages are set to the "L" state. When P-channel type transistors instead of N-channel type transistors are used, reverse voltages are applied to these wirings.

[0050] In the illustrated example, one block selection line BLKSEL is provided for each memory block BLK in the address decoder 22. However, this configuration can be changed as appropriate. For example, one block selection line BLKSEL may be provided for each of two or more memory blocks BLK.

[0051] The block selection circuit 23 includes, for example, as shown in FIG. 6, a plurality of block selection units 34 corresponding to the memory block BLK. These plurality of block selection units 34 each include a plurality of block selection transistors 35 corresponding to the word line WL and the selection gate lines (SGD, SGS). The block selection transistor 35 is, for example, a field effect type withstand voltage transistor. The drain electrodes of the block selection transistors 35 are each electrically connected to the corresponding word line WL or selection gate line (SGD, SGS). The source electrodes are each electrically connected to the voltage supply line 31 via the wiring CG and the voltage selection circuit 24. The gate electrodes are commonly connected to the corresponding block selection line BLKSEL.

[0052] The block selection circuit 23 further includes a plurality of transistors (not shown). These plurality of transistors are for the selection gate lines (SGD, SGS) and the ground voltage V SSIt is a field-effect voltage-resistant transistor connected between voltage supply lines to which voltage is supplied. These multiple transistors supply a ground voltage V SS to the selection gate lines (SGD, SGS) included in the non-selected memory block BLK. Note that the multiple word lines WL included in the non-selected memory block BLK are in a floating state.

[0053] The voltage selection circuit 24 includes, for example, as shown in FIG. 6, a plurality of voltage selection units 36 corresponding to the word lines WL and the selection gate lines (SGD, SGS). These multiple voltage selection units 36 each include a plurality of voltage selection transistors 37. The voltage selection transistor 37 is, for example, a field-effect voltage-resistant transistor. The drain terminals of the voltage selection transistors 37 are each electrically connected to the corresponding word line WL or selection gate line (SGD, SGS) via the wiring CG and the block selection circuit 23. The source terminals are each electrically connected to the corresponding voltage supply line 31. The gate electrodes are each connected to the corresponding voltage selection line 33.

[0054] [Configuration of Sense Amplifier SA] The sense amplifiers SA0, SA1 (FIG. 5) each include a sense amplifier module SAM0, SAM1 and a cache memory CM0, CM1. The cache memories CM0, CM1 each include a latch circuit XDL0, XDL1.

[0055] Note that in the following description, the sense amplifier modules SAM0, SAM1 may be referred to as the sense amplifier module SAM, the cache memories CM0, CM1 may be referred to as the cache memory CM, and the latch circuits XDL0, XDL1 may be referred to as the latch circuit XDL.

[0056] The sense amplifier module SAM includes, for example, sense circuits corresponding to a plurality of bit lines BL respectively, and a plurality of latch circuits connected to the sense circuits.

[0057] The cache memory CM includes a plurality of latch circuits XDL. The plurality of latch circuits XDL are respectively connected to the latch circuits in the sense amplifier module SAM. The latch circuit XDL stores, for example, the user data Dat written to the memory cell MC or the user data Dat read from the memory cell MC.

[0058] In addition, the user data Dat included in these plurality of latch circuits XDL is sequentially transferred to the latch circuits in the sense amplifier module SAM during the write operation. Also, the user data Dat included in the latch circuits in the sense amplifier module SAM is sequentially transferred to the latch circuits XDL during the read operation. Further, the user data Dat included in the latch circuit XDL is sequentially transferred to the input / output control circuit I / O via the column decoder COLD, the multiplexer MPX, and the data bus DB during data output.

[0059] [Configuration of Column Decoder COLD] The cache memories CM0, CM1 are respectively connected to the column decoder COLD as shown in FIG. 8, for example. The column decoder COLD includes a multiplexer 41 and a plurality of input / output circuits 42.

[0060] The multiplexer 41 decodes the column address CA stored in the address register ADR (FIG. 5), selects the latch circuit XDL corresponding to the column address CA, and conducts it with the input / output circuit 42.

[0061] The input / output circuit 42 includes an input circuit 43 and an output circuit 44.

[0062] The input circuit 43 is a receiver such as a comparator, for example. The input circuit 43 is connected to the sequencer SQC via the signal line DIN. When the signal on the signal line DIN becomes active, the input circuit 43 turns ON and outputs the data input from the multiplexer MPX to the multiplexer 41. Incidentally, the signal line DIN is commonly connected to a plurality of input circuits 43 in the plurality of column decoders COLD. Also, the signal line DIN is commonly connected to the plurality of column decoders COLD.

[0063] The output circuit 44 is a driver such as an OCD (Off Chip Driver) circuit, for example. The output circuit 44 is connected to the sequencer SQC via the signal line DOUT. When the signal on the signal line DOUT becomes active, the output circuit 44 turns ON and outputs the data input from the multiplexer 41 to the multiplexer MPX. Incidentally, the signal line DOUT is commonly connected to a plurality of input circuits 43 in the column decoder COLD. Also, the signal line DOUT is commonly connected to the plurality of column decoders COLD.

[0064] [Configuration of Multiplexer MPX] Each of the column decoders COLD is connected to the multiplexer MPX. The multiplexer MPX decodes the plane address stored in the address register ADR (Fig. 5), selects the column decoder COLD corresponding to the plane address, and conducts it with the data bus DB. Also, the multiplexer MPX is connected to the sequencer SQC via the signal lines DIN and DOUT.

[0065] In addition to the plane address, the multiplexer MPX refers to the column address CA of the defective column in the memory cell array MCA0 stored in the latch circuit BCL0 or the column address CA of the defective column in the memory cell array MCA1 stored in the latch circuit BCL1, and selects an appropriate bit.

[0066] [Configuration of Voltage Generation Circuit VG] The voltage generation circuit VG (Fig. 5) is connected to a plurality of voltage supply lines 31, as shown in Fig. 6, for example. The voltage generation circuit VG includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit 32. These step-down and step-up circuits are each connected to a voltage supply line to which the power supply voltage V CC and the ground voltage V SS (Fig. 5) is supplied. These voltage supply lines are connected to, for example, the pad electrodes P described with reference to Figs. 2 and 3. The voltage generation circuit VG generates, for example, a plurality of operation voltages to be applied to the bit lines BL, source lines SL, word lines WL, and selection gate lines (SGD, SGS) during a read operation, write operation, and erase operation on the memory cell array MCA according to a control signal from the sequencer SQC, and outputs them to the plurality of voltage supply lines 31 simultaneously. The operation voltage output from the voltage supply line 31 is appropriately adjusted according to a control signal from the sequencer SQC.

[0067] [Configuration of Sequencer SQC] The sequencer SQC (Fig. 5) outputs internal control signals to the row decoders RD0, RD1, the sense amplifier modules SAM0, SAM1, and the voltage generation circuit VG according to the command data Cmd stored in the command register CMR. The sequencer SQC also outputs status data Stt indicating the state of the memory die MD to the status register STR as appropriate. The state of the memory die MD includes the ready / busy state of the memory die MD.

[0068] Also, the sequencer SQC generates a ready / busy signal and outputs it to terminal RY / / BY. Terminal RY / / BY becomes the "L" state during operations such as, for example, a read operation, a write operation, an erase operation, etc., when supplying a voltage to the memory cell array MCA, and becomes the "H" state otherwise. Note that even when performing operations that do not supply a voltage to the memory cell array MCA, such as data out and status read, terminal RY / / BY does not become the "L" state. During the period when terminal RY / / BY is in the "L" state (busy period), access to the memory die MD is basically prohibited. Also, during the period when terminal RY / / BY is in the "H" state (ready period), access to the memory die MD is permitted. Note that terminal RY / / BY is realized by, for example, the pad electrode P described with reference to FIGS. 2 and 3.

[0069] Also, the sequencer SQC includes a feature register FR. The feature register FR is a register that holds feature data Fd. The feature data Fd includes, for example, control parameters of the memory die MD.

[0070] [Configuration of register circuit RG] The register circuit RG includes an address register ADR, a command register CMR, a status register STR, and a register CDR (FIG. 8).

[0071] As shown in FIG. 5, the address register ADR is connected to the input / output control circuit I / O and stores the address data Add input from the input / output control circuit I / O. The address register ADR includes, for example, a plurality of 8-bit register columns. The register columns hold the address data Add corresponding to the internal operation being executed when an internal operation such as a read operation, a write operation, or an erase operation is performed.

[0072] Still, the address data Add includes, for example, a column address CA (FIG. 5) and a row address RA (FIG. 5). The row address RA includes, for example, a block address that identifies a memory block BLK (FIG. 6), a page address that identifies a string unit SU and a word line WL, a plane address that identifies a memory cell array MCA (plane), and a chip address that identifies a memory die MD.

[0073] The command register CMR is connected to the input / output control circuit I / O and stores command data Cmd input from the input / output control circuit I / O. The command register CMR includes, for example, at least one set of 8-bit register columns. When command data Cmd is stored in the command register CMR, a control signal is sent to the sequencer SQC.

[0074] The status register STR is connected to the input / output control circuit I / O and stores status data Stt output to the input / output control circuit I / O. The status register STR includes, for example, a plurality of 8-bit register columns. The register columns hold status data Stt regarding the internal operation being executed, for example, when an internal operation such as a read operation, a write operation, or an erase operation is being executed. Also, the register columns hold ready / busy information indicating the ready / divisible state of the memory cell arrays MCA0 and MCA1, for example.

[0075] As shown in FIG. 8, the register CDR includes latch circuits BCL0 and BCL1. The latch circuit BCL0 stores the column address CA of a defective column in the memory cell array MCA0. The latch circuit BCL1 stores the column address CA of a defective column in the memory cell array MCA1. The latch circuits BCL0 and BCL1 include, for example, a plurality of register columns of a plurality of bits corresponding to the column address CA.

[0076] The register CDR is connected to the logic circuit CDRL. When accessing the sense amplifiers SA0 and SA1, the logic circuit CDRL refers to the column addresses CA of the defective columns stored in the latch circuits BCL0 and BCL1, decodes them, and outputs them to the multiplexer MPX. The register CDR includes a data bus with a number of bits that can be connected to one of the latch circuits BCL0 and BCL1. The logic circuit CDRL includes, for example, a data bus with the same number of bits as the column address CA.

[0077] [Configuration of data output timing adjustment unit TCT] As shown in FIG. 5, the data output timing adjustment unit TCT is connected to the data bus DB between the cache memories CM0 and CM1 and the input / output control circuit I / O. The data output timing adjustment unit TCT adjusts the start timing of data output to the cache memory CM1 in order to start the data output of the cache memory CM1 without a time gap after the completion of the data output of the cache memory CM0, for example, when continuously executing data out to the cache memories CM0 and CM1.

[0078] [Configuration of input / output control circuit I / O] The input / output control circuit I / O (FIG. 5) includes data signal input / output terminals DQ0 to DQ7, data strobe signal input / output terminals DQS and / DQS, a shift register, a buffer circuit, a connection change circuit SW, and a phase adjustment circuit PAC.

[0079] Each of the data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS and / DQS is realized by, for example, the pad electrode P described with reference to FIGS. 2 and 3. The data input through the data signal input / output terminals DQ0 to DQ7 is input from the buffer circuit to the cache memory CM according to the internal control signal from the logic circuit CTR. Also, the data output through the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or the status register STR to the buffer circuit according to the internal control signal from the logic circuit CTR.

[0080] The signals input via the data strobe signal input / output terminals DQS and / DQS (for example, the data strobe signal and its complementary signal, which may also be referred to as the "timing signal") are used when data is input via the data signal input / output terminals DQ0 to DQ7. The data input via the data signal input / output terminals DQ0 to DQ7 is captured into the shift register within the input / output control circuit I / O at the timing of the rising edge of the voltage of the data strobe signal input / output terminal DQS and the falling edge of the voltage of the data strobe signal input / output terminal / DQS, as well as at the timing of the falling edge of the voltage of the data strobe signal input / output terminal DQS and the rising edge of the voltage of the data strobe signal input / output terminal / DQS.

[0081] Also, the signals output via the data strobe signal input / output terminals DQS and / DQS (which may be referred to as the "timing signal") are used as reference signals when data is output via the data signal input / output terminals DQ0 to DQ7. The data output via the data signal input / output terminals DQ0 to DQ7 is switched at the timing of the rising edge of the voltage of the data strobe signal input / output terminal DQS and the falling edge of the voltage of the data strobe signal input / output terminal / DQS, as well as at the timing of the falling edge of the voltage of the data strobe signal input / output terminal DQS and the rising edge of the voltage of the data strobe signal input / output terminal / DQS.

[0082] Each of the data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS and / DQS is connected to the input circuit 201 and the output circuit 202, for example, as shown in FIG. 9. The input circuit 201 is a receiver such as a comparator, for example. The output circuit 202 is a driver such as an OCD circuit, for example.

[0083] The connection change circuit SW (FIG. 5) is a circuit that changes the order of the data input to the data signal input / output terminals DQ0 to DQ7 from the outside of the memory die MD and captures it into the inside of the memory die MD.

[0084] Each memory die MD determines whether it is included in the positive connection package PKGa (Fig. 4) or the reverse connection package PKGb (Fig. 4) based on, for example, the feature data Fd stored in the feature register FR.

[0085] The phase adjustment circuit PAC adjusts at least one of the phases of the signals input to the data signal input / output terminals DQ0 to DQ7, the signals output from the data signal input / output terminals DQ0 to DQ7, the signals input to the data strobe signal input / output terminals DQS, / DQS, and the signals output from the data strobe signal input / output terminals DQS, / DQS during the chip-to-chip copy operation described later.

[0086] [Configuration of the logic circuit CTR] The logic circuit CTR (Fig. 5) includes a plurality of control terminals / CE, CA1 (CLE), CA0 (ALE), CA_clk ( / WE), / RE, RE, / WP and a logic circuit connected to these plurality of control terminals / CE, CA1 (CLE), CA0 (ALE), CA_clk ( / WE), / RE, RE, / WP. The logic circuit CTR receives an external control signal from the controller die CD via the control terminals / CE, CA1 (CLE), CA0 (ALE), CA_clk ( / WE), / RE, RE, / WP, and outputs an internal control signal to the input / output control circuit I / O in response thereto.

[0087] Each of the control terminals / CE, CA1 (CLE), CA0 (ALE), CA_clk ( / WE), / RE, RE, / WP is connected to the input circuit 201, for example, as shown in Fig. 9. In addition, each of the control terminals CA1 (CLE), CA0 (ALE), / WP is also connected to the output circuit 202 in addition to the input circuit 201. Each of the control terminals / CE, CA1 (CLE), CA0 (ALE), CA_clk ( / WE), / RE, RE, / WP is realized by, for example, the pad electrode P described with reference to Figs. 2 and 3.

[0088] The signal input via the control terminal / CE (e.g., chip enable signal) is used when selecting the memory die MD. The memory die MD with "L" input to the control terminal / CE becomes in a state where input and output of user data Dat, command data Cmd, address data Add, and status data Stt (hereinafter may be simply referred to as "data") are possible. The memory die MD with "H" input to the control terminal / CE becomes in a state where input and output of data are impossible. Note that, as shown in FIG. 9, the control terminal / CE is connected to the input circuit 201.

[0089] The signal input via the control terminal CA1 (CLE) (e.g., command latch enable signal) is used when using the command register CMR and the like.

[0090] The signal input via the control terminal CA0 (ALE) (e.g., address latch enable signal) is used when using the address register ADR and the like.

[0091] Also, in this embodiment, a plurality of bits of data are input in a time-division manner by 2 bits via the control terminal CA1 (CLE) and the control terminal CA0 (ALE). This data is used as, for example, command data Cmd, address data Add, etc. Note that the plurality of bits of data input in a time-division manner are acquired by the signals input via the control terminal CA1 (CLE) and the control terminal CA0 (ALE) at the timing of the rising edge (e.g., the transition from the "L" state to the "H" state) and the falling edge (e.g., the transition from the "H" state to the "L" state) of the voltage of the control terminal CA_clk ( / WE) described later. Further, in this embodiment, a plurality of bits of data are output in a time-division manner by 2 bits via the control terminal CA1 (CLE) and the control terminal CA0 (ALE). This data is used as, for example, status data Stt. The functions and the like of the control terminal CA1 (CLE) and the control terminal CA0 (ALE) will be described later.

[0092] The signal (e.g., the write enable signal) input via the control terminal CA_clk( / WE) is used when data is input from the controller die CD to the memory die MD. The functions of the control terminal CA_clk( / WE) will be described later.

[0093] The signals (e.g., the read enable signal and its complementary signal, which may also be referred to as "timing signals") input via the control terminals / RE and RE are used when data is output via the data signal input / output terminals DQ0~DQ7. The data output from the data signal input / output terminals DQ0~DQ7 switches at the falling edge of the voltage of the control terminal / RE and the rising edge of the voltage of the control terminal RE, as well as at the rising edge of the voltage of the control terminal / RE and the falling edge of the voltage of the control terminal RE.

[0094] The signal (e.g., the write protect signal) input via the control terminal / WP is used for restricting the input of user data Dat from the controller die CD to the memory die MD. The signal input via the control terminal / WP may also be used as command data Cmd, address data Add, etc., or status data Stt may be output from the status register STR via the control terminal / WP.

[0095] [Method of Signal Input from Controller Die CD to Memory Die MD] Next, with reference to FIGS. 10 to 12, the method of signal input from the controller die CD to the memory die MD in the present embodiment will be described.

[0096] [Functions of Each Terminal] FIG. 10 is a schematic diagram for explaining the functions of the signal input / output terminals and control terminals in the memory die MD. In the following description, the data signal input / output terminals DQ0~DQ7 may be denoted as data signal input / output terminals DQ<7:0>.

[0097] As shown in, for example, FIG. 10, the memory die MD according to this embodiment uses the data signal input / output terminals DQ<7:0> for input / output of user data Dat, and does not use them for input of command data Cmd and address data Add, nor for output of status data Stt. Also, the memory die MD according to this embodiment uses the control terminals CA1 (CLE) and CA0 (ALE) for input of command data Cmd and address data Add, and for output of data such as status data Stt.

[0098] A part of the signals input / output via the control terminals CA1 (CLE) and CA0 (ALE) of the memory die MD according to this embodiment may be called a header. Also, a combination of headers constituting such signals may be called a header set. The header set includes, for example, 4-bit signals input in a time-division manner over 2 cycles.

[0099] Also, a part of the command data Cmd, address data Add, status data Stt, feature data Fd, etc. input / output following the header may be called a body. Also, a combination of bodies constituting such data or a part thereof may be called a body set. The body set includes, for example, 8-bit data input in a time-division manner over 4 cycles.

[0100] Also, a combination of 1 header set and 1 body set may be called a frame.

[0101] As described above, the data of the control terminals CA1 (CLE) and CA0 (ALE) are captured into a register (not shown) in the logic circuit CTR at the rising edge and falling edge timings of the voltage of the control terminal CA_clk ( / WE). That is, the data of the control terminals CA1 (CLE) and CA0 (ALE) are captured into a register (not shown) in the logic circuit CTR according to the toggle of the signal input to the control terminal CA_clk ( / WE). In this specification, when the voltage of the control terminal CA_clk ( / WE) rises or falls once, and accordingly, 2-bit data is input or output via at least one of the control terminals CA1 (CLE) and CA0 (ALE), this is called 1 cycle. For example, when the voltage of the control terminal CA0 (ALE) rises once and then falls, accordingly, 4-bit data is input or output via at least one of the control terminals CA1 (CLE) and CA0 (ALE). This is called 2 cycles.

[0102] [Example of Header Set Input] FIG. 11 is a schematic waveform diagram for explaining the operation of the memory die MD according to the present embodiment. FIG. 12 is a schematic table for explaining the operation of the memory die MD.

[0103] FIG. 11 shows the waveform when inputting the header set. In the example of FIG. 11, with a signal in the "L" state input to the control terminal / CE, signals in the "L" state and "H" state are input to the control terminal CA_clk ( / WE) at a substantially constant pace. That is, with the input signal of the control terminal / CE in the "L" state, the input signal of the control terminal CA_clk ( / WE) is toggled (two toggles), rising from the "L" state to the "H" state and then falling from the "L" state to the "H" state, and this is repeated.

[0104] In the example of FIG. 11, at timing t100 and timing t101, a 4-bit header set is input corresponding to the rising edge and falling edge of the signal input to the control terminal CA_clk( / WE). More specifically, at timing t100 and timing t101, the controller die CD inputs the 4-bit header set shown in FIG. 12 to the memory die MD in two cycles, 2 bits at a time. For example, when instructing to input 8-bit command data Cmd in the body set, at the input of the header in the first cycle, the voltages of the control terminals CA1(CLE) and CA0(ALE) are set according to bits "0", "0". Also, at the timing (rising edge) when the control terminal CA_clk( / WE) rises from "L" to "H", bits "0", "0" are taken into a register (not shown) of the logic circuit CTR as the header of the first cycle. At the input of the header in the second cycle, the voltages of the control terminals CA1(CLE) and CA0(ALE) are set according to bits "1", "1". Also, at the timing (falling edge) when the control terminal CA_clk( / WE) falls from "H" to "L", bits "1", "1" are taken into a register (not shown) of the logic circuit CTR as the header of the second cycle.

[0105] Also, in the example of FIG. 11, at timings t102 to t105, an 8-bit body set is input corresponding to the rising edge and falling edge of the signal input to the control terminal CA_clk( / WE). More specifically, at timings t102 to t105, the controller die CD inputs an 8-bit body set corresponding to a 4-bit header set (entry condition) to the memory die MD in 4 cycles, 2 bits at a time. For example, let the 8-bit command data Cmd be bits “0” to “7”. First, when inputting the body (data) in the first cycle, the voltages of the control terminals CA1(CLE) and CA0(ALE) are set according to bits “1” and “0”. Also, the body in the first cycle is captured at the timing when the control terminal CA_clk( / WE) rises from “L” to “H” (rising edge). When inputting the body (data) in the second cycle, the voltages of the control terminals CA1(CLE) and CA0(ALE) are set according to bits “3” and “2”. Also, the body in the second cycle is captured at the timing when the control terminal CA_clk( / WE) falls from “H” to “L” (falling edge). Similarly, when inputting the bodies in the third and fourth cycles, the voltages of the control terminals CA1(CLE) and CA0(ALE) are set according to bits “5” and “4”, and bits “7” and “6”, respectively. Also, the bodies in the third and fourth cycles are captured at the rising edge and falling edge of the control terminal CA_clk( / WE).

[0106] Note that in the above description, the operation in the case of “CMD” in the table shown in FIG. 12, that is, the operation when command data Cmd is input as the body set, is exemplified. In this case, as described above, 4-bit data “0”, “0”, “1”, “1” is input as the header set. However, this is only an example.

[0107] For example, when inputting command data Cmd as a body set, 4-bit data "0", "0", "1", "0" is input as a header set, as in the case of "ADD" in the table shown in FIG. 12. Also, for example, when outputting data as a body set, 4-bit data "0", "0", "0", "0" is input as a header set, as in the case of "DOUT" in the table shown in FIG. 12. The header set corresponding to "DOUT" is input, for example, when outputting status data Stt or feature data Fd. Also, for example, when inputting data as a body set, 4-bit data "0", "0", "0", "1" is input as a header set, as in the case of "DIN" in the table shown in FIG. 12. The header set corresponding to "DIN" is input, for example, when inputting feature data Fd. Also, for example, when outputting a ready busy state, 4-bit data "0", "1", "0", "1" is input as a header set, as in the case of "R / B output" in the table shown in FIG. 12.

[0108] Note that the Header Rise Edge shown in FIG. 12 indicates the 2-bit first header that is input corresponding to the rising edge of the signal input to the header in the first cycle, that is, the control terminal CA_clk ( / WE). Also, the Header Fall Edge indicates the 2-bit second header that is input corresponding to the falling edge of the signal input to the header in the second cycle, that is, the control terminal CA_clk ( / WE).

[0109] [Operation] Next, the operation of the memory die MD will be described.

[0110] The memory die MD is configured to be able to execute a read operation. The read operation is an operation of reading user data Dat from the memory cell array MCA by the sense amplifier module SAM (FIG. 5) and transferring the read user data Dat to the latch circuit XDL.

[0111] In addition, the memory die MD is configured to be capable of performing data output. The data output of the user data Dat is an operation of outputting the user data Dat included in the latch circuit XDL to the controller die CD. In the data output of the user data Dat, the user data Dat included in the latch circuit XDL is output to the controller die CD via the column decoder COLD, multiplexer MPX, data bus DB, and input / output control circuit I / O described with reference to FIG. 8.

[0112] In addition, the memory die MD is configured to be capable of performing a write operation. The write operation is an operation of writing the user data Dat input from the controller die CD to the memory cell array MCA. In the write operation, the user data Dat input from the controller die CD is transferred to the sense amplifier SA via the input / output control circuit I / O, data bus DB, multiplexer MPX, and column decoder COLD. Further, the user data Dat transferred to the sense amplifier SA is written to the memory cell array MCA.

[0113] [Read Operation] FIG. 13 is a schematic waveform diagram for explaining the read operation, and shows the input / output signals between the controller die CD and the memory die MD.

[0114] Before the timing t110 in FIG. 13, the voltage of the control terminal / CE has fallen from “H” to “L”.

[0115] Subsequently, the controller die CD inputs a command set for a read operation to the memory die MD at timings t110 to t135. That is, the controller die CD inputs command data Cmd for instructing a read operation to the memory die MD at timings t110 to t115, inputs address data Add for designating a plurality of memory cells MC to be the target of the read operation to the memory die MD at timings t120 to t127, and inputs command data Cmd for starting the read operation to the memory die MD at timings t130 to t135.

[0116] More specifically, at timings t110 and t111, the controller die CD inputs to the memory die MD a header set composed of a header of the first cycle indicating bits “0”, “0” and a header of the second cycle indicating bits “1”, “1” via control terminals CA1 (CLE) and CA0 (ALE). As shown in FIG. 12, this header set is a header set for instructing to input command data Cmd, and is input at the rising edge and falling edge (timing) of the signal input to the control terminal CA_clk ( / WE). In other words, at timings t110 and t111, in the frame corresponding to the command data Cmd constituting the command set of the read operation, the portion corresponding to the header set (4-bit information) is input to the memory die MD in response to two toggles of the signal input to the control terminal CA_clk ( / WE).

[0117] Also, at timings t112 to t115, the controller die CD inputs command data 00h as a body set to the memory die MD via control terminals CA1 (CLE) and CA0 (ALE). The command data “00h” is the command data Cmd that instructs a read operation. In other words, at timings t112 to t115, among the frames corresponding to the command data Cmd that constitutes the command set for the read operation, the part corresponding to the body set (8-bit information) is input to the memory die MD in response to 4 toggles of the signal input to the control terminal CA_clk ( / WE).

[0118] Also, at timings t120 and t121, the controller die CD inputs a header set composed of the first-cycle header indicating bits “0”, “0” and the second-cycle header indicating bits “1”, “0” to the memory die MD via control terminals CA1 (CLE) and CA0 (ALE). This header set is a header set that instructs to input address data Add as shown in FIG. 12, and is input at the rising edge and falling edge of the signal input to the control terminal CA_clk ( / WE). In other words, at timings t120 and t121, among the frames corresponding to the address data Add that constitutes the command set for the read operation, the part corresponding to the header set (4-bit information) is input to the memory die MD in response to 2 toggles of the signal input to the control terminal CA_clk ( / WE).

[0119] Also, at timings t122 to t125, the controller die CD inputs address data Add as a body set to the memory die MD via control terminals CA1 (CLE) and CA0 (ALE). This address data Add is data for specifying a plurality of memory cells MC that are the targets of the read operation. In other words, at timings t122 to t125, among the frames corresponding to the address data Add that constitutes the command set of the read operation, the portion corresponding to the body set (8-bit information) is input to the memory die MD in response to four toggles of the signal input to the control terminal CA_clk ( / WE).

[0120] Also, at timings t126 to t127, operations similar to those at timings t120 to t125 are executed a plurality of times (four times in the illustrated example), and a plurality of (four in the illustrated example) frames are input. As a result, a total of 8 bits × 5 times = 40 bits of address data Add are input to the memory die MD from timings t120 to t127.

[0121] Also, at timings t130 and t131, the controller die CD inputs a header set composed of a first-cycle header indicating bits “0”, “0” and a second-cycle header indicating bits “1”, “1” to the memory die MD via control terminals CA1 (CLE) and CA0 (ALE).

[0122] Also, at timings t132 to t135, the controller die CD inputs command data 30h as a body set to the memory die MD via control terminals CA1 (CLE) and CA0 (ALE). The command data “30h” is command data Cmd that instructs the start of the read operation.

[0123] When the input of the command data “30h” is executed at timing t135, the read operation is started, and the voltage of the terminal RY / / BY has fallen from “H” to “L”.

[0124] Also, in the illustrated example, the read operation ends at timing t136, and the voltage of terminal RY / / BY rises from "L" to "H".

[0125] [Data Out] FIG. 14 is a schematic waveform diagram for explaining Data Out, and shows the input / output signals between controller die CD and memory die MD.

[0126] Before timing t210 in FIG. 14, the voltage of control terminal / CE is falling from "H" to "L".

[0127] Subsequently, controller die CD inputs the command set of Data Out to memory die MD at timings t210 to t235. That is, controller die CD inputs command data Cmd for instructing Data Out to memory die MD at timings t210 to t215, inputs address data Add for designating a plurality of memory cells MC to be the target of Data Out to memory die MD at timings t220 to t227, and inputs command data Cmd for starting Data Out to memory die MD at timings t230 to t235.

[0128] The operations at timings t210 to t235 of Data Out are basically executed in the same manner as the operations at timings t110 to t135 of the read operation.

[0129] However, at timings t212 to t215, controller die CD inputs command data 05h instead of command data 00h to memory die MD. Command data "05h" is the command data Cmd for instructing Data Out.

[0130] Also, at timings t230 to t235, the controller die CD inputs command data E0h to the memory die MD instead of command data 30h. The command data "E0h" is command data Cmd that instructs the start of data output.

[0131] Also, at timings t240 to t243, the controller die CD switches the input signals of the control terminals / RE and RE (toggles the input signals of the control terminals / RE and RE) to specify the timing for outputting user data Dat. More specifically, at timing t240, the controller die CD switches the input signal of control terminal / RE from "H" to "L" and switches the input signal of control terminal RE from "L" to "H". Also, at timing t241, the controller die CD switches the input signal of control terminal / RE from "L" to "H" and switches the input signal of control terminal RE from "H" to "L". Thereafter, the switching (toggle) is repeated. As a result, the output of user data Dat starts at timing t242, and the user data Dat stored in the latch circuit XDL is output via the data signal input / output terminals DQ0 to DQ7. Note that the signals of the data strobe signal input / output terminals DQS and / DQS rise or fall at the timing when data is output to the data signal input / output terminals DQ0 to DQ7. Therefore, even when "0" is continuously output from the data signal input / output terminals DQ0 to DQ7 or when "1" is continuously output, it is possible to discriminate the data separation.

[0132] When the switching of the input signals of the control terminals / RE and RE ends at timing t243, the output of user data Dat also ends at timing t244.

[0133] Also, in the illustrated example, at timing t245, the voltage of the control terminal / CE is rising from "L" to "H".

[0134] [Write operation] FIG. 15 is a schematic waveform diagram for explaining a write operation, and shows input / output signals between the controller die CD and the memory die MD.

[0135] Before the timing t310 in FIG. 15, the voltage of the control terminal / CE has fallen from “H” to “L”.

[0136] Subsequently, at timings t310 to t345, the controller die CD inputs a command set for the write operation to the memory die MD. That is, the controller die CD inputs command data Cmd for instructing the write operation to the memory die MD at timings t310 to t315, inputs address data Add for designating a plurality of memory cells MC to be the target of the write operation to the memory die MD at timings t320 to t327, inputs user data Dat to be written to the plurality of memory cells MC at timings t330 to t333, and inputs command data Cmd for starting the write operation to the memory die MD at timings t340 to t345.

[0137] More specifically, at timings t310 and t311, the controller die CD inputs to the memory die MD a header set composed of a header of the first cycle indicating bits “0”, “0” and a header of the second cycle indicating bits “1”, “1” via the control terminals CA1 (CLE) and CA0 (ALE).

[0138] Also, at timings t312 to t315, the controller die CD inputs command data 80h as a body set to the memory die MD via the control terminals CA1 (CLE) and CA0 (ALE). The command data “80h” is command data Cmd for instructing the write operation.

[0139] Also, at timings t320 and t321, the controller die CD inputs to the memory die MD a header set composed of a header of the first cycle indicating bits "0", "0" and a header of the second cycle indicating bits "1", "0" via control terminals CA1 (CLE) and CA0 (ALE).

[0140] Also, at timings t322 to t325, the controller die CD inputs address data Add as a body set to the memory die MD via control terminals CA1 (CLE) and CA0 (ALE). This address data Add is data for specifying a plurality of memory cells MC that are the targets of the write operation.

[0141] Also, at timings t326 to t327, an operation similar to the operation at timings t320 to t325 is executed a plurality of times (4 times in the illustrated example), and a plurality of (4 in the illustrated example) frames are input. As a result, 40-bit address data Add of 8 bits × 5 times is input to the memory die MD from timings t320 to t327.

[0142] Also, at timings t330 to t333, the controller die CD switches the input signals of the data strobe signal input / output terminals DQS and / DQS (toggles the input signals of the data strobe signal input / output terminals DQS and / DQS) to specify the timing for inputting user data Dat. More specifically, at timing t330, the controller die CD switches the input signal of the data strobe signal input / output terminal DQS to “H” and switches the input signal of the data strobe signal input / output terminal / DQS to “L”. Also, at timing t331, the controller die CD switches the input signal of the data strobe signal input / output terminal DQS from “H” to “L” and switches the input signal of the data strobe signal input / output terminal / DQS from “L” to “H”. Further, at timing t332, with 8-bit data constituting the user data Dat input to the data signal input / output terminals DQ0 to DQ7, the input signal of the data strobe signal input / output terminal DQS is switched from “L” to “H”, and the input signal of the data strobe signal input / output terminal / DQS is switched from “H” to “L”. Thereafter, while 8-bit data constituting the user data Dat is input to the data signal input / output terminals DQ0 to DQ7, the switching (toggle) of the input signals of the data strobe signal input / output terminals DQS and / DQS is repeated.

[0143] Also, at timings t340 and t341, the controller die CD inputs a header set composed of a first-cycle header indicating bits “0”, “0” and a second-cycle header indicating bits “1”, “1” to the memory die MD via the control terminals CA1 (CLE) and CA0 (ALE).

[0144] Also, at timings t342 to t345, the controller die CD inputs command data 10h as a body set to the memory die MD via the control terminals CA1 (CLE) and CA0 (ALE). The command data “10h” is command data Cmd instructing the start of a write operation.

[0145] When the input of command data “10h” is executed at timing t345, the writing operation is started and the voltage of terminal RY / / BY has fallen from “H” to “L”.

[0146] Also, in the illustrated example, at timing t346, the writing operation ends and the voltage of terminal RY / / BY has risen from “L” to “H”.

[0147] Also, in the illustrated example, at timing t347, the voltage of control terminal / CE has risen from “L” to “H”.

[0148] [Inter-chip copy operation] Next, with reference to FIGS. 16 to 18, the inter-chip copy operation will be described. FIGS. 16 to 18 are schematic block diagrams for explaining the inter-chip copy operation.

[0149] When copying user data Dat written in a certain memory die MD (in the illustrated example, memory die MD0) in memory system 10 to another memory die MD (in the illustrated example, memory die MD1) in memory system 10, for example, first, the above-described read operation and data out are executed, and as shown in FIG. 16, it is conceivable to transfer user data Dat from memory die MD0 to controller die CD. Next, the above-described write operation is executed, and as shown in FIG. 17, it is conceivable to transfer the read user data Dat to memory die MD1.

[0150] Here, during the execution of the operations corresponding to timings t240 to t244 described with reference to FIG. 14 (the operation of transferring user data Dat from memory die MD to controller die CD), the data bus between controller die CD and memory die MD is occupied. Therefore, at this timing, the operations corresponding to timings t330 to t333 described with reference to FIG. 15 (the operation of transferring user data Dat from controller die CD to memory die MD) cannot be executed.

[0151] Therefore, the memory system 10 according to the present embodiment is configured to be capable of executing an inter-chip copy operation. In the inter-chip copy operation, as shown in FIG. 18, the user data Dat is directly transferred from the memory die MD0 to the memory die MD1 without passing through the controller die CD. At this time, the operations corresponding to the timings t240 to t244 described with reference to FIG. 14 and the operations corresponding to the timings t330 to t333 described with reference to FIG. 15 are executed in parallel.

[0152] According to such a method, the time required to copy the user data Dat between the memory dies MD0 and MD1 can be significantly reduced.

[0153] In addition, in the inter-chip copy operation, the user data Dat output from the memory die MD0 is not input to the controller die CD. Also, the controller die CD does not output the user data Dat input to the memory die MD1.

[0154] Next, with reference to FIGS. 19 and 20, the inter-chip copy operation will be described in more detail.

[0155] FIGS. 19 and 20 are schematic waveform diagrams for explaining the inter-chip copy operation. FIG. 20 shows a continuation of the waveform diagram of FIG. 19.

[0156] Before the timing t410 in FIG. 19, the voltage of the control terminal / CE has fallen from “H” to “L”.

[0157] Subsequently, at timings t410 to t435, the controller die CD inputs a first command set corresponding to the inter-chip copy operation to the memory die MD0 that executes operations corresponding to data out. That is, the controller die CD inputs command data Cmd for instructing the inter-chip copy operation to the memory die MD0 at timings t410 to t415, inputs address data Add for designating a plurality of memory cells MC to be the target of the inter-chip copy operation to the memory die MD0 at timings t420 to t427, and inputs command data Cmd for instructing the inter-chip copy operation to the memory die MD0 at timings t430 to t435.

[0158] The operations at timings t410 to t435 of the inter-chip copy operation are basically executed in the same manner as the operations at timings t110 to t135 of the read operation.

[0159] However, at timings t412 to t415, the controller die CD inputs command data X1h instead of command data 00h to the memory die MD0. The command data X1h is the command data Cmd for instructing the inter-chip copy operation.

[0160] Also, at timings t430 to t435, the controller die CD inputs command data X2h instead of command data 30h to the memory die MD0. The command data X2h is the command data Cmd for instructing the inter-chip copy operation.

[0161] Note that the command data X2h input to the memory die MD0 at timings t430 to t435 is different from the command data X1h input to the memory die MD0 at timings t412 to t415.

[0162] In the illustrated example, when the input of the command set is completed, the voltage of the control terminal / CE rises from "L" to "H" at timing t436. Also, the voltage of the control terminal / CE falls from "H" to "L" at timing t437.

[0163] Subsequently, the controller die CD inputs a second command set corresponding to the inter-chip copy operation to the memory die MD1 that executes an operation corresponding to the write operation at timings t440 to t475. That is, the controller die CD inputs command data Cmd for instructing the inter-chip copy operation to the memory die MD1 at timings t440 to t445, inputs address data Add for specifying a plurality of memory cells MC to be the target of the inter-chip copy operation to the memory die MD1 at timings t450 to t457, inputs user data Dat to be written to the plurality of memory cells MC to the memory die MD at timings t460 to t464, and inputs command data Cmd for starting the inter-chip copy operation to the memory die MD at timings t470 to t475.

[0164] The operations at timings t440 to t457 of the inter-chip copy operation are basically executed in the same manner as the operations at timings t310 to t327 of the write operation.

[0165] However, at timings t442 to t445, the controller die CD inputs command data X3h instead of command data 00h to the memory die MD1. The command data X3h is command data Cmd for instructing the inter-chip copy operation.

[0166] Also, the command data X3h input to the memory die MD0 at timings t442 to t445 is different from both the command data X1h input to the memory die MD0 at timings t412 to t415 and the command data X2h input to the memory die MD0 at timings t430 to t435.

[0167] Also, at timings t460 to t463, the controller die CD specifies the timings for outputting the user data Dat from the memory die MD0 (by toggling the input signals of the control terminals / RE, RE) and for inputting the user data Dat to the memory die MD1.

[0168] The operation of the memory die MD0 at timings t460 to t463 of the inter-chip copy operation is basically executed in the same manner as the operation at timings t240 to t243 (Figure 14) of the data out. That is, when the controller die CD toggles the input signals of the control terminals / RE, RE, the memory die MD0 outputs data to the data signal input / output terminals DQ0 to DQ7 at the timing of the change of the input signals of the control terminals / RE, RE. Also, at this timing, the signals of the data strobe signal input / output terminals DQS, / DQS change. However, the user data Dat output from the memory die MD0 is not input to the controller die CD.

[0169] The operation of the memory die MD1 at timings t460 to t463 of the inter-chip copy operation is basically executed in the same manner as the operation at timings t330 to t333 (Figure 15) of the write operation. However, in the inter-chip copy operation, the signals of the data strobe signal input / output terminals DQS, / DQS are output from the memory die MD0 instead of the controller die CD. Therefore, the user data Dat is input to the memory die MD1 at the timing based on the signals of the data strobe signal input / output terminals DQS, / DQS output from the memory die MD0.

[0170] When the switching of the input signals of the control terminals / RE and RE is completed at timing t463, the transfer of user data Dat is also completed at timing t464.

[0171] The operations at timings t470 to t477 of the inter-chip copy operation are basically executed in the same manner as the operations at timings t340 to t347 of the write operation.

[0172] However, at timings t472 to t475, the controller die CD inputs command data X4h instead of command data 10h to the memory die MD1. The command data X4h is the command data Cmd that instructs the start of the inter-chip copy operation.

[0173] In addition, the command data X4h input to the memory die MD1 at timings t472 to t475 is different from the command data X1h input to the memory die MD0 at timings t412 to t415, the command data X2h input to the memory die MD0 at timings t430 to t435, and the command data X3h input to the memory die MD0 at timings t442 to t445.

[0174] [Role of the Phase Adjustment Circuit PAC in the Inter-Chip Copy Operation] Next, with reference to FIGS. 21 to 24, the role of the phase adjustment circuit PAC in the inter-chip copy operation will be described. FIGS. 21 to 24 are schematic waveform diagrams for explaining the role of the phase adjustment circuit PAC in the inter-chip copy operation.

[0175] In the data output timings t242 to t244 described with reference to FIG. 14, as shown in FIG. 21, the signals of the data strobe signal input / output terminals DQS, / DQS rise or fall at the timing when data is output to the data signal input / output terminals DQ0 to DQ7. That is, the phases of the signals output from the data signal input / output terminals DQ0 to DQ7 match the phases of the signals output from the data signal input / output terminals DQ0 to DQ7.

[0176] On the other hand, in the write operation timings t332 to t333 described with reference to FIG. 15, as shown in FIG. 22, with the controller die CD inputting 8-bit data constituting the user data Dat to the data signal input / output terminals DQ0 to DQ7, the input signal of the data strobe signal input / output terminals DQS, / DQS is raised from "L" to "H" or lowered from "H" to "L". That is, the phases of the signals output from the data signal input / output terminals DQ0 to DQ7 do not match the phases of the signals output from the data signal input / output terminals DQ0 to DQ7. The phases of these signals are shifted, for example, by half a wavelength.

[0177] Since the input / output control circuit I / O (FIG. 5) is configured on the premise of such an operation, in the inter-chip copy operation, it is desirable to suitably adjust the relationship between the phases of the signals output from the data signal input / output terminals DQ0 to DQ7 and the phases of the signals output from the data signal input / output terminals DQ0 to DQ7.

[0178] Therefore, as described with reference to FIG. 5, the memory die MD according to the present embodiment includes a phase adjustment circuit PAC.

[0179] The phase adjustment circuit PAC may, for example, as shown in FIG. 23, delay the signals of the data strobe signal input / output terminals DQS, / DQS output from the memory die MD0 by half a wavelength and input them to the memory die MD1. In this case, the phase of the signals of the data strobe signal input / output terminals DQS, / DQS can be delayed by half a wavelength by the phase adjustment circuit PAC mounted on the memory die MD0. In this case, on the data bus between the memory dies MD0 and MD1, the phase of the signals of the data strobe signal input / output terminals DQS, / DQS and the phase of the signals of the data signal input / output terminals DQ0 to DQ7 will be shifted by half a wavelength.

[0180] Incidentally, the phase of the signals of the data strobe signal input / output terminals DQS, / DQS may be delayed by half a wavelength by the phase adjustment circuit PAC mounted on the memory die MD1. In this case, on the data bus between the memory dies MD0 and MD1, the phase of the signals of the data strobe signal input / output terminals DQS, / DQS and the phase of the signals of the data signal input / output terminals DQ0 to DQ7 will be the same.

[0181] Also, the phase of the signals of the data strobe signal input / output terminals DQS, / DQS may be delayed by 1 / 4 wavelength each by the phase adjustment circuits PAC mounted on the memory dies MD0 and MD1. In this case, on the data bus between the memory dies MD0 and MD1, the phase of the signals of the data strobe signal input / output terminals DQS, / DQS will be delayed by 1 / 4 wavelength compared to the phase of the signals of the data signal input / output terminals DQ0 to DQ7.

[0182] Also, the phase adjustment circuit PAC may, for example, as shown in FIG. 24, delay the signals of the data signal input / output terminals DQ0 to DQ7 output from the memory die MD0 by half a wavelength and input them to the memory die MD1. In this case, the phase of the signals of the data signal input / output terminals DQ0 to DQ7 can be delayed by half a wavelength by the phase adjustment circuit PAC mounted on the memory die MD0. In this case, on the data bus between the memory dies MD0 and MD1, the phase of the signals of the data strobe signal input / output terminals DQS, / DQS and the phase of the signals of the data signal input / output terminals DQ0 to DQ7 will be shifted by half a wavelength.

[0183] Furthermore, the phases of the signals of the data signal input / output terminals DQ0 to DQ7 may be delayed by a half wavelength by the phase adjustment circuit PAC mounted on the memory die MD1. In this case, in the data bus between the memory dies MD0 and MD1, the phases of the signals of the data strobe signal input / output terminals DQS and / DQS and the phases of the signals of the data signal input / output terminals DQ0 to DQ7 will match.

[0184] Also, the phases of the signals of the data signal input / output terminals DQ0 to DQ7 may be delayed by a quarter wavelength each by the phase adjustment circuits PAC mounted on the memory dies MD0 and MD1. In this case, in the data bus between the memory dies MD0 and MD1, the phases of the signals of the data signal input / output terminals DQ0 to DQ7 will be delayed by a quarter wavelength compared to the phases of the signals of the data strobe signal input / output terminals DQS and / DQS.

[0185] [Second Embodiment] In the first embodiment, the memory system 10 capable of executing the inter-chip copy operation of copying the user data Dat from one of the two memory dies MD to the other was described. In the second embodiment, the memory die MD2 capable of executing the inter-plane copy operation of copying the user data Dat from one of the two memory cell arrays MCA to the other will be described.

[0186] [Configuration] FIG. 25 is a schematic block diagram showing the configuration of the memory die MD2 according to the second embodiment. FIG. 26 is a schematic circuit diagram showing a part of the configuration of the memory die MD2. For convenience of explanation, some configurations are omitted in FIGS. 25 and 26.

[0187] Furthermore, in the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

[0188] The memory die MD2 according to the second embodiment is basically configured in the same manner as the memory die MD according to the first embodiment. However, as shown in FIG. 26, the memory die MD2 according to the second embodiment includes a multiplexer MPX2 instead of the multiplexer MPX. Also, the memory die MD2 according to the second embodiment includes a sequencer SQC2 instead of the sequencer SQC. Further, the input / output control circuit I / O of the memory die MD2 includes an oscillation circuit OSC (timing signal generation circuit). Also, the memory die MD2 according to the second embodiment includes a logic circuit CDRL2 instead of the logic circuit CDRL.

[0189] The multiplexer MPX2 is basically configured in the same manner as the multiplexer MPX. However, the multiplexer MPX2 includes a transfer circuit TRC. The transfer circuit TRC is a bidirectional buffer capable of inputting user data Dat output from a certain memory cell array MCA (in the illustrated example, memory cell array MCA0) in the memory die MD2 to another memory cell array MCA (in the illustrated example, memory cell array MCA1) in the memory die MD2. Also, when the transfer circuit TRC inputs the user data Dat output from the memory cell array MCA0 to the memory cell array MCA1, it is possible for the transfer circuit TRC not to output this user data Dat to the data bus DB.

[0190] The sequencer SQC2 is basically configured in the same manner as the sequencer SQC.

[0191] However, as described with reference to FIG. 8, the sequencer SQC includes signal lines DIN and DOUT. The signal line DIN is commonly connected to a plurality of column decoders COLD. Also, the signal line DOUT is commonly connected to a plurality of column decoders COLD.

[0192] On the one hand, as shown in FIG. 26, the sequencer SQC2 includes signal lines DIN0, DIN1, DOUT0, and DOUT1. The signal lines DIN0 and DOUT0 are connected to the column decoder COLD corresponding to the memory cell array MCA0, and are not connected to the column decoder COLD corresponding to the memory cell array MCA1. The signal lines DIN1 and DOUT1 are connected to the column decoder COLD corresponding to the memory cell array MCA1, and are not connected to the column decoder COLD corresponding to the memory cell array MCA0.

[0193] When executing the inter-plane copy operation and copying the user data Dat from the memory cell array MCA0 to the memory cell array MCA1, the signal lines DOUT0 and DIN1 are in the active state, and the signal lines DOUT1 and DIN0 are not in the active state. On the other hand, when copying the user data Dat from the memory cell array MCA1 to the memory cell array MCA0, the signal lines DOUT1 and DIN0 are in the active state, and the signal lines DOUT0 and DIN1 are not in the active state.

[0194] The oscillation circuit OSC is commonly connected to a plurality of column decoders COLD. When executing the inter-plane copy operation and copying the user data Dat from the memory cell array MCA0 to the memory cell array MCA1, the column decoder COLD corresponding to the memory cell array MCA0 outputs the user data Dat and the timing signal according to the timing signal output from the oscillation circuit OSC. The user data DAT is input to the column decoder COLD corresponding to the memory cell array MCA1 according to the timing signal output from the column decoder COLD corresponding to the memory cell array MCA0.

[0195] Basically, the logic circuit CDRL2 is configured in the same way as the logic circuit CDRL. However, the logic circuit CDRL2 includes a data bus with a number of bits that can be connected to both latch circuits BCL0 and BCL1. For example, the logic circuit CDRL2 includes a data bus with a number of bits that is twice the number of bits of the column address CA.

[0196] [Inter-plane Copy Operation] Next, with reference to FIGS. 27 to 29, the inter-plane copy operation will be described. FIGS. 27 to 29 are schematic block diagrams for explaining the inter-plane copy operation.

[0197] When copying user data Dat written in a certain memory cell array MCA (in the illustrated example, memory cell array MCA0) in memory die MD2 to another memory cell array MCA (in the illustrated example, memory cell array MCA1) in memory die MD2, for example, first, the above-described read operation and data out are executed, and as shown in FIG. 27, it is conceivable to transfer user data Dat from memory cell array MCA0 to controller die CD. Next, the above-described write operation is executed, and as shown in FIG. 28, it is conceivable to transfer the read user data Dat to memory cell array MCA1.

[0198] Here, during the execution of the operations corresponding to timings t240 to t244 described with reference to FIG. 14 (the operation of transferring user data Dat from memory die MD2 to controller die CD), the data bus between controller die CD and memory die MD2 is occupied. Therefore, at this timing, the operations corresponding to timings t330 to t333 described with reference to FIG. 15 (the operation of transferring user data Dat from controller die CD to memory die MD2) cannot be executed.

[0199] Therefore, memory die MD2 according to this embodiment is configured to be capable of executing an inter-plane copy operation. In the inter-plane copy operation, as shown in FIG. 29, user data Dat is directly transferred from memory cell array MCA0 to memory cell array MCA1 without passing through controller die CD. At this time, the operations corresponding to timings t240 to t244 described with reference to FIG. 14 and the operations corresponding to timings t330 to t333 described with reference to FIG. 15 are executed in parallel.

[0200] According to such a method, the time required to copy user data Dat between memory cell arrays MCA0 and MCA1 can be significantly reduced.

[0201] Also, in the inter-plane copy operation according to this embodiment, the multiplexer MPX2 electrically disconnects the signal path between the column decoder COLD and the data bus DB, and does not output the user data Dat to the data bus between the controller die CD and the memory die MD2. Also, the input / output control circuit I / O does not input the signal of the data bus between the controller die CD and the memory die MD2 into the memory die MD2 during the execution of the inter-plane copy operation. Therefore, at the timing when one of the plurality of memory dies MD2 is executing the inter-plane copy operation, the controller die CD can input the user data Dat to other memory dies MD2 or be input with the user data Dat output from other memory dies MD.

[0202] In addition, in the inter-plane copy operation, the user data Dat output from the memory cell array MCA0 is not input to the controller die CD. Also, the controller die CD does not output the user data Dat input to the memory cell array MCA1.

[0203] Next, with reference to FIG. 30, the inter-plane copy operation will be described more specifically.

[0204] FIG. 30 is a schematic waveform diagram for explaining the inter-plane copy operation.

[0205] Furthermore, in the figure, "DOUT0", "DOUT1", "DIN0", and "DIN1" respectively indicate the signals of signal lines DOUT0, DOUT1, DIN0, and DIN1. Also, "OSC" indicates the timing signal output from the oscillation circuit OSC. "S1" indicates the timing signal transferred from the column decoder COLD corresponding to the memory cell array MCA0 to the column decoder COLD corresponding to the memory cell array MCA1. "S0" indicates the user data Dat transferred from the memory cell array MCA0 to the memory cell array MCA1.

[0206] Although illustration is omitted, in the plane - to - plane copy operation as well as in the chip - to - chip copy operation, in the same way as described with reference to FIG. 19, a command set for reading user data Dat from a plurality of memory cells MC in the memory cell array MCA0 into the memory die MD2, and a command set for writing user data Dat into a plurality of memory cells MC in the memory cell array MCA1 are input.

[0207] At the timing t500 in FIG. 30, the signals of signal lines DOUT0 and DIN1 are rising from "L" to "H". Thereby, the transfer direction of the user data Dat is indicated to the transfer circuit TRC in the multiplexer MPX2.

[0208] Also, at timings t501 to t502, the oscillation circuit OSC outputs a timing signal. Accordingly, the column decoder COLD corresponding to the memory cell array MCA0 outputs the user data Dat in the latch circuit XDL0 to the transfer circuit TRC together with the timing signal. The column decoder COLD corresponding to the memory cell array MCA1 receives the transferred user data Dat in response to the timing signal transferred from the column decoder COLD corresponding to the memory cell array MCA0. The column decoder COLD corresponding to the memory cell array MCA0 transfers the transferred user data Dat to the latch circuit XDL1.

[0209] Furthermore, the user data Dat and the timing signal in the memory cell array MCA0 are not output to the data bus between the controller die CD and the memory die MD2.

[0210] When the output of the timing signal ends at timing t502, the transfer of the user data Dat also ends.

[0211] Thereafter, the user data Dat in the latch circuit XDL1 is written into the memory cell array MCA1.

[0212] [Role of the logic circuit CDRL2 in the inter-plane copy operation] Next, the role of the logic circuit CDRL2 in the inter-plane copy operation will be described.

[0213] In the timings t501 to t502 of the inter-plane copy operation described with reference to FIG. 30, the multiplexer MPX2 (FIG. 26) accesses in parallel to the sense amplifiers SA0 and SA1. Therefore, it is necessary to select appropriate bits with reference to the column address CA of the defective column in the memory cell array MCA0 stored in the latch circuit BCL0 and the column address CA of the defective column in the memory cell array MCA1 stored in the latch circuit BCL1 in parallel.

[0214] For this reason, the logic circuit CDRL2 includes a data bus with a number of bits that can be connected to both of the latch circuits BCL0 and BCL1.

[0215] [Other embodiments] As described above, the semiconductor memory devices according to the first and second embodiments have been described. However, these are merely examples, and specific configurations and the like can be adjusted as appropriate.

[0216] For example, the memory die MD according to the first embodiment may also include an oscillation circuit OSC, similar to the memory die MD2 according to the second embodiment. In such a case, at the timings t460 to t463 of the inter-chip copy operation, the controller die CD does not necessarily have to switch the input signals of the control terminals / RE, RE. Also, the timing for outputting the user data Dat from the memory die MD0 and the timing for inputting the user data Dat to the memory die MD1 may be specified by the timing signal output from the oscillation circuit OSC.

[0217] In such a case, for example, it is also conceivable to provide a plurality of switch circuits between the system implementation substrate SSB and the plurality of packages PKG. Also, when the inter-chip copy operation is being performed in one of the plurality of packages PKG, it is also conceivable to electrically disconnect this one package PKG from the system implementation substrate SSB. According to such a method, at the timing when one of the plurality of packages PKG is executing the inter-chip copy operation, the controller die CD can input the user data Dat to the memory die MD in other packages PKG or be input with the user data Dat output from the memory die MD in other packages PKG.

[0218] Similarly, the memory die MD2 does not necessarily have to include an oscillation circuit OSC. In such a case, at the timings t501 to t502 of the inter-plane copy operation, the controller die CD may switch the input signals of the control terminals / RE, RE. Also, the timing for outputting the user data Dat from the memory die MD0 and the timing for inputting the user data Dat to the memory die MD1 may be specified by the input signals of the control terminals / RE, RE.

[0219] Also, for example, the memory die MD2 does not necessarily have to include a phase adjustment circuit PAC.

[0220] [Others] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0221] CD... controller die, / CE, CA1(CLE), CA0(ALE), CA_clk( / WE), / RE, RE, / WP... control terminals, MC... memory cell (memory cell transistor), MCA... memory cell array, MD... memory die, PC... peripheral circuit, ADR... address register, CMR... command register.

Claims

1. Comprising a plurality of memory chips, Each of the plurality of memory chips, A memory cell array, A first pad electrode to which write data written to the memory cell array is input and which outputs read data read from the memory cell array, A second pad electrode to which a first timing signal is input when the write data is input and which outputs the first timing signal when the read data is output, A phase adjustment circuit for adjusting the phase of the first timing signal input from the second pad electrode, A control circuit connected to the phase adjustment circuit And comprising, Input of a first command set for instructing output of the read data to a first memory chip among the plurality of memory chips, Input of a second command set for instructing input of the write data to a second memory chip among the plurality of memory chips In response to, The control circuit of the first memory chip executes output of the read data from the first memory chip, The control circuit of the second memory chip executes input of the write data for inputting the read data output from the first memory chip as the write data to the second memory chip in parallel with output of the read data from the first memory chip, One or both of the phase adjustment circuit of the first memory chip and the phase adjustment circuit of the second memory chip adjusts the phase of the read data signal or the first timing signal Memory system.

2. Further comprising a controller connected to the plurality of memory chips, When outputting the read data from the first memory chip according to the first command set, the read data read from the first memory chip is not input to the controller The memory system according to claim 1.

3. Further comprising a controller connected to the plurality of memory chips, When inputting the write data to the second memory chip according to the second command set, the controller does not output the write data input to the second memory chip The memory system according to claim 1.

4. Further comprising a controller connected to the plurality of memory chips, After the input of the first command set and the input of the second command set, the controller outputs a second timing signal. The memory system according to claim 1.

5. Further comprising a timing signal generation circuit that outputs a second timing signal, According to the input of the first command set and the input of the second command set, the timing signal generation circuit of the first memory chip inputs the second timing signal to the second memory chip. The semiconductor memory device according to claim 1.

6. A plurality of memory cell arrays, A pad electrode to which write data to be written to any of the plurality of memory cell arrays is input, and that outputs read data read from any of the plurality of memory cell arrays, A data transfer circuit provided in a data transfer path for transferring the write data and the read data between the plurality of memory cell arrays and the pad electrode, A plurality of data input circuits provided corresponding to the plurality of memory cell arrays, electrically connected to the data transfer circuit, and inputting the write data to the corresponding memory cell array, A plurality of data output circuits provided corresponding to the plurality of memory cell arrays, electrically connected to the data transfer circuit, and outputting the read data from the corresponding memory cell array, A control circuit electrically connected to the data transfer circuit, the plurality of data input circuits, and the plurality of data output circuits, A plurality of first signal lines provided corresponding to the plurality of data input circuits, and electrically connected to the plurality of data input circuits, the data transfer circuit, and the control circuit, A plurality of second signal lines provided corresponding to the plurality of data output circuits, and electrically connected to the plurality of data output circuits, the data transfer circuit, and the control circuit A semiconductor memory device comprising.

7. The input of a first command set for instructing the output of the read data to the first memory cell array among the plurality of memory cell arrays, The input of a second command set for instructing the input of the write data to the second memory cell array among the plurality of memory cell arrays According to, The control circuit is, Executes the output of the read data from the first memory cell array, In parallel with the output of the read data from the first memory cell array, the input of the write data is executed, which inputs the read data output from the first memory cell array to the second memory cell array as the write data. The semiconductor memory device according to claim 6.

8. In response to the input of the first command set and the input of the second command set, the control circuit Among the plurality of first signal lines, those corresponding to the first memory cell array are set to an active state. Among the plurality of second signal lines, those corresponding to the second memory cell array are set to an active state. The semiconductor memory device according to claim 7.

9. When outputting the read data from the first memory cell array according to the first command set, the control circuit does not output the read data read from the first memory cell array from the pad electrode. The semiconductor memory device according to claim 7.

10. When inputting the write data to the second memory cell array according to the second command set, the write data input to the second memory cell array is not input to the pad electrode. The semiconductor memory device according to claim 7.

11. A plurality of decode circuits provided corresponding to the plurality of memory cell arrays and provided in the data transfer path between the plurality of memory cell arrays and the data transfer circuit. A timing signal generation circuit electrically connected to the plurality of decode circuits and outputting a timing signal. The semiconductor memory device according to claim 7, further comprising the above.

12. In response to the input of the first command set and the input of the second command set, the timing signal generation circuit inputs the timing signal to the decode circuit corresponding to the first memory cell array among the plurality of decode circuits. The semiconductor memory device according to claim 11.

13. In response to the timing signal, the decode circuit corresponding to the first memory cell array among the plurality of decode circuits outputs the read data from the first memory cell array to the data transfer circuit. The semiconductor memory device according to claim 12.

14. A plurality of registers provided corresponding to the plurality of memory cell arrays, in which the column addresses of the defective columns of the corresponding memory cell arrays are recorded. A first data bus that can be connected to one of the plurality of registers and is electrically connected to the data transfer circuit; A second data bus that can be connected to another one of the plurality of registers and is electrically connected to the data transfer circuit The semiconductor memory device according to claim 7, further comprising.

15. In response to the input of the first command set and the input of the second command set, the data transfer circuit Refers to the column address of the defective column corresponding to the first memory cell array via the first data bus, Refers to the column address of the defective column corresponding to the second memory cell array via the second data bus The semiconductor memory device according to claim 14.

Images