Current regulator system

Abstract

To provide a switching power supply circuit that extends an operation life of a battery.SOLUTION: A power supply system (100) includes a switching voltage regulator (102). The switching voltage regulator (102) includes at least one switch (104) configured to conduct an input current to generate an output voltage responsive to a switching signal and based on an input voltage. The system also includes a current regulator (106) configured to generate a current sample voltage based on an amplitude of the input current relative to a reference current defining a maximum average amplitude setpoint of the input current to set a switching time of the at least one switch (104). The system also includes a switch controller (110) configured to provide the switching signal to control the at least one switch (104) based on an amplitude of the output voltage relative to a reference voltage and based on the switching time.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This description generally relates to electronic circuits, and more particularly to current regulator systems.

Background Art

[0002] Power circuits can be implemented in a variety of different ways. Examples of power circuits include any of synchronous rectifier power converters, asynchronous rectifier power converters, resonant power converters, and various other types of switching power converters. Thus, a typical power circuit can activate one or more switches to convert an input voltage to an output voltage. Power circuits are typically implemented in wireless electronic devices. As a result, the input voltage is typically provided by a battery. Thus, the operating life of the battery is typically limited by the amplitude of the input current provided from the input voltage to generate the output voltage in the power circuit. For example, in a switching power circuit that provides power through an inductor, the operating life of the battery can be based on the average amplitude of the input current through the operating cycle of the switching power circuit.

Summary of the Invention

[0003] An exemplary circuit includes a switching voltage regulator having a first input, a second input, and an output. The first input is coupled to a source of input current. A current regulator has an input, a first output, and a second output. The input is coupled to a source of input current. The current regulator provides a comparison signal having a logic state responsive to a current sampling voltage at the first output. The current regulator provides a reference current at the second output that is proportional to a maximum average amplitude set point of the input current over the switching period of the switching voltage regulator. A switch controller has a first input, a second input, a third input, and an output, the first input being coupled to the first output of the current regulator circuit. The second input is coupled to the output of the switching voltage regulator and the third input is adapted to be coupled to a reference voltage source. The output is coupled to the second input of the switching voltage regulator.

[0004] An example of a power supply system includes a switching voltage regulator that includes at least one switch configured to conduct an input current to generate an output voltage based on an input voltage in response to a switching signal. The system also includes a current regulator configured to generate a current sample voltage based on an amplitude of the input current relative to a reference current that defines a maximum average amplitude set point of the input current, for setting a switching time that defines a switching period of the at least one switch. The system also includes a switch controller configured to provide a switching signal for controlling the at least one switch based on an amplitude of the output voltage relative to a reference voltage and based on the switching time.

[0005] An example of an integrated circuit (IC) includes a switching voltage regulator that includes at least one switch configured to conduct an input current to generate an output voltage based on an input voltage in response to a switching signal. The IC also includes a current regulator configured to generate a current sample voltage across a sampling capacitor. The current sample voltage can be based on an amplitude of the input current relative to a reference current that is set at a first external pin and is proportional to a maximum average amplitude set point of the input current, for setting a switching time that defines a switching period of the at least one switch. The IC includes an input pin adapted to be coupled to a source of the reference current. The IC further includes a switch controller configured to provide a switching signal for controlling the at least one switch based on an amplitude of the output voltage relative to a reference voltage set at a second external pin and based on the switching time.

Brief Description of the Drawings

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[0019] This description generally relates to electronic circuits, and more particularly, to current regulator systems. A current regulator system may be included in a power supply system such as a switching power supply system. The power supply system may also include a switching voltage regulator that is controlled by a switch signal to provide an input current from an input voltage through an inductor and generate an output voltage. The power supply system further includes a switch controller configured to generate a switch signal based on, for example, an output voltage with respect to a reference voltage and a current sampling voltage having an amplitude related to the switching time of the switching voltage regulator to adjust the amplitude of the input current.

[0020] As an example, the input voltage is provided from a battery. Therefore, the current regulator system may be configured to adjust the amplitude of the input current to reduce the current draw from the battery, and thus extend the operating life of the battery. The current regulator system may include a sampling capacitor configured to generate a current sampling voltage based on a sampling current. The sampling current may be based on a charging current related to the input current and a reference current. As an example, the charging current is generated based on the input current and is proportional to the input current. As another example, the charging current is a current having a fixed amplitude that is presumed to be proportional to the input current. The reference current may have an amplitude proportional to the maximum average amplitude set point of the input current over a switching period.

[0021] The current sampling voltage may have an amplitude based on subtracting a reference current from the amplitude of a charging current during a first switching phase of a switching voltage regulator. For example, the reference current is arranged to flow from a sampling capacitor. Accordingly, during the first switching phase of the switching voltage regulator, the amplitude of the current sampling voltage may increase. During a second switching phase of the switching voltage regulator, the amplitude of the current sampling voltage may be based only on the reference current, and as a result, during the second switching phase of the switching voltage regulator, the amplitude of the current sampling voltage may decrease. The duration of time from the start of charging of the sampling capacitor in a first sampling phase to the end of discharging of the sampling capacitor in a second sampling phase (e.g., between equal charges of approximately zero) may define the switching time of the switching voltage regulator. Accordingly, the switch controller may monitor the amplitude of the current sampling voltage to switch between switching phases of the switching voltage regulator and thus adjust the amplitudes of the output voltage and the input current.

[0022] FIG. 1 is an example of a block diagram of a power supply system 100. The power supply system 100 may be implemented in any of a variety of wireless electronic devices, such as any of a laptop computer, a tablet computer, a smartphone, or any of various other types of electronic devices. The power supply system 100 is configured to generate an output voltage V IN from an input voltage V OUT . As an example, the input voltage V IN is provided from a battery. As described herein, the power supply system 100 provides regulation of an input current I IN drawn from the battery to reduce the average amplitude of the input current I IN and thus may extend the operating life of the battery. As an example, the power supply system 100 is fabricated on or as part of an integrated circuit (IC).

[0023] The power supply system 100 includes at least one switch 104 controlled by each respective at least one switching signal shown as signal SS in the example of FIG. 1, and an input voltage V IN based on which an output voltage V OUT is generated by a switching voltage regulator 102. As an example, the switching voltage regulator 102 operates as a buck regulator or a boost regulator and / or operates in buck and boost modes to generate an output voltage V OUT . For example, the switch 104 includes a high-side switch (e.g., a p-channel field-effect transistor (PFET)) and a low-side transistor (e.g., an n-channel field-effect transistor (NFET)), which are alternately activated to provide current through an inductor to generate an output voltage V OUT at the output of the switching voltage regulator 102. As described herein, the activation of the switch 104 can be defined by switching phases that define changes in the current through the inductor, such as a first switching phase and a second switching phase, which collectively define the switching period of the switching voltage regulator 102.

[0024] The power supply system 100 also includes a current regulator system 106 configured to adjust the amplitude of the input current I IN . As described above, the input current I IN can be drawn from the battery to extend the operating life of the battery by monitoring and adjusting the amplitude of the input current I IN . In the example of FIG. 1, the current regulator system 106 includes a reference current generator 108 configured to generate a reference current having an amplitude proportional to a maximum average amplitude set point of the input current I IN over the switching period. As an example, the reference current generator 108 is set (e.g., as a grounded resistor) to an external pin of the associated IC in which the power supply system 100 is fabricated.

[0025] The current regulator system 106 includes an input current I INBased on the charging current related thereto, and also based on a reference current, a current sampling voltage V SMPL may include a sampling capacitor configured to generate. As an example, the charging current is an input current I IN generated based on, and is a current proportional to the input current I IN . As another example, the charging current is a current having a fixed amplitude estimated to be proportional to the input current. For example, the charging current and the reference current are each proportional in amplitude with respect to the input current I IN , and as a result, the reference current is proportional to the maximum average amplitude set point of the input current I IN over the switching period.

[0026] As an example, the current sampling voltage V SMPL has an amplitude based on the amplitude obtained by subtracting the reference current from the charging current during the first switching phase of the switching voltage regulator 102 as defined by the switching signal SS. For example, the reference current flows from the sampling capacitor so as to draw current from the charging current provided to the sampling capacitor. Accordingly, during the first switching phase of the switching voltage regulator 102, the amplitude of the current sampling voltage V SMPL can increase and can be proportional to the detected amplitude of the input current I IN . During the second switching phase of the switching voltage regulator 102, the amplitude of the current sampling voltage V SMPL can be based on the reference current but not on the charging current. For example, the switching signal SS can include a signal that operates a switch to control the charging current provided to the sampling capacitor. Accordingly, during the second switching phase of the switching voltage regulator 102, the amplitude of the current sampling voltage V SMPL can decrease and can thus be proportional to the target adjusted amplitude of the input current I IN .

[0027] For example, the current regulator system 106 is substantially zero volts across the sampling capacitor, and thus the current sampling voltage V SMPLincludes a sampling comparator configured to identify substantially zero-volt amplitude. As described herein, the term "substantially" can include a certain degree of deviation from an exact value (e.g., + / - 5%). Thus, the sampling comparator can identify an amplitude substantially equal to the current sampling voltage V across both ends of the sampling capacitor at the start and end of a given switching period of the switching voltage regulator 102. In the example of FIG. 1, the output of the sampling comparator is shown as the comparison signal CMP1. SMPL at the start and end of a given switching period of the switching voltage regulator 102. In the example of FIG. 1, the output of the sampling comparator is shown as the comparison signal CMP1.

[0028] The power supply system 100 further includes a switch controller 110. The switch controller 110 is configured to provide a switching signal SS in response to the comparison signal CMP1. For example, the sampling comparator monitors the amplitude of the current sampling voltage V SMPL to switch from the second switching phase of the switching voltage regulator 102 to the first switching phase of the switching voltage regulator 102, and thus to the next switching period of the switching voltage regulator 102. The next switching period can also be started based on the amplitude of the output voltage V REF with respect to the reference voltage V OUT . As an example, the reference voltage V REF can be set at an external pin of the associated IC in which the power supply system 100 is fabricated (e.g., as a fixed voltage source). Thus, the switch controller 110 can control the switching time of the switching voltage regulator 102 based on the amplitude of the current sampling voltage V SMPL . For example, the switch controller 110 also includes a state machine configured to generate the switching signal SS based on the amplitude of the current sampling voltage V SMPL , and the amplitude of the output voltage V REF with respect to the reference voltage V OUT , etc.

[0029] The switch controller 110 when the current sampling voltage V SMPLAs a result of controlling the switching period of the switching voltage regulator 102 based on this, the power supply system 100 adjusts the amplitude of the input current I IN to reduce the power consumption from the associated battery, thereby extending the operating life of the battery. For example, implementing the reference current generator 108 to draw a reference current from the sampling capacitor, and by providing a switching period transition over the time when the starting amplitude of the current sampling voltage V SMPL is approximately equal to the final amplitude of the current sampling voltage V SMPL in the second switching phase, the power supply system 100 can reduce the average amplitude of the input current I IN throughout the switching period of the switching voltage regulator 102. Accordingly, the power supply system 100 can extend the operating life of the battery that provides the input voltage V IN . Also, as will be described in more detail herein, the power supply system 100 can operate in any of various waveforms of the current through the inductor of the switching voltage regulator 102.

[0030] FIG. 2 is an example of a schematic electrical circuit diagram of the power supply circuit 200. The power supply circuit 200 can be implemented in any of various wireless electronic devices, such as any of a laptop computer, a tablet computer, a smartphone, or other various electronic devices. The power supply circuit 200 is configured to generate an output voltage V IN from an input voltage V OUT . The power supply circuit 200 can be the power supply system 100 in the example of FIG. 1. Accordingly, in the following description of the example of FIG. 2, reference is made to the example of FIG. 1.

[0031] The power supply circuit 200 includes a switching voltage regulator 202. The switching voltage regulator 202 includes a high-side switch shown as PFET P1, a low-side switch shown as NFET N1, a first output switch shown as NFET N2, and a second output switch shown as NFET N3. PFET P1 is connected to the input voltage V INConnect them to each other at the source and at the switching node 204 at the drain. The NFET N1 connects the switching node 204 at the drain and to the source shown as grounded in the example of FIG. 2 at the low voltage rail. The NFET N2 OUT connects the output voltage V at the drain and to the switching node 206 at the source. The NFET N3 connects the switching node 206 at the drain and to the low voltage rail at the source. The inductor L1 interconnects the switching nodes 204 and 206 and is configured to conduct the current I L .

[0032] The PFET P1 is controlled by the switching signal IN1, the NFET N1 is controlled by the switching signal IN2, the NFET N2 is controlled by the switching signal OUT1, and the NFET N3 is controlled by the switching signal OUT2. A series of activations of the FETs P1, N1, N2, and N3 each provide the current I L through the inductor L1 in the switching phases defined by the switching signals IN1, IN2, OUT1, and OUT2. For example, the activation of the PFET P1 and the NFET N3 provides the input current I IN flowing from the input voltage V to the switching node 204 during the first switching phase based on the switching signals IN1 and OUT2, such that during the first switching phase of the switching voltage regulator 202, the current I IN is approximately equal to the input current I L . During the second switching phase of the switching voltage regulator 202, the PFET P1 and the NFET N3 are deactivated and the NFET N1 and the NFET N2 are activated by the switching signals IN2 and OUT1 to conduct the current I IN from the low voltage rail through the inductor L1. L

[0033] ​FIG. 3 is an example of a timing diagram. The timing diagram includes a first timing diagram 302 plotted as a function of time for a converter operating in a buck mode, and a second timing diagram 304 plotted as a function of time for a converter operating in a boost mode. The inductor current I L shown in FIG. 302 and the inductor current I L shown in FIG. 304 are included. The inductor current I L can be the current through the inductor L1 of the switching voltage regulator 202 in the example of FIG. 2. Therefore, in the following description of the example of FIG. 3, the example of FIG. 2 is referred to. For simplicity, the transition times of the timing diagrams 302 and 304 are aligned. However, the transition times can be different between the buck mode and the boost mode.

[0034] In the first timing diagram 302, the switching voltage regulator 202 starts the first switching phase at time T0. At time T0, the PFET P1 and the NFET N3 are activated by the switching signals IN1 and OUT2, respectively. Therefore, the input current I IN flows from the input voltage V IN , through the PFET P1, as the current I L , through the inductor L1, and through the NFET N3. Therefore, in the example of FIG. 3, the current I L is shown as an increase from an amplitude of I L0 that is zero or greater to an amplitude of I L1 at time T1. At time T1, the NFET N3 is deactivated by the switching signal OUT2, and the NFET N2 is activated by the switching signal OUT1. Therefore, the input current I IN flows from the input voltage V IN , through the PFET P1, as the current I L , through the inductor L1, and through the NFET N2, for example to charge the output capacitor (not shown in the example of FIG. 2). Therefore, in the example of FIG. 3, the current I L is, at time T2, from an amplitude of I L1 to an amplitude of I L2is shown as an increase to, and thus as an increase with a gentler slope than between times T0 and T1.

[0035] The switching voltage regulator 202 switches from the first switching phase to the second switching phase at time T2. At time T2, the PFET P1 is deactivated, the NFET N1 is activated, and the NFET N2 remains activated, respectively, by the switching signals IN1 and IN2. Thus, the input current I IN stops, and the current I L flows from the low voltage rail, through the NFET N1, through the inductor L1, and through the NFET N2. Thus, in the example of FIG. 3, the current I L is shown as a decrease in amplitude from I L2 to amplitude I L3 , and the amplitude I L3 is smaller than the amplitude I L1 . At time T3, the NFET N2 is deactivated by the switching signal OUT1, and the NFET N3 is activated by the switching signal OUT2. Thus, the current I L flows from the low voltage rail, through the NFET N1, through the inductor L1, and through the NFET N3. Thus, in the example of FIG. 3, the current I L is shown as a decrease in amplitude from I L3 to the initial amplitude I L0 at time T4. The second switching phase ends at time T4. The first and second switching phases may define a switching period, such that in the example of FIG. 3, the next switching period is shown as starting at time T4. For example, an idle time during which the current I L remains zero may occur during the switching period, such as during deactivation of the power supply circuit 200 or during a discontinuous mode of operation of the power supply circuit 200.

[0036] The second timing diagram 304 is arranged similarly to the first timing diagram 302 and may define a boost operation mode of the power supply circuit 200. As an example, the boost operation mode is based on a change in the topology of the power supply circuit 200 and the current IL The amplitude of is changed. Therefore, the second timing diagram 304 is illustrated to show that the operating principle of the power supply circuit 200 is applicable to any of the various inductor current waveforms, as described herein.

[0037] Referring back to the example of FIG. 2, the power supply circuit 200 includes a current regulator system 208 configured to adjust the amplitude of the input current I IN . As described above, the input current I IN can be drawn from the battery, and thus, as a result of monitoring and adjusting the amplitude of the input current I IN , it may be possible to extend the operating life of the battery. In the example of FIG. 2, the current regulator system 208 is coupled to the switching node 204 via a first switch SW1 controlled by a switching signal S1, and is coupled to the input voltage V IN via a second switch SW2 controlled by a switching signal S2. The transconductance amplifier 210 includes a first input. The transconductance amplifier 210 is also coupled to the input voltage V IN via a third switch SW3 controlled by a switching signal S3, and has a second input coupled to a third switching node 212. The third switching node 212 is coupled to the input voltage V IN via a PFET P2. As an example, the PFET P2 is a replica switch with respect to the PFET P1, and as a result, the PFET P2 has a channel width reduced by a factor of K with respect to the PFET P1. In the example of FIG. 2, the PFET P2 is activated by a switching signal IN1, and as a result, the PFET P2 is activated simultaneously with the PFET P1 to generate a charging current I CH having an amplitude approximately equal to the value obtained by dividing the amplitude of the input current I IN by K (e.g., I CH = I IN / K).

[0038] The transconductance amplifier 210 is configured to generate a signal CT provided to the PFET P3 to provide a charging current I to the sampling node 214 via a switch SW4 controlled by a switching signal S4. A sampling capacitor C CH interconnects the sampling node 214 and the node 220. The sampling node 214 and the node 220 are also coupled by a switch SW5 controlled by a switching signal S5. A voltage source 218 provides an offset voltage V S to the node 220. Also, a switch SW6 controlled by a switching signal S6 interconnects the sampling node 214 and the node 216, and a switch SW7 controlled by a switching signal S7 interconnects the nodes 216 and 220. OFF

[0039] The current regulator system 208 also includes a current source 222 coupled to the sampling node 214 via a switch SW8 controlled by a switching signal S8. The current source 222 can be the reference current generator 108 in the example of FIG. 1. For example, the current source 222 is provided at an external pin of the associated IC in which the power supply circuit 200 is fabricated (e.g., as a grounded resistor). Thus, when the switch SW8 is closed, the current source 222 is configured to conduct a reference current I S from the sampling node 214, and thus from the sampling capacitor C REF . For example, an offset voltage V OFF (e.g., about 350 mV) provides sufficient headroom for the reference current I REF . As described above, the reference current I REF can have an amplitude proportional to the maximum average amplitude set point of the input current I IN over the switching period of the switching voltage regulator 202. For example, the proportionality of the reference current I IN to the maximum average amplitude set point of the input current I REF is a coefficient of K, and thus is scaled in the same way as a proportionality constant as the charging current I CH . As an example, the reference current I​REF has an amplitude represented as follows. I REF = I TAR / K Equation 1 where I TAR is the maximum average amplitude set point of the input current I over the switching period of the switching voltage regulator 202. IN

[0040] The current regulator system 208 also includes a sampling comparator 224 having inputs at nodes 216 and 220. Thus, the sampling comparator 224 is configured to monitor the sampling voltage V on the sampling capacitor C when the switch SW6 is closed (e.g., based on the common mode operation defined by the offset voltage V). The sampling comparator 224 may generate a first comparison signal CMP1 in response to a determination that the sampling voltage V has an amplitude that is approximately zero. OFF S SMPL SMPL

[0041] The power supply circuit 200 further includes a switch controller 226. The switch controller 226 includes a state machine 228. The first comparison signal CMP1 is provided to the state machine 228 which also receives a second comparison signal CMP2 from a reference comparator 230. In the example of FIG. 2, the reference comparator 230 is configured to compare the output voltage V with a fixed reference voltage V. Based on the comparison signals CMP1 and CMP2, the state machine 228 may generate switching signals IN, OUT, and S provided to the respective PFETs P1 - P3, NFETs N1 - N3, and switches SW1 - SW8. Thus, the state machine 228 may define the first and second switching phases of the switching voltage regulator 202, and thus the switching period of the switching voltage regulator 202. The state machine 228 also provides control for operating the switches SW1 - SW8 to regulate the input current I. OUT REF IN ​​​​​​​To adjust the amplitude, in each of the first and second switching phases, the operation of the current regulator system 208 can be provided.

[0042] The exemplary power supply circuit 200 can be configured differently from that shown in the example of FIG. 2. For example, the switching voltage regulator 202 is not limited to the arrangement of the high-side and low-side switches P1, N1, N2, and N3. As an example, the PFET P1, and its extension, the replica PFET P2, are arranged as n-channel transistors instead.

[0043] The operation of the power supply circuit 200 is shown in more detail in FIGS. 4-6. FIG. 4 is another example of a timing diagram. The timing diagram includes a first timing diagram 402 showing the inductor current I plotted as a function of time for a converter operating in buck mode. L The first timing diagram 402 is thus the same as the first timing diagram 302 in the example of FIG. 3. A second timing diagram 404 is the sampled voltage V plotted as a function of time. SMPL FIG. 5 is an example of a schematic electrical circuit diagram 500 of the current flow within the power supply circuit 200 in the first switching phase of the switching voltage regulator 202, and FIG. 6 is an example of a schematic electrical circuit diagram 600 of the current flow within the power supply circuit 200 in the second switching phase of the switching voltage regulator 202. Thus, in the following description, reference is made to the examples of FIGS. 4-6.

[0044] In the first timing diagram 402, the switching voltage regulator 202 starts the first switching phase at time T0. At time T0, the PFET P1 and the NFET N3 are activated by the switching signals IN1 and OUT2, respectively. Also, referring to the example of FIG. 5, the switches SW1, SW4, SW7, and SW8 are closed by the switching signals S1, S4, S7, and S8, respectively. Thus, the input current I IN flows from the input voltage V IN through the PFET P1 and the current I Lflows through the inductor L1 and through the NFET N3. Thus, in the example of FIG. 4, the current I L is shown as an increase from the amplitude of I L0 to the amplitude I L1 .

[0045] At time T1, the NFET N3 is deactivated by the switching signal OUT2 and the NFET N2 is activated by the switching signal OUT1. Thus, the input current I IN flows from the input voltage V IN , through the PFET P1, through the inductor L1 as the current I L , and through the NFET N2. Thus, the current I L continues to increase in amplitude from time T1 to time T2 during the first switching phase of the switching voltage regulator 202. Further referring to the example of FIG. 5, during the first switching phase defined between time T0 and time T2, the input current I IN is emulated by the charging current I CH through the replica PFET P2 based on the matched PFET P1 and P2 that are simultaneously activated by the switching signal IN1, where the charging current I CH has a scaled amplitude that is approximately equal to the amplitude of the input current I IN divided by the channel width scaling factor K (e.g., I CH = I IN / K).

[0046] Due to the closing of the switch SW1, the transconductance amplifier 210 receives substantially equal voltages at each of the inputs at the switching node 204 and the node 212 due to the high gain of the transconductance amplifier 210. The transconductance amplifier 210 can be configured as a high bandwidth transconductance amplifier 210 to track the slope of the current I L (e.g., the input current I IN during the first switching phase of the switching voltage regulator 202), and the current I LIt can be configured using a low offset to measure. The low offset can be implemented, for example, by providing trimming, calibration, or chopping of the transconductance amplifier 210, or by providing an auto-zero technique using switches SW2 and SW3 as detailed herein.

[0047] The transconductance amplifier 210 provides a control signal CT to PFET P3 and conducts the charging current I CH through PFET P3 and through switch SW4 to the sampling node 214. Based on the closing of switch SW8, while the charging current I CH is provided to the sampling node 214, the reference current I REF flows from the sampling node 214. As a result, the sampling current I S is provided through the sampling capacitor C SMPL . Therefore, the current I SMPL has an amplitude equal to the charging current I CH minus the reference current I REF . Thus, the sampling current I SMPL starts to charge the sampling capacitor C S and increases the amplitude of the sampling voltage V SMPL . During the first switching phase of the switching voltage regulator 202, since switch SW6 is open and switch SW7 is closed, the sampling comparator 224 is not monitoring the sampling voltage V SMPL . Therefore, the first comparison signal CMP1 is asserted in the logic high state.

[0048] Referring back to FIG. 4, the switching voltage regulator 202 switches from the first switching phase to the second switching phase at time T2. At time T2, the PFET P1 is deactivated, the NFET N1 is activated, and the NFET N2 remains activated, respectively, by the switching signals IN1 and IN2. Also, referring to the example of FIG. 6, the switches SW1, SW4, and SW7 are opened by the switching signals S1, S4, and S7, respectively, and the switches SW2, SW3, and SW6 are closed by the switching signals S2, S3, and S6, respectively. The switch SW8 remains closed during the second switching phase of the switching voltage regulator 202. Therefore, the input current I IN stops, and the current I L flows from the low voltage rail, through the NFET N1, through the inductor L1, and through the NFET N2. Therefore, in the example of FIG. 4, the current I L is shown as a decrease from the amplitude I L2 to the amplitude I L3 at time T3. At time T3, the NFET N2 is deactivated by the switching signal OUT1, and the NFET N3 is activated by the switching signal OUT2. Therefore, the current I L flows from the low voltage rail, through the NFET N1, through the inductor L1, and through the NFET N3. Therefore, in the example of FIG. 4, the current I L is shown as a decrease from the amplitude I L3 at time T4 to the initial amplitude I L0 .

[0049] Referring to the example of FIG. 6, in the second switching phase of the switching voltage regulator 202, both the PFET P1 and P2 are deactivated, thereby stopping the flow of the input current I IN , and by extension, the charging current I CH stops. The switches SW2 and SW3 are closed to provide zeroing of the transconductance amplifier 210. Since the charging current I CH stops flowing, the charging current I CHis no longer provided to the sampling node 214. However, switch SW8 is still closed during the second switching phase of the switching voltage regulator 202, and as a result, the reference current I REF continues to draw charge from the sampling capacitor C S . As a result, the sampling voltage V SMPL decreases during the second switching phase of the switching voltage regulator 202 starting at time T2.

[0050] Due to switch SW6 being closed, the sampling comparator 224 compares the sampling voltage V SMPL at the sampling node 214 with the voltage at node 220, and thus monitors the voltage across the sampling capacitor C S . In response to the sampling voltage V SMPL having an amplitude that is approximately zero, and thus the sampling capacitor C S having an electric charge that is approximately zero, the sampling comparator 224 may de-assert the first comparison signal CMP1. As described herein, the zero amplitude of the sampling voltage V SMPL refers to an amplitude that is approximately zero across the sampling capacitor C OFF with reference to the offset voltage V SMPL at node 220. The zero amplitude of the sampling voltage V S may also refer to an amplitude that is approximately negative of the sampling voltage V SMPL based on the sampling capacitor C S , such that the inverting input of the sampling comparator 224 has a voltage amplitude that is greater than the sampling voltage V SMPL at the non-inverting input of the sampling comparator 224. SMPL

[0051] In response to the de-assertion of the first comparison signal CMP1, in response to the logic low amplitude of the second comparison signal CMP2 as provided by the reference comparator 230 (e.g., the reference voltage V REF is the output voltage V OUTIn response to being greater than), the state machine 228 may change the states of the switching signals IN, OUT, and S. Accordingly, the state machine 228 can switch the switching voltage regulator 202 from the second switching phase to the first switching phase, and thus to the start of the next switching period. Accordingly, the state machine 228 can adjust the amplitude of the input current I IN by instructing the duration of the switching period of the switching voltage regulator 202 based on the amplitude of the input current I REF with respect to the reference current I IN (e.g., based on the sampling voltage V SMPL ).

[0052] As an example, at the end of the switching period, the state machine 228 implements an idle (e.g., sleep) mode for the power supply circuit 200, such as based on an inactivation mode for the power supply circuit 200 or a discontinuous operation mode for the switching voltage regulator 202. For example, during the idle mode, the switch SW8 can be opened by the switching signal S8 to disconnect the reference voltage I S from the sampling capacitor C REF . Also, the switches SW2 and SW3 can remain closed to provide zeroing of the transconductance amplifier 210, the switch SW5 can be closed by the switching signal S5 to provide zeroing of the sampling capacitor C S , and the switch SW6 can remain closed to latch the first comparison signal CMP1 provided by the sampling comparator 224. The state machine 228 can thus wait for a change in the state of the second comparison signal CMP2 to start the next switching period.

[0053] Since the power supply circuit 200 provides the switching time based on the amplitude of the input current I REF with respect to the reference current I IN (e.g., based on the sampling voltage V SMPL ), the power supply circuit 200 adjusts the input current I INThe amplitude can be adjusted. For example, as described above, the current adjustment of the power supply circuit 200 is not limited to a triangular inductor current waveform with an initial zero amplitude as in the case of a typical power supply circuit, but is implemented for a more complex waveform of the inductor current I L or a non-zero initial amplitude of the inductor current I L . Also, the power supply circuit 200 provides a real-time measurement of the input current I IN during each cycle of the switching voltage regulator 202, and thus provides the actual peak amplitude of the inductor current I L . This is in contrast to adjusting the input current based on an estimated fixed peak current amplitude provided in a typical power supply circuit. Further, a typical power supply circuit requires a plurality of capacitors to compare a plurality of charges (e.g., the charge transmitted from the input and the charge of the desired average input current) to perform input current adjustment. The power supply circuit 200 includes only a single capacitor (e.g., the sampling capacitor C S ) for current control, and thus can provide a more compact circuit and eliminate the requirement for matching between two or more capacitors. Therefore, the input current adjustment provided by the power supply circuit 200 can be substantially more efficient than the input current adjustment of a typical power supply circuit.

[0054] FIG. 7 is another example of a schematic electrical circuit diagram of a power supply circuit 700. The power supply circuit 700 can be implemented in any of various wireless electronic devices such as any of a laptop computer, a tablet computer, a smartphone, or any of other various electronic devices. The power supply circuit 700 converts an input voltage V IN to an output voltage V OUTconfigured to generate. The power supply circuit 700 can be the power supply system 100 in the example of FIG. 1. Accordingly, reference is also made to FIG. 1 for the description of the example of FIG. 7. The power supply circuit 700 in the example of FIG. 7 is provided as another example of a current control technique that implements an open-loop topology (described in more detail herein) for the transconductance amplifier, as opposed to the closed-loop topology for the transconductance amplifier 210 in the example of FIG. 2. Accordingly, the power supply circuit 700 does not necessarily require stability compensation, and as a result, based on a smaller inductance of the inductor L1, the inductor current I L supports a high slope of.

[0055] The power supply circuit 700 includes a switching voltage regulator 702. The switching voltage regulator 702 includes a high-side switch shown as PFET P1, a low-side switch shown as NFET N1, a first output switch shown as NFET N2, and a second output switch shown as NFET N3. PFET P1 interconnects at the source with the input voltage V IN and at the drain with the switching node 704. NFET N1 interconnects at the drain with the switching node 704 and at the source with the low voltage rail grounded as shown in the example of FIG. 7. NFET N2 interconnects at the drain with the output voltage V OUT and at the source with the switching node 706. NFET N3 interconnects at the drain with the switching node 706 and at the source with the low voltage rail. The inductor L1 interconnects the switching nodes 704 and 706 and is configured to conduct the current I L through.

[0056] PFET P1 is controlled by switching signal IN1, NFET N1 is controlled by switching signal IN2, NFET N2 is controlled by switching signal OUT1, and NFET N3 is controlled by switching signal OUT2. The sequential activation of FETs P1, N1, N2, and N3 results in a current I through inductor L1 during switching phases defined by switching signals IN1, IN2, OUT1, and OUT2, respectively. L For example, activation of PFET P1 is based on switching signal IN1 during the first switching phase by decreasing input voltage V IN to the switching node 704. IN and thus the current I L represents the input current I during the first switching phase of the switching voltage regulator 702. IN During a second switching phase of switching voltage regulator 702, PFET P1 is deactivated by switching signal IN2 and NFET N1 is activated to supply current I L from the low voltage rail through inductor L1. Thus, switching voltage regulator 702 operates substantially similarly to switching voltage regulator 202 in the example of FIG.

[0057] The power supply circuit 700 also receives an input current I IN 7, the current regulator system 708 is coupled to the switching node 704 via a first switch SW1 controlled by a switching signal S1, and coupled to the input voltage V via a second switch SW2 controlled by a switching signal S2. IN The first transconductance amplifier 710 also includes a first input coupled to an input voltage V IN The current regulator system 708 also has a second input coupled to a node 714 and receives an input voltage V through a switch SW3 controlled by a switching signal S3.IN The first and second transconductance amplifiers 710 and 712 may be fabricated substantially similarly and therefore may have substantially equal transconductance (GM) coefficients. The second transconductance amplifier 712 also receives an input voltage V IN Node 714 is coupled to the input voltage V through a PFET P2. IN As an example, PFET P2 is a replica switch with respect to PFET P1, so that PFET P2 has a channel width that is scaled down by a factor of K relative to PFET P1.

[0058] In the example of FIG. 7, PFET P2 is activated by switching signal IN1, which results in PFET P2 being activated simultaneously with PFET P1, and the reference current I generated by current source 716. REF via switch SW4, which is controlled by switching signal S4. Current source 716 may be reference current generator 108 in the example of FIG. 1. For example, current source 716 is provided (e.g., as a resistor to ground) at an external pin of the associated IC in which power supply circuit 700 is fabricated. Thus, when switch SW4 is closed, current source 716 conducts reference current I REF is the input voltage V IN 1 through PFET P2. As described above, the reference current I REF is the input current I of the switching voltage regulator 702 IN For example, the input current I IN The maximum average amplitude set point (I TAR (expressed as) REF The proportionality of is similarly scaled by a factor of K, as provided in Equation 1 above.

[0059] The first transconductance amplifier 710 provides a charging current I to a sampling node 718 via a switch SW5 controlled by a switching signal S5. CHis configured to generate. For example, the charging current I CH has an amplitude that is expressed as follows. I CH =GM×I IN ×R DSON Equation 2 Here, GM is the transconductance of the first transconductance amplifier 710, and R DSON is the activation resistance of PFET P1. Also, the second transconductance amplifier 712 is configured to generate the current I R provided via the diode-connected NFET N4 through the switch SW6 controlled by the switching signal S6. As an example, in the example of FIG. 7, the amplitude of the current I R is expressed as follows. I R =GM×I TAR ×K×R DSON Equation 3 Here, GM is the transconductance of the second transconductance amplifier 712, which is approximately equal to the transconductance of the first transconductance amplifier 710. K×R DSON is the activation resistance of PFET P2, which is approximately equal to K times the activation resistance of PFET P1.

[0060] The diode-connected NFET N4 has a gate and a drain coupled to the gate of the sample-and-hold capacitor C1 and the gate of NFET N5 through the switch SW7 controlled by the switching signal S7. Accordingly, NFETs N4 and N5 are arranged as a current mirror, and when the switch SW7 is closed to charge the capacitor C1, the current I R is provided to the capacitor C1. The voltage V1 on the capacitor C1 thus provides the activation voltage for NFET N5 and mirrors the current I R through NFET N5. Accordingly, NFET N5 also conducts the current I R .

[0061] Similar to the power supply circuit 200, the sampling node 718 is coupled to a sampling capacitor C S and has a sampling voltage V SMPL . The sampling capacitor C S interconnects the sampling node 718 and the node 720. The sampling node 718 and the node 720 are also coupled by a switch SW8 controlled by a switching signal S8. A voltage source 722 provides an offset voltage V OFF to the node 720. Also, a switch SW9 controlled by a switching signal S9 interconnects the sampling node 718 and the node 724, and a switch SW 10 controlled by a switching signal S 10 interconnects the nodes 720 and 724. In the example of FIG. 7, the NFET N5 is coupled to the sampling node 718 at its drain. Thus, the NFET N5 is configured to conduct a current I S from the sampling node 718 and thus from the sampling capacitor C R . For example, an offset voltage V OFF (e.g., about 350 mV) provides sufficient headroom for the current I R .

[0062] The current regulator system 708 includes a sampling comparator 726 having inputs at nodes 724 and 720. Thus, the sampling comparator 726 is configured to monitor the sampling voltage V OFF on the sampling capacitor C S when the switch SW9 is closed (e.g., based on a common mode operation defined by an offset voltage V SMPL ). The sampling comparator 726 may generate a first comparison signal CMP1 in response to determining that the sampling voltage V SMPL has an amplitude that is approximately zero.

[0063] The power supply circuit 700 further includes a switch controller 728 including a state machine 730. A first comparison signal CMP1 is provided to the state machine 730 that also receives a second comparison signal CMP2 from a reference comparator 732. In the example of FIG. 7, the reference comparator 732 is configured to compare the output voltage V OUT with a fixed reference voltage V REF . Based on the comparison signals CMP1 and CMP2, the state machine 730 can generate switching signals IN, OUT, and S provided to respective PFETs P1 - P3, NFETs N1 - N3, and switches SW1 - SW 10 , respectively. Thus, the state machine 730 can define the first and second switching phases of the switching voltage regulator 702, and thus the switching period of the switching voltage regulator 702. The state machine 730 can also provide control for operating the switches SW1 - SW 10 to provide operation of the current regulator system 708 in each of the first and second switching phases to adjust the amplitude of the input current I IN .

[0064] The power supply circuit 700 is not limited to the example shown in FIG. 7. For example, the switching voltage regulator 702 is not limited to the arrangement of the high - side and low - side switches P1, N1, N2, and N3. As an example, PFET P1, and its replica PFET P2 in its extension, are arranged as n - channel transistors instead.

[0065] The operation of the power supply circuit 700 is shown in more detail in FIGS. 4, 8, and 9. FIG. 8 is another example of a schematic electrical circuit diagram 800 of the current flow in the power supply circuit 700 in the first switching phase of the switching voltage regulator 702, and FIG. 9 is another example of a schematic electrical circuit diagram 900 of the current flow in the power supply circuit 700 in the second switching phase of the switching voltage regulator 702. Thus, the following description also refers to the examples of FIGS. 4, 8, and 9.

[0066] In the first timing diagram 402, the switching voltage regulator 702 starts the first switching phase at time T0. At time T0, PFET P1 and NFET N3 are activated by switching signals IN1 and OUT2, respectively. Also, referring to the example of FIG. 8, switches SW1, SW4, SW5, SW6, SW7, and SW 10 are closed by switching signals S1, S4, S5, S6, S7, and S 10 respectively. Accordingly, the input current I IN flows from the input voltage V IN , through PFET P1, as current I L , through inductor L1, and through NFET N3. Accordingly, in the example of FIG. 4, the current I L is shown as an increase from amplitude I L0 to amplitude I L1 .

[0067] At time T1, NFET N3 is deactivated by switching signal OUT2, and NFET N2 is activated by switching signal OUT1. Accordingly, the input current I IN flows from the input voltage V IN , through PFET P1, as current I L , through inductor L1, and through NFET N2. Accordingly, the current I L continues to increase in amplitude from time T1 to time T2 during the first switching phase of the switching voltage regulator 702. Also, referring further to the example of FIG. 8, during the first switching phase defined between time T0 and time T2, the input current I IN flows through PFET P1, and the reference current flows through PFET P2 based on PFET P1 and P2 that are simultaneously activated and matched by switching signal IN1. The first transconductance amplifier 710, based on the input current I IN , has a charging current I CH with an amplitude defined by Equation 2 above based on the closing of switch SW1.is generated. Similarly, the second transconductance amplifier 712 generates a current I having an amplitude defined by the above equation 3 based on the reference current and based on the closing of switch SW4. R is generated.

[0068] Based on the closing of switch SW5, the charging current I CH is provided from the first transconductance amplifier 710 to the sampling node 718. Based on the closing of switch SW6, the current I R is provided from the second transconductance amplifier 712 via NFET N4. The current I R charges the capacitor C1, provides a voltage V1 at the gate of NFET N5, and the current I R is mirrored from NFET N4 to NFET N5. As a result, a sampling current I S is provided via the sampling capacitor C SMPL . The current I SMPL therefore has an amplitude equal to that obtained by subtracting the current I CH from the charging current I R . Thus, the sampling current I SMPL starts to charge the sampling capacitor C S and increases the amplitude of the sampling voltage V SMPL . During the first switching phase of the switching voltage regulator 702, switch SW9 is open and switch SW 10 is closed, so the sampling comparator 726 does not monitor the sampling voltage V SMPL . Accordingly, the first comparison signal CMP1 is asserted in the logic high state.

[0069] Referring back to FIG. 4, at time T2, the switching voltage regulator 702 switches from the first switching phase to the second switching phase. At time T2, the PFET P1 is deactivated, the NFET N1 is activated, and the NFET N2 remains activated, respectively, by the switching signals IN1 and IN2. Also, referring to the example of FIG. 9, the switches SW1, SW4, SW5, SW6, SW7, and SW 10 are opened by the switching signals S1, S4, S5, S6, S7, and S 10 respectively, and the switches SW2, SW3, and SW9 are closed by the switching signals S2, S3, and S9 respectively. Accordingly, the input current I IN stops, and the current I L flows from the low voltage rail, through the NFET N1, through the inductor L1, and through the NFET N2. Therefore, in the example of FIG. 4, the current I L is shown as a decrease from the amplitude I L2 to the amplitude I L3 at time T3. At time T3, the NFET N2 is deactivated by the switching signal OUT1, and the NFET N3 is activated by the switching signal OUT2. Accordingly, the current I L flows from the low voltage rail, through the NFET N1, through the inductor L1, and through the NFET N3. Therefore, in the example of FIG. 4, the current I L is shown as a decrease from the amplitude I L3 to the initial I L0 at time T4.

[0070] Referring to the example of FIG. 9, in the second switching phase of the switching voltage regulator 702, both the PFET P1 and P2 are deactivated, thereby stopping the flow of the input current I IN , and the reference current I REF along with its extension. The switches SW2 and SW3 are closed to provide zeroing of the first and second transconductance amplifiers 710 and 712. The charging current I CHTo stop the flow from the first transconductance amplifier 710, the charging current I CH is not provided to the sampling node 718. Similarly, the current I R stops flowing from the second transconductance amplifier 712. However, the sampled voltage V1 across the capacitor C1 continues to provide activation of the NFET N5 during the second switching phase of the switching voltage regulator 702, and as a result, the current I R continues to draw charge from the sampling capacitor C S . As a result, the sampling voltage V SMPL decreases during the second switching phase of the switching voltage regulator 702 starting at time T2.

[0071] Due to the closing of the switch SW9, the sampling comparator 726 compares the sampling voltage V SMPL at the sampling node 718 with the voltage at the node 720, and thus monitors the voltage across the sampling capacitor C S . In response to the sampling voltage V SMPL having an amplitude that is approximately zero and thus the sampling capacitor C S having a charge that is approximately zero, the sampling comparator 726 may deassert the first comparison signal CMP1. In response to the deassertion of the first comparison signal CMP1 and in response to the logical low amplitude of the second comparison signal CMP2 as provided by the reference comparator 732 (e.g., in response to the reference voltage V REF being greater than the output voltage V OUT ), the state machine 730 may change the states of the switching signals IN, OUT, and S. Thus, the state machine 730 may switch the switching voltage regulator 702 from the second switching phase to the first switching phase and thus to the start of the next switching period. Thus, the state machine 730 is based on the amplitude of the input current I REF relative to the reference current I IN (e.g., the sampling voltage V SMPLBased on), it can indicate the duration of the switching period of the switching voltage regulator 702 and can adjust the amplitude of the input current I IN of.

[0072] Similar to the above, at the end of the switching period, the state machine 730 can implement an idle (e.g., sleep) mode for the power supply circuit 700 based on an inactivation mode for the power supply circuit 700 or a discontinuous operation mode for the switching voltage regulator 702, etc. For example, during the idle mode, the switches SW2 and SW3 remain closed, providing zeroing of the transconductance amplifiers 710 and 712, the switch SW8 is closed by the switching signal S8 to provide zeroing of the sampling capacitor C S of, the switch SW9 remains closed, providing zeroing of the sampling comparator 726. The state machine 730 can thus wait for a change in the state of the second comparison signal CMP2 to start the next switching period.

[0073] FIG. 10 is another example of a schematic electrical circuit diagram showing the current flow in the power supply circuit 1000. The power supply circuit 1000 can be implemented in any of various wireless electronic devices such as any of a laptop computer, a tablet computer, a smartphone, or any of other various electronic devices. The power supply circuit 1000 is configured to generate an output voltage V IN from an input voltage V OUT . The power supply circuit 1000 can be the power supply system 100 in the example of FIG. 1. Therefore, the description of FIG. 10 also refers to FIG. 1. The power supply circuit 1000 in the example of FIG. 10 provides another example of a current adjustment technique that implements estimated values for the peak and valley amplitudes of the inductor current I L . For example, the estimated values for the peak and valley amplitudes of the inductor current I L are calculated in any of various ways such as the operating mode of the power supply circuit 1000, the relative amplitudes of the input voltage V IN and the output voltage V OUT , the duty cycle, factory testing / calibration, or any of various methods.

[0074] The power supply circuit 1000 includes a switching voltage regulator 1002. The switching voltage regulator 1002 includes a high-side switch shown as PFET P1, a low-side switch shown as NFET N1, a first output switch shown as NFET N2, and a second output switch shown as NFET N3. PFET P1 interconnects with the input voltage V IN at the source and the switching node 1004 at the drain, and NFET N1 interconnects with the switching node 1004 at the drain and the low voltage rail at the source shown as ground in the example of FIG. 10. NFET N2 interconnects with the output voltage V OUT at the drain and the switching node 1006 at the source, and NFET N3 interconnects with the switching node 1006 at the drain and the low voltage rail at the source. Inductor L1 interconnects the switching nodes 1004 and 1006 and is configured to conduct the current I L .

[0075] PFET P1 is controlled by the switching signal IN1, NFET N1 is controlled by the switching signal IN2, NFET N2 is controlled by the switching signal OUT1, and NFET N3 is controlled by the switching signal OUT2. A series of activations of FETs P1, N1, N2, and N3 respectively provide the current I L through the inductor L1 in the switching phases defined by the switching signals IN1, IN2, OUT1, and OUT2. For example, the activation of PFET P1 causes the input current I IN to flow from the input voltage V IN to the switching node 1004 during the first switching phase based on the switching signal IN1, and as a result, the current I L flows through the input current I INMake it approximately equal to. During the second switching phase of the switching voltage regulator 1002, by the switching signal IN2, the PFET P1 is deactivated and the NFET N1 is activated to conduct the current I L from the low voltage rail through the inductor L1. Therefore, the switching voltage regulator 1002 operates substantially the same as the switching voltage regulator 202 in the example of FIG. 2.

[0076] The power supply circuit 1000 also includes a current regulator system 1008 configured to adjust the amplitude of the input current I IN . In the example of FIG. 10, the current regulator system 1008 includes a first current source 1010 that generates a first current I1, a second current source 1012 that generates a second current I2, and a third current source 1014 that generates a third current I3. As an example, as will be described in more detail herein, the combination of the currents I1, I2, and I3 is the charging current I CH during the first switching phase. The first current source 1010 interconnects the input voltage V IN , and a switch SW1 controlled by the switching signal S1. The second current source 1012 interconnects the input voltage V IN , and a switch SW2 controlled by the switching signal S2. The third current source 1014 interconnects the input voltage V IN , and a switch SW3 controlled by the first switching signal S3. The parallel arrangement of the current source 1010 and the switch SW1, the current source 1012 and the switch SW2, and the current source 1014 and the switch SW3 is arranged in series with a switch SW4 controlled by the switching signal S4.

[0077] The switch SW4 is coupled to the sampling node 1016. A sampling capacitor C S interconnects the sampling node 1016 and the node 1018. The sampling node 1016 and the node 1018 are also coupled to a switch SW5 controlled by the switching signal S5. A voltage source 1020 provides an offset voltage V OFFis provided to node 1018. Also, a switch SW6 controlled by a switching signal S6 interconnects the sampling node 1016 and the node 1022, and a switch SW7 controlled by a switching signal S7 interconnects the nodes 1018 and 1022.

[0078] The current regulator system 1008 also includes a current source 1024 coupled to the sampling node 1016 via a switch SW8 controlled by a switching signal S8. The current source 1024 can be the reference current generator 108 in the example of FIG. 1. For example, the current source 1024 is provided at an external pin of the associated IC in which the power supply circuit 1000 is fabricated (e.g., as a grounded resistor). Thus, when the switch SW8 is closed, the current source 1024 conducts a reference current I S from the sampling node 1016 and thus from the sampling capacitor C REF configured to conduct. For example, an offset voltage V OFF (e.g., about 350 mV) provides sufficient headroom for the reference current I REF . As described above, the reference current I REF can have an amplitude proportional to the maximum average amplitude set point of the input current I IN of the switching voltage regulator 1002. For example, the proportionality of the reference current I IN to the maximum average amplitude set point of the input current I TAR (represented as I REF ) is similarly scaled by a coefficient K as provided in Equation 1 above. Also, the current regulator system 1008 includes a current source 1026 coupled to the sampling node 1016 via a switch SW9 controlled by a switching signal S9. The current source 1026 generates a current I3 that is approximately equal to the current I3 generated by the current source 1014 described above.

[0079] The switching voltage regulator 1008 includes a sampling comparator 1028 having inputs at nodes 1018 and 1022. Thus, the sampling comparator 1028 has (e.g., an offset voltage V OFF(Based on the common mode operation defined by), when switch SW6 is closed, sampling capacitor C S The sampling voltage V on SMPL is configured to be monitored. Sampling comparator 1028 may generate a first comparison signal CMP1 in response to determining that the sampling voltage V SMPL has an amplitude that is approximately zero.

[0080] Power supply circuit 1000 further includes a switch controller 1030 that includes a state machine 1032. The first comparison signal CMP1 is provided to the state machine 1032 that also receives a second comparison signal CMP2 from a reference comparator 1034. In the example of FIG. 10, the reference comparator 1034 is configured to compare the output voltage V OUT with a reference voltage V REF . Based on the comparison signals CMP1 and CMP2, the state machine 1032 may generate switching signals IN, OUT, and S provided to respective PFET P1, NFET N1 - N3, and switches SW1 - SW9, respectively. Thus, the state machine 1032 may define the first and second switching phases of the switching voltage regulator 1002, and thus the switching period of the switching voltage regulator 1002. The state machine 1032 may also provide control to operate switches SW1 - SW9 and provide the operation of the current regulator system 1008 in each of the first and second switching phases to adjust the amplitude of the input current I IN .

[0081] Power supply circuit 1000 is not limited to the circuit shown in FIG. 10. For example, the switching voltage regulator 1002 is not limited to the arrangement of high - side and low - side switches P1, N1, N2, and N3. As an example, PFET P1 is arranged as an n - channel transistor instead.

[0082] The operation of the power supply circuit 1000 is shown in more detail in FIGS. 4 and 11 to 13. FIG. 11 is another example of a schematic electrical circuit diagram 1100 of the current flow in the power supply circuit 1000 in the first switching phase of the switching voltage regulator 1002, FIG. 12 is another example of a schematic electrical circuit diagram 1200 of the current flow in the power supply circuit 1000 in the first switching phase of the switching voltage regulator 1002, and FIG. 13 is another example of a schematic electrical circuit diagram 1300 of the current flow in the power supply circuit 1000 in the second switching phase of the switching voltage regulator 1002. Therefore, the description of FIG. 11 also refers to FIGS. 4 and 11 to 13.

[0083] In the first timing diagram 402, the switching voltage regulator 1002 starts the first switching phase at time T0. At time T0, the PFET P1 and the NFET N3 are activated by the switching signals IN1 and OUT2, respectively. Therefore, the input current I IN flows from the input voltage V IN , through the PFET P1, as the current I L , through the inductor L1, and through the NFET N3. Therefore, in the example of FIG. 4, the current I L is shown as an increase from the amplitude of I L0 to the amplitude I L1 .

[0084] Also, referring to FIG. 11, the switches SW1, SW4, SW7, and SW8 are closed by the switching signals S1, S4, S7, and S8, respectively, from time T0 to time T1. Therefore, from time T0 to T1, the current I1 flows from the current source 1010, through the closed switches SW1 and SW4, to the sampling node 1016. While the current I1 is being provided to the sampling node 1016, based on the closing of the switch SW8, the reference current I REF flows from the sampling node 1016. As a result, the sampling current I S is provided through the sampling capacitor C SMPL . The current I SMPLTherefore, it has an amplitude equal to that obtained by subtracting the reference current I from the current I1. Thus, the sampling current I REF starts to charge the sampling capacitor C SMPL and increases the amplitude of the sampling voltage V S from time T0 to time T1. During the first switching phase of the switching voltage regulator 1002, since the switch SW6 is open and the switch SW7 is closed, the sampling comparator 1028 does not monitor the sampling voltage V SMPL . Therefore, the first comparison signal CMP1 is asserted in the logic high state. SMPL Referring to the example of FIG. 4, at time T4, the NFET N3 is deactivated by the switching signal OUT2 and the NFET N2 is activated by the switching signal OUT1. Therefore, the input current I

[0085] flows from the input voltage V IN through the PFET P1, through the inductor L4 as the current I IN , and through the NFET N2. Therefore, the current I L continues to increase in amplitude from time T4 to time T2 during the first switching phase of the switching voltage regulator 1002. Also, referring to the example of FIG. 12, the switch SW1 is opened by the switching signal S1, the switches SW4, SW7, and SW8 remain closed, the switch SW2 is closed by the switching signal S2, and one of the switches SW3 and SW9 is closed by one of the switching signals S3 and S9, respectively, according to the operating mode of the switching voltage regulator 1002. L Referring to the example of FIG. 4, at time T4, the NFET N3 is deactivated by the switching signal OUT2 and the NFET N2 is activated by the switching signal OUT1. Therefore, the input current I

[0086] For example, in the case of the buck mode operation of the timing diagram 402 (and the timing diagram 302 in the example of FIG. 3), the switch SW3 is closed. However, in the case of the boost mode operation shown in the timing diagram 304 in the example of FIG. 3, the switch SW9 is closed instead. Therefore, in the buck operation mode, at the sampling node 1016, the amplitude of the current I3 is added to the amplitude of the current I2, or in the boost operation mode, the amplitude of the current I3 is subtracted from the amplitude of the current I2. The example of FIG. 12 shows an example where both switches SW3 and SW9 are closed simultaneously, but at a given time, only one of the switches SW3 and SW9 is closed according to the operation mode of the switching voltage regulator 1002. Therefore, the current I1 is the charging current I provided to the sampling node 1016 from time T0 to time T1 CH and the combination (addition or subtraction) of the currents I2 and I3 can be the charging current provided to the sampling node 1016 from time T1 to time T2 ICH and can be.

[0087] Based on the closing of the switch SW, the charging current I CH is provided to the sampling node 1016 during the first switching phase of the switching voltage regulator 1002. The charging current I CH is provided to the sampling node 1016 based on the closing of the switch SW8, and during this time, the reference current I REF flows from the sampling node 1016. As a result, the sampling current I S is provided through the sampling capacitor C SMPL . The current I SMPL therefore has an amplitude equal to that obtained by subtracting the reference current I CH from the charging current I REF . Thus, the sampling current I SMPL starts to charge the sampling capacitor C S and the sampling voltage V SMPLIncrease the amplitude. During the first switching phase of the switching voltage regulator 1002, since the switch SW6 is open and the switch SW7 is closed, the sampling comparator 1028 does not monitor the sampling voltage V SMPL . Therefore, the first comparison signal CMP1 is asserted in the logic high state.

[0088] Referring back to FIG. 4, the switching voltage regulator 1002 switches from the first switching phase to the second switching phase at time T2. At time T2, the PFET P1 is deactivated, the NFET N1 is activated, and the NFET N2 remains activated by the switching signals IN1 and IN2, respectively. Also, referring to the example of FIG. 13, the switches SW2, SW3, SW9, SW4, and SW7 are opened by the switching signals S1, S3, S9, S4, and S7, respectively, and the switch SW6 is closed by the switching signal S6. The switch SW8 remains closed during the second switching phase of the switching voltage regulator 1002. Therefore, the current I IN stops, and the current I L flows from the low voltage rail, through the NFET N1, through the inductor L1, and through the NFET N2. Therefore, in the example of FIG. 4, the current I L is shown as a decrease from the amplitude I L2 to the amplitude I L3 at time T3. At time T3, the NFET N2 is deactivated by the switching signal OUT1, and the NFET N3 is activated by the switching signal OUT2. Therefore, the current I L flows from the low voltage rail, through the NFET N1, through the inductor L1, and through the NFET N3. Therefore, in the example of FIG. 4, the current I L is shown as a decrease from the amplitude I L3 at time T4 to the initial amplitude I L0 .

[0089] Referring to the example of FIG. 13, in the second switching phase of the switching voltage regulator 1002, the currents I1, I2, and I3 stop. Accordingly, the charging current I CH stops flowing into the sampling node 1016. However, the reference current I REF continues to flow from the sampling node 1016 and continues to draw charge from the sampling capacitor C S . As a result, the sampling voltage V SMPL decreases during the second switching phase of the switching voltage regulator 1002 starting at time T2.

[0090] Due to the closing of the switch SW6, the sampling comparator 1028 compares the sampling voltage V SMPL at the sampling node 1016 with the voltage at the node 1018 and thus monitors the voltage across the sampling capacitor C S . In response to the sampling voltage V SMPL having a substantially zero amplitude and thus the sampling capacitor C S having a substantially zero charge, the sampling comparator 1028 may de-assert the first comparison signal CMP1. In response to the de-assertion of the first comparison signal CMP1 and also in response to the logic low amplitude of the second comparison signal CMP2 as provided by the reference comparator 1034 (e.g., in response to the reference voltage V REF being greater than the output voltage V OUT ), the state machine 1032 may change the states of the switching signals IN, OUT, and S. Accordingly, the state machine 1032 may switch the switching voltage regulator 1002 from the second switching phase to the first switching phase and thus to the start of the next switching period. Accordingly, the state machine 1032 may indicate the duration of the switching period of the switching voltage regulator 1002 based on the amplitude of the input current I REF relative to the reference current I IN (e.g., based on the sampling voltage V SMPL ) and adjust the amplitude of the input current I IN .

[0091] Similarly, at the end of the switching period, the state machine 1032 may implement an idle (e.g., sleep) mode for the power supply circuit 1000 based on an inactivation mode for the power supply circuit 1000, or a discontinuous operation mode for the switching voltage regulator 1002, etc. For example, during the idle mode, the switch SW8 is opened by the switching signal S8 to stop the flow of the reference current I REF and the switch SW5 is closed by the switching signal S5 to provide zeroing of the sampling capacitor C S . The switch SW6 may remain closed and latch the first comparison signal CMP1 provided by the sampling comparator 1028. The state machine 1032 may thus wait for a change in the state of the second comparison signal CMP2 to start the next switching period.

[0092] Therefore, the examples of FIGS. 7 to 13 illustrate another example of a power supply circuit that can adjust the input current I REF based on the amplitude of the input current I IN with respect to the reference current I (e.g., based on the sampling voltage V SMPL ). Therefore, similar to the power supply circuit 200, the power supply circuits 700 and 1000 can adjust the amplitude of the input current I IN in a more efficient manner than the input current adjustment in a typical power supply circuit. For example, as described above, the current adjustment of the power supply circuits 700 and 1000 is implemented for a more complex waveform of the inductor current I IN as well as for a non-zero initial amplitude of the inductor current I L . Also, the power supply circuit 700 provides a real-time measurement of the amplitude of the input current I L , and thus the inductor current I IN , during each cycle of the switching voltage regulator 702 in an open-loop manner that eliminates the need for stability compensation to limit the bandwidth. Alternatively, the power supply circuit 1000 provides a measurement of the estimated amplitude of the input current I L at each cycle of the switching voltage regulator 1002 and, compared to a typical power supply circuit, the input current I IN ​IN To provide a simpler circuit that can achieve excellent regulation. Thus, the input current regulation provided by power circuits 700 and 1000 can be substantially more effective than the input current regulation of typical power circuits.

[0093] As used herein, the term "coupled" may encompass a connection, communication, or signal path that enables a functional relationship consistent with the description herein. For example, if device A generates a signal for controlling control device B to perform a certain action, (a) in a first example, device A is directly coupled to device B, and (b) in a second example, device A is indirectly coupled to device B via an intermediate component C, provided that the intervening component C does not substantially alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0094] Also, in this description, a device “configured” to perform a certain task or function can be configured (e.g., programmed and / or hardwired) by the manufacturer at the time of manufacture to perform those functions, and / or they can be configurable (or reconfigurable) by the user after manufacture to perform those functions and / or other additional or alternative functions. Such configurations can be via the device's firmware and / or software programming, or via the hardware components, and the configuration and / or layout of the device's interconnections, or a combination thereof. Also, a circuit or device described as including certain components may instead be configured to couple to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (such as a semiconductor die and / or an integrated circuit (IC) package), and may be configured to couple to at least some of the passive elements and / or sources, thereby forming the described structure at any point in time during or after manufacture, e.g., by an end user and / or a third party.

[0095] Within the scope of the claims, changes are possible in the described embodiments, and other embodiments are possible.

Claims

1. 1. A circuit comprising: A switching voltage regulator; A current regulator; A switch controller, Including, the switching voltage regulator having a first input, a second input, and an output, the first input coupled to a source of input current; the current regulator having an input, a first output, and a second output, the input coupled to the source of the input current, the current regulator configured to provide a comparison signal at the first output having a logic state responsive to a current sampling voltage, the current regulator configured to provide a reference current at the second output proportional to a maximum average amplitude set point of the input current over a switching period of the switching voltage regulator; the switch controller having a first input, a second input, a third input, and an output, the first input coupled to the first output of the current regulator circuit, the second input coupled to the output of the switching voltage regulator, the third input adapted to be coupled to a reference voltage source, and the output coupled to the second input of the switching voltage regulator.

2. 2. The circuit of claim 1, 1. A circuit comprising: a sampling capacitor having an input for receiving a sampling current during a first switching phase of the switching voltage regulator responsive to a switching signal provided from the output of the switch controller, the sampling current having an amplitude equal to a charging current flowing into the sampling capacitor minus the reference current flowing from the sampling capacitor, the charging current having an amplitude responsive to the input current, and the sampling capacitor charging in response to the sampling current to generate the current sampling voltage.

3. 3. The circuit of claim 2, a sampling capacitor discharging during a second switching phase of the switching voltage regulator to reduce the current sampling voltage in response to the reference current flowing from the sampling capacitor, and a switch controller monitoring the current sampling voltage and switching from the second switching phase to the first switching phase in response to the current sampling voltage having approximately zero amplitude.

4. 3. The circuit of claim 2, 11. The circuit of claim 1, wherein the current regulator includes a transconductance amplifier configured to monitor the input current and generate the charging current responsive to the input current, the charging current having an amplitude scaled proportional to the input current.

5. 5. The circuit of claim 4, the transconductance amplifier is a first transconductance amplifier; The current regulator further comprises: a second transconductance amplifier configured to generate the reference current; a current mirror configured to mirror the reference current through a transistor coupled to the sampling capacitor; The circuit includes:

6. 3. The circuit of claim 2, the current regulator is configured to switch between a plurality of current sources configured to provide a respective plurality of currents to generate the charging current in response to at least one of a step-down and step-up operation of the switching voltage regulator.

7. 2. The circuit of claim 1, The switch controller, a sampling comparator having an input for receiving the current sampling voltage and an output for providing a first comparison signal; a reference comparator having a first input for receiving the output voltage and a second input for receiving a reference voltage, the reference comparator having an output for providing a second comparison signal; a state machine having a first input for receiving the first comparison signal and a second input for receiving the second comparison signal; Including, The circuit, wherein the state machine also has a first output providing a switching signal provided from the output of the switch controller, and a second output providing a switch control signal.

8. 8. The circuit of claim 7, the current regulator having a second input for receiving the switch control signal, the switch control signal controlling a switch to provide a current path for each of the input current and the reference current to generate the current sampling voltage in response to switching phases defined by the state machine.

9. 1. A power supply system, comprising: A switching voltage regulator; A current regulator; A switch controller, Including, the switching voltage regulator including at least one switch configured to conduct an input current and generate an output voltage responsive to a switching signal and an input voltage; the current regulator is configured to generate a current sample voltage in response to an amplitude of the input current relative to a reference current defining a maximum average amplitude set point of the input current to set a switching time defining a switching period of the at least one switch; The system, wherein the switch controller is configured to provide the switching signal to control the at least one switch in response to an amplitude of the output voltage relative to a reference voltage and in response to the switching time.

10. 10. The system of claim 9, the current regulator includes a sampling capacitor that samples a sampling current in a first switching phase of the switching voltage regulator in response to the switching signal to generate the current sampling voltage, the sampling current having an amplitude equal to a charging current flowing into the sampling capacitor minus the reference current flowing from the sampling capacitor, the charging current having an amplitude responsive to the input current.

11. 11. The system of claim 10, the sampling capacitor discharges during a second switching phase of the switching voltage regulator responsive to the reference current flowing from the sampling capacitor to reduce the current sampling voltage, the switch controller monitors the current sampling voltage and switches from the second switching phase to the first switching phase in response to the current sampling voltage having approximately zero amplitude, the switching time having an equal duration for the first and second switching phases.

12. 11. The system of claim 10, 11. The system of claim 1, wherein the current regulator includes a transconductance amplifier configured to monitor the input current and generate the charging current responsive to the input current, the charging current having an amplitude that is scaled proportionally to the input current.

13. 13. The system of claim 12, the transconductance amplifier is a first transconductance amplifier; The current regulator a second transconductance amplifier configured to generate the reference current; a current mirror configured to mirror the reference current through a transistor coupled to the sampling capacitor; The system further comprises:

14. 11. The system of claim 10, The current regulator is configured to switch between a plurality of current sources configured to provide respective plurality of currents to generate the charging current responsive to at least one of a step-down and step-up operation of the switching voltage regulator.

15. 1. An integrated circuit (IC), comprising: A switching voltage regulator; A current regulator; An input pin, A switch controller, Including, the switching voltage regulator including at least one switch configured to conduct an input current to generate an output voltage responsive to a switching signal and an input voltage; the current regulator is configured to generate a current sample voltage across a sampling capacitor, the current sample voltage being responsive to an amplitude of the input current relative to a reference current proportional to a maximum average amplitude set point of the input current to set a switching time defining a switching period of the at least one switch; the input pin is adapted to be coupled to a source of the reference current; The switch controller is configured to provide the switching signal to control the at least one switch in response to the switching time and in response to an amplitude of the output voltage relative to a reference voltage.

16. 16. The IC of claim 15, the sampling capacitor integrates a sampling current in a first switching phase of the switching voltage regulator in response to the switching signal to generate the current sampling voltage, the sampling current having an amplitude equal to a charging current flowing into the sampling capacitor minus the reference current flowing from the sampling capacitor; The charging current has an amplitude responsive to the input current.

17. 17. The IC of claim 16, the sampling capacitor discharges during a second switching phase of the switching voltage regulator in response to the reference current flowing from the sampling capacitor to reduce the current sampling voltage; the switch controller monitoring the current sampling voltage and switching from the second switching phase to the first switching phase in response to the current sampling voltage having an amplitude of approximately zero; The switching time has an equal duration to the first and second switching phases.

18. 17. The IC of claim 16, an input current regulator configured to generate a charging current in response to the input current, the charging current having an amplitude scaled proportional to the input current;

19. 20. The IC of claim 18, the transconductance amplifier is a first transconductance amplifier; The current regulator a second transconductance amplifier configured to generate the reference current; a current mirror configured to mirror the reference current through a transistor coupled to the sampling capacitor; The IC further comprises:

20. 17. The IC of claim 16, The current regulator is configured to switch between a plurality of current sources configured to provide respective plurality of currents to generate the charging current in response to at least one of a step-down and step-up operation of the switching voltage regulator.

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