Semiconductor device

Abstract

To provide a semiconductor device having different mesa structures on both sides.SOLUTION: A semiconductor device has a first groove 21 formed on one surface of a semiconductor wafer 20 or a semiconductor layer, and a second groove 22 formed on the other surface of the semiconductor wafer 20 or the semiconductor layer. In a plan view, a central portion 21a of the first groove 21 and a central portion 22a of the second groove 22 do not overlap each other, the central portion 21a of the first groove 21 has a width which is 50% of the surface groove width 21b of the first groove 21, and the central portion 22a of the second groove 22 has a width which is 50% of the surface groove width 22b of the second groove 22.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] FIG. 5 is a cross-sectional view of a conventional thyristor having a double-sided mesa structure. The dotted line in the drawing indicates a PN junction. By dicing along the one-dot chain line 111 on the drawing, a diced thyristor is manufactured. Passivation layers 112 are formed on both sides of the dicing portion. When manufacturing a semiconductor device (thyristor) having a mesa structure or a mesa planner structure in which grooves 113 and 114 filled with a passivation layer are formed on the front and back surfaces, it is necessary to form the grooves deep and wide in order to ensure high breakdown voltage and high reliability.

[0003] However, as shown in FIG. 5, if the grooves on the front surface 113 and the grooves on the back surface 114 are formed deep with the same positions, the grooves will penetrate each other at that time, and the chips will come off from the semiconductor wafer 20. Related techniques are disclosed in Patent Document 1. On the other hand, if the thickness of the semiconductor wafer 20 is increased, penetration between the grooves can be prevented even when deep grooves are formed, but the loss during energization of the thyristor increases.

[0004] Therefore, there is a demand for a thyristor that has grooves on both sides and does not penetrate through the grooves.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] By the way, a thyristor that does not allow the grooves to penetrate each other is required by forming a first groove on one side of a semiconductor wafer or a semiconductor layer, forming a second groove on the other side of the semiconductor wafer or the semiconductor layer, and arranging them so that the central portions of the first groove and the second groove do not overlap in plan view. When considering such a thyristor, it is conceivable that a thyristor having different mesa structures on the front and back of the semiconductor wafer or the semiconductor layer can be manufactured by using a semiconductor wafer or a semiconductor layer having a thickness such that the grooves do not penetrate each other.

[0007] Therefore, various aspects of the present invention aim to provide a semiconductor device having different mesa structures on both sides. Also, various aspects of the present invention aim to provide a semiconductor device that can prevent the grooves from penetrating each other even when the grooves are provided on both sides.

Means for Solving the Problems

[0008] Hereinafter, various aspects of the present invention will be described.

[0009] [1] A first groove formed on one side of a semiconductor wafer or a semiconductor layer, A second groove formed on the other side of the semiconductor wafer or the semiconductor layer, having In plan view, the central portions of the first groove and the second groove do not overlap, The central portion of the first groove has a width of 50% with respect to the surface groove width of the first groove, A semiconductor device, wherein the central portion of the second groove has a width of 50% with respect to the surface groove width of the second groove.

[0010] According to the semiconductor device of the above [1] according to one aspect of the present invention, since the central portions of the first groove and the second groove do not overlap in plan view, when a semiconductor wafer or a semiconductor layer having a thickness such that the grooves do not penetrate each other is used, a semiconductor device having different groove structures (mesa structures) on both sides of the semiconductor wafer or the semiconductor layer can be provided.

[0011] [2] In the above [1], A semiconductor device characterized in that the first groove and the second groove do not penetrate each other.

[0012] According to the semiconductor device of the above [2] according to one aspect of the present invention, a first groove is formed on one surface of a semiconductor wafer or a semiconductor layer, and a second groove is formed on the other surface of the semiconductor wafer or the semiconductor layer. In a plan view, the central portion of the first groove and the central portion of the second groove do not overlap. The central portion of the first groove has a width of 50% with respect to the surface groove width of the first groove, and the central portion of the second groove has a width of 50% with respect to the surface groove width of the second groove. The first groove and the second groove do not penetrate each other. Therefore, even if there are grooves on both sides and deep grooves are formed, since the central portion of the first groove and the central portion of the second groove do not overlap, it is possible to prevent penetration between the grooves.

[0013] [3] In the above [2], A semiconductor device characterized in that the first groove and the second groove do not overlap in a plan view.

[0014] According to the semiconductor device of the above [3] according to one aspect of the present invention, since the first groove and the second groove do not overlap in a plan view, even if there are grooves on both sides and deep grooves are formed, it is possible to prevent penetration between the grooves.

[0015] [4] In any one of the above [1] to [3], A first PN junction surface formed on one surface side of the semiconductor wafer or the semiconductor layer, A second PN junction surface formed on the other surface side of the semiconductor wafer or the semiconductor layer, having The first groove is formed deeper than the first PN junction surface, A semiconductor device characterized in that the second groove is formed deeper than the second PN junction surface.

[0016] According to the above [4] related to one aspect of the present invention, even if the first groove is formed deeper than the first PN junction surface and the second groove is formed deeper than the second PN junction surface, it is possible to prevent the grooves from penetrating each other.

[0017] [5] In the above [4], The semiconductor wafer or the semiconductor layer has a first P-type semiconductor layer, a first N-type semiconductor layer, and a second P-type semiconductor layer. The first PN junction surface is a junction surface between the first P-type semiconductor layer and the first N-type semiconductor layer. A semiconductor device, wherein the second PN junction surface is a junction surface between the first N-type semiconductor layer and the second P-type semiconductor layer.

[0018] According to the above [5] related to one aspect of the present invention, even if the first and second grooves are formed deeper, they do not penetrate each other, so a semiconductor device (thyristor) with high breakdown voltage and high reliability can be realized. In addition, since it is a structure that prevents the grooves from penetrating each other, it is not necessary to make the semiconductor layer thicker than necessary, and it is possible to suppress an increase in the loss during energization of the thyristor while ensuring high breakdown voltage and high reliability.

[0019] [6] In the above [5], A first passivation film is formed on the inner surface of the first groove formed on one surface of the semiconductor layer. A second passivation film is formed on the inner surface of the second groove formed on the other surface of the semiconductor layer. In a plan view, the first groove has a rectangular shape, and the second groove is located inside the first groove. A semiconductor device, wherein the first passivation film, the first N-type semiconductor layer, and the second P-type semiconductor layer have a cut surface cut along the center of the first groove.

[0020] [7] In the above [6], The thyristor structure has a second N-type semiconductor layer formed on the first P-type semiconductor layer or the second P-type semiconductor layer and electrically connected to the cathode electrode. It has a gate electrode electrically connected to the first P-type semiconductor layer or the second P-type semiconductor layer. It has an anode electrode electrically connected to the second P-type semiconductor layer or the first P-type semiconductor layer. A semiconductor device, wherein in a plan view, the anode electrode is surrounded by the second groove or the first groove.

[0021] [8] In the above [7], A semiconductor device, wherein in a plan view, the cathode electrode and the gate electrode are surrounded by the first groove or the second groove.

[0022] [9] In the above [6], The second P-type semiconductor layer has a thyristor structure in which a second N-type semiconductor layer electrically connected to the cathode electrode is formed. It has a gate electrode electrically connected to the second P-type semiconductor layer. It has an anode electrode electrically connected to the first P-type semiconductor layer. In a plan view, the anode electrode is surrounded by the first groove. A semiconductor device, characterized by having a current-carrying member provided with a conductive surface joined to the anode electrode.

[0023]

[10] In the above [9], The semiconductor device, characterized in that the current-carrying member is a lead frame or a heat sink. [Advantages of the Invention]

[0024] According to various aspects of the present invention, a semiconductor device having different mesa structures on both sides can be provided. Also, according to various aspects of the present invention, a semiconductor device can be provided that can prevent grooves from penetrating each other even when there are grooves on both sides. [Brief Description of the Drawings]

[0025]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below.

[0027] (First Embodiment) FIG. 1 is a cross-sectional view showing a semiconductor device according to one aspect of the present invention, and shows a case where the back surface as the anode surface has a mesa planner structure. FIG. 3(A) is a cross-sectional view showing a semiconductor device that is diced by cutting the semiconductor wafer 20 shown in FIG. 1 along the center of the first groove 21 and is electrically connected to the current-carrying member 51.

[0028] In the semiconductor device of the above [1] according to one aspect of the present invention, a first groove 21 is formed on one surface of the semiconductor wafer 20 or the semiconductor layer 120. A second groove 22 is formed on the other surface of the semiconductor wafer 20 or the semiconductor layer 120.

[0029] In the semiconductor device shown in FIG. 1, the first groove 21 and the second groove 22 are arranged so as not to overlap in a plan view. However, as shown in FIG. 4, in the plan view, the central portion 21a of the first groove 21 and the central portion 22a of the second groove 22 do not overlap, the central portion 21a of the first groove 21 has a width of 50% with respect to the surface groove width 21b of the first groove 21, and the central portion 22a of the second groove 22 may have a width of 50% with respect to the surface groove width 22b of the second groove 22.

[0030] According to the above semiconductor device, since the central portion 21a of the first groove 21 and the central portion 22a of the second groove 22 do not overlap in a plan view, when a semiconductor wafer 20 or a semiconductor layer 120 that is thick enough so that the grooves do not penetrate each other is used (in other words, when a thick semiconductor wafer 20 or a semiconductor layer 120 is used in which the positions of the grooves on one side and the grooves on the other side are the same and the grooves do not penetrate each other), a semiconductor device having different groove structures (mesa structures) on both surfaces of the semiconductor wafer 20 or the semiconductor layer 120 can be realized.

[0031] Also, if the first groove 21 and the second groove 22 overlap in a plan view, even when the thickness of the semiconductor wafer 20 is thin enough that there is a possibility of penetration by both grooves, as shown in FIG. 1, by arranging the first groove 21 and the second groove 22 so as not to overlap, it can be said that the first groove 21 and the second groove 22 do not penetrate. Also, if the central portion 21a of the first groove 21 and the central portion 22a of the second groove 22 overlap in a plan view, even when the thickness of the semiconductor wafer 20 is thin enough that there is a possibility of penetration by both grooves, as shown in FIG. 4, in the plan view, the central portion 21a of the first groove 21 has a width of 50% with respect to the surface groove width 21b of the first groove 21, the central portion 22a of the second groove 22 has a width of 50% with respect to the surface groove width 22b of the second groove 22, and by arranging the central portion 21a of the first groove 21 and the central portion 22a of the second groove 22 so as not to overlap, it can be said that the first groove 21 and the second groove 22 do not penetrate. In other words, even if grooves are formed on both surfaces and deep grooves are formed with respect to the thickness of the semiconductor wafer 20, since the central portion 21a of the first groove 21 and the central portion 22a of the second groove 22 do not overlap, penetration between the grooves can be prevented.

[0032] As shown in FIGS. 1 and 3(A), a first PN junction surface 31 is formed on one surface side of the semiconductor wafer 20 or the semiconductor layer 120, and a second PN junction surface 32 is formed on the other surface side of the semiconductor wafer 20 or the semiconductor layer 120. Also, the conductivity type of the semiconductor wafer 20 or the semiconductor layer 120 is N-type. That is, by introducing P-type impurities from both sides of the N-type semiconductor wafer 20, a first P-type semiconductor layer 11, a first N-type semiconductor layer 12, and a second P-type semiconductor layer 13 are formed on the semiconductor wafer 20 in this order from one surface side thereof. In other words, the semiconductor wafer 20 or the semiconductor layer 120 has a first P-type semiconductor layer 11, a first N-type semiconductor layer 12, and a second P-type semiconductor layer 13. The first PN junction surface 31 is the junction surface between the first P-type semiconductor layer 11 and the first N-type semiconductor layer 12, and the second PN junction surface 32 is the junction surface between the first N-type semiconductor layer 12 and the second P-type semiconductor layer 13. Also, the first groove 21 is formed deeper than the first PN junction surface 31, and the second groove 22 is formed deeper than the second PN junction surface 32.

[0033] As shown in FIGS. 1 and 3(A), a first groove 21 is formed on one surface of the semiconductor wafer 20 or the semiconductor layer 120, and a first passivation film 41 is formed on the inner surface of the first groove 21. A second groove 22 is formed on the other surface of the semiconductor wafer 20 or the semiconductor layer 120, and a second passivation film 42 is formed on the inner surface of the second groove 22. The first and second passivation layers 41, 42 are insulating layers made of a glass composition formed, for example, by electrophoresis. Also, in plan view, the first groove 21 has a rectangular shape (not shown), and the second groove 22 is located inside the first groove 21. The first passivation film 41, the first N-type semiconductor layer 12, and the second P-type semiconductor layer 13 have a cut surface cut along the center of the first groove 21 (see FIG. 3(A)). This cut surface is formed by cutting along the center of the first groove 21 of the semiconductor wafer 20 shown in FIG. 1, and the semiconductor layer 120 shown in FIG. 3(A) is formed.

[0034] As shown in FIGS. 1 and 3(A), a second N-type semiconductor layer 14 electrically connected to the cathode electrode K is formed in the first P-type semiconductor layer 11. The second N-type semiconductor layer 14 is formed by introducing N-type impurities into the first P-type semiconductor layer 11. Thereby, a thyristor structure is formed. Also, a gate electrode G electrically connected to the first P-type semiconductor layer 11 is formed on the first P-type semiconductor layer 11. Further, an anode electrode A electrically connected to the second P-type semiconductor layer 13 is formed under the second P-type semiconductor layer 13. The cathode electrode K and the gate electrode G are electrically insulated by an insulating layer 23. Also, each of the anode electrode A, the cathode electrode K, and the gate electrode G is formed by solder. Further, in a plan view, the anode electrode A is surrounded by a second groove 22. Also, in a plan view, the cathode electrode K and the gate electrode G are surrounded by a first groove 21.

[0035] The energizing member 51 shown in FIG. 3(A) is electrically connected to the anode electrode A, and the energizing member 51 is preferably a lead frame or a heat sink.

[0036] According to the present embodiment, a first groove 21 is formed on one surface of the semiconductor wafer 20 or the semiconductor layer 120, and a second groove 22 is formed on the other surface of the semiconductor wafer 20 or the semiconductor layer 120. In a plan view, the central portion 21a of the first groove 21 has a width of 50% with respect to the surface groove width 21b of the first groove 21, and the central portion 22a of the second groove 22 has a width of 50% with respect to the surface groove width 22b of the second groove 22, and the central portion 21a of the first groove 21 and the central portion 22a of the second groove 22 are arranged so as not to overlap. Thereby, the first groove 21 and the second groove 22 do not penetrate. Therefore, even if both surfaces have grooves and deep grooves are formed, since the central portion 21a of the first groove 21 and the central portion 22a of the second groove 22 do not overlap, it is possible to prevent the grooves from penetrating each other. Also, even if the first groove 21 is formed deeper than the first PN junction surface 31 and the second groove 22 is formed deeper than the second PN junction surface 32, it is possible to prevent the grooves from penetrating each other (see FIGS. 1 and 3(A)).

[0037] Also, according to the present embodiment, even if the first and second grooves 21 and 22 are formed deeply, they do not penetrate each other, so that a semiconductor device (thyristor) with high breakdown voltage and high reliability can be realized. Further, since it is a structure that prevents the grooves from penetrating each other, it is not necessary to make the semiconductor layer 120 thicker than necessary, and it is possible to suppress an increase in the loss during energization of the thyristor while ensuring high breakdown voltage and high reliability.

[0038] (Second Embodiment) FIG. 2 is a cross-sectional view showing a semiconductor device according to an aspect of the present invention, and shows a case where the surface as the cathode-gate surface has a mesa planner structure. FIG. 3(B) is a cross-sectional view showing a semiconductor device that is diced by cutting the semiconductor wafer 20 shown in FIG. 2 along the center of the first groove 21 and is electrically connected to the current-carrying member 51. FIG. 4 is a cross-sectional view for explaining a modified example of the semiconductor device shown in FIG. 2. Note that FIGS. 2, 3(B), and 4 are given the same reference numerals as the same parts in FIGS. 1 and 3(A), and the description of the same parts is omitted.

[0039] In the semiconductor device shown in FIG. 2, the first groove 21 and the second groove 22 are arranged so as not to overlap in plan view. However, as shown in FIG. 4, in plan view, the central portion 21a of the first groove 21 and the central portion 22a of the second groove 22 do not overlap, and the central portion 21a of the first groove 21 has a width of 50% with respect to the surface groove width 21b of the first groove 21, and the central portion 22a of the second groove 22 may have a width of 50% with respect to the surface groove width 22b of the second groove 22.

[0040] As shown in FIGS. 2 and 3(B), a second N-type semiconductor layer 14 electrically connected to the cathode electrode K is formed in the second P-type semiconductor layer 13. The second N-type semiconductor layer 14 is formed by introducing N-type impurities into the second P-type semiconductor layer 13. Thereby, a thyristor structure is formed. Also, a gate electrode G electrically connected to the second P-type semiconductor layer 13 is formed on the second P-type semiconductor layer 13. Further, an anode electrode A electrically connected to the first P-type semiconductor layer 11 is formed under the first P-type semiconductor layer 11. Also, in plan view, the anode electrode A is surrounded by the first groove 21. Also, in plan view, the cathode electrode K and the gate electrode G are surrounded by the second groove 22.

[0041] Also, as shown in FIG. 3(B), the anode electrode A is joined to the conductive surface 51a of the current-carrying member 51.

[0042] In this embodiment as well, the same effects as those of the first embodiment can be obtained.

[0043] Also, according to this embodiment, in plan view, the anode electrode A is surrounded by the first groove 21, and the first passivation film 41, the first N-type semiconductor layer 12, and the second P-type semiconductor layer 13 have a cut surface cut along the center of the first groove 21, and have a current-carrying member 51 having a conductive surface 51a joined to the anode electrode A. Therefore, the distance L1 between the conductive surface 51a joined to the anode electrode A shown in FIG. 3(B) and the groove bottom of the cut surface of the first groove 21 can be made longer than the distance L2 shown in FIG. 3(A). Thereby, the thyristor shown in FIG. 3(B) can enhance the reliability as a semiconductor device compared to the thyristor shown in FIG. 3(A). However, even the thyristor shown in FIG. 3(A) has sufficient reliability to withstand practical use.

Description of Reference Numerals

[0044] 11 First P-type semiconductor layer 12 First N-type semiconductor layer 13 Second P-type semiconductor layer 14 Second N-type semiconductor layer 20 Semiconductor wafer 21 First groove 21a Central part of the first groove 21b Surface groove width 22 Second groove 22a Central part of the second groove 22b Surface groove width 31 First PN junction surface 32 Second PN junction surface 41 First passivation film 42 Second passivation film 51 Current-carrying member 51a Conductive body surface 120 Semiconductor layer A Anode electrode K Cathode electrode G Gate electrode L1 Distance between the conductive body surface and the bottom of the groove in the cross-section of the first groove L2 Distance between the conductive body surface and the second PN junction surface in the cross-section of the first groove

Claims

1. A first groove formed on one surface of a semiconductor wafer or a semiconductor layer, and a second groove formed on the other surface of the semiconductor wafer or the semiconductor layer, having in a plan view, a central portion of the first groove and a central portion of the second groove do not overlap, the central portion of the first groove has a width of 50% with respect to a surface groove width of the first groove, the central portion of the second groove has a width of 50% with respect to a surface groove width of the second groove, and a semiconductor device characterized thereby.

2. In claim 1, the first groove and the second groove do not penetrate, and a semiconductor device characterized thereby.

3. In claim 2, in a plan view, the first groove and the second groove do not overlap, and a semiconductor device characterized thereby.

4. In any one of claims 1 to 3, a first PN junction surface formed on one surface side of the semiconductor wafer or the semiconductor layer, and a second PN junction surface formed on the other surface side of the semiconductor wafer or the semiconductor layer, having the first groove is formed deeper than the first PN junction surface, the second groove is formed deeper than the second PN junction surface, and a semiconductor device characterized thereby.

5. In claim 4, the semiconductor wafer or the semiconductor layer has a first P-type semiconductor layer, a first N-type semiconductor layer, and a second P-type semiconductor layer, the first PN junction surface is a junction surface between the first P-type semiconductor layer and the first N-type semiconductor layer, the second PN junction surface is a junction surface between the first N-type semiconductor layer and the second P-type semiconductor layer, and a semiconductor device characterized thereby.

6. In claim 5, a first passivation film is formed on an inner surface of the first groove formed on one surface of the semiconductor layer, a second passivation film is formed on an inner surface of the second groove formed on the other surface of the semiconductor layer, in a plan view, the first groove has a rectangular shape, the second groove is located inside the first groove, the first passivation film, the first N-type semiconductor layer, and the second P-type semiconductor layer have a cut surface cut along the center of the first groove, and a semiconductor device characterized thereby.

7. In claim 6, the first P-type semiconductor layer or the second P-type semiconductor layer has a thyristor structure in which a second N-type semiconductor layer electrically connected to a cathode electrode is formed, and has a gate electrode electrically connected to the first P-type semiconductor layer or the second P-type semiconductor layer. having an anode electrode electrically connected to the second P-type semiconductor layer or the first P-type semiconductor layer, a semiconductor device characterized in that, in a plan view, the anode electrode is surrounded by the second groove or the first groove. **Claim 8** In claim 7, a semiconductor device characterized in that, in a plan view, the cathode electrode and the gate electrode are surrounded by the first groove or the second groove. **Claim 9** In claim 6, having a thyristor structure in which a second N-type semiconductor layer electrically connected to a cathode electrode is formed in the second P-type semiconductor layer, having a gate electrode electrically connected to the second P-type semiconductor layer, having an anode electrode electrically connected to the first P-type semiconductor layer, in a plan view, the anode electrode is surrounded by the first groove, having a current-carrying member provided with a conductive surface joined to the anode electrode, a semiconductor device characterized in that, in a plan view, the anode electrode is surrounded by the first groove. **Claim 10** In claim 9, a semiconductor device characterized in that the current-carrying member is a lead frame or a heat sink.

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