Clock generating circuit, processing method, and program

Abstract

To provide a clock generating circuit capable of generating a clock adjusted to an appropriate phase.SOLUTION: A clock generating circuit includes detection means for detecting, at the time of initialization of a device that operates according to a clock, a first phase difference of j steps at a normal frequency and a second phase difference of (j / k) steps at a frequency that is 1 / k-th of the normal frequency, conversion means for converting the first phase difference and the second phase difference into respective analog voltage values, comparison means for comparing the two voltage values after conversion by the conversion means, and transmission means for transmitting an output characteristic control signal to a correction circuit at a value that minimizes an error, which is the comparison result by the comparison means.SELECTED DRAWING: Figure 15

Description

Technical Field

[0001] The present disclosure relates to a clock generation circuit, a processing method, and a program.

Background Art

[0002] In a device that processes digital data, data processing may be performed at a timing based on a clock. Patent Document 1 discloses a technique related to a circuit that adjusts the phase of a clock as a related technique.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in a circuit related to the technique described in Patent Document 1, a technique capable of generating a clock adjusted to an appropriate phase is required.

[0005] Each aspect of the present disclosure aims to provide a clock generation circuit, a processing method, and a program capable of solving the above problems.

Means for Solving the Problems

[0006] According to one aspect of the present disclosure, a clock generation circuit includes: a detection unit that detects a first phase difference of j steps at a normal frequency and a second phase difference of (j / k) steps at a frequency of 1 / k of the normal frequency when initializing a device that operates according to a clock; a conversion unit that converts each of the first phase difference and the second phase difference into an analog voltage value; a comparison unit that compares two voltage values after conversion by the conversion unit; and a transmission unit that transmits an output characteristic control signal to a correction circuit at a value at which an error, which is a comparison result by the comparison unit, is minimized.

[0007] According to another aspect of the present disclosure, a processing method includes: detecting a first phase difference of j steps at a normal frequency and a second phase difference of (j / k) steps at a frequency of 1 / k of the normal frequency when initializing a device that operates according to a clock; converting each of the first phase difference and the second phase difference into an analog voltage value; comparing two voltage values after conversion; and transmitting an output characteristic control signal to a correction circuit at a value at which an error, which is a comparison result, is minimized.

[0008] According to another aspect of the present disclosure, a program causes a computer to execute: detecting a first phase difference of j steps at a normal frequency and a second phase difference of (j / k) steps at a frequency of 1 / k of the normal frequency when initializing a device that operates according to a clock; converting each of the first phase difference and the second phase difference into an analog voltage value, comparing two voltage values after conversion, and transmitting an output characteristic control signal to a correction circuit at a value at which an error is minimized.

Advantages of the Invention

[0009] According to each aspect of the present disclosure, a clock adjusted to an appropriate phase can be generated.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described in detail with reference to the drawings. <Embodiment> (Configuration of the reception circuit) The reception circuit 1 in FIG. 1 according to an embodiment of the present disclosure will be described with reference to the drawings. In the reception circuit 1, a multi-phase clock generation circuit 20, which will be described later, detects and corrects the deviation width (variation width) of the delay amount of one step of the delay adjustment by a clock data recovery (CDR) circuit that occurs when the clock speed is switched to a low speed (for example, operating at half the speed of the normal clock) during the initialization of the reception circuit 1 (an example of a device that operates according to a clock) performed after the power-on of the reception circuit 1.

[0012] FIG. 1 is a diagram showing an example of the configuration of a reception circuit 1 according to some embodiments of the present disclosure. As shown in FIG. 1, the reception circuit 1 includes a PLL (Phase Locked Loop) 10, a multi-phase clock generation circuit 20, a sampling latch 30, a Demux 40, and a phase detection circuit 50. Note that in the reception circuit 1, a clock data recovery (CDR) circuit is configured by the multi-phase clock generation circuit 20 and the phase detection circuit 50.

[0013] PLL10 outputs input differential clocks IN000 / IN180 and IN090 / IN270. Clock IN180 is a clock that is 180° out of phase, i.e., phase-inverted, with respect to clock IN000. Clocks IN000 and IN180 indicate the input differential clock IN000 / IN180, which is a pair of differential clocks. Clock IN090 is a waveform with a phase delay of 90° with respect to the rising edge of clock IN000. Clock IN270 is a clock that is 180° out of phase, i.e., phase-inverted, with respect to clock IN090. Clocks IN090 and IN270 indicate the input differential clock IN090 / IN270, which is a pair of differential clocks. FIG. 2 is a diagram showing an example of clocks IN000, IN090, IN180, and IN270 in some embodiments of the present disclosure. As shown in FIG. 2, with clock IN000 as a reference, clocks IN090, IN180, and IN270 have waveforms with phase delays of 90°, 180°, and 270° in this order.

[0014] The sampling latch 30, Demux 40, and phase detection circuit 50 detect the phase relationship between data and the clock, which is a function of clock data recovery. Based on the result of this phase detection, the phase detection circuit 50 determines whether to delay or advance the phase of the sampling clock. FIG. 3 is a diagram showing an example of each adjustment code at the time of phase switching in some embodiments of the present disclosure. When the phase detection circuit 50 delays the phase of the clock, for example, it controls the steps in the plus direction (downward direction in the table) according to the control code correspondence table shown in FIG. 3. When advancing the phase, for example, it controls the steps in the minus direction (upward direction in the table) according to the control code correspondence table shown in FIG. 3. As a result, the phase detection circuit 50 controls whether to delay the 8-phase clock output (output in FIG. 3) in FIG. 1 by one step plus or one step minus with respect to the data. Note that PLL10 is a clock generation source.

[0015] FIG. 4 is a diagram showing an example of the configuration of a multiphase clock generation circuit 20 according to some embodiments of the present disclosure. As shown in FIG. 4, the multiphase clock generation circuit 20 includes an input path switching unit 201, a 4-phase / 8-phase conversion unit 202, an 8-phase output switching unit 203, a control switching unit 204, and a phase difference detection unit 205.

[0016] The input path switching unit 201 switches the path of the clock signal input when performing (validly) phase difference detection. The input path switching unit 201 usually selects the Low (logical 0) side by the input path switching signal. Also, when performing clock phase difference detection, the input path switching unit 201 switches the input path switching signal to the High (logical 1) side.

[0017] As shown in FIG. 4, the 4-phase / 8-phase conversion unit 202 includes buffers 202a and 202b. The 4-phase / 8-phase conversion unit 202 receives the 4-phase clock, which is the output of the previous-stage input path switching unit 201, as an input clock.

[0018] The buffer 202a is, for example, a CML (Current Mode Logic) buffer. The buffer 202a delays each of the input differential clocks IN000 / IN180 and IN090 / IN270 by 45° in order to generate 8 phases from 4 phases. This delay amount varies due to manufacturing variations for each buffer 202a. As a result, as a clock data recovery (CDR) circuit, it becomes a circuit that is easily affected by clock jitter due to such variations for each buffer 202a, and in order to configure a clock data recovery (CDR) circuit corresponding to a plurality of frequencies (transmission speeds), it is necessary to optimize each one. The buffer 202b receives the differential signal output by the buffer 202a and outputs a desired differential signal to the 8-phase output switching unit 203.

[0019] FIG. 5 is a diagram showing an example of an image of the phase relationship of the clocks output by the 4-phase / 8-phase conversion unit 202 according to some embodiments of the present disclosure. When the clock corresponding to the input differential clock IN000 is clock clk000i, the clock corresponding to the input differential clock IN090 is clock clk090i, the clock corresponding to the input differential clock IN180 is clock clk180i, and the clock corresponding to the input differential clock IN270 is clock clk270i, the 4-phase / 8-phase conversion unit 202 outputs eight-phase clocks of clocks clk000i, clk045i, clk090i, clk135i, clk180i, clk225i, clk270i, and clk315i as shown in FIG. 5. As shown in FIG. 5, based on the clock clk000i, the waveforms of the clocks clk045i, clk090i, clk135i, clk180i, clk225i, clk270i, clk315i are delayed by 45°, 90°, 135°, 180°, 225°, 270°, 315° in this order.

[0020] Note that the slew rates of the buffers 202a and 202b can be controlled by the output characteristic control signal shown in FIG. 4.

[0021] FIG. 6 is a diagram showing an example of the configuration of the PI circuit 203b according to some embodiments of the present disclosure. The PI circuit 203b includes first to fourth MOS transistors M1 to M4, first and second resistors R1 and R2, and first and second current sources Ia and Ib. The sources of the first and third MOS transistors M1 and M3 are commonly connected to each other and connected to the power supply potential VDD via the resistor R1. The sources of the second and fourth MOS transistors M2 and M4 are commonly connected to each other and connected to the power supply potential VDD via the resistor R2. The drains of the first and second MOS transistors M1 and M2 are commonly connected to each other and connected to the current source Ia. The drains of the third and fourth MOS transistors M3 and M4 are commonly connected to each other and connected to the current source Ib.

[0022] Also, the gate of the first MOS transistor M1 is connected to the input terminal A. The gate of the second MOS transistor M2 is connected to the input terminal AB. The gate of the third MOS transistor M3 is connected to the input terminal B. The gate of the fourth MOS transistor M4 is connected to the input terminal BB. Further, a control bit SB is applied to the current source Ia through a control terminal, and a control bit SA is applied to the current source Ib through a control terminal. Then, an output terminal OUT is connected between the commonly connected sources of the second and fourth MOS transistors M2 and M4 and the resistor R2, and an output terminal OUTB is connected between the commonly connected sources of the first and third MOS transistors M1 and M3 and the resistor R1.

[0023] The 8-phase output switching unit 203 includes a front-stage unit 203a and a rear-stage unit 203b (i.e., the above-described PI circuit 203b). The 8-phase output switching unit 203 uses the output of the 4-phase / 8-phase conversion unit 202 as an input clock.

[0024] The front-stage unit 203a switches the clock path by switching between 1 and 0 of the control signal of SELC[7:0]. The rear-stage unit 203b outputs a sampling clock in 1STEP increments by switching the control between 1 and 0 of SELP1[15:0] and SELP2[15:0]. FIG. 7 is a diagram showing an example of the clock output by the 8-phase output switching unit 203 according to some embodiments of the present disclosure, and shows three of the representative 8 clocks. The part (a) of FIG. 7 shows the input clock. The part (c) of FIG. 7 shows the output clock. The part (b) of FIG. 7 shows how the phase of the clock changes by 1STEP each time the control signal changes by 1 code. Since there are only 8 clocks for the output clock, the phase of each clock is maintained at 45°. Therefore, when the control code shown in the part (c) of FIG. 7 for the output clock is a control code that delays 1STEP plus, the entire 8-phase clock is delayed by 1STEP.

[0025] The control switching unit 204 switches between two groups of phase control signals according to the phase switching signal from the phase detection circuit 50 of the CDR circuit. The first group of phase control signals is the phase control signal (Auto). The phase control signal (Auto) is SELC* and SELP*. During normal operation, the phase control signal of the control switching unit 204 is set (fixed) to Low (logical 0). Thereby, the path to the 8-phase output switching unit 203 through which the phase control signal (Auto) propagates is selected.

[0026] The second group of phase control signals is the phase control signal (Manual). The control switching unit 204 sets the control switching signal to High (logical 1). Thereby, the path to the 8-phase output switching unit 203 through which the phase control signal (Manual) propagates is selected.

[0027] The phase difference detection unit 205 detects the delay amount of the difference between the inputs by taking the clocks of OUT045 and OUT135 output by the 8-phase output switching unit 203 as inputs. Then, the phase difference detection unit 205 outputs the phase difference as a voltage level. For example, the circuit inside the phase difference detection unit 205 is a phase detection circuit used in a general PLL or the like.

[0028] Note that the processing performed by the receiving circuit 1 according to an embodiment of the present disclosure is not limited to the above-described processing. For example, the receiving circuit 1 may perform the processing described below.

[0029] (Processing performed by the receiving circuit) Next, the processing performed by the receiving circuit 1 according to an embodiment of the present disclosure will be described. FIG. 8 is a diagram showing a first example of the processing flow of the receiving circuit 1 according to some embodiments of the present disclosure. FIG. 9 is a diagram showing a second example of the processing flow of the receiving circuit 1 according to some embodiments of the present disclosure. First, with reference to FIG. 8, the operation of the entire multi-phase clock generation circuit 20 during normal operation will be described.

[0030] It is assumed that the following settings are made before the operation of the entire multi-phase clock generation circuit 20 during normal operation.

[0031] During normal operation, the input path switching signal selects Low (logical 0). Accordingly, it is assumed that the input path switching unit 201 is set to output IN090 / IN270 to the next-stage 4-phase / 8-phase conversion unit 202. Also, during normal operation, Low (0) is selected as the control switching signal. Accordingly, it is assumed that the phase control signal (Auto) output by the phase detection circuit 50 is selected. Also, it is assumed that the 4-phase / 8-phase conversion unit 202 is set to adjust the phase of the 4-phase clock between 0° and 90° by using the delay of the CML buffer.

[0032] The input path switching unit 201 receives the 4-phase clocks of IN000, IN180, IN090, and IN270 shown in FIG. 2 that are in a phase shift relationship output by the PLL 10 (step S1). According to the setting, the input path switching unit 201 outputs IN090 / IN270 to the next-stage 4-phase / 8-phase conversion unit 202 (step S2).

[0033] According to the setting, the 4-phase / 8-phase conversion unit 202 adjusts the phase of the 4-phase clock between 0° and 90° by using the delay of the CML buffer (step S3). For example, as shown in FIG. 5, the 4-phase / 8-phase conversion unit 202 generates 8-phase clocks with a 45° phase shift between each clock. Then, the 4-phase / 8-phase conversion unit 202 outputs the generated 8-phase clocks to the next-stage 8-phase output switching unit 203.

[0034] The 8-phase output switching unit 203 samples data with the 8-phase clocks shown in FIG. 5 output by the 4-phase / 8-phase conversion unit 202 (step S4). The 8-phase output switching unit 203 optimizes the phase of the 8-phase clocks under the control of SELC[7:0], SELP1[15:0], and SELP2[15:0] (step S5).

[0035] According to the setting, the phase control signal (Auto) output by the phase detection circuit 50 is selected. Specifically, for example, the control code of the 8-phase output switching unit 203 is the control code shown in FIG. 3. The 8-phase output switching unit 203 generates an optimal clock according to the codes shown in FIG. 3 and in response to SELC[7:0], SELP1[15:0], and SELP2[15:0].

[0036] Examples of the output clocks OUT00, OUT045, and OUT090 are shown in the part (c) of FIG. 7. Note that the output clocks OUT00, OUT045, and OUT090 shown in the part (c) of FIG. 7 are examples when SELC[7:0]=00000011, SELP1[15:0]=SELP2[15:0]=0000000011111111 are selected as internal control codes respectively.

[0037] Note that a part of the input clock of the 8-phase output switching unit 203 in this case is the clocks clk000i, clk045i, and clk090i shown in the part (a) of FIG. 7. Also, the waveform shown in the part (b) of FIG. 7 is an image diagram of the synthesized waveform obtained by the PI circuit 203b interpolating the waveform when switching the 16 steps of SELP*[15:0] every 2STEP. That is, the waveform shown in the part (b) of FIG. 7 is the waveform when displayed skipping 1STEP, and only 8 waveforms out of 16 waveforms are displayed, and further, 8 waveforms interpolated by the PI circuit 203b are displayed. More specifically, the PI circuit 203b interpolates the waveforms of 16STEP of the clocks clk000i and clk045i shown in the part (a) of FIG. 7, interpolates the waveforms of 16STEP of the clocks clk045i and clk090i, and overwrites the waveforms interpolated between the clock clk090i and the next clock clk135i, which is the waveform shown in the part (b) of FIG. 7. Furthermore, the waveform shown in the part (c) of FIG. 7 is an image diagram of the optimal clock output from the 8-phase output switching unit 203. However, in the waveform shown in the part (c) of FIG. 7, the waveforms after OUT135 are omitted.

[0038] FIG. 10 is a diagram showing an example of a clock generated by the 8-phase output switching unit 203 according to some embodiments of the present disclosure. As a result, as shown in FIG. 10, the 8-phase output switching unit 203 generates a clock that is optimally adjusted to the edge of the data change point and the center of the data. Then, the clock generated by the 8-phase output switching unit 203 in this way is used as the clock of the sampling latch.

[0039] Here, consider the details of the waveform interpolated and overwritten by the PI circuit 203b shown in the part (b) of FIG. 7. FIG. 11 is a diagram showing a part of the waveform interpolated and overwritten by the PI circuit 203b according to some embodiments of the present disclosure. As shown in FIG. 11, the waveform interpolated and overwritten by the PI circuit 203b shown in the part (b) of FIG. 7 may have a large delay amount near the center at intervals of 1STEP and a non-uniform delay amount. This is because each phase interpolation by the PI circuit 203b is a phase interpolation synthesized from waveforms with a phase difference of 45°, and the maximum phase difference of 1STEP is due to the waveform selected in the middle by SELP*[15:0]. That is, 1STEP is created by correcting between each clock, and the 45° phase is divided into 16 parts, but it may be difficult to make the phase difference of each STEP from 0 to 15 the same delay difference. Note that the tendency for the delay amount near the center to be large and non-uniform at intervals of 1STEP becomes more prominent as the rise of the clock waveform is faster and the clock frequency is slower. As a result, the optimal point of the sampling clock fluctuates, resulting in clock jitter, which may affect the performance of the receiving circuit 1 (for example, deterioration of the transmission error rate (transmission error)). Therefore, it is desirable for the PI circuit 203b to correct the clock (that is, interpolate the phase of the clock) so as to be as uniform as possible in STEP.

[0040] Next, a second example of the processing flow of the reception circuit 1 according to some embodiments of the present disclosure shown in FIG. 9 will be described. Examples of methods for correcting the clock so that the PI circuit 203b has as uniform a STEP as possible include the following methods. In the polyphase clock generation circuit 20, by setting the input path switching signal of the input path switching unit 201 to High (logical 1), only the clocks of IN000 and IN180 are used (step S11). Also, the control switching unit 204 disconnects the control code of the phase detection circuit 50 from the feedback by setting the control switching signal to High (logical 1) so that SELC[7:0], SELP1[15:0], and SELP2[15:0] can be freely switched (step S12). FIG. 12 is a first diagram for explaining clock correction in some embodiments of the present disclosure. FIG. 13 is a second diagram for explaining clock correction in some embodiments of the present disclosure. Here, a method for detecting the phase of jSTEP (or an arbitrary STEP position, number of STEPs) (for example, 1STEP) and correcting the clock will be described.

[0041] The diagram shown in the (a) part of FIG. 12 shows a state where the phase detection circuit 50 is disconnected from the feedback. Assume that the control code SELC[7:0]=00000011. When the phase difference detection unit 205 performs phase detection, it switches the input path switching unit 201 to "1". Therefore, when SELP1 [15:0] and SELP2[15:0] have the same value, the 8-phase output switching unit 203 outputs clocks with the same phase to clock OUT045A and clock OUT045B, and clock OUT225A and clock OUT225B. When the 8-phase output switching unit 203 changes SELP2 while keeping SELP1 fixed, it outputs clocks with a phase difference. For example, when the control codes SLEP1[0000000001111111] and SELP2[0000000111111111] are selected, the phase difference detection unit 205 outputs the voltage level detecting a phase difference ΔT of jSTEP (for example, 2STEP) shown in the (b) part of FIG. 12 to clocks OUT045A and OUT045B shown in the (a) part of FIG. 12 (step S13).

[0042] Next, by setting the frequency of the clock of PLL10 to 1 / k (for example, 1 / 2) and further selecting only SELP2[15:0] as SELP2[0000000011111111], the phase difference detection unit 205 outputs the voltage levels at which the phase differences ΔT' of (j / k)STEP (for example, 1STEP) are detected for the clocks OUT045A' and OUT045B' shown in part (a) of FIG. 13 (step S14). Since the frequency (speed) of the clock is 1 / k (for example, 1 / 2) and the STEP of SLEP2[15:0] is (j / k)STEP (for example, 1STEP), ΔT = ΔT', and ideally the level outputs match (in practice, they are close values). When the frequency of the clock is low, the variation in the delay amount becomes significant. Therefore, the phase difference detection unit 205 uses, as a reference, the output level of the phase difference ΔT of (j / k)STEP (for example, 2STEP) when the clock of PLL10 is the normal clock, such that the phase difference ΔT' is a phase difference ΔT with a small variation in STEP, and while comparing with the voltage level of the phase difference ΔT' of (j / k)STEP (for example, 1STEP) when the frequency of the clock is set to 1 / k (for example, 1 / 2), it feeds back to the output characteristic control signal shown in FIG. 4. By this process of the phase difference detection unit 205, it becomes possible to optimally adjust the phase difference of (j / k)STEP (for example, 1STEP) (that is, the delay amount for each (j / k)STEP (for example, 1STEP) becomes the same delay, and the variation in the phase difference is made uniform, thereby improving the linearity when the delay amounts are integrated) (step S15). The output characteristic signal shown in FIG. 3 indicates the control of the rise / fall of the output signals of the CML buffers of the buffers 202a and 202b. The phase difference detection unit 205 changes the input waveforms of the 8-phase output switching unit 203 by performing control to soften the output signals of the CML buffers of the buffers 202a and 202b according to the output characteristic signal. Note that the variation in the delay amount refers to the difference between the designed delay of (j / k)STEP (for example, 1STEP) created by phase interpolation and the actual delay of (j / k)STEP (for example, 1STEP).

[0043] FIG. 14 is a diagram showing an example of the configuration of the 4-phase / 8-phase conversion unit 202 according to some embodiments of the present disclosure. The 4-phase / 8-phase conversion unit 202 shown in FIG. 14 shows the configuration of the 4-phase / 8-phase conversion unit when the phase interpolation from 0° to 45° cannot be adjusted only by the through rate. The 4-phase / 8-phase conversion unit 202 shown in FIG. 14 enables a wider range of highly accurate adjustment of phase interpolation by not only controlling the through rate but also changing the 45° phase switching for each frequency.

[0044] As described above, the receiving circuit 1 according to an embodiment of the present disclosure has been described. In the multi-phase clock generation circuit 20 (an example of a clock generation circuit) of the receiving circuit 1, the phase difference detection unit 205 (an example of detection means) detects, at the time of initialization of the receiving circuit 1 (an example of a device that operates according to a clock), a first phase difference for j steps at the normal frequency and a second phase difference for (j / k) steps at a frequency of 1 / k of the normal frequency (for example, each of j and k is 2, and a first phase difference for 2 steps at the normal frequency and a second phase difference for 1 step at a frequency of 1 / 2 of the normal frequency are detected). The phase difference detection unit 205 (an example of conversion means, an example of comparison means, an example of transmission means) converts each of the first phase difference and the second phase difference into an analog voltage value, compares the two converted voltage values, and transmits an output characteristic control signal to the 4-phase / 8-phase conversion unit 202 (an example of a correction circuit) with a value that minimizes the error.

[0045] Here, a general multi-phase clock generation circuit using a PI (Phase Interpolator) circuit will be described. A general multi-phase clock generation circuit generates an intermediate phase by synthesizing clock waveforms with different phases (delays) with each other, and creates a clock waveform having an optimal phase for sampling data. For example, the phase of the sampling clock of the digital circuit configuration created by the PI circuit can switch phases of 360°. Therefore, if a circuit can divide the input phase into 360 parts, it can create phases shifted by 1° (in the case of a circuit that can divide into 180 parts, it can create phases shifted by 2°).

[0046] However, when synthesizing waveforms with a phase shift of 45° (or 90°), it is necessary to optimize for each frequency. When changing the operating speed, it is necessary to install a frequency divider circuit or the like in the subsequent stage, or to control according to the speed. Generally, as one of the drawbacks of a multiphase clock generation circuit using a PI circuit, if the operating speed is simply reduced, the synthesized waveform will have a phase shift from the optimal delay, resulting in a non-uniform STEP (delay width). And depending on the design, distortion may occur in the waveform, which may cause signal transmission errors and design specification constraints. Therefore, a design that optimizes the clock according to the frequency is necessary. As an example, when the phase difference is large (for example, 45°), there are methods to linearize the phase by smoothing the waveform with a mechanism to control the slew rate, or to adjust the phase of the clock by adding a 45° phase delay according to the frequency. However, simply adding a function to control the slew rate will cause waveform distortion and there is a limit to the phase adjustment of the clock. Therefore, it is desirable to add a circuit that generates a 45° phase. However, in order to create a 45° phase with a delay buffer, it is necessary to design more precisely according to the variations in the LSI process.

[0047] For such a general multiphase clock generation circuit, the multiphase clock generation circuit 20 in this receiving circuit 1 can generate a clock adjusted to an appropriate phase.

[0048] <Other Embodiments> The multiphase clock generation circuit 20 according to an embodiment of the present disclosure has been described as a multiphase clock generation circuit that converts 4-phase input and 8-phase output. However, the multiphase clock generation circuit 20 according to other embodiments of the present disclosure may be a multiphase clock circuit such as 4-phase input, 4-phase output, or 4-phase input, 16-phase output, and may realize the same functions as the multiphase clock generation circuit 20 according to an embodiment of the present disclosure.

[0049] Also, in the receiving circuit 1 according to one embodiment of the present disclosure, it has been described that one PLL 10 is connected to one multi-phase clock generation circuit 20. However, the receiving circuit 1 according to another embodiment of the present disclosure may include a plurality of multi-phase clock generation circuits 20, and those plurality of multi-phase clock generation circuits 20 may share one PLL 10. By doing so, it is possible to reduce the PLL 10 with a large mounting area, and it becomes possible to reduce the overall mounting area.

[0050] Also, in another embodiment of the present disclosure, the number of phase difference detection units 205 may be increased to a plurality.

[0051] FIG. 15 is a diagram showing an example of the configuration of a clock generation circuit 300 according to some embodiments of the present disclosure. As shown in FIG. 15, the clock generation circuit 300 includes a detection means 301, a conversion means 302, a comparison means 303, and a transmission means 304.

[0052] The detection means 301 detects, at the time of initialization of the receiving circuit 1, a first phase difference for j steps at the normal frequency and a second phase difference for (j / k) steps at a frequency of 1 / k of the normal frequency. The conversion means 302 converts each of the first phase difference and the second phase difference into an analog voltage value. The comparison means 303 compares the two voltage values after conversion by the conversion means 302. The transmission means 304 transmits to the correction circuit a value at which the error, which is the comparison result by the comparison means 303, is minimized.

[0053] The detection means 301, the conversion means 302, the comparison means 303, and the transmission means 304 can be realized by using, for example, the functions of the phase difference detection unit 205 exemplified in FIG. 4 and the like.

[0054] FIG. 16 is a diagram showing an example of the processing flow of the clock generation circuit 300 according to some embodiments of the present disclosure. Next, the processing performed by the clock generation circuit 300 according to the embodiment of the present disclosure will be described with reference to FIG. 16.

[0055] The detection means 301 detects, at the time of initialization of the reception circuit 1, a first phase difference for j steps at the normal frequency and a second phase difference for (j / k) steps at a frequency of 1 / k of the normal frequency (step S101). The conversion means 302 converts each of the first phase difference and the second phase difference into an analog voltage value (step S102). The comparison means 303 compares the two voltage values after conversion by the conversion means 302 (step S103). The transmission means 304 transmits to the correction circuit a value at which the error, which is the comparison result by the comparison means 303, is minimized (step S104).

[0056] As described above, the clock generation circuit 300 according to the embodiment of the present disclosure has been described. With this clock generation circuit 300, a clock adjusted to an appropriate phase can be generated.

[0057] Note that, in the embodiment of the present disclosure, the order of processing may be changed as long as appropriate processing is performed.

[0058] Although the embodiment of the present disclosure has been described, the above-described reception circuit 1, multiphase clock generation circuit 20, and other control devices may have a computer system inside. And the processes described above are stored in a computer-readable recording medium in the form of a program, and the above processes are performed by a computer reading and executing this program. Specific examples of the computer are shown below.

[0059] FIG. 17 is a schematic block diagram showing the configuration of a computer according to at least one embodiment. As shown in FIG. 17, the computer 5 includes a CPU (Central Processing Unit) 6, a main memory 7, a storage 8, and an interface 9.

[0060] For example, each of the above-described receiving circuit 1, polyphase clock generation circuit 20, and other control devices is implemented in computer 5. And the operations of the above-described respective processing units are stored in storage 8 in the form of a program. CPU 6 reads the program from storage 8 and expands it in main memory 7, and executes the above processing according to the program. Further, CPU 6 secures a storage area corresponding to each of the above-described storage units in main memory 7 according to the program.

[0061] Examples of storage 8 include HDD (Hard Disk Drive), SSD (Solid State Drive), magnetic disk, magneto-optical disk, CD-ROM (Compact Disc Read Only Memory), DVD-ROM (Digital Versatile Disc Read Only Memory), semiconductor memory, and the like. Storage 8 may be an internal medium directly connected to the bus of computer 5, or may be an external medium connected to computer 5 via interface 9 or a communication line. Also, when this program is distributed to computer 5 via a communication line, computer 5 that has received the distribution may expand the program in main memory 7 and execute the above processing. In at least one embodiment, storage 8 is a non-transitory tangible storage medium.

[0062] Also, the above program may implement a part of the aforementioned functions. Furthermore, the above program may be a file, so-called differential file (differential program), that can realize the above functions in combination with a program already recorded in the computer system.

[0063] Although some embodiments of the present disclosure have been described, these embodiments are examples and do not limit the scope of the disclosure. These embodiments may be subject to various additions, omissions, replacements, and changes without departing from the gist of the disclosure.

[0064] Note that some or all of the above embodiments can also be described as follows in the appended claims, but are not limited thereto.

[0065] (Appendix 1) At the time of initializing a device that operates according to a clock, detection means for detecting a first phase difference for j steps at a normal frequency and a second phase difference for (j / k) steps at a frequency of 1 / k of the normal frequency; Conversion means for converting each of the first phase difference and the second phase difference into an analog voltage value; Comparison means for comparing two voltage values after conversion by the conversion means; Transmission means for transmitting an output characteristic control signal to a correction circuit at a value at which an error, which is a comparison result by the comparison means, is minimized; A clock generation circuit comprising the above.

[0066] (Appendix 2) j is 2, k is 2, The clock generation circuit according to Appendix 1.

[0067] (Appendix 3) When the speed of the clock is switched to low speed, The detection means detects the first phase difference and the second phase difference, The transmission means transmits the output characteristic control signal to the correction circuit. The clock generation circuit according to Appendix 1 or Appendix 2.

[0068] (Appendix 4) When the speed of the clock is switched to low speed means when the speed of the clock is switched to a speed of 1 / 2. The clock generation circuit according to Appendix 3.

[0069] (Appendix 5) At the time of initializing a device that operates according to a clock, detecting a first phase difference for j steps at a normal frequency and a second phase difference for (j / k) steps at a frequency of 1 / k of the normal frequency; Converting each of the first phase difference and the second phase difference into an analog voltage value, comparing the two converted voltage values, transmitting an output characteristic control signal to a correction circuit with a value at which the error as the comparison result is minimized, and a processing method including the above.

[0070] (Appendix 6) where j is 2, and k is 2, and a processing method according to Appendix 5.

[0071] (Appendix 7) when the speed of the clock is switched to low speed, detecting the first phase difference and the second phase difference, transmitting the output characteristic control signal to the correction circuit, and a processing method according to Appendix 5 or Appendix 6 including the above.

[0072] (Appendix 8) when the speed of the clock is switched to low speed means when the speed of the clock is switched to a half speed, and a processing method according to Appendix 7.

[0073] (Appendix 9) when initializing a device that operates according to a clock, detecting a first phase difference for j steps at a normal frequency and a second phase difference for (j / k) steps at a frequency of 1 / k of the normal frequency, converting each of the first phase difference and the second phase difference into an analog voltage value, comparing the two converted voltage values, and transmitting an output characteristic control signal to a correction circuit with a value at which the error is minimized, and a program for causing a computer to execute the above.

[0074] (Appendix 10) where j is 2, and k is 2, and a program according to Appendix 9.

[0075] (Appendix 11) When the speed of the clock is switched to a low speed, detecting the first phase difference and the second phase difference; transmitting the output characteristic control signal to the correction circuit; The program according to Appendix 9 or Appendix 10 for causing a computer to execute.

[0076] (Appendix 12) When the speed of the clock is switched to a low speed means when the speed of the clock is switched to half the speed. The program according to Appendix 11.

Explanation of Signs

[0077] 1 ··· Receiving circuit 5 ··· Computer 6 ··· CPU 7 ··· Main memory 8 ··· Storage 9 ··· Interface 10 ··· PLL (Phase Locked Loop) 20 ··· Multiphase clock generation circuit 30 ··· Sampling latch 40 ··· Demux 50 ··· Phase detection circuit 201 ··· Input path switching section 202 ··· 4-phase / 8-phase conversion section 202a, 202b ··· Buffer 203 ··· 8-phase output switching section 203a ··· Front stage section 203b ··· Rear stage section (PI (Phase Interpolation) circuit) 204 ··· Control switching section 205 ··· Phase difference detection section

Claims

1. Detection means for detecting, at the time of initialization of a device that operates in response to a clock, a first phase difference for j steps at a normal frequency and a second phase difference for (j / k) steps at a frequency of 1 / k of the normal frequency; Conversion means for converting each of the first phase difference and the second phase difference into an analog voltage value; Comparison means for comparing two voltage values after conversion by the conversion means; Transmission means for transmitting an output characteristic control signal to a correction circuit at a value at which an error, which is a comparison result by the comparison means, is minimized; A clock generation circuit comprising the above.

2. The j is 2, The k is 2, The clock generation circuit according to Claim 1.

3. When the speed of the clock is switched to a low speed, The detection means detects the first phase difference and the second phase difference, The transmission means transmits the output characteristic control signal to the correction circuit, The clock generation circuit according to Claim 1 or Claim 2.

4. The case where the speed of the clock is switched to a low speed means the case where the speed of the clock is switched to a speed of 1 / 2, The clock generation circuit according to Claim 3.

5. At the time of initialization of a device that operates in response to a clock, detecting a first phase difference for j steps at a normal frequency and a second phase difference for (j / k) steps at a frequency of 1 / k of the normal frequency; Converting each of the first phase difference and the second phase difference into an analog voltage value; Comparing two converted voltage values; Transmitting an output characteristic control signal to a correction circuit at a value at which an error, which is a comparison result, is minimized; A processing method including the above.

6. At the time of initialization of a device that operates in response to a clock, detecting a first phase difference for j steps at a normal frequency and a second phase difference for (j / k) steps at a frequency of 1 / k of the normal frequency; Converting each of the first phase difference and the second phase difference into an analog voltage value, comparing two converted voltage values, and transmitting an output characteristic control signal to a correction circuit at a value at which an error is minimized; A program for causing a computer to execute the above.

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