Analog-to-digital converter and analog-to-digital converting method
The ADC design addresses high power consumption and area issues by employing a correlated double sampling method and a decreasing reference voltage, enhancing efficiency and reducing resource use in applications like CMOS image sensors and ACiM systems.
Patent Information
- Application Number
- JP2024199619
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-07-24
- Filing Date
- 2024-11-15
- Publication Date
- 2025-07-03
AI Technical Summary
Existing analog-to-digital converters (ADCs) face challenges in high power consumption and increased area requirements when operating at high speeds, particularly in applications requiring multiple converters.
The proposed ADC includes a comparator, counter, register, and blocking capacitor, utilizing a correlated double sampling method to minimize power consumption and area by compensating for offset and noise, and using a reference voltage that decreases with each clock cycle to generate a digital count value.
This approach reduces power consumption and area while maintaining high operating speed, suitable for applications like CMOS image sensors and ACiM systems, offering improved efficiency and reduced resource utilization.
Smart Images
Figure 2025100369000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to an analog-to-digital converter and an analog-to-digital conversion method, and more particularly to an analog-to-digital converter and a conversion method thereof that can be provided in a small area while increasing the operating speed and reducing the power consumption.
Background Art
[0002] An analog-to-digital converter (ADC) is an electronic circuit that converts an analog electrical signal into a digital electrical signal. That is, the analog-to-digital converter can extract and quantize the amplitude of the analog signal at a preset period and convert it into a digital signal.
[0003] In recent image processing devices, as the amount of data to be processed increases, a large number of analog-to-digital converters are provided and need to operate at a high operating speed simultaneously. And in order to provide a large number of analog-to-digital converters, the area can be increased significantly. Also, when operating at a high operating speed, the power consumption can be increased.
Summary of the Invention
Problems to be Solved by the Invention
[0004] Accordingly, various embodiments of the present disclosure provide an analog-to-digital converter capable of reducing the area and lowering the power consumption in an environment that requires a large number of analog-to-digital converters.
[0005] However, the technical problems to be achieved in the present disclosure are not limited to the above-mentioned technical problems. Incidentally, other technical problems not mentioned in the present disclosure will also be clearly understood by those having ordinary knowledge in the technical field to which the present invention pertains from the following description.
Means for Solving the Problems
[0006] According to various embodiments of the present disclosure, an analog-to-digital conversion device includes a first input terminal, a second input terminal, and an output terminal, and compares an input signal input to the first input terminal with a reference voltage that is input to the second input terminal and decreases from a previous value to a preset value in response to the input of each clock signal, and outputs a comparison result value to the output terminal; a comparator, a counter that outputs a digital count value that increases one by one each time the clock signal is input, a register that latches and stores the digital count value based on the comparison result value, and generates a digital value corresponding to the input signal based on the latched digital count value, a first blocking capacitor having one end connected to the first input terminal and transmitting the input signal to the first input terminal, and a control circuit that generates the clock signal.
[0007] According to various embodiments of the present disclosure, an analog-to-digital conversion device includes a reference voltage generator that generates a reference voltage that decreases from a previous value to a preset value in response to the input of each clock signal, a counter that outputs a digital count value that increases one by one each time the clock signal is input, a control circuit that generates the clock signal, and a plurality of analog-to-digital conversion circuits. Each of the plurality of analog-to-digital conversion circuits includes a first input terminal, a second input terminal, and an output terminal, and compares a signal input to the first input terminal with the reference voltage input to the second input terminal, and outputs a comparison result value to the output terminal; a comparator, a register that latches and stores the digital count value based on the comparison result value, and generates a digital value corresponding to the input signal based on the latched digital count value, and a first blocking capacitor having one end connected to the first input terminal and transmitting the input signal to the first input terminal.
[0008] According to various embodiments of the present disclosure, a CMOS image sensor includes a pixel array including a plurality of pixels configured at intersections where a plurality of rows and a plurality of columns intersect, a row decoding circuit that selects a row for outputting a pixel signal from the pixel array, a reference voltage generator that generates a reference voltage at which a preset value decreases from a previous value in response to an input of each clock signal, a counter that outputs a digital count value that increases one by one each time the clock signal is input, a control circuit that generates the clock signal, and a plurality of analog-to-digital conversion circuits provided for each of the plurality of columns and configured to generate a digital value for the pixels of each column using the reference voltage. Each of the plurality of analog-to-digital conversion circuits includes a first input terminal, a second input terminal, and an output terminal, and includes a comparator that compares an input signal input to the first input terminal with the reference voltage input to the second input terminal and outputs a comparison result value to the output terminal, a register that latches and stores the digital count value based on the comparison result value and generates a digital value corresponding to the input signal based on the latched digital count value, and a first blocking capacitor having one end connected to the first input terminal and configured to transmit the input signal to the first input terminal.
[0009] According to various embodiments of the present disclosure, a memory array including a memory storing weighted value information, which is configured at intersections where a plurality of rows and a plurality of columns intersect, a plurality of digital-to-analog converters provided at input ends of each of the plurality of rows to convert each of a plurality of digital input signals into an analog signal, a reference voltage generator that generates a reference voltage whose preset value decreases from a previous value in response to an input of each clock signal, a counter that outputs a digital count value that increases one by one each time the clock signal is input, a control circuit that generates the clock signal, and a plurality of analog-to-digital conversion circuits provided in each of the plurality of columns, each of which physically multiplies an analog signal input to a row where each column intersects by corresponding weighted value information and converts the summed analog signal into a digital signal. Each of the plurality of analog-to-digital conversion circuits includes a first input terminal, a second input terminal, and an output terminal, and a comparator that compares an input signal input to the first input terminal with the reference voltage input to the second input terminal and outputs a comparison result value to the output terminal, a register that latches and stores the digital count value based on the comparison result value and generates a digital value corresponding to the input signal based on the latched digital count value, and a first blocking capacitor whose one end is connected to the first input terminal and transmits the input signal to the first input terminal may be included.
Advantages of the Invention
[0010] The embodiment of the analog-to-digital converter proposed in the present disclosure can be used to minimize the power consumption and the area occupied by the analog-to-digital converter in a product in which a large number of analog-to-digital converters must operate simultaneously.
Brief Description of the Drawings
[0011]
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Embodiments for Carrying Out the Invention
[0012] Hereinafter, with reference to the accompanying drawings, embodiments of the present disclosure will be described in detail so that those having ordinary knowledge in the technical field to which the present invention pertains can easily implement it. However, the present invention can be embodied in various different forms and is not limited to the embodiments described below. And, in order to clearly explain the present disclosure, parts not directly related to the description of the present invention are omitted from the drawings, and similar parts are given similar drawing reference numerals.
[0013] Throughout the present disclosure, when a part is said to "include" a certain component, unless otherwise stated to the contrary, this means that it can further include other components rather than excluding other components.
[0014] In the embodiments of the present disclosure, the terms used are, as much as possible, general terms that are currently widely used while considering the functions in the present invention. However, this may change depending on the intentions of those skilled in the art, case law, the emergence of new technologies, etc. Also, in some cases, there may be terms arbitrarily used in the present disclosure, and in such cases, the meaning will be described in detail in the description of the corresponding embodiments. Therefore, the terms used in the embodiments of the present disclosure must be defined based on the overall content of the embodiments of the present disclosure without simply defining the meaning of the terms unambiguously.
[0015] In the embodiments of the present disclosure, terms including ordinal numbers such as "first", "second", etc. are used to describe various components, but the components are not limited by these terms. These terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the rights of the present invention, the first component may be named the second component, and similarly, the second component may also be named the first component. The term "and / or" includes combinations of a plurality of related described items or any one of the plurality of related described items.
[0016] Also, in the embodiments of the present disclosure, a singular expression includes plural meanings unless the context clearly has a different meaning.
[0017] FIG. 1 is a drawing showing the structure of the analog-digital conversion circuit proposed in the present disclosure. And, FIG. 2 is a drawing conceptually explaining the correlated double sampling (CDS) method for sampling an analog input signal (IN) in the analog-digital conversion circuit proposed in the present disclosure. And, FIG. 3 is a signal timing diagram when sampling the analog input signal (IN) by the correlated double sampling (CDS) method in the analog-digital conversion circuit proposed in the present disclosure. And, FIG. 4 is a flowchart explaining the correlated double sampling method for deriving one sampling result based on the analog-digital conversion circuit of FIG. 1.
[0018] Referring to FIG. 1, the analog-digital conversion circuit 4000 can include a comparator 410, a counter 420, a control circuit 425, a register (REG) 430, and a switch 440. The analog-digital conversion circuit 4000 can further include DC blocking capacitors 451, 453 and switches 461, 463 for connecting the power supply voltage (VDD) to each of the two input terminals of the comparator 410.
[0019] The DC blocking capacitors 451, 453 can prevent the DC component from propagating inside the analog-digital conversion circuit 4000 when the input signal has a DC component, and can match the input signal to the input range of the analog-digital conversion circuit 4000.
[0020] Switches 461 and 463 can maximize the input range of comparator 410 by applying the power supply voltage (VDD) to the input of comparator 410 during the initialization stage of comparator 410. Switches 461 and 463 are connected during the auto-zeroing (AZ) operation shown in FIG. 2 to initialize comparator 410 and are not connected during the reset operation and the determination operation, so that the analog input signal (IN) to be sampled can be input to comparator 410.
[0021] Comparator 410 can have an analog input signal (IN) 470 to be sampled input to one terminal, and a ramp signal (RAMP) 460 applied from a ramp signal generator (not shown) input to the other terminal, and compare the values of the two signals to output a comparison result signal (CMP). Here, the ramp signal (RAMP) can be a reference voltage for comparison, and the ramp signal generator can also be referred to as a reference voltage generator. The comparison result signal (CMP) can be either "1" corresponding to logic high or "0" corresponding to logic low. At this time, since the ramp signal (RAMP) 460 is a signal whose voltage level decreases (or increases) as time passes, there comes a point when the values of the two signals input to comparator 410 match, and the value of the comparison result signal (CMP) output from comparator 410 while passing through the matching point will invert from logic low to logic high or from logic high to logic low.
[0022] The counter 420 can count the reference clock (CLK) from the time when the ramp signal (RAMP) decreases (or increases), and output the count information (CNTO). When the value of the comparison result signal (CMP) output from the comparator 410 is inverted, the switch 440 is operated, and as a result, the count information (CNTO) output from the counter 420 can be latched and stored in the register 430. In FIG. 1, it is shown that the comparison result signal (CMP) output from the comparator 410 turns the switch 440 on and off. According to other embodiments, the comparison result signal (CMP) output from the comparator 410 can function as an enable signal for the register 430, and the count information output from the counter 420 may be directly connected to the input of the register 430. Then, at the time when the comparison result signal (CMP) is inverted, the count information (CNTO) can be temporarily stored in the register 430 by the enable signal of the register 430. The count information stored in the register 430 can be output as a digital signal.
[0023] The control circuit 425 can generate a reference clock (CLK) and transmit it to the counter 420. Also, the control circuit 425 can control the on and off of the switches 461 and 463.
[0024] When a plurality of analog-to-digital conversion circuits are used, each analog-to-digital conversion circuit can have different characteristics from each other, and thereby an undesirable offset may be added to the sampling result. Thus, in order to compensate for the offset included during analog-to-digital conversion, the analog input signal can be sampled using a correlated double sampling (CDS) method as shown in FIG. 2.
[0025] Referring to FIG. 2, the correlated double sampling (CDS) method may be an analog-to-digital conversion method including an auto zeroing (AZ) operation 481, a first reset operation 483, a first determination operation 485, a second reset operation 487, and a second determination operation 489.
[0026] In the correlated double sampling (CDS) method, during the auto zeroing operation 481, an operation for removing the offset existing in the comparator 410 can be performed. For this purpose, the switches 461 and 463 in FIG. 1 can be turned on (ON) to connect the input terminals of the comparator 410 to the power supply voltage (VDD).
[0027] During the first reset operation 483, the ramp signal (RAMP) can be boosted and raised to a preset voltage.
[0028] During the first determination operation 485, the analog input signal (IN) is a reset analog signal, and the ramp signal (RAMP) can be a voltage that decreases from the preset voltage at a constant slope. The analog-to-digital conversion circuit 4000 can count the reset analog input signal (IN) as a reference for removing the noise contained in the analog input signal (IN) and obtaining accurate data. The analog-to-digital conversion circuit 4000 can use the value counted until the output (CMP) of the comparator 410 is converted during the first determination operation 485 as a reference value. The value counted during the first determination operation 485 may vary depending on the noise or offset contained in the input signal (IN).
[0029] When the output (CMP) of the comparator 410 is converted, the ramp signal (RAMP) can be raised again to the preset voltage while the second reset operation 487 is being performed.
[0030] If so, during the second reset operation 487, the output (CMP) of the comparator 410 can be converted back to logic high, as shown in FIG. 2. During the second reset operation 487, the analog input signal has its reset state released and can be the actually measured value.
[0031] During the second determination operation 489, the analog input signal (IN) is the actually measured value, and the ramp signal (RAMP) can be a voltage that decreases from the already set voltage at a constant slope. During the second determination operation 489, the analog-to-digital conversion circuit 4000 can latch the counted value until the output (CMP) of the comparator 410, which compares the analog input signal (IN) and the ramp signal (RAMP), is converted. And the final result can be the value counted during the second determination operation 489 minus the value counted during the first determination operation 485.
[0032] Referring to FIG. 4, the analog-to-digital conversion circuit 4000 can perform an auto-zeroing operation in operation S610. The analog-to-digital conversion circuit 4000 can turn on the switches 461, 463 in FIG. 1 and connect the input terminals of the comparator 410 to the power supply voltage (VDD) for the auto-zeroing operation to remove the offset existing in the comparator 410.
[0033] Referring to FIGS. 3 and 4, in operation S620, the analog-to-digital conversion circuit 4000 can perform analog-to-digital (AD) conversion on a reference signal. For this purpose, the control circuit 425 of the analog-to-digital conversion circuit 4000 can generate an offset detection control signal that turns off the switches 461 and 463 in FIG. 1 and controls to apply a preset reference value to the input signal (IN). According to one embodiment, the analog-to-digital conversion circuit 4000 can further include a reference value generator (not shown) that provides a preset reference value corresponding to the offset detection control signal. However, the preset reference value is determined by the logic provided at the front end of the analog-to-digital conversion circuit 4000 that generates the input signal (IN). Therefore, according to other embodiments, the preset reference value may also be generated by the logic provided at the front end of the analog-to-digital conversion circuit 4000 that generates the input signal (IN).
[0034] The analog-to-digital conversion circuit 4000 can perform a first reset operation 483 and a first determination operation 485, and can perform analog-to-digital conversion on a reference signal. During the first reset operation 483, the ramp signal (RAMP) can be output at the maximum value, and a reset state analog input signal, which is a reference signal, can be input to the analog input signal (IN) of the comparator 410. Here, the reset state analog input signal can be the maximum value that the analog input signal can have. During the first reset operation 483, the analog-to-digital conversion circuit 4000 can sample and hold the signal input by the analog input signal (IN1). The analog-to-digital conversion circuit 4000 can measure and hold the value of the analog input signal (IN1) at the time when the first reset operation 483 is performed and can use it as it is in the first determination operation 485. Thus, even if the analog input signal (IN1) is changed after sampling, it can have no effect on the digital value to be converted.
[0035] The analog-to-digital conversion circuit 4000 can determine a digital conversion value for a reference signal in the first determination operation of operation S620. During the first determination operation 485, as shown in FIG. 3, the counter 420 can output a count value (CNTO) that increases one by one based on a reference clock (CLK). Also, the ramp signal (RAMP) can become a voltage that continuously decreases by a certain magnitude (dV) based on the reference clock (CLK). The comparator 410 can output a comparison result signal (CMP) that compares the ramp signal (RAMP) and the analog input signal (IN1) based on the reference clock (CLK). The comparator 410 can output a logic high as the result value when the ramp signal (RAMP) is greater than the analog input signal (IN1), and can output a logic low result value when the ramp signal (RAMP) is less than the analog input signal (IN1). The analog-to-digital conversion circuit 4000 can repeat the above operation until the output (CMP) of the comparator 410 is converted from logic high to logic low.
[0036] When the result value of the comparator 410 becomes logic low, the analog-to-digital conversion circuit 4000 can latch the count value (CNTO) (e.g., 3) of the counter 420 and temporarily store it, end the first determination operation 485, and proceed to operation S630.
[0037] In operation S630, the control circuit 425 of the analog-digital conversion circuit 4000 can generate a conversion control signal for controlling such that an analog signal to be converted into a digital value is applied to the input signal (IN). As a result, the analog-digital conversion circuit 4000 can perform the second reset operation 487 and the second determination operation 489, and can perform analog-digital conversion on the actually acquired analog signal. During the second reset operation 487, the ramp signal (RAMP) can be output at the maximum value, and an actual analog input signal can be input to the analog input signal (IN1) of the comparator 410. According to one embodiment, the analog input signal (IN1) can be a signal from which the DC component has been removed from the actually acquired analog input signal (IN) by the DC blocking capacitor 451.
[0038] During the second reset operation 487, the analog-digital conversion circuit 4000 can sample and hold (S&H) the signal input as the analog input signal (IN1). The analog-digital conversion circuit 4000 measures and holds the value of the analog input signal (IN1) at the time when the second reset operation 487 is performed, and can use it as it is in the second determination operation 489. As a result, even if the analog input signal (IN1) is changed after sampling, it can have no influence on the digital value to be converted. According to one embodiment, the operation of sampling and holding the signal can be performed not by the analog-digital conversion circuit 4000 but by an external device that acquires the analog input signal.
[0039] The analog-digital conversion circuit 4000 can determine the digital conversion value for the actually measured analog input signal (IN1) in the second determination operation 489 of operation S630. During the second determination operation 489, as shown in FIG. 3, the counter 420 can output a count value (CNTO) that increases one by one based on the reference clock (CLK). Also, the ramp signal (RAMP) can become a voltage that continuously decreases by a certain magnitude (dV) based on the reference clock (CLK). The comparator 410 can output a comparison result signal (CMP) that compares the ramp signal (RAMP) and the analog input signal (IN1) based on the reference clock (CLK). The comparator 410 can output a logic high as the result value when the ramp signal (RAMP) is greater than the analog input signal (IN1), and can output a logic low result value when the ramp signal (RAMP) is less than the analog input signal (IN1). The analog-digital conversion circuit 4000 can repeat the above operation until the output (CMP) of the comparator 410 is converted from logic high to logic low. When the result value of the comparator 410 becomes logic low, the analog-digital conversion circuit 4000 can latch and temporarily store the count value (CNTO) (e.g., 7) of the counter 420, end the second determination operation 489, and proceed to operation S640.
[0040] In operation S640, the analog-digital conversion circuit 4000 can output the difference between the digital value (e.g., 3) for the reference signal acquired and temporarily stored in operation S620 and the digital value for the analog signal actually acquired in operation S630 as the final digital value (OUT). In the example of FIG. 3, the analog-digital conversion circuit 4000 can output 4, which is obtained by subtracting 3 from 7, as the final digital value (OUT).
[0041] FIG. 5 is a drawing showing the input signal (IN), the output (OUT), and the signal (IN1) from which the DC component has been removed while the input signal passes through the DC blocking capacitor in FIG. 1.
[0042] Referring to FIG. 5, the input signal can have a constant DC component (Vdc). When such an input signal passes through the DC blocking capacitor 451, the DC component is removed, and only the analog signal can remain. This analog signal can have a voltage between 0V and VDD and can match the input range of the comparator 410.
[0043] The signal input to the analog-to-digital conversion circuit 4000 can generate an output (OUT) according to the operating speed of the analog-to-digital conversion circuit 4000. Here, the output (OUT) can be a digital signal composed of multiple bits. When the operating speed is fast, the output can more precisely follow the analog input signal (IN1). In each time interval T1, T2, …, T19 in FIG. 5, it can operate with the analog-to-digital conversion circuit 4000 described based on FIGS. 3 and 4 and provide the output (OUT). As described above, during analog-to-digital conversion, the input signal (IN) can be sampled and held (S&H) at the start of each time interval T1, T2, …, T19 so that the change in the input signal (IN) has no effect.
[0044] FIG. 6 is a drawing showing the structure of an analog-to-digital conversion device provided with a plurality of analog-to-digital conversion circuits proposed in the present disclosure.
[0045] Referring to FIG. 6, in order to process a large amount of data, a plurality of analog-to-digital conversion circuits 630-1, …, 630-K can be provided on one chip or one device. At this time, each of the plurality of analog-to-digital conversion circuits 630-1, …, 630-K can have a structure in which the counter 420 and the control circuit 425 are removed in the analog-to-digital conversion circuit 4000 of FIG. 1. Instead, as shown in FIG. 6, only one counter 620 is provided outside the analog-to-digital conversion circuits 630-1, …, 630-K and is connected to all the analog-to-digital conversion circuits 630-1, …, 630-K to transmit the same count value to each of the analog-to-digital conversion circuits 630-1, …, 630-K.
[0046] Also, as shown in FIG. 6, the control circuit 640 is also provided only outside the analog-digital conversion circuits 630-1, …, 630-K, and can provide a reference clock (CLK) to the counter 620, and can additionally control the lamp signal generator 610.
[0047] Also, as shown in FIG. 6, the lamp signal generator 610 is provided outside, and the same lamp signal can be provided to all the analog-digital conversion circuits 630-1, …, 630-K.
[0048] The configuration of the plurality of analog-digital conversion circuits shown in FIG. 6 can be applied to an ACiM (analog computing in memory) system or a CMOS image sensor.
[0049] FIG. 7 is a drawing showing an example in which the plurality of analog-digital conversion circuits of FIG. 6 are applied to an ACiM system.
[0050] Referring to FIG. 7, the ACiM system can include a digital-to-analog converter (DAC) that converts digital input signals (X1 to X4) into analog signals (V1 to V4), and an analog-to-digital converter (ADC) that converts internal operation results (A1 to A4) into digital output signals (D1 to D4).
[0051] Also, inside the ACiM system, weighted values (from g11 to g44) can be stored as analog values in the memory or register of the nodes where each row and column intersect. The weighted values (from g11 to g44) can be conductances and can perform a multiplication operation on the applied analog signals (from V1 to V4) to output a current. Then, the currents output from the nodes in the same column are summed up to become internal operation results (from A1 to A4) and can be input to the ADC block 710. Here, the ADC block 710 can be composed of a plurality of analog-to-digital conversion circuits shown in FIG. 6. According to one embodiment, the internal operation results (from A1 to A4) can be converted into voltages before being input to the ADC block 710.
[0052] FIG. 8 is a drawing showing an example in which a plurality of analog-to-digital conversion circuits in FIG. 6 are applied to a CMOS image sensor.
[0053] Referring to FIG. 8, the CMOS image sensor 1000 can include a pixel array 110, a row decoding circuit 120, a ramp signal generator 130, an ADC block (analog-to-digital converter block) 140, a data output circuit 150, and a control unit 160. Here, the ramp signal generator 130 is the same as the ramp signal generator 610 in FIG. 6, and the ADC block 140 can include the counter 620 and a plurality of analog-digital converter circuits (analog-digital converter circuit) 630-1,..., 630-K in FIG. 6. Also, the control unit 160 can include the control circuit 425 in FIG. 6.
[0054] The pixel array 110 can include a plurality of pixels arranged in a matrix structure. The pixel array 110 can output an analog pixel signal (POUT), which converts the incident optical signal into an electrical signal, to the ADC block 140. Here, the pixel array 110 can be driven by drive signals such as a reset signal (RX), a transmission signal (TX), or a selection signal (SX) applied from the load decoding circuit 120.
[0055] The load decoding circuit 120 selects a row of the pixel array 110. That is, the load decoding circuit 120 can select each pixel in the pixel array 110 row by row and control its operation according to a control signal (CON) applied from the control unit 160.
[0056] The ramp signal generator 130 can generate a ramp signal (RAMP) according to a control signal (CON) applied from the control unit 160. The ramp signal generated by the ramp signal generator 130 can be input to all the analog-digital conversion circuits 630-1, …, 630-K in the ADC block 140.
[0057] According to one embodiment, the ramp signal generator 130 can output a ramp signal (RAMP) of a voltage that decreases by a preset value from the previous value every time a clock is input in synchronization with the reference clock (CLK). For example, the first clock can output a voltage of VDD-dV during the clock cycle, and the second clock can output a voltage of VDD-2dV during the clock cycle.
[0058] The ADC block 140 can convert the analog pixel signal (POUT) output from the pixel array 110 into a digital signal. Each of the analog-digital conversion circuits 630-1, …, 630-K in the ADC block 140 can convert the analog pixel signal (POUT) into a digital signal by the method described with reference to FIG. 3 or FIG. 4.
[0059] The ADC block 140 can compare the pixel signal (POUT) output from the pixel array 110 with the ramp signal (RAMP) applied from the ramp signal generator 130. The ADC block 140 counts the reference clock (CLK) approved from the control unit 600 corresponding to the comparison value between the pixel signal (POUT) and the ramp signal (RAMP), and for the analog pixel signal (POUT) of each column, digital signals (from D1 to D K ) can be output.
[0060] The data output circuit 150 can latch the digital signals (from D1 to D K ) applied from the ADC block 140. The data output circuit 150 can latch the count information and sequentially output pixel data (DOUT) in digital format corresponding to the output control signal (OCON) and the reference clock (CLK).
[0061] The control unit 160 can control the operations of the load decoding circuit 120, the ramp signal generator 130, the ADC block 140, and the data output circuit 150. According to one embodiment, the control unit 160 can include a timing generator. Also, the control unit 160 can use this to control various procedures from the sensing of the image until the sensed image data is output by time information.
[0062] The control unit 160 can generate a control signal (CON) and output it to the load decoding circuit 120 and the ramp signal generator 130. Also, the control unit 160 can generate a reference clock (CLK) and output it to the ADC block 140. Further, the control unit 160 can generate an output control signal (OCON), a reference clock (CLK), and a sensing enable signal (SEN) and transmit them to the data output circuit 150.
[0063] The control unit 160 generates a control signal that enables the signals received from the pixels of the pixel array 110 to be converted into digital signals using a correlated double sampling method, and can control the lamp signal generator 130 and the ADC block 140.
[0064] As described above, the analog-to-digital conversion circuit proposed in the present disclosure can be used in an ACiM system or a CMOS image sensor. In particular, it can be developed from a single-slope analog-to-digital conversion circuit based on a static comparator used in a conventional image sensor to a single-slope analog-to-digital conversion circuit based on a dynamic comparator that operates in synchronization with a clock. This has the advantage of reducing the power consumed by the analog-to-digital conversion circuit, increasing the operating speed, and further reducing the area required for implementing the embodiments of the present disclosure.
[0065] Also, as shown in FIG. 7, the analog-to-digital conversion circuit proposed in the present disclosure can be used in an ACiM system. Compared with the SAR (Successive Approximation Register) analog-to-digital conversion circuit used in a conventional ACiM system, it has the advantage that it can be implemented in a smaller area and can significantly increase the operating speed.
[0066] In addition, the analog-to-digital conversion circuit proposed in the present disclosure can maximize the input range of the analog-to-digital conversion circuit while solving the problem of mismatch in the operating range between the output of the ACiM system and the input of the comparator.
[0067] In FIGS. 7 and 8, an example of applying the analog-to-digital conversion circuit proposed in the present disclosure to an ACiM system or a CMOS image sensor is described. However, the application of the analog-to-digital conversion circuit proposed in the present disclosure is not limited to this, and it can also be used in the same or a similar manner in all necessary electronic devices.
Explanation of Reference Numerals
[0068] 110 pixel array 120 load decoding circuit 130 lamp signal generator 140 ADC block 150 data output circuit 160 control unit 410 comparator 420 counter 425 control circuit 430 register 440 switch 451, 453 DC blocking capacitor 460 ramp signal (RAMP) 461, 463 switch 600 control unit 610 lamp signal generator 620 counter 630-1 analog-to-digital conversion circuit 640 control circuit 710 ADC block 1000 CMOS image sensor 4000 analog-to-digital conversion circuit
Claims
1. A comparator comprising a first input terminal, a second input terminal, and an output terminal, which compares an input signal input to the first input terminal with a reference voltage that is input to the second input terminal and decreases from a previous value by a preset value in response to the input of each clock signal, and outputs a comparison result value to the output terminal; A counter that outputs a digital count value that increases one by one each time the clock signal is input; A register that latches and stores the digital count value based on the comparison result value, and generates a digital value corresponding to the input signal based on the latched digital count value; A first blocking capacitor having one end connected to the first input terminal and transmitting the input signal to the first input terminal; and A control circuit that generates the clock signal, An analog-to-digital conversion device.
2. A first switch connected between the first blocking capacitor and the first input terminal and providing a power supply voltage (VDD) to the first input terminal; and The analog-to-digital conversion device according to claim 1, further comprising a second switch connected to the second input terminal and providing the power supply voltage to the second input terminal. The analog-to-digital conversion device according to claim 1.
3. The control circuit Generates a switch control signal for controlling the first switch and the second switch, The analog-to-digital conversion device according to claim 2.
4. The control circuit Generates a switch control signal for turning on the first switch and the second switch to perform an auto-zeroing operation, The analog-to-digital conversion device according to claim 3.
5. The control circuit Generates the switch control signal for turning off the first switch and the second switch, and generates an offset detection control signal for controlling so that a preset reference value is applied to the input signal, The analog-to-digital conversion device according to claim 4.
6. The control circuit Further includes a reference value generator connected to the other end of the first blocking capacitor and providing the preset reference value in response to the offset detection control signal, The analog-to-digital conversion device according to claim 5.
7. The register Stores a first digital count value obtained by latching the digital count value corresponding to the preset reference value, The analog-to-digital conversion device according to claim 5.
8. The control circuit generates a conversion control signal for controlling such that an analog signal to be converted is applied to the input signal, The register subtracts the first digital count value from the second digital count value obtained by latching and acquiring the digital count value corresponding to the analog signal, and generates the digital value, The analog-to-digital conversion device according to claim 7.
9. further comprising a reference voltage generator for generating the reference voltage, The analog-to-digital conversion device according to claim 1.
10. further comprising a second blocking capacitor connected between the second input terminal and the reference voltage generator for transmitting the reference voltage to the second input terminal, The analog-to-digital conversion device according to claim 9.
11. The comparator outputs, as the comparison result value, a first value if the reference voltage is greater than the input signal, and a second value different from the first value if the reference voltage is smaller than or equal to the input signal, The analog-to-digital conversion device according to claim 1.
12. The register latches the digital count value when the comparison result value changes from the first value to the second value, The analog-to-digital conversion device according to claim 11.
13. The control circuit outputs the clock signal when the comparison result value output by the comparator is the first value, The analog-to-digital conversion device according to claim 11.
14. a reference voltage generator that generates a reference voltage whose preset value decreases from a previous value in response to an input of each clock signal; a counter that outputs a digital count value that increases one by one each time the clock signal is input; a control circuit that generates the clock signal; and including a plurality of analog-to-digital conversion circuits, each of the plurality of analog-to-digital conversion circuits includes a first input terminal, a second input terminal, and an output terminal, and a comparator that compares an input signal input to the first input terminal with the reference voltage input to the second input terminal and outputs a comparison result value to the output terminal; a register that latches (stores) the digital count value based on the comparison result value and generates a digital value corresponding to the input signal based on the latched digital count value; and including a first blocking capacitor having one end connected to the first input terminal for transmitting the input signal to the first input terminal, An analog-to-digital conversion device.
15. Each of the plurality of analog-to-digital conversion circuits includes a first switch connected between the first blocking capacitor and the first input terminal to provide a power supply voltage (VDD) to the first input terminal; and further includes a second switch connected to the second input terminal to provide the power supply voltage to the second input terminal, wherein the control circuit generates a switch control signal for controlling all of the first switches and the second switches of the plurality of analog-to-digital conversion circuits, The analog-to-digital conversion device according to claim 14.
16. The control circuit generates the switch control signal to turn on all of the first switches and the second switches of the plurality of analog-to-digital conversion circuits in order to perform an auto-zeroing operation of the plurality of analog-to-digital conversion circuits, after a predetermined time, generates the switch control signal to turn off the first switch and the second switch, and generates an offset detection control signal for controlling so that a preset reference value is applied to the first input terminal of the plurality of analog-to-digital conversion circuits, after all of the plurality of analog-to-digital conversion circuits have obtained a first digital count value for the preset reference value, generates a conversion control signal for controlling so that a first input signal to be converted is applied to the first input terminal, The analog-to-digital conversion device according to claim 15.
17. Each register of the plurality of analog-to-digital conversion circuits stores the first digital count value obtained by latching the digital count value corresponding to the preset reference value, subtracts the first digital count value from the first digital count value obtained by latching the digital count value corresponding to the first input signal to generate the digital value, The analog-to-digital conversion device according to claim 16.
18. Each comparator of the plurality of analog-to-digital conversion circuits outputs a first value as the comparison result value if the reference voltage is greater than the first input signal, and outputs a second value different from the first value if it is smaller than or equal to the first input signal, The analog-to-digital conversion device according to claim 16.
19. Each register of the plurality of analog-to-digital conversion circuits Latch the digital count value when the comparison result value changes from the first value to the second value. The analog-to-digital conversion device according to claim 18.
20. A pixel array including a plurality of pixels formed at intersections where a plurality of rows and a plurality of columns intersect; A row decoding circuit that selects a row that outputs a pixel signal from the pixel array; A reference voltage generator that generates a reference voltage whose preset value decreases from a previous value in response to an input of each clock signal; A counter that outputs a digital count value that increases one by one each time the clock signal is input; A control circuit that generates the clock signal; and Including a plurality of analog-to-digital conversion circuits provided for each of the plurality of columns, and generating digital values for the pixel signals of each column using the reference voltage, Each of the plurality of analog-to-digital conversion circuits A comparator having a first input terminal, a second input terminal, and an output terminal, comparing an input signal input to the first input terminal with the reference voltage input to the second input terminal, and outputting a comparison result value to the output terminal; A register that latches and stores the digital count value based on the comparison result value, and generates a digital value corresponding to the input signal based on the latched digital count value; and Including a first blocking capacitor having one end connected to the first input terminal and transmitting the input signal to the first input terminal, A CMOS image sensor.
21. A memory array including a memory in which weighting value information is stored, formed at intersections where a plurality of rows and a plurality of columns intersect; A plurality of digital-to-analog converters provided at input ends of each of the plurality of rows, and converting each of the plurality of digital input signals into an analog signal; A reference voltage generator that generates a reference voltage whose preset value decreases from a previous value in response to an input of each clock signal; A counter that outputs a digital count value that increases one by one each time the clock signal is input; A control circuit that generates the clock signal; and Including a plurality of analog-to-digital conversion circuits provided for each of the plurality of columns, physically multiplying the analog signal corresponding to the weighting value information input to the row where each column intersects, and converting the summed analog signal into a digital signal, Each of the plurality of analog-to-digital conversion circuits A comparator comprising a first input terminal, a second input terminal, and an output terminal, which compares an input signal input to the first input terminal with the reference voltage input to the second input terminal and outputs a comparison result value to the output terminal; A register that latches and stores the digital count value based on the comparison result value and generates a digital value corresponding to the input signal based on the latched digital count value; and A first blocking capacitor having one end connected to the first input terminal and transmitting the input signal to the first input terminal, An ACiM (analog computing in memory) system.