Power supply circuit

Abstract

To solve the problem in a conventional power supply circuit which is difficult to supply power to a load circuit with a voltage maintaining a maximum voltage applicable to the load circuit using a charge pump circuit.SOLUTION: A power supply circuit comprises: a charge pump circuit 11; an output suppression circuit which is connected in parallel with an output capacitor of the charge pump circuit 11 and in which an output limitation resistor RDL and a switch circuit SW are connected in series; and an enable control circuit 12 which outputs an enable signal EN instructing switching between an active state and an inactive state to a load circuit LD1. A resistance value of the output limitation resistor RDL is set equal to or less than a value at which an output voltage of the charge pump circuit 11 becomes equal to or less than a load end allowable voltage in a stationary state where a current supply capability of the charge pump circuit 11 becomes equal to current consumption in the output limitation resistor RDL.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a power supply circuit, for example, a power supply circuit that supplies an output voltage generated by a charge pump circuit to a load circuit.

Background Art

[0002] In an electronic circuit system, even when an external power supply outputs only one power supply voltage, power is supplied to the system from the external power supply, the power supply voltage of the external power supply is voltage-converted within the system, and is supplied to circuits within the system, so that a plurality of circuits operating at different power supply voltages within the system can be operated. Therefore, techniques for converting the power supply voltage output by the external power supply within the system are disclosed in Patent Documents 1 and 2.

[0003] The power supply fluctuation suppression device described in Patent Document 1 is a power supply fluctuation suppression device that is connected to a load circuit that operates based on the input of an activation signal and suppresses fluctuations in the output current of the power supply based on the operation of the load circuit. The power supply fluctuation suppression device includes a current consumption circuit that passes a consumption current in parallel with the load current flowing through the load circuit, and a data generation circuit that generates a digital output signal for controlling the current consumption circuit so as to suppress fluctuations in the output current, which is the sum of the load current and the consumption current, when the load current rises and falls. The power supply fluctuation suppression device is configured by a D / A converter that converts the digital output signal into an analog signal and controls the consumption current of the current consumption circuit.

[0004] The power supply circuit system described in Patent Document 2 is configured to be able to control the oscillation frequency, and includes an oscillation circuit that outputs an oscillation output signal, a charge pump circuit that outputs a boosted voltage obtained by boosting an input voltage in response to the oscillation output signal, a voltage regulator circuit that adjusts the boosted voltage of the charge pump circuit to a predetermined voltage, and a control circuit that outputs a control signal for controlling the oscillation circuit such that when a first current flowing through the voltage regulator circuit is smaller than a first reference current, the oscillation frequency of the oscillation circuit is increased, when the first current is larger than a second reference current, the oscillation frequency of the oscillation circuit is decreased, and when the first current is between the first reference current and the second reference current, the oscillation frequency of the oscillation circuit is maintained.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] Here, in a power supply circuit that uses a charge pump circuit as a power source, the output voltage has a characteristic that it is limited to a multiple of the number of boosting stages. On the other hand, in a load circuit that receives power supply from the power supply circuit, a maximum rated voltage determined by the characteristics of elements such as internal transistors is set. When trying to operate such a load circuit at the highest possible power supply voltage, if a charge pump type power supply circuit is applied, there will be a problem that the output voltage of the charge pump circuit exceeds the maximum rated voltage of the load circuit and the performance of the load circuit has to be degraded.

[0007] On the one hand, the power supply fluctuation suppression device described in Patent Document 1 controls a current consumption circuit so that the output current from a power supply circuit does not fluctuate between the state where a load circuit is operating and the state where it is not operating. However, in Patent Document 1, although the power supply voltage fluctuation can be suppressed in a state where the power supply voltage is set to be equal to or lower than the maximum rated voltage of the load circuit, a power supply voltage that exceeds the maximum rated voltage of the load circuit cannot be suppressed to be equal to or lower than the maximum rated voltage of the load circuit, and the above problem cannot be solved.

[0008] Also, the power supply circuit system described in Patent Document 2 suppresses the output voltage fluctuation of a charge pump circuit by changing the operating frequency of the charge pump circuit in accordance with the fluctuation of the consumption current of the load circuit. However, also in Patent Document 2, the output voltage of the charge pump circuit that exceeds the maximum rated voltage of the load circuit cannot be suppressed to be equal to or lower than the maximum rated voltage of the load circuit, and the above problem cannot be solved.

Means for Solving the Problem

[0009] One aspect of the power supply circuit according to the present invention includes a charge pump circuit having a power supply capability capable of outputting a maximum output voltage equal to or higher than a load terminal allowable voltage calculated by subtracting a margin voltage preset in the load circuit from the maximum rated voltage of the load circuit when there is no load, an output suppression circuit connected in parallel with the output capacitance of the charge pump circuit and having an output limiting resistor and a switch circuit connected in series, and an enable control circuit that outputs an enable signal for instructing the load circuit to switch between an operating state and a non-operating state. The resistance value of the output limiting resistor is set to be equal to or lower than a value at which the output voltage of the charge pump circuit becomes equal to or lower than the load terminal allowable voltage in a steady state where the current supply capability of the charge pump circuit is equal to the current consumption in the output limiting resistor, and the enable control circuit controls the switch circuit to be in a conducting state during a period in which the load circuit is controlled to be in a non-operating state by the enable signal.

[0010] The power supply circuit according to the present invention uses an output limiting resistor to make the output voltage of the charge pump circuit lower than the maximum value of the output voltage of the charge pump circuit and lower than the load terminal voltage calculated by subtracting a margin voltage preset in the load circuit from the maximum rated voltage of the load circuit.

Advantages of the Invention

[0011] According to the power supply circuit of the present invention, the load circuit can be supplied with power at a voltage that maintains the maximum voltage that can be applied to the load circuit using the charge pump circuit.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0013] Embodiment 1 For clarity of explanation, the following description and drawings are appropriately omitted and simplified. Also, in each drawing, the same elements are denoted by the same reference numerals, and duplicate explanations are omitted as necessary.

[0014] FIG. 1 shows a block diagram of a circuit system 1 including a power supply circuit 10 according to Embodiment 1. The circuit system 1 can be formed on one semiconductor chip, or the power supply circuit 40 and the load circuit LD1 can be implemented as separate circuits. The load circuit LD1 can be a circuit having various functions such as a constant voltage circuit, a regulator circuit, an arithmetic circuit, and an input / output interface circuit.

[0015] As shown in FIG. 1, the power supply circuit 10 includes a charge pump circuit 11, an enable control circuit 12, an output limiting resistor RDL, and a switch circuit SW. The charge pump circuit 11 generates a charge pump output voltage Vcp by boosting the power supply voltage VDD externally supplied to the circuit system 1. Also, the charge pump circuit 11 uses a clock signal CLK supplied from a clock generation circuit (not shown in FIG. 1) provided in the circuit system 1 for the boosting operation. The charge pump circuit 11 supplies the charge pump output voltage Vcp to the load circuit LD1.

[0016] The output limiting resistor RDL and the switch circuit SW are connected in series between the output terminal and the ground terminal of the charge pump circuit 11, and constitute an output suppression circuit connected in parallel with the output capacitance Co (details will be described with reference to FIG. 2) in the charge pump circuit 11.

[0017] The enable control circuit 12 outputs an enable signal EN for instructing the load circuit LD1 to switch between an operating state and a non-operating state. Further, the enable control circuit 12 controls the switch circuit SW to be in a conducting state during the period when the load circuit LD1 is controlled to be in a non-operating state by the enable signal EN. That is, the enable control circuit 12 exclusively controls the effective state and the invalid state of the output limiting resistor RDL and the load circuit LD1 by applying the enable signal EN to the switch circuit SW and the load circuit LD1.

[0018] In FIG. 1, as an example of the enable control circuit 12, an enable signal EN output from an enable signal generation circuit in a circuit system 1 (not shown) is directly supplied to a load circuit LD1, and an enable signal EN having an inverted logic is supplied to a switch circuit SW via an inverter circuit 13. The configuration is shown.

[0019] Here, the charge pump circuit 11 will be described in detail. FIG. 2 shows a circuit diagram for explaining an example of the charge pump circuit 11 according to the first embodiment. Note that in FIG. 2, an output limiting resistor RDL is illustrated to explain the relationship between the charge pump circuit 11 and the output limiting resistor RDL.

[0020] As shown in FIG. 2, the charge pump circuit 11 includes diodes 21, 23, 25, inverter circuits 22, 24, boost capacitors C1, C2, and an output capacitor Co. The anode of diode 21 is supplied with a power supply voltage VDD. The input of inverter circuit 22 is supplied with a clock signal CLK. Inverter circuit 22 outputs a signal having the inverted logic of the input clock signal CLK. Then, boost capacitor C1 is provided between the cathode of diode 21 and the output terminal of inverter circuit 22. The anode of diode 23 is connected to the cathode of diode 21. The input of inverter circuit 24 is supplied with the output signal of inverter circuit 22. Inverter circuit 24 outputs a signal having the inverted logic of the input signal. Then, boost capacitor C2 is provided between the cathode of diode 23 and the output terminal of inverter circuit 24. The anode of diode 25 is connected to the cathode of diode 23. And output capacitor Co is provided between the cathode of diode 25 and the ground terminal. The cathode of diode 25 serves as the output terminal of charge pump circuit 11, and charge pump circuit 11 outputs a charge pump output voltage Vcp generated at the cathode of diode 25. Also, when switch circuit SW is in the conductive state, output limiting resistor RDL is connected between the output terminal of charge pump circuit 11 and the ground terminal. That is, when switch circuit SW is in the conductive state, output limiting resistor RDL and output capacitor Co are connected in parallel between the output terminal of charge pump circuit 11 and the ground terminal.

[0021] Here, the charge pump circuit 11 accumulates, in the boost capacitor C1, a charge that results in a voltage (VDD - Vf), which is the power supply voltage VDD minus the diode voltage Vf, via the diode 21 during the period when the output signal of the inverter circuit 22 is at a low level. Then, during the period when the output signal of the inverter circuit 22 is at a high level and the output signal of the inverter circuit 24 is at a low level, the charge accumulated in the boost capacitor C1 is transferred to the boost capacitor C2. As a result, a charge with a maximum voltage of 2×(VDD - Vf) is accumulated in the boost capacitor C2. And during the period when the output signal of the inverter circuit 24 is at a high level, the charge accumulated in the boost capacitor C2 is transferred to the output capacitor Co. As a result, a charge with a maximum voltage of 3×(VDD - Vf) is accumulated in the output capacitor Co. That is, if the output current drawn from the output capacitor Co is zero (Io = 0 mA) in a no-load state, the output voltage of the charge pump circuit 11 becomes a maximum of 3×(VDD - Vf).

[0022] In the circuit system 1 according to the first embodiment, by enabling the output limiting resistor RDL, even in a state where there is no current consumption by the load circuit DL1, the output current is drawn from the output capacitor Co by the output limiting resistor RDL, thereby suppressing the output voltage Vcp of the charge pump circuit 11 to a voltage lower than the charge pump maximum output voltage Vcp_max. Therefore, the magnitude of the output voltage Vcp set in the circuit system 1 according to the first embodiment will be described.

[0023] Therefore, FIG. 3 shows a diagram for explaining the output voltage setting of the charge pump circuit 11 according to Embodiment 1. As shown in FIG. 3, the power supply circuit 10 according to Embodiment 1 has the ability to output a maximum output voltage Vcp_max that is equal to or higher than the maximum rated voltage VE of the load circuit LD1 when there is no load. More specifically, in order to stably operate the load circuit LD1, the maximum voltage of the load terminal voltage applied to the load circuit LD1 must not be higher than the allowable load terminal voltage (VE - Vm) obtained by subtracting the margin voltage width Vm determined in consideration of variations in circuit manufacturing and the like from the maximum rated voltage VE. That is, when the power supply circuit 10 according to Embodiment 1 has the performance of being able to output a maximum output voltage Vcp_max at which the load terminal voltage applied to the load circuit LD1 is higher than the allowable load terminal voltage (VE - Vm) obtained by subtracting the margin voltage width Vm from the maximum rated voltage VE, the effect of safely using the load circuit LD1 is achieved. In the power supply circuit 10, an output limiting resistor RDL is used to suppress the charge pump output voltage Vcp when there is no load.

[0024] Also, as shown in FIG. 3, the power supply circuit 10 according to Embodiment 1 is required to have a current supply ability that can maintain a voltage equal to or higher than the operating lower limit voltage VD at which the operation is guaranteed while the load circuit LD1 is operating. That is, in the power supply circuit 10, in both the non-operating state and the operating state of the load circuit LD1, it is necessary to set the charge pump output voltage Vcp within the range of not less than the operating lower limit voltage VD and not more than the allowable load terminal voltage (VE - Vm). For this reason, in the power supply circuit 10, it is necessary to set the magnitude of the resistance value of the output limiting resistor RDL so that the charge pump output voltage Vcp is not less than the operating lower limit voltage VD even when there is no load.

[0025] Here, in the power supply circuit 10 according to Embodiment 1, a method for calculating the set value of the output limiting resistor RDL for setting the charge pump output voltage Vcp within the range of Vcp_max ≧ (VE - Vm) ≧ Vcp ≧ VD will be described.

[0026] In the following description, a method for calculating the resistance value of the output limiting resistor RDL will be described on the premise of the charge pump circuit 11 shown in FIG. 2. Further, in the following description, the power supply voltage is VDD, the clock period of the clock signal CLK for driving the charge pump circuit 11 is T, the charge pump output voltage of the charge pump circuit 11 is Vcp, the charge pump output voltage of the charge pump circuit 11 without load is Vcp_max, the charge pump output voltage of the charge pump circuit 11 is Vcp, the diode voltage of the diode in the charge pump circuit 11 is Vf, the capacitance value of the boost capacitor C2 of the charge pump circuit 11 is C2, the capacitance value of the output capacitor Co is Co, the resistance value of the output limiting resistor is RDL, the current flowing through the output limiting resistor RDL is Iout, the maximum rated voltage of the load circuit LD1 is VE, the margin voltage width set for the load circuit LD1 is Vm, the lower limit operating voltage of the load circuit LD1 is VD, and the current consumption in the operating state of the load circuit LD1 is IL will be used for the description.

[0027] First, the maximum charge pump output voltage Vcp_max of the charge pump circuit 11 is expressed by the formula (1). Vcp_max=(VDD-Vf)×3 ··· (1)

[0028] Also, the current Iout flowing through the output limiting resistor RDL is expressed by the formula (2). Iout=Vcp / RDL ··· (2) And, in the state where only the current Iout is consumed, the ripple voltage width ΔVout1 by which the charge pump output voltage Vcp fluctuates during one cycle of the clock signal CLK is expressed by the formula (3). ΔVout1=Iout×T / Co=Vcp / RDL×T / Co ··· (3) On the other hand, the rising voltage width ΔVout2 of the charge pump output voltage Vcp during one cycle of the clock signal CLK is determined by the ratio of the capacitance value of the boost capacitor C2 to the capacitance value of the output capacitor Co, and the ratio of the maximum charge pump output voltage Vcp_max to the charge pump output voltage Vcp, and is expressed by the formula (4). ΔVout2=(Vcp_max-Vcp)×C2 / (C2×Co) ··· (4)

[0029] Here, as the charge pump circuit 11 repeats the boosting operation, the charge pump output voltage Vcp converges to a voltage at which the ripple voltage width ΔVout1 and the rising voltage width ΔVout2 become equal. Therefore, Equation (5) can be derived from Equations (3) and (4). Vcp / RDL×T / Co =(Vcp_max - Vcp)×C2 / (C2×Co) ··· (5)

[0030] Subsequently, in the power supply circuit 10, since it is necessary to suppress the charge pump output voltage Vcp to be equal to or lower than the load-end allowable voltage (VE - Vm) obtained by subtracting the margin voltage width Vm from the maximum rated voltage VE, substituting it into the relationship (Equation (5)) where Vcp = VE - Vm, Equation (6) is derived. (VE - Vm) / RDL×T / Co =(Vcp_max - (VE - Vm))×C2 / (C2×Co) ··· (6) Then, the resistance value of the output limiting resistor RDL is obtained from Equation (7) derived from Equation (6). RDL < (VE - Vm) / (Vcp_max - VE + Vm)) ×(C2 + Co) / (C2×Co)×T ··· (7)

[0031] Note that the current Iout flowing through the output limiting resistor RDL can also be expressed by Equation (8). Iout = (VE - Vm) / RDL =(Vcp_max - VE + Vm))×(C2×Co) / (C2 + Co) / T ··· (8) Also, from Equation (8), the output limiting resistor RDL can also be expressed by Equation (9). RDL < (VE - Vm) / Iout ··· (9)

[0032] That is, the resistance value of the output limiting resistor RDL is set to a value at which the charge pump output voltage Vcp becomes equal to or lower than the load-end allowable voltage in the steady state where the current supply capacity of the charge pump circuit 11 and the current consumption amount in the output limiting resistor RDL become equal.

[0033] Also, the resistance value of the output limiting resistor RDL calculated by the above formula (7) or (9) is the maximum value. However, considering the relationship of Iout < IL where IL is the current consumption of the load circuit LD1, the minimum value of the resistance value of the output limiting resistor RDL is expressed by formula (10). RDL > VD / IL ··· (10)

[0034] That is, the resistance value of the output limiting resistor RDL is set to a value at which the charge pump output voltage Vcp is equal to or higher than the operation lower limit voltage VD in the steady state where the current supply capacity of the charge pump circuit 11 and the current consumption amount in the load circuit LD1 are equal.

[0035] Note that when the current supply capacity of the charge pump circuit 11 is determined by the magnitude of the current consumption IL of the load circuit LD1 in the operating state, the length T of one cycle of the clock signal CLK, and the allowable ripple voltage width VA, it can be adjusted by the magnitudes of the boost capacitor C2 and the output capacitor Co. Here, when the boost capacitors C1, C2, and the output capacitor Co have the same capacitance C, the capacitance value C can be determined by formula (11). C = IL × T / VA ··· (11)

[0036] Subsequently, the operation of the power supply circuit 10 having the output limiting resistor RDL with the resistance value set using formula (7) and formula (10) will be described. Therefore, FIG. 4 shows a timing chart for explaining the operation of the power supply circuit according to Embodiment 1. In FIG. 4, the horizontal axis represents time, and the vertical axis represents the variation of the charge pump output voltage Vcp. Also, in FIG. 4, a first comparative example and a second comparative example are shown as comparative examples. The first comparative example is the operation of a power supply circuit that performs three-stage boosting shown in FIG. 2 and does not have an output limiting resistor RDL. The second comparative example is the operation of a power supply circuit that performs two-stage boosting with the diode 21, the inverter circuit 22, and the boost capacitor C1 omitted from the charge pump circuit shown in FIG. 2 and does not have an output limiting resistor RDL.

[0037] As shown in FIG. 4, in the first comparative example, when the operation of the charge pump circuit is started at timing T1 with the load circuit LD1 stopped, the charge pump output voltage Vcp rises to the charge pump maximum output voltage Vcp_max at no load. That is, since the charge pump maximum output voltage Vcp_max exceeding the maximum rated voltage VE is applied to the load circuit LD1 at this point, there is a risk of a failure occurring in the load circuit LD1. On the other hand, in the first comparative example, when the operation of the load circuit LD1 is started at timing T2, the charge pump output voltage Vcp stabilizes within a range not exceeding the load terminal allowable voltage (VE - Vm) obtained by subtracting the margin voltage width Vm from the maximum rated voltage VE and not less than the operation lower limit voltage VD because the power supply circuit 10 draws the consumption current IL.

[0038] On the other hand, in the power supply circuit 10 according to the first embodiment, when the load circuit LD1 is stopped and the switch circuit SW is in the conductive state, and the charge pump circuit 11 is operated from timing T1 to increase the charge pump output voltage Vcp, the charge pump output voltage Vcp stabilizes within a range maintaining a voltage not exceeding the load terminal allowable voltage (VE - Vm) obtained by subtracting the margin voltage width Vm from the maximum rated voltage VE. Then, at timing T2, by shifting the load circuit LD1 to the operating state and setting the switch circuit SW to the cut-off state, the charge pump output voltage Vcp stabilizes within a range not exceeding the load terminal allowable voltage (VE - Vm) obtained by subtracting the margin voltage width Vm from the maximum rated voltage VE and not less than the operation lower limit voltage VD. That is, in the power supply circuit 10 according to the first embodiment, it is possible to set the charge pump output voltage Vcp within a range not exceeding the load terminal allowable voltage (VE - Vm) obtained by subtracting the margin voltage width Vm from the maximum rated voltage VE and not less than the operation lower limit voltage VD regardless of whether the load circuit LD1 is operating, and it is possible to prevent a state where the voltage applied to the load circuit LD1 violates the maximum rated voltage.

[0039] Here, refer to a second comparative example in which the number of boost stages is reduced by one in the power supply circuit according to the first comparative example so that the charge pump output voltage Vcp does not exceed the maximum rated voltage VE. In the power supply circuit according to the second comparative example, it is possible to set the maximum charge pump output voltage Vcp_max to be equal to or less than the maximum rated voltage VE. However, when the load circuit LD1 is in an operating state, a problem occurs in that the charge pump output voltage Vcp falls below the operating lower limit voltage VD, causing the load circuit LD1 to stop operating.

[0040] From the above description, in the power supply circuit 10 according to Embodiment 1, there is a charge pump circuit 11 having sufficient capacity to operate the load circuit LD1. However, even when the maximum charge pump output voltage Vcp_max output by the charge pump circuit 11 at no load becomes the load terminal voltage allowed by the load circuit LD1, there is an output limiting resistor RDL that suppresses the voltage of the charge pump output voltage Vcp when the load circuit LD1 stops. Thereby, in the power supply circuit 10 according to Embodiment 1, it becomes possible to supply a sufficient load terminal voltage to the load circuit LD1 during the period when the load circuit LD1 operates. The load circuit LD1 can maximize its performance such as driving ability and operating speed by supplying the highest possible load terminal voltage during the operating period. That is, in the circuit system 1 having the power supply circuit 10 according to Embodiment 1, it becomes easy to improve the performance of the load circuit LD1.

[0041] Embodiment 2 In Embodiment 2, a power supply circuit 30, which is a modified example of the power supply circuit 10 of Embodiment 1, will be described. In the description of Embodiment 2, the same components as those described in Embodiment 1 will be denoted by the same reference numerals as in Embodiment 1, and the description thereof will be omitted.

[0042] FIG. 5 shows a block diagram of a circuit system 2 including a power supply circuit 40 according to Embodiment 2. As shown in FIG. 5, the circuit system 2 according to Embodiment 2 is obtained by replacing the power supply circuit 10 of the circuit system 1 with a power supply circuit 30. The power supply circuit 30 is obtained by adding an AND circuit 31 to the power supply circuit 10 and replacing the enable control circuit 12 with an enable control circuit 32. Further, in the circuit system 2 according to Embodiment 2, an operation switching circuit that generates an operation start signal OP_EN for switching between an operation state and a stop state of the power supply circuit 30 is provided as a peripheral circuit (not shown in FIG. 5) of the power supply circuit 30. The AND circuit 31 blocks the clock signal CLK transmitted to the charge pump circuit 11 during the period when the operation start signal OP_EN is in the disabled state (for example, low level), and transmits the clock signal CLK to the charge pump circuit 11 during the period when the operation start signal OP_EN is in the enabled state (for example, high level).

[0043] The enable control circuit 32 controls the enable signal so as to keep the switch circuit SW in the off state and the load circuit in the non-operating state for a preset fixed period after an operation start signal OP_EN given from another circuit instructs the charge pump circuit 11 to start operation (for example, sets the operation start signal OP_EN to the enabled state). Further, after the elapse of the fixed period, the enable control circuit 32 exclusively enables the switch circuit SW and the load circuit LD1 in the same manner as the enable control circuit 12.

[0044] In the example shown in FIG. 5, the enable control circuit 32 includes an inverter circuit 13, a timer circuit 33, and AND circuits 34 and 35. When the operation start signal OP_EN changes from the disabled state to the enabled state, the timer circuit 33 maintains the output signal at the low level for a certain period in advance and then switches it to the high level. During the period when the output signal of the timer circuit 33 outputs the low level, both AND circuits 34 and 35 maintain the enable signal transmitted to the load circuit LD1 and the switch circuit SW at the low level. On the other hand, during the period when the output signal of the timer circuit 33 is at the high level, the AND circuit 34 directly transmits the logic level of the enable signal EN to the load circuit LD1. Also, during the period when the output signal of the timer circuit 33 is at the high level, the AND circuit 35 directly transmits the logic level of the signal obtained by inverting the enable signal EN by the inverter circuit 13 to the switch circuit SW.

[0045] Here, in the power supply circuit 30, after the charge pump circuit 11 starts operating by the timer circuit 33, the switch circuit SW is kept in the off state and the load circuit LD1 is kept in the non-operating state for a certain period. This certain period can be set to the time from when the charge pump circuit 11 starts operating until the charge pump output voltage Vcp reaches the operating lower limit voltage VD. By setting such a certain time, the output limiting resistor RDL and the load circuit LD1 are invalidated during the period from when the charge pump circuit 11 starts operating until the charge pump output voltage Vcp reaches the operating lower limit voltage VD. As a result, since there is no current consumption by the output limiting resistor RDL until the charge pump output voltage Vcp reaches the operating lower limit voltage VD after the charge pump circuit 11 starts operating, it becomes possible to shorten the time until the charge pump output voltage Vcp reaches the operating lower limit voltage VD. Also, by performing such an operation, the time until the load circuit LD1 starts up can be shortened.

[0046] Embodiment 3 In Embodiment 3, a power supply circuit 40, which is a modification of the power supply circuit 10 in Embodiment 1, will be described. Note that, for the components that are the same as those described in Embodiment 1 in the description of Embodiment 1, the same reference numerals as those in Embodiment 1 are given and the description thereof is omitted.

[0047] FIG. 6 is a block diagram of a circuit system 3 including the power supply circuit 40 according to Embodiment 3. The circuit system 3 according to Embodiment 3 is obtained by replacing the power supply circuit 10 in Embodiment 1 with the power supply circuit 40. The power supply circuit 40 is obtained by replacing the enable control circuit 12 of the power supply circuit 10 in Embodiment 1 with an enable control circuit 42. The enable control circuit 42 controls the enable signal so as to keep the switch circuit SW in an off state until the charge pump output voltage Vcp of the charge pump circuit 11 reaches a preliminary threshold voltage Vth that is lower than the lower operating limit voltage at which the load circuit LD1 can operate.

[0048] The enable control circuit 42 includes an inverter circuit 13, a comparator COMP, and a logical product circuit 43. The comparator COMP has the charge pump output voltage Vcp input to the positive input terminal and the preliminary threshold voltage Vth input to the negative input terminal. When the charge pump output voltage Vcp exceeds the preliminary threshold voltage Vth, the output signal is switched from the low level to the high level. Also, the enable control circuit 42 directly transmits the enable signal EN to the load circuit LD1 and transmits the enable signal EN inverted by the inverter circuit 13 to the switch circuit SW. At this time, while the comparator COMP is at the low level, the enable control circuit 42 maintains the enable signal EN transmitted to the switch circuit SW at the low level by the logical product circuit 43. On the other hand, while the comparator COMP is at the low level, the enable control circuit 42 transmits the inverted logical enable signal EN output by the inverter circuit 13 to the switch circuit SW by the logical product circuit 43.

[0049] From the above description, the power supply circuit 40 according to the third embodiment turns off the switch circuit SW until the charge pump output voltage Vcp reaches the lower threshold voltage Vth set to a voltage lower than the operation lower limit voltage VD, thereby stopping the current extraction from the output capacitor Co by the output limiting resistor RDL. As a result, in the power supply circuit 40 according to the third embodiment, it becomes possible to shorten the time until the charge pump output voltage Vcp reaches the lower threshold voltage Vth.

[0050] Embodiment 4 In Embodiment 4, a circuit system 4 which is a modification of the circuit system 1 of Embodiment 1 will be described. In the description of Embodiment 4, the same components as those described in Embodiment 1 will be denoted by the same reference numerals as in Embodiment 1 and the description thereof will be omitted.

[0051] FIG. 7 is a block diagram of the circuit system 4 according to Embodiment 4. As shown in FIG. 7, in the circuit system 4 according to Embodiment 4, the load circuit LD1 of Embodiment 1 is replaced with a load circuit LD2. The load circuit LD2 is a control circuit of a low dropout voltage regulator circuit. In the low dropout voltage regulator circuit shown in FIG. 7, an NMOS transistor is used as the output transistor Trp. The output transistor Trp has a power supply (for example, the input voltage VIN) supplied from a power supply circuit other than the charge pump circuit 11 to the drain, and resistors R1 and R2 are connected in series between the source and the ground terminal. The source of the output transistor Trp serves as the output terminal of the low dropout voltage regulator circuit and outputs the output voltage Vo.

[0052] Also, in a low dropout voltage regulator circuit, a control circuit that controls the output transistor Trp receives power supply from a charge pump circuit. This control circuit is the load circuit LD2. The load circuit LD2 has an operational amplifier OP. The operational amplifier OP controls the gate voltage of the power transistor Trp such that the feedback voltage obtained by dividing the output voltage Vo by the reference voltage Vref and the resistors R1 and R2 matches the reference voltage Vref. Also, the operational amplifier OP is switched between an operating state and a non-operating state by an enable signal EN output from the enable control circuit 12.

[0053] In such a low dropout voltage regulator circuit, the voltage of the output voltage Vo can be increased by making the maximum voltage of the gate voltage of the output transistor Trp as high as possible. Therefore, by using the power supply circuit 10, it becomes possible to apply the highest possible load terminal voltage within the range of the maximum rated voltage VE or less to the operational amplifier OP. That is, the power supply circuit 10 according to Embodiment 1 is most effective when power supply is provided to the control circuit of the low dropout voltage regulator circuit as in the circuit system 4 according to Embodiment 4.

[0054] Note that the present invention is not limited to the above-described embodiments, and can be appropriately modified without departing from the gist thereof.

Explanation of Reference Numerals

[0055] 1 Circuit system 2 Circuit system 3 Circuit system 4 Circuit system 10, 30, 40 Power supply circuit 11 Charge pump circuit 12, 32, 42 Enable control circuit 13 Inverting circuit 21, 23, 25 Diode 22, 24 Inverter circuit 31, 34, 35, 43 AND circuit 33 Timer circuit COMP Comparator C1, C2 Boost Capacitors Co Output Capacitor LD1, LD2 Load Circuits OP Operational Amplifier Vref Reference Voltage Trp Power Transistor Vcp Charge Pump Output Voltage RDL Output Limiting Resistor Vcp_max Charge Pump Maximum Output Voltage VE Maximum Rated Voltage Vm Margin Voltage Width VD Operating Lower Limit Voltage SW Switching Circuit

Claims

1. A charge pump circuit having a power supply capability capable of outputting, when unloaded, a maximum output voltage that is equal to or higher than the load terminal allowable voltage calculated by subtracting a margin voltage preset in the load circuit from the maximum rated voltage of the load circuit; An output suppression circuit connected in parallel with the output capacitance of the charge pump circuit, in which an output limiting resistor and a switch circuit are connected in series; An enable control circuit that outputs an enable signal for instructing switching between an operating state and a non-operating state of the load circuit, and The resistance value of the output limiting resistor is set to a value equal to or lower than a value at which the output voltage of the charge pump circuit becomes equal to or lower than the load terminal allowable voltage in a steady state in which the current supply capability of the charge pump circuit and the current consumption in the output limiting resistor are equal; The enable control circuit is a power supply circuit that controls the switch circuit to be in a conducting state during a period in which the load circuit is controlled to be in a non-operating state by the enable signal.

2. The power supply circuit according to claim 1, wherein the resistance value of the output limiting resistor is set to a value at which the output voltage of the charge pump circuit becomes equal to or higher than an operating lower limit voltage set as a lower limit value of a voltage at which the load circuit can operate in a steady state in which the current supply capability of the charge pump circuit and the amount of current consumption in the load circuit are equal.

3. The power supply circuit according to claim 1, wherein the enable control circuit controls the enable signal so that the switch circuit is in an open state and the load circuit is maintained in a non-operating state for a preset fixed period after an operation start signal given from another circuit instructs the charge pump circuit to start operating.

4. The power supply circuit according to claim 1, wherein the load circuit is a low dropout voltage regulator circuit in which a power supply is supplied to an output transistor from a power supply circuit other than the charge pump circuit, and a control circuit that controls the output transistor receives power supply from the charge pump circuit.

5. The power supply circuit according to claim 1, wherein the enable control circuit controls the enable signal so that the switch circuit is maintained in an open state until the output voltage of the charge pump circuit reaches a preliminary threshold voltage lower than an operating lower limit voltage set as a lower limit value of a voltage at which the load circuit can operate.

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