Pixel circuit board, spatial light modulator, and display system

Abstract

To provide a pixel circuit board, a spatial light modulator, and a display system with which the withstand voltage of a drive switch is secured, and a scanning line or data line connected to the drive switch is made to be allocatable.SOLUTION: The pixel circuit board comprises: a plurality of active layer regions extending across a pixel electrode adjacent at a position overlapping with the pixel surface of the pixel electrode; a plurality of drive switches each of which has a scanning terminal, a data terminal and a control terminal; a plurality of control lines connected between each control terminal and one of the plurality of pixel electrodes; a scanning line connected to the scanning terminal; and a data line connected to the data terminal. The scanning line extends between the plurality of drive switches and the plurality of pixel electrodes bypassing the plurality of control lines. The spatial light modulator includes the pixel circuit board, and a display system includes the spatial light modulator.SELECTED DRAWING: Figure 4I

Description

Technical Field

[0001] The present disclosure relates to a pixel circuit board for a spatial light modulator, a spatial light modulator including the pixel circuit, and a display system including the spatial light modulator.

Background Art

[0002] In recent years, in order to realize a high-definition display, a pixel electrode having a fine pixel surface has been required. However, as the pixel surface of the pixel electrode is made finer, if the channel length of the drive switch of the pixel circuit is shortened, the breakdown voltage resistance is known to decrease. In Patent Document 1, a circuit configuration in which two pixel circuits having an aspect ratio of 4:1 straddle two pixel electrodes is disclosed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the circuit configuration of Patent Document 1, even if the pixel surface of the pixel electrode is made finer, it is possible to ensure the breakdown voltage resistance of the drive switch. However, since the width of the pixel circuit in the short side direction is shorter than the width of the pixel electrode in the short side direction, there is a problem that it is difficult to wire the scanning line or the data line connected to the drive switch.

[0005] An object of the present disclosure is to provide a pixel circuit board, a spatial light modulator, and a display system that ensure the breakdown voltage resistance of a drive switch and enable the arrangement of a scanning line or a data line connected to the drive switch.

Means for Solving the Problems

[0006] The pixel circuit board of the present disclosure is for a spatial light modulator, and includes a plurality of pixel electrodes each having a pixel plane that are arranged at intervals from each other and define pixels of the spatial light modulator, and a plurality of active layer regions that extend across the adjacent pixel electrodes at positions overlapping the pixel plane and are arranged at intervals from each other in a direction intersecting the arrangement direction of the plurality of pixel electrodes, a plurality of driving switches each formed in each of the plurality of active layer regions and having a scanning terminal, a data terminal, and a control terminal, a plurality of control lines connected between each of the control terminals and one of the plurality of pixel electrodes, a scanning line disposed between the plurality of driving switches and the plurality of pixel electrodes and connected to the scanning terminal, and a data line disposed between the plurality of driving switches and the plurality of pixel electrodes and connected to the data terminal, wherein the scanning line extends between the plurality of driving switches and the plurality of pixel electrodes while bypassing the plurality of control lines.

[0007] Further, the spatial light modulator of the present disclosure includes the above-described pixel circuit board, a transparent electrode that forms a driving circuit together with the plurality of pixel electrodes, and a light modulation layer disposed between the plurality of pixel electrodes and the transparent electrode and to which a voltage is applied from the driving circuit.

[0008] Further, the display system of the present disclosure includes the above-described spatial light modulator.

Advantages of the Invention

[0009] According to the present disclosure, it is possible to provide a pixel circuit board, a spatial light modulator, and a display system that ensure the withstand voltage of the driving switch and enable the arrangement of a scanning line or a data line connected to the driving switch.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2A

Figure 2B

Figure 3

Figure 4A

Figure 4B

Figure 4C

Figure 4D

Figure 4E

Figure 4F

Figure 4G

Figure 4H

Figure 4I

Figure 5

Figure 6A

Figure 6B

Figure 6C

Figure 6D

Figure 6E

Figure 7A

Figure 7B

Figure 8A

Figure 8B

Figure 8C

Figure 9A

Figure 9B

Figure 9C

Figure 10

Figure 11

DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments according to the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the same members or parts or members or parts having the same function are denoted by the same reference numerals or the reference numerals are omitted. Further, the following embodiments are examples, and the content of the present disclosure should not be construed in a limited manner by the description of the embodiments.

[0012] First, with reference to FIGS. 1, 2A, and 2B, a display system 1 according to an embodiment will be described. In FIGS. 1, 2A, and 2B, the flow of an optical signal is indicated by a solid-line arrow, the flow of data is indicated by a broken line, and the flow of an electrical signal is indicated by a double-line arrow.

[0013] The display system 1 is configured as a high-definition display. In FIG. 1, as an example of a high-definition display, an example of the configuration of a holographic display for hologram reproduction is shown.

[0014] The display system 1 includes an arithmetic system 2. The arithmetic system 2 acquires an image for hologram reproduction as a three-dimensional (3D) model or the like, and calculates a hologram by a hologram generation algorithm. The arithmetic system 2 is configured as a computer device or a microcomputer.

[0015] The method by which the arithmetic system 2 acquires an image for hologram reproduction is not particularly limited. For example, the image for hologram reproduction by the arithmetic system 2 may be acquired by connecting a wired or wireless connection to an external device (not shown) capable of reproducing an image, such as an imaging device such as a camera or a video device such as a television receiver. Further, the image for hologram reproduction by the arithmetic system 2 may be acquired by reading a removable medium such as a USB memory in which the image is stored.

[0016] Also, the hologram generation algorithm can be selected from any algorithm depending on the purpose or application of hologram reproduction, and without limitation, for example, it may be a wavefront recording method or a random-free phase method.

[0017] The display system 1 includes a control system 3. The control system 3 receives the hologram calculated in the arithmetic system 2 as a video signal and outputs a control signal based on the video signal.

[0018] The control system 3 is configured as a computer device, a microcomputer, dedicated hardware, or a combination thereof. When the control system 3 is configured as a computer device or a microcomputer, the control system 3 may be configured as the same computer device or microcomputer as the arithmetic system 2, or as a separate computer device or microcomputer.

[0019] When the control system 3 is a computer device or a microcomputer, the control system 3 has a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). When the control system 3 has a CPU or an MPU, each function executed by the control system 3 is realized by software, firmware, or a combination of software and firmware. The software or firmware is described as a program in a programming language. The program is stored in an internal memory (not shown) of the control system 3, and the program stored in the internal memory (not shown) is read out and executed by the CPU or the MPU. By the CPU or the MPU reading out and executing the program stored in the internal memory (not shown), each function in the control system 3 is realized. The internal memory (not shown) is a non-volatile or volatile semiconductor memory such as, for example, RAM, ROM, flash memory, EPROM, or EEPROM.

[0020] When the control system 3 is dedicated hardware, the control processing in the control system 3 is realized by, for example, a single circuit, a composite circuit, an ASIC (application specific integrated circuit), an FPGA (field-programmable gate array), or a circuit combining these. Each function realized by the control system 3 may be realized in individual hardware, or all of the functions may be realized in a single hardware.

[0021] Note that when the arithmetic system 2 or the control system 3 is a computer device, the type of the computer device is not particularly limited. The computer device may be, for example, a virtual server that provides cloud services, or a physical server that provides various services to a group within a local network. Also, the computer device may be a quantum computer, a general-purpose desktop or laptop computer, or a portable terminal such as a tablet-type terminal or a smartphone. Further, the arithmetic system 2 or the control system 3 may be designed to perform distributed processing using a plurality of computer devices.

[0022] The display system 1 includes a light source 5, a beam expander 7, a projection optical system 9, and a spatial light modulator 10. The operations of the light source 5 and the spatial light modulator 10 are controlled by control signals received from the control system 3.

[0023] Based on the control signal received from the control system 3, the light source 5 irradiates a light beam toward the spatial light modulator 10. As the light source 5, a coherent light source having a coherence length corresponding to the purpose or application of hologram reproduction is used. As the coherent light source, although not limited, a solid light source including a light-emitting diode is used, and for example, a laser light source including a laser diode or an SLD (Super Luminescent Diode) light source including a superluminescent diode is suitable.

[0024] The beam expander 7 expands the beam of light emitted from the light source 5 and guides it to the entire light modulation region of the spatial light modulator 10. The beam expander 7 is disposed on the optical propagation path between the light source 5 and the spatial light modulator 10. Any optical element is selected for the beam expander 7 according to the purpose or application of hologram reproduction. For example, the beam expander 7 may be, but is not limited to, a Galilean transmissive beam expander including a concave lens and a convex lens, a Keplerian transmissive expander including two convex lenses, or a reflective expander including a curved mirror. Further, in the transmissive beam expander, the concave lens and the convex lens may be diffractive optical elements having similar refractive characteristics. Further, in the reflective expander, the curved mirror may be a diffractive optical element having similar reflective characteristics.

[0025] The spatial light modulator 10 is an optical device that modulates the spatial distribution such as the amplitude, phase, or propagation direction of the light from the light source 5. The spatial light modulator 10 is provided with a light modulation region. The optical characteristics such as reflection or refraction in the light modulation region of the spatial light modulator 10 are electrically controlled by a control signal from the control system 3. The parameters such as the amplitude, phase, or propagation direction of the beam of light irradiated from the light source 5 and expanded by the beam expander 7 are modulated in the light modulation region of the spatial light modulator 10 by the control signal from the control system 3. The detailed configuration of the spatial light modulator 10 will be described later.

[0026] The projection optical system 9 processes the beam of light modulated by the spatial light modulator 10 at the position to be viewed by the user to reproduce a stereoscopic image such as a three-dimensional hologram. The projection optical system is formed by combining, but is not limited to, lenses, mirrors, and diffractive optical elements having optical characteristics equivalent to those of the lenses and mirrors.

[0027] Although not shown, when the spatial light modulator 10 modulates the amplitude of the incident light, the display system 1 includes a polarization separation element that separates the light beam into two light beams in the light propagation path between the spatial light modulator 10 and a viewer such as a viewer of a stereoscopic video. The polarization separation element is an optical element that adjusts the ratio of vertically polarized light and horizontally polarized light by a polarization plane separation operation. Here, it has a function of controlling the light intensity according to the polarization state of the input light. As the polarization separation element, but not limited to, for example, a polarizing plate or a polarizing beam splitter (PBS) may be used. The polarization separation element may be further arranged in the light propagation path between the light source 5 and the spatial light modulator 10 according to the polarization characteristics of the light source 5. When the spatial light modulator 10 does not modulate the amplitude of the incident light, the polarization separation element can be omitted.

[0028] When the light source 5 is a coherent light source, it is preferable that the display system 1 includes a speckle noise suppression module 5a. Speckle noise can occur in highly coherent light, such as a light beam irradiated from a coherent light source, and is noise generated by multiple waves overlapping and interfering with each other in a complex manner.

[0029] The speckle noise suppression module 5a is formed, for example, but not limited to, as a high-frequency superposition circuit that gives frequency modulation to the power supply of the light source 5, for example, the drive current. The speckle noise suppression module 5a is electrically controlled by a control signal from the control system 3. The speckle noise suppression module 5a can preferably reduce the coherence of the light beam irradiated from the light source 5 by giving frequency modulation to the power supply of the light source 5, so that speckle noise can be reduced.

[0030] The speckle noise suppression module 5a may be separate from the light source 5 or may be built into the light source 5.

[0031] Further, when the light source 5 is a coherent light source, it is preferable that the display system 1 includes a speckle noise suppression mechanism 5b on the light output side of the light source 5. The speckle noise suppression mechanism 5b has, for example, but not limited to, a rotatable diffuser plate, and is configured such that the rotation of the diffuser plate is electrically controlled by a control signal from the control system 3. Since the speckle noise suppression mechanism 5b can suitably reduce the coherence of the light beam emitted from the light source 5 by the rotation of the diffuser plate, speckle noise can be reduced.

[0032] Note that the speckle noise suppression mechanism 5b may be separate from the light source 5 or may be incorporated in the light source 5.

[0033] Also, the speckle noise suppression module 5a and the speckle noise suppression mechanism 5b can be omitted when, for example, a coherent light source is not used or when there is no need to consider speckle noise.

[0034] Further, it is preferable that the display system 1 includes an optical isolator 5c on the output side of the light source 5. The optical isolator 5c suppresses the light beam emitted from the light source 5 from returning to the light source 5 by reflection. By providing the optical isolator 5c on the output side of the light source 5, fluctuations in the output of the light source 5 can be suppressed, so that the stability of the light source 5 or the entire display system 1 can be improved. Also, by providing the optical isolator 5c on the output side of the light source 5, optical damage to the light source 5 can be prevented.

[0035] Note that the optical isolator 5c may be separate from the light source 5 or may be incorporated in the light source 5. Also, when the optical isolator 5c is provided on the output side of the light source 5, it is preferable not to arrange optical components between the light source 5 and the optical isolator 5c in order to prevent reflection between the light source 5 and the optical isolator 5c. Also, the optical isolator 5c can be omitted when, for example, there is no need to consider reflection of the light beam emitted from the light source 5.

[0036] Further, the display system 1 preferably includes a beam shaping element 5d on the output side of the light source 5 according to the quality of the light beam emitted from the light source 5, for example, the parallelism or the in-plane uniformity of the intensity. The beam shaping element 5d can be, for example, a spatial filter having a lens and a pinhole, but is not limited thereto. By providing the beam shaping element 5d on the output side of the light source 5, it is possible to shape a light beam with reduced parallelism due to interference with optical components, so that a light beam with high parallelism can be incident on the spatial light modulator 10.

[0037] Therefore, the beam shaping element 5d is preferably arranged on the upstream side of the beam expander 7 in the light propagation path between the light source 5 and the spatial light modulator 10. Further, it is preferable not to arrange an optical component between the beam expander 7 and the beam shaping element 5d. With the above-described arrangement, a light beam with high parallelism shaped by the beam shaping element 5d can be expanded by the beam expander 7, and the expanded light beam with high parallelism can be incident on the light modulation region of the spatial light modulator 10.

[0038] Note that the beam shaping element 5d may be replaced with an optical device having the same function as the spatial light modulator 10. In this case, the optical device having the same function as the spatial light modulator 10 can electrically control the quality of the light beam according to a control signal from the control system 3.

[0039] Further, for example, when there is no decrease in the quality of the light beam emitted from the light source 5, such as a decrease in parallelism, the beam shaping element 5d can be omitted.

[0040] In FIGS. 2A and 2B, an arrangement example of the spatial light modulator 10 for realizing full-color hologram reproduction in the display system 1 is shown. Note that the arrangement examples in FIGS. 2A and 2B are merely examples, and the arrangement example of the spatial light modulator 10 is not limited to either FIG. 2A or FIG. 2B. The arrangement of the spatial light modulator 10 for realizing full-color hologram reproduction can be arbitrarily selected according to the purpose or application of the hologram reproduction.

[0041] In the display system 1 in FIGS. 2A and 2B, a multiplexing system 8 is provided. The multiplexing system 8 multiplexes a plurality of light beams having different wavelengths into a single light beam. The multiplexing system 8 is formed, for example, as a filter type, prism type, grating type, or waveguide type optical multiplexer, without limitation. It is preferable to form the multiplexing system 8 as a waveguide type optical multiplexer.

[0042] FIG. 2A is an example in which a spatial light modulator 10 is arranged for each of a red light source 5-1, a green light source 5-2, and a blue light source 5-3 arranged as the light source 5 of the display system 1. In the arrangement example of FIG. 2A, a red light beam, a green light beam, and a blue light beam modulated by each spatial light modulator 10 are multiplexed by the multiplexing system 8 and propagated to the projection optical system 9 as a single light beam.

[0043] On the other hand, FIG. 2B is an example in which a single spatial light modulator 10 is arranged for the red light source 5-1, the green light source 5-2, and the blue light source 5-3. In the arrangement example of FIG. 2B, a red light beam, a green light beam, and a blue light beam irradiated from the red light source 5-1, the green light source 5-2, and the blue light source 5-3 respectively are multiplexed by the multiplexing system 8, and the multiplexed single light beam is incident on the spatial light modulator 10. Thereafter, the single light beam modulated by the spatial light modulator 10 is propagated to the projection optical system 9.

[0044] In the arrangement example of FIG. 2A, since the red light beam, the green light beam, and the blue light beam can be modulated simultaneously in separate spatial light modulators 10, the video can be updated at a high frequency. Therefore, in the arrangement example of FIG. 2A, the video characteristics in hologram reproduction can be improved.

[0045] On the other hand, in the arrangement example of FIG. 2A, since the spatial light modulator 10 is arranged for each of the red light source 5-1, the green light source 5-2, and the blue light source 5-3, the number of optical components of the display system 1 increases as compared with the arrangement example of FIG. 2B. Further, since the modulated light beams are to be propagated from each spatial light modulator 10 to the multiplexing system 8, it may be difficult to adjust the position of the spatial light modulator 10. Therefore, in the case of the arrangement example of FIG. 2A, the configuration of the display system 1 may become complicated.

[0046] In the arrangement example of FIG. 2B, since a single light beam multiplexed in a single spatial light modulator 10 is modulated, the configuration of the display system 1 can be simplified.

[0047] On the other hand, in the arrangement example of FIG. 2B, full-color hologram reproduction is realized by sequentially turning on and off each of the red light source 5-1, the green light source 5-2, and the blue light source 5-3. Therefore, in order to improve the video characteristics in hologram reproduction, it is necessary to drive each color light source 5 at a high frequency. Thus, as compared with the arrangement example of FIG. 2A, the power consumption in the display system 1 may increase.

[0048] Note that when realizing full-color hologram reproduction in the display system 1, since the hologram changes according to the wavelength of light, the light source 5 and the spatial light modulator 10 need to be synchronized with each other. The synchronization between the light source 5 and the spatial light modulator 10 may be executed in the control system 3 or may be executed in a control mechanism such as another electronic circuit for the purpose of such synchronization.

[0049] In addition, when realizing hologram reproduction in the display system 1, the gradation of the light intensity on the reproduced stereoscopic image may be adjusted by the hologram, or a combination of the modulation of the intensity of the light source 5 and the adjustment by the hologram may be used. Further, as a method for adjusting the gradation of the light intensity in the reproduction of the stereoscopic image, a time-division gradation display method is known in which a plurality of lighting times within one frame are set, and a predetermined luminance gradation is expressed by combining desired lighting times among the plurality of lighting times and lighting. When realizing full-color hologram reproduction, the gradation of the light intensity on the reproduced stereoscopic image may be a combination of the time-division gradation display method and the adjustment by the hologram.

[0050] In addition, when realizing hologram reproduction in the display system 1, depending on the purpose or use of the hologram reproduction, the number of light sources 5 in the display system can be any number.

[0051] As described above, the display system 1 for realizing hologram reproduction has been described. However, the display system 1 may be other than for hologram reproduction use. For example, by reducing the coherence of the light beam in the entire display system 1 compared to the display system 1 for hologram reproduction use, the display system 1 can be a high-definition display system that projects the display content of the spatial light modulator 10 onto the projection optical system 9.

[0052] Next, the spatial light modulator 10 according to the embodiment will be described with reference to FIG. 3.

[0053] The spatial light modulator 10 is an optical device that modulates the spatial distribution of the amplitude, phase, propagation direction, intensity, polarization plane, etc. of light.

[0054] The spatial light modulator 10 includes a cover glass 20. The cover glass 20 forms the design surface of the spatial light modulator 10 and defines the light input surface of the light modulation region of the spatial light modulator 10. The material of the cover glass is preferably for display use, and without limitation, for example, it can be sapphire glass, quartz glass, or non-alkali glass.

[0055] Note that, on the design surface side of the cover glass 20, an antireflection film may be provided according to the purpose or application of the spatial light modulator 10. By providing the antireflection film on the cover glass 20, the reflection of light incident on the surface of the cover glass 20 is suppressed, so that the modulation efficiency in the spatial light modulator 10 can be improved.

[0056] Note that, as the material of the antireflection film, although not limited, for example, SiO2, MgF2, TiO2, Ta2O5, ZrO2, or Nb2O5 is used. Further, the antireflection film may be formed in multiple layers on the design surface of the cover glass 20 by performing an organic resist coating with an organic acid such as alkylsulfonic acid on the design surface of the cover glass 20 and then depositing magnesium fluoride or the like.

[0057] The spatial light modulator 10 includes a light modulation layer 30. The light modulation layer 30 is formed of a liquid crystal, which is a dielectric material having both properties of fluidity similar to that of a liquid and anisotropy similar to that of a crystal. By forming the light modulation layer 30 of a liquid crystal, the anisotropy of the liquid crystal molecules 30a can be changed according to the magnitude of the applied voltage or the like, so that the optical properties such as reflection or refraction in the light modulation layer 30 can be modulated.

[0058] For the light modulation layer 30, any liquid crystal material can be used according to the purpose or application of the spatial light modulator 10. The light modulation layer 30 is, although not limited, for example, a ferroelectric liquid crystal or a nematic liquid crystal. As the light modulation layer 30, it is preferable to use a ferroelectric liquid crystal. The ferroelectric liquid crystal has a spontaneous polarization of the liquid crystal molecules 30a, and can prevent interference between adjacent pixels in the spatial light modulator 10 due to an electric field as compared with a nematic liquid crystal.

[0059] The spatial light modulator 10 includes an alignment film 40. The alignment film 40 is disposed in contact with both surfaces of the light modulation layer 30, that is, the surface of the light modulation layer 30 on the cover glass 20 side and the surface on the opposite side thereof. The alignment film 40 is formed of an insulator and is formed of, for example, an organic material such as polyimide or an inorganic material such as SiO2 (silica), although not limited thereto.

[0060] The film surface of the alignment film 40 can adjust the alignment state of the liquid crystal molecules in the light modulation layer 30 by an operation such as rubbing. Note that the alignment direction of the liquid crystal molecules 30a provided by the alignment film 40 disposed on one surface of the light modulation layer 30 may be parallel to the alignment direction of the liquid crystal molecules 30a provided by the alignment film 40 disposed on the opposite surface thereof, or may be in a twisted position.

[0061] The spatial light modulator 10 includes a transparent electrode 50 and a pixel circuit board 100.

[0062] The transparent electrode 50 is disposed between the cover glass 20 and the alignment film 40 disposed on the cover glass side surface of the light modulation layer 30. The transparent electrode 50, together with the pixel circuit 150 of the pixel circuit board 100, forms a drive circuit 200 in the spatial light modulator 10.

[0063] The transparent electrode 50 is formed as a conductive film capable of propagating light. The transparent electrode 50 is formed of, for example, indium tin oxide (ITO: Indium Tin Oxide) such as refractive index matching type ITO (IMITO: Index - Matching ITO), tin oxide, magnesium silver alloy, or a polythiophene - based conductive polymer using PEDOT (polyethylenedioxythiophene), although not limited thereto.

[0064] The pixel circuit board 100 has a substrate 60 and a pixel circuit 150 formed on the substrate 60. The pixel circuit 150 has a drive switch circuit 70, a plurality of pixel electrodes 90, and a plurality of control lines 80 connecting each of the drive switch circuit 70 and the plurality of pixel electrodes 90.

[0065] In the pixel circuit substrate 100, a plurality of pixel electrodes 90 are arranged to face a transparent electrode 50 via an optical modulation layer 30 and alignment films 40 disposed on both sides thereof. That is, in the spatial light modulator 10, the optical modulation layer 30 is disposed between the plurality of pixel electrodes 90 and the transparent electrode 50.

[0066] In the spatial light modulator 10, by disposing the optical modulation layer 30 between the plurality of pixel electrodes 90 and the transparent electrode 50, a voltage is applied from the drive circuit 200 to the optical modulation layer 30, and the optical characteristics of the optical modulation layer 30 can be modulated by electrical control based on the voltage. For example, but not limited to, when the optical modulation layer 30 is formed of a ferroelectric liquid crystal, during the operation of the spatial light modulator 10, an operating voltage (e.g., V DD ) is applied to the drive switch circuit 70. Half of the voltage (V DD / 2) is constantly applied to the transparent electrode 50. On the other hand, to the pixel electrode 90, either a voltage identical to the operating voltage (V DD ) or a reference voltage (GND) is applied by switching of the drive switch circuit 70, whereby the optical characteristics of the optical modulation layer 30 are modulated.

[0067] Note that the spatial light modulator 10 may modulate only a part of the spatial distribution such as the amplitude, phase, propagation direction, intensity, and polarization plane of light. For example, the spatial light modulator 10 may be a spatial light phase modulator that modulates only the phase of light.

[0068] Also, the light output format of the spatial light modulator 10 can be arbitrarily selected according to the purpose or application of the spatial light modulator 10, and it may be a transmissive type or a reflective type.

[0069] In addition, when the light output format of the spatial light modulator 10 is reflective, a reflection enhancement film formed of aluminum or the like may be disposed between the alignment film 40 disposed on the surface opposite to the cover glass 20 side of the light modulation layer 30 and the pixel electrode 90. By providing the reflection enhancement film, the modulation efficiency of the spatial light modulator 10 can be improved. Further, the reflection enhancement film may be subjected to a passivation treatment such as oxide film formation. By performing the passivation treatment on the reflection enhancement film, corrosion of the reflection enhancement film can be prevented.

[0070] Further, the spatial light modulator 10 of the present disclosure may be used for applications other than hologram reproduction. For example, the spatial light modulator 10 can be used for, but not limited to, a three-dimensional printer or a laser processing beam.

[0071] Next, the pixel circuit board 100 according to the embodiment will be described with reference to FIGS. 4A to 4I. The pixel circuit board 100 can be manufactured by using, for example, a three-dimensional printer or the like in at least some steps.

[0072] Note that FIGS. 4A to 4I are described by appropriately adding each component in the order from FIG. 4A to FIG. 4I for the purpose of facilitating understanding of the configuration of the pixel circuit board 100, but FIGS. 4A to 4I do not disclose the manufacturing order of the pixel circuit board 100. Further, although the gap between the components of the pixel circuit board 100 is filled with an insulating material 79 (see FIGS. 6A to 6E), the illustration of the insulating material 79 is omitted in FIGS. 4A to 4I for the purpose of clarifying the internal structure. In the drawings showing the pixel circuit board 100 including FIGS. 4A to 4I, there are some places where boundary lines are shown even within the same member, but it is not intended that there must be a boundary. In the following drawings, for convenience of explanation, the XYZ axes are described, and the pixel circuit board 100 exists at a position where all of XYZ are positive (the first quadrant in the XY plane), but the actual arrangement of the pixel circuit board 100 in the spatial light modulator 10 is not limited in any way.

[0073] As shown in FIG. 4A, the substrate 60 has a plurality of active layer regions 65 extending in one direction. The plurality of active layer regions 65 are arranged at intervals in a direction intersecting the extending direction of the active layer regions 65. At the ends of the active layer regions 65 in the direction in which the active layer regions 65 extend, doping regions 65-1 doped with impurities such as boron or phosphorus are formed according to the purpose or application of the pixel circuit board 100.

[0074] The active layer region 65 is preferably formed as a single crystal material. By using a single crystal material for the active layer region 65, an active layer region 65 with a higher purity and a regular atomic arrangement can be formed compared to a polycrystalline material. Therefore, the electrical resistance value can be reduced, and the error in electrical characteristics including the electrical resistance value of each active layer region 65 can be reduced. In addition, by using a single crystal material for the active layer region 65, an active layer region 65 with a regular atomic arrangement can be formed compared to a polycrystalline material. Therefore, the mobility of electrons or holes in the active layer region 65 can be improved.

[0075] Furthermore, the active layer region 65 is more preferably formed of a single crystal material selected from the group consisting of Si, SiC, GaN, and Ga2O3. By forming the active layer region 65 with the above-mentioned single crystal material, the power conversion efficiency in the pixel circuit 150 can be improved, and the breakdown voltage resistance can be improved.

[0076] On the outer peripheral side of each active layer region 65, a trench insulating portion 65a is formed. The material of the trench insulating portion 65a can be any material selected according to the purpose or application of the pixel circuit board 100. Without limitation, for example, an insulator such as SiO2 is used. The trench insulating portion 65a is formed, for example, by a shallow trench isolation (STI) method. Note that the trench insulating portion 65a may be formed by another method according to the purpose or application of the pixel circuit board 100, but it is preferable to adopt a method capable of coping with the miniaturization of the active layer region 65. Further, if the adjacent active layer regions 65 can be electrically insulated, another insulating structure other than the trench type may be adopted for the trench insulating portion 65a.

[0077] In FIG. 4A, a plurality of active layer regions 65 are arranged at intervals in the direction (positive direction of the Y axis) orthogonal to the direction in which the active layer region 65 extends (positive direction of the X axis), but it is not limited thereto. For example, the plurality of active layer regions 65 may be arranged obliquely such that the line connecting the centers of the respective active layer regions 65 forms an angle with the positive direction of the Y axis.

[0078] Also, in FIG. 4A, the shape of the active layer region 65 is a rectangular shape with a large aspect ratio, but any shape according to the purpose or application of the pixel circuit board 100 can be selected. For example, the shape of the active layer region 65 may be an oval shape.

[0079] As shown in FIGS. 4B to 4D, the pixel circuit board 100 includes an insulating film 71. The insulating film 71 is disposed at the central portion of each active layer region 65 and extends along the direction (positive direction of the X axis) in which the active layer region 65 extends. As the material of the insulating film 71, any material can be selected according to the purpose or application of the pixel circuit board 100. Without limitation, for example, an insulator such as SiO2 or SiO x N y (silicon oxynitride) or the like is used.

[0080] Further, as shown in FIG. 4D, the pixel circuit board 100 includes a scanning terminal 72. The scanning terminal 72 is disposed so as to sandwich an insulating film 71 between each active layer region 65. The scanning terminal 72 extends in the same direction as the insulating film 71 and covers the insulating film 71. The scanning terminal 72 forms one of the two input terminals of the driving switch circuit 70.

[0081] Also, as shown in FIG. 4B, the pixel circuit board 100 includes a data terminal 73 and a control terminal 81. The data terminal 73 and the control terminal 81 are each disposed in one of the doped regions 65-1 of each active layer region 65. The data terminal 73 forms the other one of the two input terminals of the driving switch circuit 70. The control terminal 81 forms the output terminal of the driving switch circuit 70.

[0082] The materials of the scanning terminal 72, the data terminal 73, and the control terminal 81 can be arbitrarily selected according to the purpose or application of the pixel circuit board 100. Without limitation, for example, conductors such as aluminum or copper are used. In the following description, when the components of the pixel circuit board 100 are formed of a conductor, the material is assumed to be selected in the same manner unless otherwise specified.

[0083] Each active layer region 65, and the insulating film 71, the scanning terminal 72, the data terminal 73, and the control terminal 81 disposed on each active layer region 65 form a plurality of driving switches Tr.

[0084] In the following description, as shown in FIG. 4B, the n-th driving switch Tr n is the driving switch Tr closest to the X-axis in the first quadrant of the XYZ plane. Also, the (n + 1)-th driving switch Tr n+1 is the driving switch Tr closest to the n-th driving switch Tr n . Also, the (n + 2)-th driving switch Tr n+2 is the driving switch Tr closest to the (n + 1)-th driving switch Tr n+1 . Also, the (n + 3)-th driving switch Tr n+3 is the driving switch Tr closest to the (n + 2)-th driving switch Tr n+2Let it be the drive switch Tr closest thereto. Also, the nth drive switch Tr n , the (n + 1)th drive switch Tr n+1 , the (n + 2)th drive switch Tr n+2 , and the (n + 3)th drive switch Tr n+3 When there is no need to particularly distinguish them, they are collectively referred to as the drive switch Tr.

[0085] The drive switch Tr can be formed as an arbitrary electronic component according to the purpose or application of the pixel circuit board 100. For example, it is formed as a transistor. For example, it is preferable to form the drive switch as a field effect transistor (FET) such as a MOSFET. By forming the drive switch as a MOSFET, the drive switch circuit 70 can be formed by a CMOS circuit capable of a high-speed switching operation.

[0086] Note that when the drive switch is formed as a MOSFET, the MOSFET may be an n-type MOSFET or a p-type MOSFET. Also, the MOSFET may be an enhancement type or a depletion type. Further, in FIGS. 4B to 4D, the insulating film 71 is disposed on the upper surface of the active layer region 65 and is formed as a drive switch similar to a planar type MOSFET, but is not limited thereto, and may be formed as a trench type MOSFET in which the insulating film 71 is embedded in the active layer region 65.

[0087] Note that when the drive switch Tr is formed as a transistor, the scanning terminal 72 may be referred to as a "gate terminal" or a "base terminal". Also, the pair of the data terminal 73 and the control terminal 81 may be referred to as a "source terminal" and a "drain terminal", or a "collector terminal" and an "emitter terminal".

[0088] As shown in FIG. 4B, the data terminals 73 of the nth drive switch Tr n and the (n + 1)th drive switch Tr n+1 are arranged in substantially the same column along the direction (positive direction of the Y axis) in which the respective active layer regions 65 are arranged. On the other hand, the (n + 2)th drive switch Trn+2 and the n+3rd drive switch Tr n+3 The data terminals 73 of the are arranged in substantially the same column in a column different from the column of the data terminals 73 of the nth drive switch Tr along the direction in which the respective active layer regions 65 are arranged. Also, the nth drive switch Tr n is arranged in substantially the same column in a column different from the column of the data terminals 73 of the nth drive switch Tr. Further, the control terminals 81 of the nth drive switch Tr n and the n+1st drive switch Tr n+1 are arranged in substantially the same column in a column different from the two columns of the data terminals 73 described above along the direction in which the respective active layer regions 65 are arranged. On the other hand, the control terminals 81 of the n+2nd drive switch Tr n+2 and the n+3rd drive switch Tr n+3 are arranged in substantially the same column in a column different from the two columns of the data terminals 73 described above and in a column different from the column of the control terminals 81 of the nth drive switch Tr n described above along the direction in which the respective active layer regions 65 are arranged.

[0089] Although it will be described later with reference to the drawings after FIG. 8A, the arrangement examples of the data terminals 73 and the control terminals 81 in the description of FIG. 4B are merely a preferred example and are not limited thereto. The data terminals 73 and the control terminals 81 can be arranged in any of the doped regions 65-1 on the respective active layer regions 65 according to the purpose or application of the pixel circuit board 100.

[0090] As shown in FIG. 4C, the pixel circuit board 100 includes the nth data line DL n and the n+1st data line DL n+1 The nth data line DL n is connected to the data terminals 73 of the nth drive switch Tr n and the n+1st drive switch Tr n+1 The n+1st data line DL n+1 is connected to the data terminals 73 of the n+2nd drive switch Tr n+2 and the n+3rd drive switch Tr n+3 The nth data line DL n and the n+1st data line DL n+1extends across each active layer region 65 along the direction (the positive direction of the Y axis) in which each active layer region 65 is arranged. In the following description, when there is no need for particular distinction, the nth data line DL n and the (n + 1)th data line DL n+1 are collectively referred to as the data line 74. The nth data line DL n and the (n + 1)th data line DL n+1 are formed of a conductor.

[0091] Note that in FIG. 4C, the data line 74 is formed as a separate body from the data terminal 73, but they may be integrally formed. The cross section of the data line 74 can be selected to have an arbitrary shape according to the purpose or application of the pixel circuit board 100. Without limitation, for example, it may have a rectangular shape or a circular shape. Also, in a layer different from the data line 74, for the purpose of reducing the electrical resistance and capacitance of the data line 74, there may be an auxiliary conductor line that runs parallel to the data line 74 and is in contact with the data line 74 in part.

[0092] Also, the term "line" of the data line 74 does not limit the thickness or diameter of the data line 74. The thickness or diameter of the data line 74 can be any value according to the purpose or application of the pixel circuit board 100.

[0093] As shown in FIG. 4D, the pixel circuit board 100 includes a scan terminal line 75. The scan terminal line 75 is connected to each scan terminal 72. Each scan terminal line 75 extends in the direction away from the active layer region 65 (the positive direction of the Z axis) starting from the scan terminal 72. The scan terminal line 75 is formed of a conductor.

[0094] The scan terminal lines 75 of the nth driving switch Tr n and the (n + 2)th driving switch Tr n+2 are arranged in substantially the same row along the direction (the positive direction of the Y axis) in which each active layer region 65 is arranged. The scan terminal lines 75 of the (n + 1)th driving switch Tr n+1 and the (n + 3)th driving switch Tr n+3The scanning terminal lines 75 are arranged in substantially the same column in a column different from the column of the data terminals 73 of the n-th driving switch Tr along the direction (the positive direction of the Y-axis) in which each active layer region 65 is arranged. n

[0095] The arrangement example of the scanning terminal lines 75 in the description of FIG. 4D is only a preferred example and is not limited thereto. The scanning terminal lines 75 can be arranged at arbitrary positions according to the purpose or application of the pixel circuit substrate 100. For example, the scanning terminal lines 75 may be provided outside the active layer region 65 by extending the scanning terminals 72.

[0096] In FIG. 4C, the scanning terminal lines 75 are formed separately from the scanning terminals 72, but they may be integrally formed. The cross-section of the scanning terminal lines 75 can be selected to have an arbitrary shape according to the purpose or application of the pixel circuit substrate 100, and without limitation, for example, it may be a rectangular shape or a circular shape.

[0097] Also, the term "line" of the scanning terminal lines 75 does not limit the thickness or diameter of the scanning terminal lines 75. The thickness or diameter of the scanning terminal lines 75 can be set to an arbitrary value according to the purpose or application of the pixel circuit substrate 100.

[0098] As shown in FIG. 4E, the pixel circuit substrate 100 includes an n-th scanning line GL n and an n + 1-th scanning line GL n+1 . The n-th scanning line GL n is connected to the scanning terminal lines 75 of the n-th driving switch Tr n and the n + 2-th driving switch Tr n+2 . The n + 1-th scanning line GL n+1 is connected to the scanning terminal lines 75 of the n + 1-th driving switch Tr n+1 and the n + 3-th driving switch Tr n+3 . In the following description, when there is no particular need for distinction, the n-th scanning line GL n and the n + 1-th scanning line GL n+1 are collectively referred to as the scanning line 76. The scanning line 76 is formed of a conductor.

[0099] The scanning line 76 has a wiring segment 76a that extends across adjacent active layer regions 65 along the direction (positive direction of the Y-axis) in which each active layer region 65 is arranged. The n-th scanning line GL n 's wiring segment 76a is connected to the scanning terminal line 75 of the n-th drive switch Tr n and the (n + 2)-th drive switch Tr n+2 . The wiring segment 76a of the (n + 1)-th scanning line GL n+1 is connected to the scanning terminal line 75 of the (n + 1)-th drive switch Tr n+1 and the (n + 3)-th drive switch Tr n+3 .

[0100] One of the remaining wirings of the n-th scanning line GL n extends along the active layer region 65 of the n-th drive switch Tr n starting from the point where the wiring segment 76a is connected to the scanning terminal line 75 of the n-th drive switch Tr n . Also, one of the remaining wirings of the n-th scanning line GL n extends in the direction of the n-th data line DL n while leaving a gap from the active layer region 65 of the n-th drive switch Tr n and straddling it in the positive direction of the Z-axis n .

[0101] One of the other remaining wirings of the n-th scanning line GL n extends along the active layer region 65 of the (n + 2)-th drive switch Tr n+2 starting from the point where the wiring segment 76a is connected to the scanning terminal line 75 of the (n + 2)-th drive switch Tr n+2 . Also, one of the other remaining wirings of the n-th scanning line GL n extends in the direction of the (n + 1)-th data line DL n+2 while leaving a gap from the active layer region 65 of the (n + 2)-th drive switch Tr n+1 and straddling it in the positive direction of the Z-axis n+1 .

[0102] The (n + 1)-th scanning line GL n+1One of the remaining wirings has a wiring segment 76a starting from the point where it is connected to the scanning terminal line 75 of the (n + 1)-th driving switch Tr n+1 and extends along the active layer region 65 of the (n + 1)-th driving switch Tr n+1 . Also, one of the remaining wirings of the (n + 1)-th scanning line GL n+1 extends in a direction away from the active layer region 65 of the (n + 1)-th driving switch Tr n+1 in the positive direction of the Z-axis, spanning across with a gap from the n-th data line DL n in the direction of the n-th data line DL n .

[0103] The (n + 1)-th scanning line GL n+1 has another one of its remaining wirings starting from the point where the wiring segment 76a is connected to the scanning terminal line 75 of the (n + 3)-th driving switch Tr n+3 and extending along the active layer region 65 of the (n + 3)-th driving switch Tr n+3 . Also, another one of the remaining wirings of the (n + 1)-th scanning line GL n+1 extends in a direction away from the active layer region 65 of the (n + 3)-th driving switch Tr n+3 in the positive direction of the Z-axis, spanning across with a gap from the (n + 1)-th data line DL n+1 in the direction of the (n + 1)-th data line DL n+1 .

[0104] Note that in Fig. 4E, the wiring segment 76a is formed as a separate body from the scanning terminal line 75, but it may also be integrally formed. Also, the cross-section of the scanning line 76 and its wiring segment 76a can be selected to have any shape according to the purpose or application of the pixel circuit board 100. Without limitation, for example, it may be a rectangular shape or a circular shape

[0105] . Also, the term "line" of the scanning line 76 and its wiring segment 76a does not limit the thickness or diameter of the scanning line 76 and its wiring segment 76a. The thickness or diameter of the scanning line 76 and its wiring segment 76a can be any value according to the purpose or application of the pixel circuit board 100

[0106] As shown in FIG. 4F, the pixel circuit board 100 includes the n-th common potential line C n The n-th common potential line C n is arranged away from the scanning line 76 in the direction away from the active layer region 65 (the positive direction of the Z axis). The n-th common potential line C n extends in the arrangement direction (the positive direction of the Y axis) of each active layer region 65 with the central position in the direction in which the active layer region 65 extends (the positive direction of the X axis). The n-th common potential line C n is collectively referred to as the common potential line 77. The common potential line 77 is formed of a conductor.

[0107] Further, the pixel circuit board 100 includes a plurality of branch lines 77a connected to the common potential line 77. The plurality of branch lines 77a are arranged away from the scanning line 76 in the direction away from the active layer region 65 (the positive direction of the Z axis). Two of the plurality of branch lines 77a extend along both sides of the common potential line 77 along the active layer region 65 of the n-th driving switch Tr n Two of the other plurality of branch lines 77a extend along both sides of the common potential line 77 along the active layer region 65 of the (n + 1)-th driving switch Tr n+1 Two of the other plurality of branch lines 77a extend along both sides of the common potential line 77 along the active layer region 65 of the (n + 2)-th driving switch Tr n+2 Two of the other plurality of branch lines 77a extend along both sides of the common potential line 77 along the active layer region 65 of the (n + 3)-th driving switch Tr n+3 The plurality of branch lines 77a are formed of a conductor.

[0108] In FIG. 4F, the common potential line 77 and the plurality of branch lines 77a are formed separately, but they may be integrally formed. Further, the cross section of the common potential line 77 and the plurality of branch lines 77a can be selected to have an arbitrary shape according to the purpose or application of the pixel circuit board 100, and without limitation, for example, it may be a rectangular shape or a circular shape.

[0109] Also, the term "line" for the common potential line 77 and the plurality of branch lines 77a does not limit the thickness or diameter of the common potential line 77 and the plurality of branch lines 77a. The thickness or diameter of the common potential line 77 and the plurality of branch lines 77a can be any value according to the purpose or application of the pixel circuit board 100.

[0110] As shown in FIG. 4G, the pixel circuit board 100 includes control terminal lines 80a. The control terminal lines 80a are each connected to each control terminal 81 and extend from each control terminal 81 in a direction away from each active layer region 65 (the positive direction of the Z-axis).

[0111] Note that the control terminal lines 80a may be formed separately from the control terminals 81 or integrally with the control terminals 81. When the control terminal lines 80a are integrally formed with the control terminals 81, they may be collectively referred to as the control terminal lines 80a. Conversely, they may be referred to as the control terminals 81. The cross-section of the control terminal lines 80a can be selected to have any shape according to the purpose or application of the pixel circuit board 100, and is not limited, but for example, it may be a rectangular shape or a circular shape.

[0112] Also, the term "line" for the control terminal lines 80a does not limit the thickness or diameter of the control terminal lines 80a. The thickness or diameter of the control terminal lines 80a can be any value according to the purpose or application of the pixel circuit board 100.

[0113] As shown in FIGS. 4G and 4H, the pixel circuit board 100 includes an auxiliary capacitance dielectric 78, relay lines 80b, and electrode lines 80c.

[0114] The auxiliary capacitive dielectric 78 is arranged in layers so as to cover a branch line 77a extending in the same direction (the positive direction of the X-axis) in which each active layer region 65 extends and a part of the common potential line 77 in the extending direction of the branch line 77a. The auxiliary capacitive dielectric 78 functions as a buffer capable of maintaining the information of the control output of the pixel circuit board 100 for a certain period. As the material of the auxiliary capacitive dielectric 78, any material can be selected according to the purpose or application of the pixel circuit board 100. Without limitation, for example, dielectrics such as SiO2, alumina, or tantalum oxide are used.

[0115] As shown in FIG. 4H, the relay line 80b and the electrode line 80c form a control line 80 together with the control terminal line 80a. The relay line 80b and the electrode line 80c are formed of a conductor.

[0116] The relay line 80b is connected to the tip of each control terminal line 80a in the extending direction of the control terminal line 80a. The relay line 80b extends from the tip of the control terminal line 80a in the extending direction of the branch line 77a. The relay line 80b is arranged so as to sandwich the auxiliary capacitive dielectric 78 between the common potential line 77 and the branch line 77a in the extending direction of the branch line 77a. By sandwiching the auxiliary capacitive dielectric 78 between the relay line 80b and the common potential line 77 and the branch line 77a, the auxiliary capacitive dielectric 78 is made to function as a capacitor, and the information of the control output of the pixel circuit board 100 can be maintained for a certain period. In FIG. 4H, a single-layer capacitor is configured by sandwiching a single capacitive dielectric between two conductors. However, as will be described later, a multilayer capacitor in which more capacitive dielectrics and conductors are laminated may be configured.

[0117] The electrode line 80c is connected to each relay line 80b and extends in a direction away from the relay line 80b in the direction away from the active layer region 65 (the positive direction of the Z-axis). The electrode line 80c can be arranged at an arbitrary position of the relay line 80b according to the arrangement position of the pixel electrode 90. In FIG. 4H, the electrode line 80c is obliquely arranged with respect to the extending direction of the active layer region 65 such that the line connecting the centers of the electrode lines 80c is away from the extending direction of the active layer region 65 (the positive direction of the X-axis).

[0118] In FIG. 4H, the control terminal line 80a, the relay line 80b, and the electrode line 80c are each formed as separate bodies, but a part or all of them may be integrally formed. Further, the cross-sections of the control terminal line 80a, the relay line 80b, and the electrode line 80c can be selected to have any shape according to the purpose or application of the pixel circuit board 100. Without limitation, for example, they may have a rectangular shape or a circular shape.

[0119] Also, the term "line" for the control terminal line 80a, the relay line 80b, and the electrode line 80c does not limit the thickness or diameter of the control terminal line 80a, the relay line 80b, and the electrode line 80c. The thickness or diameter of the control terminal line 80a, the relay line 80b, and the electrode line 80c can be any value according to the purpose or application of the pixel circuit board 100.

[0120] As shown in FIG. 4I, the pixel circuit board 100 includes a plurality of pixel electrodes 90. Each pixel electrode 90 has a pixel surface 90a that defines a pixel of the spatial light modulator 10. Each pixel electrode 90 is connected to the electrode line 80c on a surface opposite to the pixel surface 90a.

[0121] The material of the pixel electrode 90 can be selected from any conductive material according to the purpose or application of the pixel circuit board 100. Examples of the material of the pixel electrode 90 include, but are not limited to, conductors such as aluminum, copper, indium tin oxide (ITO) such as refractive index matching type ITO (IMITO), tin oxide, magnesium silver alloy, or polythiophene-based conductive polymers using PEDOT (polyethylenedioxythiophene).

[0122] In the pixel circuit board 100, the plurality of pixel electrodes 90 are arranged at intervals along the direction (X-axis direction) in which the active layer region 65 extends. In FIG. 4I, the plurality of pixel electrodes 90 are aligned at intervals in the same direction as the direction (positive direction of the X-axis) in which the active layer region 65 extends, but it is not limited to this. For example, the plurality of pixel electrodes 90 may be arranged obliquely such that the line connecting the centers of the respective pixel electrodes 90 forms an angle with the positive direction of the X-axis. Also, the intervals between the pixel electrodes 90 are preferably constant in that the load of hologram calculation can be reduced, but may be random. When the intervals between the pixel electrodes 90 are random, for example, a hologram can be calculated by machine learning of the correlation between the comparison of the input data to the spatial light modulator 10 and the reproduced three-dimensional image.

[0123] Also, in FIG. 4I, the shape of the pixel electrode 90 is a rectangular shape, but any shape according to the purpose or use of the pixel circuit board 100 can be selected. For example, the shape of the active layer region 65 may be a circle, an ellipse, or a polygon other than a rectangular shape. Also, the shapes of all the pixel electrodes 90 do not necessarily have to be the same, but it is preferable to have the same shape in consideration of the ease of arrangement.

[0124] Note that the shape of the pixel electrode 90 is preferably a rectangular shape. By making the shape of the pixel electrode 90 a rectangular shape, the gap between adjacent pixel electrodes 90 can be reduced, so that the aperture ratio in the light modulation region of the spatial light modulator 10 can be improved.

[0125] Also, the shape of the pixel electrode 90 is more preferably a square. Also, by making the shape of the pixel electrode 90 a square, the gap between adjacent pixel electrodes 90 can be reduced and the number of pixels in the light modulation region of the spatial light modulator 10 can be increased. Therefore, by making the shape of the pixel electrode 90 a square, the aperture ratio in the light modulation region of the spatial light modulator 10 can be improved and the miniaturization of the pixels in the light modulation region of the spatial light modulator 10 can be ensured.

[0126] As shown in FIG. 4I and FIG. 6B described later, the n-th driving switch Tr n is connected to the n-th pixel electrode Pix n via a control line 80. Also, as shown in FIG. 4I and FIG. 6C described later, the (n + 1)-th driving switch Tr n+1 is connected to the (n + 1)-th pixel electrode Pix n+1 via a control line 80. Also, as shown in FIG. 4I and FIG. 6D described later, the (n + 2)-th driving switch Tr n+2 is connected to the (n + 2)-th pixel electrode Pix n+2 via a control line 80. Also, as shown in FIG. 4I and FIG. 6E described later, the (n + 3)-th driving switch Tr n+3 is connected to the (n + 3)-th pixel electrode Pix n+3 via a control line 80. The n-th pixel electrode Pix n , the (n + 1)-th pixel electrode Pix n+1 , the (n + 2)-th pixel electrode Pix n+2 , and the (n + 3)-th pixel electrode Pix n+3 are collectively referred to as pixel electrode 90 when there is no need to particularly distinguish them.

[0127] As shown in FIGS. 4I and 5, each active layer region 65 is arranged at a position overlapping with the pixel plane 90a with a gap from each pixel electrode 90.

[0128] Also, the plurality of active layer regions 65 extend across adjacent pixel electrodes 90 at positions overlapping with the pixel plane 90a of the plurality of pixel electrodes 90. In other words, as shown in FIGS. 4I and 5, in the extending direction of the active layer region 65 (for example, the X-axis direction), the length L of the active layer region 65 is longer than the width P1 of the pixel plane 90a.

[0129] For example, the viewing angle 2θ max at which hologram reproduction is possible, when the wavelength is a variable λ and the pixel pitch is a variable p, is given by the formula: 2θ max = 2sin -1 [λ / 2p] It is represented by this formula. According to this formula, in order to secure the viewing angle 2θ required for hologram reproduction max in order to secure max , it is necessary that both the width P1 and the width P2 of the pixel plane 90a are as fine as the wavelength of light (for example, less than 1 μm).

[0130] On the other hand, in order to make the spatial light modulator 10 respond at high speed, a high voltage (for example, 5 V or more) is required. Therefore, in conjunction with the miniaturization of the pixel plane, if the length L (that is, the channel length) of the active layer region 65 is shortened, the breakdown voltage resistance of the active layer region 65 decreases, which may induce a failure or malfunction of the drive switch Tr.

[0131] However, in the pixel circuit board 100 of the present disclosure, since the width L of the active layer region 65 can be made longer than the width P1 of the pixel plane 90a, it is possible to secure the breakdown voltage resistance of the active layer region 65 while miniaturizing the pixel plane 90a.

[0132] In addition, the plurality of active layer regions 65 are arranged at intervals in a direction (for example, the Y-axis direction) intersecting the arrangement direction (for example, the X-axis direction) of the plurality of pixel electrodes 90 at a position overlapping the pixel plane 90a. Specifically, in the arrangement direction (for example, the Y-axis direction) of the plurality of active layer regions 65, the width W of the active layer region 65 is shorter than the width P2 of the pixel plane 90a.

[0133] If the width W of the active layer region 65 is made shorter than the width P2 of the pixel plane 90a, one pixel plane 90a can be superimposed on the plurality of active layer regions 65, so that the density of the pixel electrodes 90 connected to the plurality of active layer regions 65 can be improved. Therefore, by making the width W of the active layer region 65 shorter than the width P2 of the pixel plane 90a, the aperture ratio in the light modulation region of the spatial light modulator 10 can be improved.

[0134] Note that it is preferable that the length L and the width W of each active layer region 65 are the same, so that the electrical characteristics of the active layer region 65 such as the resistance value can be made substantially the same, but they may have different widths.

[0135] In addition, if the number of active layer regions 65 and pixel electrodes arranged on the pixel circuit board 100 is plural, any quantity according to the purpose or use of the pixel circuit board 100 can be selected.

[0136] In addition, by making the distance L1 between the scanning terminal 72 and the control terminal 81 shown in FIG. 5A the same as the distance L2 between the scanning terminal 72 and the data terminal 73, stable operation becomes possible regardless of the direction of the current of the drive switch Tr.

[0137] In FIGS. 6A to 6E, wirings and the like on the pixel circuit board 100 are described. FIGS. 6A to 6E show the same configuration as FIGS. 4A to 4I except that an insulating material 79 is shown in the gap between components. The material of the insulating material 79 is not limited, but for example, SiO2 is used.

[0138] As shown in the perspective view of FIG. 6A, the scanning line 76 extends between the drive switch Tr and the pixel electrode 90 without intersecting the control line 80. Further, as shown in FIGS. 6B to 6E, all the scanning lines 76 bypass all the control lines 80 and extend between the drive switch Tr and the pixel electrode 90. More specifically, the scanning line 76 bypasses without intersecting the control terminal line 80a of the control line 80 and extends between the drive switch Tr and the relay line 80b.

[0139] According to the above configuration, while ensuring the withstand voltage of the drive switch Tr, a pixel circuit board 100 capable of wiring the scanning line 76 connected to the drive switch Tr can be provided, so that the spatial light modulator 10 having fine pixels can be realized, and suitable hologram reproduction and the like can be realized.

[0140] In addition, the scanning line 76 has a wiring segment 76a that extends across adjacent active layer regions, so that the bypass of the scanning line 76 can be efficiently realized.

[0141] Note that the pixel circuit board 100 of the present disclosure can also be realized by bypassing the data line 74 instead of the scanning line 76.

[0142] In FIG. 7A, a cross-section of the (n + 3)-th driving switch Tr n+3 is shown. As described above, a voltage (V DD / 2) which is half of the operating voltage (V DD ) of the driving switch Tr is constantly applied to the transparent electrode 50, and a voltage identical to the operating voltage (V DD ) or a reference voltage (GND) is applied to the data terminal 73.

[0143] Also, the active layer region 65 is constantly maintained at the reference voltage (GND). Further, a voltage (V DD / 2) which is half of the operating voltage (V DD ) of the driving switch Tr is constantly applied to the common potential line 77 or the branch line 77a.

[0144] A scanning voltage (V n+3 ) is applied to the scanning terminal 72 when driving the (n + 3)-th driving switch Tr G . Therefore, the operating voltage (V DD ) is applied to the data terminal 73, and the operating voltage (V G ) is applied to the scanning terminal 72. Only in this case, the operating voltage (V DD ) is applied to the pixel electrode 90, and the reference voltage (GND) is applied in other cases.

[0145] When the operating voltage (V DD ) is applied to the data terminal 73 and the scanning voltage (V G ) is applied to the scanning terminal 72, information on the control output of the pixel circuit board 100 is maintained in the auxiliary capacitive dielectric 78 for a certain period.

[0146] In FIG. 7B, a modified example of FIG. 7A is shown. In FIG. 7B, a first relay line 80b1 and a second relay line 80b1 are provided. A first auxiliary capacitive dielectric 78-1 is provided between the first relay line 80b1 and the common potential line 77 or the branch line 77a, and a second auxiliary capacitive dielectric 78-2 is provided between the second relay line 80b2 and the common potential line 77 or the branch line 77a. Other structures are the same as those in FIG. 7A.

[0147] According to the above configuration, the holding capacity of the information of the control output of the pixel circuit board 100 can be increased.

[0148] In FIGS. 8A to 8C, the circuit when the pixel circuit board 100 is applied to the light modulation region of the spatial light modulator 10 is shown. As shown in FIGS. 8A and 8B, the circuit region having the (n-1)-th driving switch Tr n-1 to the (n-4)-th driving switch Tr n-4 is a mirror image of the circuit region having the n-th driving switch Tr n to the (n+3)-th driving switch Tr n+3 , that is, the circuit region of the pixel circuit board 100. Therefore, a mirror image of the pixel circuit board 100 with respect to the YZ plane in FIG. 4I is arranged in the circuit region having the (n-1)-th driving switch Tr n-1 to the (n-4)-th driving switch Tr n-4 and will be coupled by the scanning line 76. The pixel circuit board 100 and its mirror image form a unit circuit of the light modulation region of the spatial light modulator 10. In the light modulation region of the spatial light modulator 10, the unit circuits are repeatedly arranged in the extending direction of the scanning line 76 (X-axis direction) and the extending directions of the data line 74 and the common potential line 77 (Y-axis direction).

[0149] Two data lines and two scanning lines are wired in the circuit region of the pixel circuit board 100. By independently applying voltages to the two data lines and the two scanning lines, the n-th driving switch Tr n to the (n+3)-th driving switch Tr n+3 can be independently driven and stopped.

[0150] In FIGS. 8A to 8C, the data terminals 73 of the n-th driving switch Tr n and the (n+1)-th driving switch Tr n+1 are connected to the n-th data line DL n . Also, the data terminals 73 of the (n+2)-th driving switch Tr n+2 and the (n+3)-th driving switch Tr n+3 are connected to the (n+1)-th data line DL n+1is connected thereto. Accordingly, the control terminals 81 of the n-th drive switch Tr n and the (n + 1)-th drive switch Tr n+1 are arranged close to the (n + 1)-th data line DL n+1 . Also, the control terminals 81 of the (n + 2)-th drive switch Tr n+2 and the (n + 3)-th drive switch Tr n+3 are arranged close to the n-th data line DL n .

[0151] When the control terminals 81 of the n-th drive switch Tr n to the (n + 3)-th drive switch Tr n+3 are arranged in a substantially straight line, since the control terminal line 80a extends in the Z-axis direction, there is a possibility that the wiring space for the scanning line 76 cannot be secured. In contrast, in FIGS. 8A to 8C, since the control terminals 81 of the n-th drive switch Tr n to the (n + 3)-th drive switch Tr n+3 are not arranged in a substantially straight line, the wiring space for the scanning line 76 can be secured. Also, as shown in FIG. 8B, since the scanning line 76 has the wiring segment 76a, the detour of the control terminal line 80a can be easily performed.

[0152] In FIGS. 9A to 9C, the data terminals 73 of the n-th drive switch Tr n and the (n + 2)-th drive switch Tr n+2 are connected to the n-th data line DL n . Also, the data terminals 73 of the (n + 1)-th drive switch Tr n+1 and the (n + 3)-th drive switch Tr n+3 are connected to the (n + 1)-th data line DL n+1 . Accordingly, the control terminals 81 of the n-th drive switch Tr n and the (n + 2)-th drive switch Tr n+2 are arranged close to the (n + 1)-th data line DL n+1 . Also, the control terminals 81 of the (n + 1)-th drive switch Tr n+1 and the (n + 3)-th drive switch Tr n+3 are arranged close to the n-th data line DL n . Other configurations are the same as those in FIGS. 8A to 8C.

[0153] Also in FIGS. 9A to 9C, the control terminals 81 of the n-th drive switch Tr n to the (n + 3)-th drive switch Tr n+3 are not arranged in a substantially straight line, so that a wiring space for the scanning line 76 can be secured. Further, since the scanning line 76 has the wiring segment 76a, the control terminal line 80a can be easily formed. Therefore, the same effects as those in FIGS. 8A to 8C can be obtained.

[0154] Also, as shown in FIG. 10, among the unit circuits in FIGS. 9A to 9C, the unit circuit formed from the portion of the (n - 2)-th drive switch Tr n-2 to the (n + 1)-th drive switch Tr n+1 can also obtain the same effects as described above.

[0155] Note that in the light modulation region of the spatial light modulator 10, the unit circuits in FIGS. 8A to 8C, FIGS. 9A to 9C, and FIG. 10 may be combined and used.

[0156] Also, as shown in FIG. 11, the drive switch Tr may have a memory element 75a. The memory element 75a is connected to the data line 74 and the scanning line 76, and based on the signals from the data line 74 and the scanning line 76, by transmitting an electrical signal to the scanning terminal line 75, the drive switch Tr can be driven. In the case of the configuration of FIG. 11, the operating voltage (V DD ) of the drive switch Tr is always applied to the end 73a of the data terminal 73. Further, when storing data in the memory element 75a, the positive power supply (V DD ) of the drive switch Tr is applied to the first terminal 75a1 of the memory element 75a, and the negative power supply (V SS ) of the drive switch Tr is applied to the second terminal 75a2 of the memory element 75a.

[0157] Note that the memory element 75a can be any one according to the purpose or application of the pixel circuit board 100. The memory element 75a is selected from, for example, DRAM, SRAM, FeRAM, or ReRAM, etc.

Description of Reference Numerals

[0158] 1 represents a system, 2 an arithmetic system, 3 a control system, 5 a light source, 5-1 a red light source, 5-2 a green light source, 5-3 a blue light source, 5a a speckle noise suppression module, 5b a speckle noise suppression mechanism, 5c an optical isolator, 5d a beam shaping element, 7 a beam expander, 8 a multiplexing system, 9 a projection optical system, 10 a spatial light modulator, 20 a cover glass, 30 a light modulation layer, 30a liquid crystal molecules, 40 an alignment film, 50 a transparent electrode, 60 a substrate, 65 an active layer region, 65-1 a doped region, 65a a trench insulating portion, 70 a drive switch circuit, 71 an insulating film, 72 a scanning terminal, 73 a data terminal, 73a a terminal end, 74 a data line, 75 a scanning terminal line, 75a a memory element, 75a1 a first terminal, 75a2 a second terminal, 76 a scanning line, 76a a wiring segment, 77 a common potential line, 77a a branch line, 78 an auxiliary capacitance dielectric, 78-1 a first auxiliary capacitance dielectric, 78-2 a second auxiliary capacitance dielectric, 79 an insulating material, 80 a control line, 80a a control terminal line, 80b a relay line, 80b1 a first relay line, 80b2 a second relay line, 80c an electrode line, 81 a control terminal, 90 a pixel electrode, 90a a pixel surface, 100 a pixel circuit board, 150 a pixel circuit, 200 a drive circuit.

Claims

1. A pixel circuit board for a spatial light modulator, comprising: a plurality of pixel electrodes arranged at intervals from each other and each having a pixel surface defining a pixel of the spatial light modulator; a plurality of active layer regions extending across adjacent pixel electrodes at a position overlapping the pixel surface and arranged at intervals from each other in a direction intersecting the arrangement direction of the plurality of pixel electrodes; a plurality of drive switches formed in each of the plurality of active layer regions and each having a scan terminal, a data terminal, and a control terminal; a plurality of control lines connected between each of the control terminals and one of the plurality of pixel electrodes; a scan line disposed between the plurality of drive switches and the plurality of pixel electrodes and connected to the scan terminal; a data line disposed between the plurality of drive switches and the plurality of pixel electrodes and connected to the data terminal ; wherein the scan line extends between the plurality of drive switches and the plurality of pixel electrodes while bypassing the plurality of control lines. The pixel circuit board.

2. The pixel circuit board according to claim 1, wherein the scan line has a wiring segment extending across adjacent active layer regions. The pixel circuit board according to claim 1.

3. Each of the plurality of control lines includes: a control terminal line extending in a direction away from each of the control terminals; an electrode line extending in a direction away from one of the plurality of pixel electrodes; a relay line connecting between the control terminal line and the electrode line and extending in the arrangement direction of the plurality of pixel electrodes ; wherein the scan line extends between the plurality of drive switches and the relay line while bypassing the control terminal line. The pixel circuit board according to claim 1 or 2.

4. The pixel circuit board according to claim 1 or 2, wherein the pixel surface has a rectangular shape. The pixel circuit board according to claim 1 or 2.

5. The pixel circuit board according to claim 4, wherein in the extending direction of the active layer region, the width of the active layer region is longer than the width of the pixel surface. The pixel circuit board according to claim 4.

6. The pixel circuit board according to claim 4, wherein in the arrangement direction of the plurality of active layer regions, the width of the active layer region is shorter than the width of the pixel surface. The pixel circuit board according to claim 4.

7. The pixel circuit board according to claim 4, wherein the pixel surface is square. The pixel circuit board according to claim 4.

8. The plurality of active layer regions are formed of a single crystal material selected from the group consisting of Si, SiC, GaN, and Ga ２ O ３ ​ The pixel circuit board according to claim 1 or 2.

9. A spatial light modulator, comprising: the pixel circuit board according to claim 1 or 2; a transparent electrode forming a drive circuit together with the pixel circuit of the pixel circuit board; a light modulation layer disposed between the plurality of pixel electrodes and the transparent electrode and to which a voltage is applied from the drive circuit .

10. The light modulation layer is formed of a ferroelectric liquid crystal The spatial light modulator according to claim 9

11. Comprising the spatial light modulator according to claim 9 Display system

12. The display system is a holographic display for hologram reproduction The display system according to claim 11

Images