Solar cell, method for preparing the same, and photovoltaic module

Abstract

To provide a solar cell, a method for preparing the same, and a photovoltaic module, according to the present embodiment relating to the field of photovoltaics.SOLUTION: The solar cell includes: a substrate which has a first surface including an edge region and a center region, and in which the edge region surrounds the center region, and the edge region is flush with or lower than the center region; a dielectric layer and a doped semiconductor layer which are installed stacked on one another, and in which the dielectric layer is positioned over the center region; a passivation layer that covers the edge region and a surface of the doped semiconductor layer; and electrodes that are positioned in the center region, and penetrate the passivation layer in a thickness direction to be in electrical contact with the doped semiconductor layer. The solar cell, the method for preparing the same, and the photovoltaic module that are provided in an embodiment of the present invention, are advantageous at least in improvement of a photoelectric conversion efficiency of the solar cell.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the present application relate to the field of photovoltaic power, and more particularly, to solar cells and their manufacturing methods, and photovoltaic modules.

Background Art

[0002] Currently, with the depletion of fossil energy, solar cells are being increasingly widely used as an alternative for new energy. A solar cell is a device that converts solar light energy into electrical energy. Solar cells utilize the principle of photovoltaic power generation to generate carriers, and by extracting carriers at the electrodes, they contribute to the effective utilization of electrical energy.

[0003] TOPCon (Tunnel Oxide Passivated Contact) cells or TBC (TOPCon-BC) cells consisting of IBC using TOPCon technology require the formation of an ultrathin tunnel oxide layer and a highly doped polycrystalline silicon layer on the silicon surface. By utilizing the chemical passivation of the tunnel oxide layer and the field passivation effect of the polycrystalline silicon layer, the recombination rate of minority carriers on the silicon surface can be significantly reduced. On the other hand, the highly doped polycrystalline layer significantly improves the conductive performance of majority carriers and contributes to the improvement of the open-circuit voltage and the backing factor of the battery.

[0004] Low Pressure Chemical Vapor Deposition (LPCVD) is the main technology for manufacturing the tunnel oxide layer and the polycrystalline silicon layer. It has the advantages of low cost, high production volume, and high performance of the manufactured film, and is currently widely applied. However, during the process of manufacturing the polycrystalline silicon layer using LPCVD, there may be problems that affect the battery efficiency, such as poor removal or over-etching during the removal process of the silicon glass layer formed by the oxidation of the polycrystalline silicon layer.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Examples of the present application provide a solar cell, a method for manufacturing the same, and a photovoltaic module that are at least advantageous for improving the photoelectric conversion efficiency of the solar cell.

Means for Solving the Problems

[0006] According to some examples of the present application, in one aspect of the examples of the present application, a solar cell is provided, the solar cell including a substrate having a first surface and a second surface opposite to the first surface, the first surface including a peripheral region and a central region, the peripheral region surrounding the central region, the peripheral region being substantially flush with the central region or closer to the second surface than the central region, a dielectric layer located in the central region, a doped semiconductor layer located on a surface of the dielectric layer away from the substrate, a passivation layer covering surfaces of the peripheral region and the doped semiconductor layer, and an electrode including a first number of electrodes, the first number of electrodes being located in the central region and being in electrical contact with the doped semiconductor layer through the thickness of the passivation layer.

[0007] In some examples, the substrate has a first boundary, a boundary of the central region towards the peripheral region is a second boundary, the first boundary faces the second boundary, and a distance between the second boundary and the first boundary is less than 300 μm.

[0008] In some examples, the peripheral region has a texture structure, and the passivation layer covers the texture structure.

[0009] In some examples, the texture structure includes a tower foundation structure, a pyramid structure, or a platform protrusion structure.

[0010] In some examples, a range of a height difference between the peripheral region and the central region is 1.5 μm to 15 μm.

[0011] In some embodiments, the range of the height difference between the top of the texture structure and the central region is 1 μm to 14 μm.

[0012] In some embodiments, the central region includes alternately arranged P regions and N regions, there is a spacing region between the P region and the N region, the doped semiconductor layer includes a first doped semiconductor layer located in the P region and a second doped semiconductor layer located in the N region, the electrodes include a first electrode and a second electrode, the first electrode is in electrical contact with the first doped semiconductor layer, the second electrode is in electrical contact with the second doped semiconductor layer, and the passivation layer covers the surface of the substrate in the spacing region.

[0013] In some embodiments, the peripheral region is provided with a first texture structure, the spacing region is provided with a second texture structure, and the roughness of the first texture structure is greater than or equal to the roughness of the second texture structure.

[0014] In some embodiments, the spacing region is flush with the P region and the N region, or the spacing region is lower than the P region and the spacing region is lower than the N region.

[0015] In some embodiments, the substrate further includes a second surface disposed opposite to the first surface, and the solar cell further includes an emitter located on the second surface.

[0016] In some embodiments, the electrodes further include a second number of electrodes, the second number of electrodes is located in the peripheral region, and the electrodes penetrate through the thickness of the passivation layer and are in electrical contact with the peripheral region.

[0017] In some embodiments, the electrode further includes a third number of electrodes, the third number of electrodes including a first portion and a second portion arranged along a first direction, the first portion being located in the central region, the second portion being located in the peripheral region, and the first direction being the arrangement direction of the electrodes.

[0018] In some embodiments, the doped semiconductor layer includes at least one of an amorphous silicon doped layer, a polycrystalline silicon doped layer, a microcrystalline silicon doped layer, a silicon carbide doped layer, or a crystalline silicon doped layer.

[0019] According to some embodiments of the present application, in another aspect of the embodiments of the present application, a photovoltaic module is provided, the photovoltaic module including a cell string formed by connecting solar cells in any of the above-described embodiments, a sealing adhesive film for covering the surface of the cell string, and a cover plate for covering the surface of the sealing adhesive film away from the cell string.

Advantages of the Invention

[0020] The technical solution provided by the embodiments of the present application has at least the following advantages.

[0021] In the embodiments of the present application, a solar cell is provided. After dividing the substrate into a peripheral region and a central region, different designs are performed on the film layers of the peripheral region and the central region, thereby avoiding overetching in the peripheral region and ensuring good electrical performance in the central region. The peripheral region is flush with the central region or lower than the central region, and the passivation layer covers the surfaces of the peripheral region and the doped semiconductor layer, thereby reducing surface defects and flatness at the edge and realizing sufficient and effective passivation for the edge of the battery. In this way, electrical recombination and leakage at the edge of the battery can be reduced, the open-circuit voltage and short-circuit current of the battery can be improved, and the photoelectric conversion efficiency of the battery can be increased.

Brief Description of the Drawings

[0022] One or more embodiments are exemplarily illustrated in the figures in the corresponding accompanying drawings. These exemplary descriptions do not limit the embodiments. Unless otherwise specified, the figures in the accompanying drawings are not limited by scale. To more clearly explain the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative labor.

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DETAILED DESCRIPTION OF THE INVENTION

[0023] As can be seen from the background art, the current photoelectric conversion efficiency of solar cells is not good.

[0024] As can be seen from the analysis, one of the reasons for the poor photoelectric conversion efficiency of solar cells is that, currently, in the process of forming a semiconductor layer with a P-type doping element or an N-type doping element, generally, the LPCVD process is adopted for deposition. The LPCVD process includes a first growth for forming an intrinsic semiconductor film, a second growth for introducing a doping element into the intrinsic semiconductor film, and an oxidation treatment. Thus, it is inevitable to form a silicon-doped glass layer on the surface of the formed doped semiconductor layer and the substrate (emitter). When removing the silicon-doped glass layer on the surface of the substrate (emitter), a protective layer can be formed on the surface of the doped semiconductor layer to reduce damage to the doped semiconductor layer. As can be seen from research, when the entire substrate is immersed in an etching solution, since no protective layer is formed on the side surface of the substrate, the etching solution corrodes a part of the surface of the doped semiconductor layer through the side surface of the substrate, causing an increase in surface defects of the doped semiconductor layer, which may affect the improvement of photoelectric conversion efficiency.

[0025] The embodiment of the present application provides a solar cell. After dividing the substrate into a peripheral region and a central region, different designs are made for the film layers in the peripheral region and the central region to avoid over-etching in the peripheral region and ensure good electrical performance in the central region. The peripheral region is flush with or lower than the central region, and the passivation layer covers the surfaces of the peripheral region and the doped semiconductor layer, thereby reducing surface defects and flatness at the edge and realizing sufficient and effective passivation for the edge of the cell. In this way, the electrical recombination and leakage at the edge of the cell can be reduced, the open-circuit voltage and short-circuit current of the cell can be improved, and the photoelectric conversion efficiency of the cell can be enhanced.

[0026] Hereinafter, each embodiment of the present application will be described in detail in combination with the drawings. However, as those skilled in the art can understand, for the better understanding of the readers, although many technical details are proposed in the embodiments of the present application, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed by the embodiments of the present application can be realized.

[0027] FIG. 1 is a diagram showing the structure of a solar cell provided in an embodiment of the present application. FIG. 2 is a diagram showing a first type of cross-sectional structure along a1-a2 of FIG. 1. FIG. 3 is a diagram showing a second type of cross-sectional structure along a1-a2 of FIG. 1. FIG. 4 is a diagram showing a first type of cross-sectional structure along b1-b2 of FIG. 1.

[0028] As shown in FIGS. 1 and 2, according to some embodiments of the present application, in one aspect of the embodiments of the present application, a solar cell including a substrate 100 is provided. The substrate 100 has a first surface 11, and the first surface 11 includes a peripheral region 111 and a central region 112. The peripheral region 111 surrounds the central region 112, and the peripheral region 111 is flush with the central region 112 or lower than the central region 112.

[0029] In some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, for example, it may be silicon or germanium. Here, the elemental semiconductor material may be in a single crystal state, a polycrystalline state, an amorphous state or a microcrystalline state (a state having both a single crystal state and an amorphous state is called a microcrystalline state). For example, silicon may be at least one of single crystal silicon, polycrystalline silicon, amorphous silicon or microcrystalline silicon.

[0030] In some embodiments, the material of the substrate 100 may be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, materials such as silicon germanium, silicon carbide, gallium arsenide, indium gallium arsenide, perovskite, cadmium telluride, copper indium selenide, etc. The substrate 100 may be a sapphire substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.

[0031] In some embodiments, the substrate 100 may be an N-type semiconductor substrate or a P-type semiconductor substrate. In the N-type semiconductor substrate, an N-type doping element is doped, and the N-type doping element may be any of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). In the P-type semiconductor substrate, a P-type doping element is doped, and the P-type doping element may be any of group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0032] In some embodiments, the substrate 100 further includes a second surface 12 disposed opposite to the first surface 11.

[0033] In some embodiments, the solar cell is a single-sided cell, and the second surface 12 is used to receive incident light as a light-receiving surface, and the first surface 11 can be used as a backlight surface. The first surface can be used as the light-receiving surface, and the second surface can be used as the backlight surface. Here, although the backlight surface can also receive incident light, the light-receiving efficiency of the incident light on the backlight surface is weaker than that of the incident light on the light-receiving surface. In the embodiments of the present application, the example of using the first surface as the backlight surface and the second surface as the light-receiving surface is described.

[0034] In some embodiments, the solar cell is a double-sided cell, that is, both the first surface and the second surface of the substrate can be used to receive incident light as light-receiving surfaces.

[0035] In some embodiments, the first surface 11 of the substrate is a polished surface, and the polished surface refers to a flat surface formed by removing the original texture structure of the surface by a polishing liquid or laser etching. After polishing, the flatness of the first surface increases, the reflection of long-wavelength light increases, the secondary absorption of the projected light is promoted, the short-circuit current increases, and at the same time, the specific surface area of the first surface becomes smaller, thereby reducing the recombination of the first surface and improving the passivation effect of the first surface.

[0036] In some embodiments, the second surface 2 of the substrate 100 is provided with a third texture structure 13, and the third texture structure 13 can include a pyramid texture structure having a regular shape and black silicon having an irregular shape. The inclined surface of the third texture structure can increase the internal reflection of the incident light, improve the absorption utilization rate of the substrate 100 for the incident light, and improve the efficiency of the solar cell.

[0037] In some embodiments, the third texture structure 13 includes a plurality of protrusion structures 131, and the shape of the protrusion structure 131 may include a pyramid shape, a parabolic shape, or an ellipsoidal shape.

[0038] In some embodiments, the peripheral region 111 and the central region 112 are for explaining the structural distribution of each film layer of the solar cell based on the functional division of the substrate 100. As shown in FIG. 1, the region surrounded by the dotted line in the figure is the central region, and the region surrounded by the dotted line region and the edge region of the substrate is the peripheral region.

[0039] Here, there is a chamfer at the boundary between the edges of the substrate so that the widths of the peripheral regions are substantially the same, and the same installation is also provided in the region corresponding to the chamfer of the central region, which is used to improve the edge leakage of the solar cell.

[0040] In some embodiments, as shown in FIGS. 1 and 2, the substrate 100 includes a first boundary 121, and the boundary towards the peripheral region 111 of the central region 112 is a second boundary 122. The first boundary 121 faces the second boundary 122, and the distance s between the second boundary 122 and the first boundary 121 is less than 300 μm. The distance s between the first boundary 121 and the second boundary 122 may be less than 280 μm, 268 μm, 235 μm, or 200 μm. The distance s between the first boundary 121 and the second boundary 122 can limit the width of the peripheral region 111. When the width of the peripheral region 111 is small, that is, the region that needs to be adjusted is small, the impact on the original process is also small, optimizing the battery performance at the edge location while ensuring the battery performance of the central region 112.

[0041] In some embodiments, the range of the height difference h between the peripheral region 111 and the central region 112 is 1.5 μm to 15 μm. For example, the range of h may be 1.5 μm to 3 μm, 3 μm to 4.5 μm, 4.5 μm to 7 μm, 7 μm to 10 μm, or 10 μm to 15 μm. If the height difference h between the peripheral region 111 and the central region 112 is within the above range, it will be clearly distinguishable between the peripheral region 111 and the central region 112. Thereby, the doping semiconductor layer located in the peripheral region 111 is removed as much as possible, ensuring that the passivation layer can sufficiently passivate the peripheral region 111. The height difference h between the peripheral region 111 and the central region 112 can also improve the leakage problem of the peripheral region and the breakage problem at the edge, enhancing the yield and appearance of the battery.

[0042] In some embodiments, as shown in FIGS. 2 and 3, the peripheral region 111 includes a texture structure 14. The texture structure 14 can increase the internal reflectance of the incident light in the peripheral region 111 and improve the passivation effect of the passivation layer 114, thereby enhancing the photoelectric conversion efficiency of the solar cell.

[0043] In some embodiments, the texture structure 14 includes a tower base structure, a pyramid structure, or a platform protrusion structure. Here, the tower base structure is the bottom structure after removing the tip portion of the pyramid structure, and is the remaining texture structure lower than 1 / 4 of the height of the original pyramid structure. The platform protrusion structure is a plane formed by removing the tip portion of the pyramid structure, and is the remaining texture structure higher than 1 / 4 of the height of the original pyramid structure.

[0044] In some embodiments, the tower base structure may be a polished surface structure. The tower base structure increases the flatness of the peripheral region 111, increases the reflection of long-wavelength light, promotes the secondary absorption of the projected light, and improves the short-circuit current. At the same time, since the specific surface area of the peripheral region 111 decreases, the recombination of the peripheral region 111 can be reduced, and the passivation effect of the peripheral region 111 can be enhanced.

[0045] In some embodiments, the range of the height difference h1 between the top of the texture structure 14 and the central region 112 is 1 μm to 14 μm. The range of h1 may be 1.5 μm to 3.2 μm, 3.2 μm to 5 μm, 5 μm to 7.5 μm, 7.5 μm to 11 μm, or 11 μm to 14 μm.

[0046] In some embodiments, as shown in FIG. 3, the texture structure 14 is a pyramid structure, the pyramid structure includes a plurality of pyramids 141, the range of the one-dimensional dimension d2 of the pyramid 141 includes 0.1 μm to 3 μm, and the range of the height d1 of the pyramid 141 includes 0.1 μm to 3 μm.

[0047] In some embodiments, the one-dimensional dimension refers to the distance between two diagonals at the bottom of the pyramid 141 or the distance between two opposite sides at the bottom of the pyramid 141.

[0048] In some embodiments, as shown in FIG. 3, the height difference h between the peripheral region 111 and the central region 112 may be the height difference between the top of the pyramid 141 and the central region 112.

[0049] In some embodiments, the height difference h between the peripheral region 111 and the central region 112 refers to the height difference between the bottom of the pyramid and the central region 112, and the range of the height difference between the top surface of the pyramid and the central region is 1 μm to 14 μm.

[0050] As shown in FIG. 2, the solar cell includes a dielectric layer 102 located in the central region 112 and a doped semiconductor layer 103 located on the surface of the dielectric layer 102.

[0051] In some embodiments, the dielectric layer 102 may be a tunnel dielectric layer. A passivation contact structure is formed between the tunnel dielectric layer and the doped semiconductor layer 103. The doped semiconductor layer 103 can form a band bend on the surface of the substrate 100. The tunnel dielectric layer causes an asymmetric offset in the band on the surface of the substrate 100, such that the potential barrier for majority carriers in the carriers is lower than the potential barrier for minority carriers in the carriers. Therefore, majority carriers can easily pass through the tunnel dielectric layer to perform quantum tunneling, while minority carriers have difficulty passing through the tunnel dielectric layer, thus realizing selective transport of carriers.

[0052] In addition, the tunnel dielectric layer exhibits the effect of chemical passivation. Specifically, since there are interface state defects at the interface between the substrate 100 and the tunnel dielectric layer, the interface state density on the first surface of the substrate 100 increases. The increase in the interface state density promotes the recombination of photo-generated carriers, increases the back factor, short-circuit current, and open-circuit voltage of the solar cell, and improves the photoelectric conversion efficiency of the solar cell. By installing the tunnel dielectric layer so that it is located on the first surface of the substrate 100, the tunnel dielectric layer exerts the effect of chemical passivation on the surface of the substrate 100. Specifically, by saturating the dangling bonds of the substrate 100, reducing the density of defect levels of the substrate 100, and reducing the recombination centers of the substrate 100, the recombination rate of carriers is reduced.

[0053] The doped semiconductor layer 103 exhibits the effect of field passivation. Specifically, an electrostatic field directed from the surface of the substrate 100 into the interior of the substrate 100 is formed, and minority carriers are caused to escape from the interface, thereby reducing the concentration of minority carriers, decreasing the carrier recombination rate at the interface of the substrate 100, increasing the open-circuit voltage, short-circuit current, and back-bias factor of the solar cell, and enhancing the photoelectric conversion efficiency of the solar cell.

[0054] The doped semiconductor layer 103 may be doped with a doping element of the same type as the substrate 100. For example, when the type of the doping element of the substrate 100 is N-type, the doped semiconductor layer 103 is doped with an N-type doping element.

[0055] The concentration of the doping element in the doped semiconductor layer 103 is greater than the concentration of the doping element of the substrate 100, thereby forming a sufficiently high potential barrier on the surface of the substrate 100 and enabling the majority carriers in the substrate 100 to reach the doped semiconductor layer 103 by passing through the tunneling dielectric layer.

[0056] In some embodiments, the doped semiconductor layer 103 may be doped with a doping element having a conductivity type different from that of the substrate 100. For example, when the type of the doping element of the substrate 100 is P-type, the type of the doping element in the doped semiconductor layer 103 may be N-type. Thereby, a PN junction is constructed between the doped semiconductor layer 103 and the substrate 100. When sunlight irradiates the PN junction, new electron-hole pairs are formed. Under the action of the built-in electric field of the PN junction, the photo-generated holes flow into the P region, the photo-generated electrons flow into the N region, and a current is generated when the circuit is turned on.

[0057] In some embodiments, the thickness of the tunnel dielectric layer is from 0.5 nm to 5 nm. The thickness range of the tunnel dielectric layer is from 0.5 nm to 1.3 nm, from 1.3 nm to 2.6 nm, from 2.6 nm to 4.1 nm, or from 4.1 nm to 5 nm. If the tunnel dielectric layer is within any of the above ranges, the thickness of the tunnel dielectric layer is thin, and majority carriers can easily pass through the tunnel dielectric layer to perform quantum tunneling. However, since minority carriers have difficulty passing through the tunnel dielectric layer, selective transport of carriers can be realized.

[0058] In some embodiments, the material of the dielectric layer 102 includes at least one of silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, or silicon carbide.

[0059] In some embodiments, the doped semiconductor layer 103 includes at least one of an amorphous silicon doped layer, a polycrystalline silicon doped layer, a microcrystalline silicon doped layer, a silicon carbide doped layer, or a crystalline silicon doped layer.

[0060] As shown in FIG. 2, the solar cell includes a passivation layer 114 covering the surface of the peripheral region 111 and the doped semiconductor layer 103, and electrodes 116 including a first number of electrodes. The first number of electrodes are located in the central region 112 and are in electrical contact with the doped semiconductor layer 103 through the thickness of the passivation layer 114.

[0061] In some embodiments, the passivation layer 114 may have a single-layer structure or a stacked structure, and the material of the passivation layer 114 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbynitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0062] In some embodiments, as shown in FIG. 3, the passivation layer 114 covers the texture structure 14.

[0063] In some embodiments, the solar cell further includes an antireflection layer 105, the antireflection layer 105 is located on the surface of the passivation layer 114, and the first number of electrodes penetrate the thickness of the antireflection layer 105 and are in electrical contact with the doped semiconductor layer 103. The antireflection layer 105 is used to reduce or remove the reflected light on the surface of the solar cell, increase the light transmission amount on the surface of the solar cell, and reduce or remove the stray light of the system. The material of the antireflection layer 105 includes silicon nitride or silicon oxynitride.

[0064] In some embodiments, the solar cell further includes an emitter 101 located on the second surface 12, a first passivation layer 104 covering the surface of the emitter 101, and a thin grid 106 that penetrates the first passivation layer 104 and is in electrical contact with the emitter 101.

[0065] In some embodiments, the materials of the emitter 101 and the substrate 100 are the same, and the emitter 101 and the substrate 100 may be formed by doping the same original substrate. The type of doping element in the emitter 101 is different from the type of doping element in the substrate 100. Doping treatment is performed on a part of the thickness of the original substrate, and the doped part of the original substrate is used as the emitter, and the remaining original substrate is used as the substrate.

[0066] In some embodiments, the emitter 101 is a doped layer formed on the second surface of the substrate, and is a semiconductor layer formed by a deposition process and doped with an N-type doping element or a P-type doping element, and the semiconductor layer may be silicon, germanium or polycrystalline silicon.

[0067] In some embodiments, the first passivation layer 104 may have a single-layer structure or a laminated structure, and the material of the first passivation layer 104 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, titanium oxide, hafnium oxide or aluminum oxide.

[0068] In some embodiments, the material of the first passivation layer 104 is the same as the material of the passivation layer 114, and the first passivation layer 104 and the passivation layer 114 are manufactured in the same manufacturing process.

[0069] In some embodiments, either the electrode 116 or the thin grid 106 can be formed by sintering with a sputtered paste. The method of forming the electrode 116 includes adopting a silk screen printing process to print a metal paste on the surface of some of the passivation layers 114. The method of forming the thin grid 106 includes adopting a silk screen printing process to print a metal paste on the surface of some of the first passivation layers 104. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead or nickel.

[0070] In some embodiments, as shown in FIG. 2 or FIG. 4, the electrode 116 and the thin grid 106 are located in the central region 112.

[0071] FIG. 5 is a diagram showing a cross-sectional structure of a solar cell provided in an embodiment of the present application, FIG. 6 is a diagram showing another cross-sectional structure of a solar cell provided in an embodiment of the present application, and FIG. 7 is a diagram showing another cross-sectional structure of a solar cell provided in an embodiment of the present application.

[0072] In some embodiments, as shown in FIGS. 5 and 7, the electrode 116 further includes a third number of electrodes, and the third number of electrodes includes a first portion 136 and a second portion 126 arranged along a first direction. The first portion 136 is located in the central region 112, the second portion 126 is located in the peripheral region 111, and the first direction is the arrangement direction of the electrode 116. Thereby, the collection area of the electrode 116 is increased, and the efficiency of the battery is improved.

[0073] In some embodiments, the first portion 136 is in electrical contact with the doped semiconductor layer 103, and the second portion 126 is in electrical contact with the substrate 100.

[0074] In some embodiments, as shown in FIG. 6, the electrode 116 further includes a second number of electrodes, the second number of electrodes are located in the peripheral region, and the electrode 116 penetrates the thickness of the passivation layer 114 and is in electrical contact with the peripheral region 111.

[0075] Embodiments of the present application provide a solar cell, which divides the substrate 100 into a peripheral region 111 and a central region 112, and by performing different designs on the film layers of the peripheral region 111 and the central region 112, over-etching of the peripheral region 111 is avoided, and good electrical performance of the central region 112 is ensured. The peripheral region 111 is flush with the central region 112 or lower than the central region 112, and the passivation layer 114 covers the surfaces of the peripheral region 111 and the doped semiconductor layer 103, thereby reducing surface defects and flatness at the edge location, and realizing sufficient and effective passivation for the edge of the battery. Thereby, electrical recombination and leakage at the edge of the battery can be reduced, the open-circuit voltage and short-circuit current of the battery can be improved, and the photoelectric conversion efficiency of the battery can be increased.

[0076] Furthermore, other embodiments of the present application provide a solar cell, which includes a first electrode and a second electrode, and both the first electrode and the second electrode are located on the first surface. For the same technical features or corresponding technical features as the above embodiments, they will not be described repeatedly here.

[0077] FIG. 8 is a diagram showing the structure of a solar cell provided in another embodiment of the present application, FIG. 9 is a diagram showing a first type of cross-sectional structure along a3-a4 of FIG. 8, and FIG. 10 is a diagram showing a second type of cross-sectional structure along a3-a4 of FIG. 8.

[0078] As shown in FIGS. 8 and 9, the solar cell includes a substrate 200 having a first surface 21, a dielectric layer located in a central region 212, a doped semiconductor layer located on the surface of the dielectric layer, a passivation layer 214 covering the surfaces of the peripheral region 211 and the doped semiconductor layer, and an electrode located in the central region 212 and electrically contacting the doped semiconductor layer through the thickness of the passivation layer 214. Here, the first surface 21 includes a peripheral region 211 and a central region 212, the peripheral region 211 surrounds the central region 212, and the peripheral region 211 is flush with the central region 212 or lower than the central region 212.

[0079] In some embodiments, the substrate 200 includes opposing first and second surfaces 21 and 22, the surface of the second surface 22 has a third texture structure 23, and the third texture structure 23 includes a plurality of protrusion structures 231. The second surface 22 has a front surface field (FSF), and the conduction type of its dopant ions is the same as that of the dopant ions in the substrate 200. By utilizing the field passivation effect, the minority carrier concentration on the surface can be reduced, the surface recombination rate can be decreased, the series resistance can be reduced, and the electron transport ability can be enhanced.

[0080] In some embodiments, the central region 212 includes alternately arranged P regions and N regions, and there is a spacing region 20 between the P regions and the N regions.

[0081] In some embodiments, the spacing region 20 is flush with the P regions and the N regions, that is, without etching the substrate, insulation between the P regions and the N regions is achieved by several isolated film layers. The isolated film layer may be a passivation layer.

[0082] In some embodiments, as shown in FIG. 9, the spacer region 20 is lower than the P region and the spacer region 20 is lower than the N region. The spacer region 20 includes a trench 208 that extends from the first surface 21 to the second surface 22. The trench 208 is used to achieve automatic isolation between regions of different conductivity types, and can prevent the formation of a tunneling junction between the highly doped P region and the N region in an IBC (Interdigitated Back Contact) cell from causing leakage current and affecting the battery efficiency.

[0083] In some embodiments, the depth H of the trench 208 is greater than or equal to the height difference h between the peripheral region 211 and the central region 212.

[0084] Here, the height difference h between the peripheral region 211 and the central region 212 refers to the height difference between the peripheral region 211 and the P region or the height difference between the peripheral region 211 and the N region.

[0085] In some embodiments, as shown in FIG. 10, the peripheral region 211 includes a first texture structure 24, the spacer region 20 includes a second texture structure 25, and the roughness of the first texture structure 24 is greater than or equal to the roughness of the second texture structure 25.

[0086] Here, the "roughness" refers to setting an average horizontal line for a sampled length and taking the arithmetic mean value of the absolute value of the vertical deviation amount with respect to the average horizontal line of the peaks and valleys within the sampled length. The roughness can be measured by the comparison method, the optical cutting method, the interference method, and the probe scanning method.

[0087] In some embodiments, the doped semiconductor layer includes a first doped semiconductor layer 2031 located in the P region and a second doped semiconductor layer 2032 located in the N region. The electrodes include a first electrode 2161 and a second electrode 2162. The first electrode 2161 is in electrical contact with the first doped semiconductor layer 2031, the second electrode 2162 is in electrical contact with the second doped semiconductor layer 2032, and the passivation layer 214 covers the surface of the substrate 200 in the spacer region 20.

[0088] In some embodiments, the dielectric layer includes a first dielectric layer 2021 and a second dielectric layer 2022. The first doped semiconductor layer 2031 is located in the first dielectric layer 2021, and the second doped semiconductor layer 2032 is located in the second dielectric layer 2022.

[0089] In some embodiments, the first dielectric layer 2021 and the second dielectric layer 2022 may be the same as the dielectric layer 102 in the previous embodiment, that is, the first dielectric layer 2021 and the second dielectric layer 2022 are tunnel dielectric layers. Similarly, the first doped semiconductor layer 2031 and the second doped semiconductor layer 2032 may be the doped semiconductor layer 103 in the previous embodiment. The difference is that one of the N-type doping element or the P-type doping element is doped in the first doped semiconductor layer 2031, and the other of the N-type doping element or the P-type doping element is doped in the second doped semiconductor layer 2032.

[0090] In some embodiments, the first electrode 2161 and the second electrode 2162 may refer to the electrode 116 in the previous embodiment, the first passivation layer 204 on the second surface 22 may refer to the first passivation layer 104 in the previous embodiment, the antireflection layer 205 may refer to the antireflection layer 105 in the previous embodiment, and the passivation layer 214 may refer to the passivation layer 114 in the previous embodiment. Here, it will not be described repeatedly.

[0091] Embodiments of the present application provide a solar cell. The substrate 200 is divided into a peripheral region 211 and a central region 212, and different designs are made for the film layers in the peripheral region 211 and the central region 212, thereby avoiding over-etching of the peripheral region 211 and ensuring good electrical performance of the central region 212. The peripheral region 211 is flush with or lower than the central region 212, and the passivation layer 214 covers the surfaces of the peripheral region 211 and the doped semiconductor layer, thereby reducing surface defects and flatness at the edge location and realizing sufficient and effective passivation for the edge of the battery. In this way, electrical recombination and leakage at the battery edge can be reduced, the open-circuit voltage and short-circuit current of the battery can be improved, and the photoelectric conversion efficiency of the battery can be increased.

[0092] Correspondingly, according to some embodiments of the present application, in one aspect of the embodiments of the present application, a method for manufacturing a solar cell for manufacturing the solar cell provided in the above embodiments is provided. For the same or corresponding technical features as those in the above embodiments, they will not be repeatedly described here.

[0093] FIGS. 11 to 18 are diagrams showing cross-sectional structures of solar cells corresponding to respective steps in a method for manufacturing a solar cell provided in other embodiments. Embodiments of the present application take the solar cell provided in other embodiments as an example.

[0094] As shown in FIG. 11, the manufacturing method includes providing a substrate 200 having a first surface 21, where the first surface 21 includes a peripheral region 211 and a central region 212, and the peripheral region 211 surrounds the central region 212.

[0095] In some embodiments, the substrate 200 includes a second surface 22 opposite to the first surface 21.

[0096] The manufacturing method includes performing a texturing process on the second surface 22 so as to give the second surface 22 a third texture structure 23. Here, the third texture structure 23 includes a plurality of protrusion structures 231.

[0097] In some embodiments, the texture formation process may include chemical etching. For example, the substrate 200 is cleaned with a mixed solution of potassium hydroxide and hydrogen peroxide. Specifically, a texture structure with a morphology that conforms to the desired shape can be formed by controlling the concentration ratio of potassium hydroxide to hydrogen peroxide. In some embodiments, a texture structure can be formed by methods such as laser etching, mechanical methods, and plasma etching. In laser etching, a texture structure with a morphology that conforms to the desired shape is obtained by controlling the parameters of the laser process.

[0098] As shown in FIG. 12, the manufacturing method includes forming a dielectric layer 202 located in the central region 212 and the peripheral region 211, and forming a doped semiconductor layer 203 located on the surface of the dielectric layer 202. Here, when forming the doped semiconductor layer 203, a silicon-doped glass layer 223 is formed on the second surface 22 of the substrate 200 and the surface of the doped semiconductor layer at the same time.

[0099] In some embodiments, the dielectric layer 202 is formed by thermal oxidation or chemical vapor deposition.

[0100] In some embodiments, the manufacturing method for forming the doped semiconductor layer 203 includes a first deposition, a second deposition, and a high-temperature oxidation step. Here, in the first deposition, the deposition gas contains silane, the flow rate is controlled to 100 - 1,000 sccm, and the deposition temperature is controlled to 400 - 700 °C to form an intrinsic semiconductor film. In the second deposition, the deposition gas contains a dopant source gas and oxygen gas, the flow rate is controlled to 100 - 3,000 sccm, and the deposition temperature is controlled to 700 - 1000 °C to form a doped semiconductor film. In the high-temperature oxidation step, the gas contains nitrogen gas and oxygen gas. In this process, the doped semiconductor film is converted into a doped semiconductor layer, and a silicon-doped glass layer 223 is formed on the second surface 22 of the substrate 200 and the surface of the doped semiconductor layer 203.

[0101] As shown in FIG. 13, the manufacturing method includes performing pretreatment on the silicon-doped glass layer 223, where the pretreatment includes being used to remove the silicon-doped glass layer 223 in the peripheral region 211.

[0102] In some embodiments, the pretreatment includes a laser treatment step. The laser can be a picosecond laser or a nanosecond laser. The parameters of the laser treatment step include a laser power of 8 W to 40 W and a speed of 10,000 mm / s to 35,000 mm / s.

[0103] In some embodiments, as shown in FIGS. 14 and 15, the process steps of the pretreatment include removing the silicon-doped glass layer 223 in the peripheral region 211, and at the same time, removing the doped semiconductor layer 203 in the peripheral region 211 and the dielectric layer 202 in the peripheral region 211.

[0104] As shown in FIG. 15, the manufacturing method includes removing the silicon-doped glass layer 223 on the second surface 22 and the silicon-doped glass layer 223 in the central region 212.

[0105] In some embodiments, in the process of removing the silicon-doped glass layer 223, the etching solution may etch the doped semiconductor layer 203 and the dielectric layer 202 and remove the doped semiconductor layer 203 and the dielectric layer 202.

[0106] In some embodiments, the central region 212 includes alternately arranged P regions and N regions, there is a spacing region 20 between the P region and the N region, and the doped semiconductor layer 203 is located in the P region, the N region, and the spacing region 20.

[0107] As shown in FIG. 16, the manufacturing method includes removing the doped semiconductor layer in the spacing region 20 and the first region, where the first region is one of the P region or the N region.

[0108] In some embodiments, the doped semiconductor layer and the dielectric layer in the spacer region 20 were removed, but the substrate was not etched and there were no trenches formed in the substrate. In some embodiments, the doped semiconductor layer and the dielectric layer in the spacer region 20 were removed, and a part of the thickness of the substrate was also removed, that is, trenches were formed in the substrate.

[0109] As shown in FIG. 18, the manufacturing method includes forming a doped semiconductor film on the surface of the substrate 200 in the first region, and making the remaining doped semiconductor layer and the doped semiconductor film into a first doped semiconductor layer 2031 and a second doped semiconductor layer 2032, respectively.

[0110] In some embodiments, as shown in FIG. 17, the pre-treatment process steps include removing the silicon-doped glass layer 223 in the peripheral region 211, and at the same time removing the silicon-doped glass layer 223 in the spacer region 20 and the first region, where the first region is one of the P region or the N region. As shown in FIG. 16, the silicon-doped glass layer 223 on the second surface 22 and the silicon-doped glass layer 223 in the central region 212 are removed, the doped semiconductor layers in the spacer region 20 and the first region are removed, and the first region is one of the P region or the N region. As shown in FIG. 18, after removing the silicon-doped glass layer 223 on the second surface 22 and the silicon-doped glass layer 223 in the central region 212, a doped semiconductor film is further formed in the first region, and the remaining doped semiconductor layer and the doped semiconductor film are made into a first doped semiconductor layer 2031 and a second doped semiconductor layer 2032, respectively.

[0111] In some embodiments, a laser processing step is used to remove the silicon-doped glass layer 223 in the spacer region 20, the peripheral region 211, and the first region. The laser can use a picosecond laser and a nanosecond laser. The parameters of the laser processing step include a laser power of 8W to 40W and a speed of 10,000 mm / s to 35,000 mm / s.

[0112] In some embodiments, the doped semiconductor layer and the dielectric layer in the spacer region 20 are removed, but the substrate is not etched and no trench is formed in the substrate. In some embodiments, the doped semiconductor layer and the dielectric layer in the spacer region 20 are removed, and a part of the thickness of the substrate is also removed, that is, a trench is formed in the substrate.

[0113] As shown in FIG. 9, the manufacturing method includes forming a passivation layer 214 covering the surfaces of the peripheral region 211 and the doped semiconductor layer. In some embodiments, the passivation layer 214 covers the surfaces of the peripheral region 211, the spacer region 20, the first doped semiconductor layer 2031, and the second doped semiconductor layer 2032.

[0114] As shown in FIG. 9, the manufacturing method includes forming a first passivation layer 204 covering the second surface 22 of the substrate 200.

[0115] In some embodiments, the passivation layer 214 and the first passivation layer 204 are formed by the same manufacturing process.

[0116] As shown in FIG. 9, the manufacturing method is to form electrodes, the electrodes are located in the central region 212, and the electrodes penetrate through the thickness of the passivation layer 214 and are in electrical contact with the doped semiconductor layer. The electrodes include a first electrode 2161 and a second electrode 2162. The first electrode 2161 penetrates through the thickness of the passivation layer 214 and is in electrical contact with the first doped semiconductor layer 2031, and the second electrode 2162 penetrates through the thickness of the passivation layer 214 and is in electrical contact with the second doped semiconductor layer 2032.

[0117] In some embodiments, the manufacturing method of the first electrode 2161 and the second electrode 2162 includes printing a metal paste on the surface of a part of the passivation layer 214 by a silk screen printing process. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel. Then, a sintering process is performed on the metal paste. Since the metal paste contains highly corrosive components such as glass powder, the corrosive components corrode the passivation layer 214 during sintering, and the metal paste penetrates into the passivation layer 214, thereby electrically contacting the first doped semiconductor layer 2031 to form the first electrode 2161 and electrically contacting the second doped semiconductor layer 2032 to form the second doped semiconductor layer 2162.

[0118] Correspondingly, according to some embodiments of the present application, in another aspect of the embodiments of the present application, a photovoltaic module including the solar cell of the above-described embodiment is provided. For the same parts as those in the above-described embodiment, the description will not be repeated here.

[0119] FIG. 19 is a diagram showing the structure of a photovoltaic module provided in another embodiment, and FIG. 20 is a diagram showing the cross-sectional structure along the M1-M2 cross-section of FIG. 19. The embodiment of the present application takes a photovoltaic module composed of a solar cell provided in another embodiment as an example.

[0120] As shown in FIGS. 19 and 20, the photovoltaic module includes a cell string in which a plurality of solar cells 30 in any of the above-described embodiments or a plurality of solar cells 30 manufactured by the manufacturing method in any of the above-described embodiments are connected, a sealing adhesive film 37 for covering the surface of the cell string, and a cover plate 38 for covering the surface of the sealing adhesive film 37 away from the cell string.

[0121] Specifically, in some embodiments, between a plurality of battery cells are electrically connected by a connection member 309, and between the connection member 309 and the main grid 224 in the battery cell can be welded.

[0122] In some embodiments, no gap is provided between the battery cells, that is, the battery cells overlap each other.

[0123] In some embodiments, the connection member and the sub-grid in the battery cell are welded, and the sub-grid includes a first electrode 2161 and a second electrode 2162. In some embodiments, the connection member and the main grid 224 in the battery cell are welded, and the main grid includes a first main grid and a second main grid. The first main grid and the first electrode 2161 are welded, and the second main grid and the second electrode 2162 are welded.

[0124] In some embodiments, the encapsulation adhesive film includes a first encapsulation adhesive film and a second encapsulation adhesive film. The first encapsulation adhesive film covers one of the front surface or the back surface of the solar cell, and the second encapsulation adhesive film covers the other of the front surface or the back surface of the solar cell. Specifically, at least one of the first encapsulation adhesive film and the second encapsulation adhesive film may be an organic encapsulation adhesive film such as a polyvinyl butyral (PVB) adhesive film, an ethylene vinyl acetate copolymer (EVA) adhesive film, a polyethylene-octene copolymer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film.

[0125] Before the lamination process, there is a boundary line between the first encapsulation adhesive film and the second encapsulation adhesive film. After the lamination process, when the photovoltaic module is formed, the concept of the first encapsulation adhesive film and the second encapsulation adhesive film no longer exists. That is, the first encapsulation adhesive film and the second encapsulation adhesive film are integrated to form an encapsulation adhesive film 47.

[0126] In some embodiments, the cover plate 38 may be a cover plate having a light transmission function such as a glass cover plate or a plastic cover plate. Specifically, the surface of the cover plate 48 facing the sealing adhesive film 37 side may be an uneven surface, whereby the utilization rate of incident light can be increased. The cover plate 38 includes a first cover plate and a second cover plate, the first cover plate faces the first sealing adhesive film, and the second cover plate faces the second sealing adhesive film. Alternatively, the first cover plate faces one side of the solar cell, and the second cover plate faces the other side of the solar cell.

[0127] Those skilled in the art will understand that each of the above embodiments is a specific example for implementing the present application, but in practice, various changes can be made in form and details without departing from the scope of the present application. Any person skilled in the art can make changes and modifications respectively as long as they do not depart from the spirit and scope of the present application. Therefore, the protection scope of the present application should be based on the scope limited by the claims.

Claims

Claim 1 A substrate, wherein the substrate has a first surface and a second surface facing the first surface, the first surface includes a peripheral region and a central region, the peripheral region surrounds the central region, and the peripheral region is substantially flush with the central region or closer to the second surface than the central region, and a dielectric layer located in the central region, a doped semiconductor layer located on the surface of the dielectric layer away from the substrate, a passivation layer covering the surfaces of the peripheral region and the doped semiconductor layer, an electrode including a first number of electrodes, the first number of electrodes being located in the central region and being in electrical contact with the doped semiconductor layer through the thickness of the passivation layer, a solar cell characterized by the above. Claim 2 The substrate has a first boundary, the boundary of the central region towards the peripheral region is a second boundary, the first boundary faces the second boundary, and the distance between the second boundary and the first boundary is less than 300 μm, The solar cell according to claim 1, characterized by the above. Claim 3 The peripheral region has a texture structure, and the passivation layer covers the texture structure, The solar cell according to claim 1, characterized by the above. Claim 4 The texture structure includes a tower foundation structure, a pyramid structure or a platform protrusion structure, The solar cell according to claim 3, characterized by the above. Claim 5 The range of the height difference between the peripheral region and the central region is 1.5 μm to 15 μm, The solar cell according to claim 1, characterized by the above. Claim 6 The range of the height difference between the top of the texture structure and the central region is 1 μm to 14 μm, The solar cell according to claim 4, characterized by the above. Claim 7 The central region includes alternately arranged P regions and N regions, there is a spacing region between the P region and the N region, the doped semiconductor layer includes a first doped semiconductor layer located in the P region and a second doped semiconductor layer located in the N region, the electrode includes a first electrode and a second electrode, the first electrode is in electrical contact with the first doped semiconductor layer, the second electrode is in electrical contact with the second doped semiconductor layer, and the passivation layer covers the surface of the substrate in the spacing region, The solar cell according to claim 1, characterized by the above. Claim 8 The peripheral region has a first texture structure, the spacing region has a second texture structure, and the roughness of the first texture structure is equal to or greater than that of the second texture structure. The solar cell according to claim 7, characterized in that.

9. The spacing region is flush with the P region and the N region, or the spacing region is lower than the P region and the spacing region is lower than the N region. The solar cell according to claim 7, characterized in that.

10. The substrate further includes a second surface disposed opposite the first surface, and the solar cell further includes an emitter located on the second surface. The solar cell according to claim 1, characterized in that.

11. The electrode further includes a second number of electrodes, the second number of electrodes is located in the peripheral region, and electrically contacts the peripheral region through the thickness of the passivation layer. The solar cell according to claim 10, characterized in that.

12. The electrode further includes a third number of electrodes, the third number of electrodes includes a first portion and a second portion arranged along a first direction, the first portion is located in the central region, the second portion is located in the peripheral region, and the first direction is the arrangement direction of the electrodes. The solar cell according to claim 10, characterized in that.

13. The doped semiconductor layer includes at least one of an amorphous silicon doped layer, a polycrystalline silicon doped layer, a microcrystalline silicon doped layer, a silicon carbide doped layer, or a crystalline silicon doped layer. The solar cell according to claim 10, characterized in that.

14. A cell string formed by connecting the solar cells according to any one of claims 1 to 13, A sealing layer for covering the surface of the cell string, A cover plate for covering the surface of the sealing layer away from the cell string, comprising. The photovoltaic module, characterized in that.

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