Display device

Abstract

To provide a display device capable of mitigating current imbalance in a configuration having power source voltage applied thereto.SOLUTION: A display device according to one embodiment disclosed herein comprises: a display area having a plurality of pixels disposed therein to display an image; a non-display area located outside the display area, the non-display area including a pad area; a power shorting bar located on one side of the display area in the non-display area; a power pad provided in the pad area; and a bottleneck portion connecting the power shorting bar to a power pad. The power shorting bar has a mesh structure consisting of a plurality of first power lines extending in a first direction connected to a plurality of second power lines extending in a second direction.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] This specification relates to a display device.

Background Art

[0002] As the information society develops, the requirements for display devices for displaying images are increasing in various forms. As a result, in recent years, various display devices such as liquid crystal display devices (LCDs), plasma display devices (PDPs), quantum dot light emitting display devices (QLEDs), and organic light emitting display devices (OLEDs) have been utilized.

[0003] A display device includes two substrates and can display an image by including a plurality of pixels between the two substrates. The pixels can be driven by receiving power supply through a power line. Since a high voltage is applied to the power line, a large amount of heat can be generated when current is biased in a predetermined region. As a result, phenomena such as damage to the power line, generation of static electricity between the power line and surrounding signal lines, and rupture can occur.

Summary of the Invention

Problems to be Solved by the Invention

[0004] This specification aims to provide a display device capable of alleviating the bias of current in a configuration to which a power supply voltage is applied as a technical problem.

[0005] In addition, this specification aims to provide a display device capable of reducing the generation of greenhouse gas that may be generated by a manufacturing process for manufacturing a display device and constituting ESG (Environment / Social / Governance) as another technical problem.

Means for Solving the Problems

[0006] A display device according to an embodiment of the present specification includes a display area in which a plurality of pixels are arranged to display an image, a non-display area arranged on the outer periphery of the display area and including a pad area, a power short bar arranged on one side of the display area in the non-display area, a power pad arranged in the pad area, and a bottleneck portion connecting the power short bar and the power pad. The power short bar has a mesh structure in which a plurality of first power lines extending in a first direction and a plurality of second power lines extending in a second direction are connected to each other.

Advantages of the Invention

[0007] In the present specification, by forming the power short bar with a mesh structure composed of a plurality of first power lines and a plurality of second power lines, and designing the widths of the plurality of first power lines and the plurality of second power lines to be different, it is possible to alleviate the current bias in the end region of the bottleneck portion.

[0008] In addition, the present specification can reduce the metal stress compared to forming the power short bar as an electrode on a flat plate (or in a thin film shape), and further prevent damage caused by the metal stress.

[0009] In addition, in the present specification, the thickness of the insulating film between the power short bar and the pixel power line can be reduced, thereby reducing the overall thickness of the display panel.

[0010] In addition, the present specification can prevent the occurrence of an electrostatic discharge phenomenon between the power short bar and the pixel power line.

[0011] In addition, the present specification can disperse the current in the end region of the drawing portion by forming a concave portion in a streamline shape or a curved shape in the drawing portion of the bottleneck portion.

[0012] In addition, this specification can reduce the manufacturing process cost, shorten the manufacturing process time, and further reduce the production energy by decreasing the defect rate of the power short bar. Also, this specification can reduce the generation of greenhouse gases that may be generated in the manufacturing process and can contribute to ESG (Environment / Social / Governance).

Brief Description of the Drawings

[0013]

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Embodiments for Carrying Out the Invention

[0014] Hereinafter, preferred embodiments of the present specification will be described in detail with reference to the accompanying drawings.

[0015] FIG. 1 is a perspective view schematically showing a display device according to an embodiment of the present specification, and FIG. 2 is a plan view schematically showing a display panel according to an embodiment of the present specification.

[0016] Hereinafter, the X-axis indicates a direction parallel to the scan line, the Y-axis indicates a direction parallel to the data line, and the Z-axis indicates the height direction of the display device 100.

[0017] The display device 100 according to an embodiment of the present specification has been mainly described as being configured by an organic light emitting display device (Organic Light Emitting Display), but may also be configured by a liquid crystal display device (Liquid Crystal Display), a plasma display device (PDP: Plasma Display Panel), a quantum dot light emitting display device (QLED: Quantum dot Light Emitting Display), or an electrophoresis display device (Electrophoresis display).

[0018] Referring to FIGS. 1 to 2, the display device 100 according to an embodiment of the present specification includes a display panel 110, a source drive integrated circuit (hereinafter referred to as "IC") 210, a flexible film 220, a circuit board 230, and a timing control unit 240.

[0019] The display panel 110 includes a first substrate 111 and a second substrate 112 facing each other. The second substrate 112 can be a sealing substrate. The first substrate 111 can be a plastic film, a glass substrate, or a silicon wafer substrate formed using semiconductor processes. The second substrate 112 can be a plastic film, a glass substrate, or a sealing film. Such first substrate 111 and second substrate 112 can be made of a transparent material.

[0020] The display panel 110 can be divided into a display area (DA) where pixels are formed to display an image and a non-display area (NDA) where no image is displayed.

[0021] The display area (DA) can include a first signal line (SL1), a second signal line (SL2), and sub-pixels, and the non-display area (NDA) can include a pad area (PA) where pads are arranged and at least one scan driving unit 205.

[0022] The first signal line (SL1) can extend in a first direction (e.g., the Y-axis direction) and intersect the second signal line (SL2) in the display area (DA). The first signal line (SL1) can include a pixel power line, a data line, and a common power line. In one embodiment, the first signal line (SL1) can further include a reference line.

[0023] The pixel power line can supply a first power voltage to the driving transistor of each sub-pixel. The common power line can supply a second power voltage to the cathode electrode of the sub-pixel. Here, the second power voltage can be a common power supply commonly supplied to the sub-pixels.

[0024] The reference line can supply an initialization voltage (or reference voltage) to each driving transistor of the sub-pixel. Each of the data lines can supply a data voltage to the sub-pixel.

[0025] The second signal line (SL2) can extend in the second direction (e.g., the X-axis direction) in the display area (DA). The second signal line (SL2) can include scan lines. The scan lines can supply scan signals to the sub-pixels.

[0026] The sub-pixels are provided in an area where the first signal line (SL1) is provided or in an area where the first signal line (SL1) and the second signal line (SL2) intersect, and emit predetermined light to display an image.

[0027] A plurality of pads can be arranged in the pad area (PA). Since the size of the first substrate 111 is larger than the size of the second substrate 112, a part of the first substrate 111 can be exposed without being covered by the second substrate 112. Pads such as power pads and data pads can be provided on a part of the first substrate 111 that is exposed without being covered by the second substrate 112.

[0028] The scan driving unit 205 is connected to the scan lines and supplies scan signals. Such a scan driving unit 205 can be formed in a GIP (gate driver in panel) manner in a non-display area (NDA) outside one or both sides of the display area (DA) of the display panel 110. Alternatively, the scan driving unit 205 can be manufactured by a driving chip, mounted on a flexible film, and attached to a non-display area (NDA) outside one or both sides of the display area (DA) of the display panel 110 in a TAB (tape automated bonding) manner.

[0029] The source drive IC 210 receives an input of digital video data and a data control signal from the timing control unit 240. The source drive IC 210 converts the digital video data into an analog data voltage according to the data control signal and supplies it to the data line. When the source drive IC 210 is manufactured by a driving chip, it can be mounted on the flexible film 220 in a COF (chip on film) or COP (chip on plastic) manner.

[0030] On the flexible film 220, wirings for connecting the pads and the source drive IC 210, and wirings for connecting the pads and the wirings of the circuit board 230 can be formed. The flexible film 220 is attached onto the pads using an anisotropic conductive film, whereby the pads and the wirings of the flexible film 220 can be connected.

[0031] The circuit board 230 can be attached to the flexible film 220. The circuit board 230 can mount a plurality of circuits configured as drive chips. For example, a timing control unit 240 can be mounted on the circuit board 230. The circuit board 230 can be a printed circuit board or a flexible printed circuit board.

[0032] The timing control unit 240 receives an input of digital video data and a timing signal from an external system board (not shown). The timing control unit 240 generates a scan control signal for controlling the operation timing of the scan drive unit based on the timing signal, and a data control signal for controlling the source drive IC 210. The timing control unit 240 supplies the scan control signal to the scan drive unit 205 and supplies the data control signal to the source drive IC 210.

[0033] FIG. 3 is a plan view showing an example of a sub-pixel provided in a display panel according to an embodiment of the present specification, FIG. 4 is a circuit diagram showing an example of the sub-pixel of FIG. 3, and FIG. 5 is a cross-sectional view showing an example of a configuration arranged in the non-transmissive region and the transmissive region of FIG. 3.

[0034] The display panel 110 according to an embodiment of the present specification may include a display area (DA) and a non-display area (NDA, Fig. 2). As shown in Fig. 3, the display area (DA) may include a first area (NTA) where a plurality of sub-pixels (SP1, SP2, SP3, SP4) are arranged and a second area (TA) where the plurality of sub-pixels (SP1, SP2, SP3, SP4) are not arranged. The first area (NTA) is a non-transmissive area that does not transmit most of the light incident from the outside, and the second area (TA) may be a transmissive area that allows most of the light incident from the outside to pass through.

[0035] As an example, the transmissive area (TA) may be an area where the light transmittance is greater than α%, and the non-transmissive area (NTA) may be an area where the light transmittance is less than β%. Here, α may be a value greater than β. Through the transmissive area (TA), the things or background arranged on the back surface of the display panel 110 can be seen.

[0036] In the non-transmissive area (NTA)1, a plurality of sub-pixels (SP1, SP2, SP3, SP4), a plurality of circuit elements, and a plurality of signal lines (SL1, SL2) are arranged, and the light incident from the outside can be prevented from passing through.

[0037] The plurality of signal lines may include a first signal line (SL1) and a second signal line (SL2). The first signal line (SL1) may extend in a first direction (e.g., the Y-axis direction) in the non-transmissive area (NTA). The first signal line (SL1) may include a pixel power supply line (VDDL), a data line (DL), and a common power supply line (VSSL). In one embodiment, the first signal line (SL1) may further include a reference line.

[0038] The pixel power line (VDDL) can supply a first power voltage to the driving transistors of the respective sub-pixels (SP1, SP2, SP3, SP4). The common power line (VSSL) can supply a second power voltage to the cathode electrodes of the sub-pixels (SP1, SP2, SP3, SP4). Here, the second power voltage can be a common power supply commonly supplied to the sub-pixels (SP1, SP2, SP3, SP4). And the common power line (VSSL) can be arranged separated from the pixel power line with the transmission region (TA) interposed therebetween.

[0039] The reference line can supply an initialization voltage (or a reference voltage) to the driving transistors of the respective sub-pixels (SP1, SP2, SP3, SP4). Each of the data lines (DL) can supply a data voltage to the sub-pixels (SP1, SP2, SP3, SP4).

[0040] The second signal line (SL2) can extend in a second direction (e.g., the X-axis direction) in the non-transmission region (NTA). The second signal line (SL2) can include a scan line (SCANL). The scan line (SCANL) can supply a scan signal to the sub-pixels (SP1, SP2, SP3, SP4).

[0041] In the non-transmission region (NTA), sub-pixels (SP1, SP2, SP3, SP4) are provided to emit predetermined light to display an image.

[0042] The sub-pixels (SP1, SP2, SP3, SP4) can be any one of the first sub-pixel (SP1) that emits red light, the second sub-pixel (SP2) that emits green light, the third sub-pixel (SP3) that emits blue light, and the fourth sub-pixel (SP4) that emits white light, but is not necessarily limited thereto. The unit pixel (P) can include at least two or more sub-pixels (SP1, SP2, SP3, SP4). As an example, the unit pixel (P) can include the first sub-pixel (SP1), the second sub-pixel (SP2), the third sub-pixel (SP3), and the fourth sub-pixel (SP4). As another example, one unit pixel (P) can include the first sub-pixel (SP1) and the second sub-pixel (SP2), and another unit pixel (P) can include the second sub-pixel (SP2) and the third sub-pixel (SP3). The arrangement order of each sub-pixel (SP1, SP2, SP3, SP4) can be variously changed.

[0043] Each of the first sub-pixel (SP1), the second sub-pixel (SP2), the third sub-pixel (SP3), and the fourth sub-pixel (SP4) can include a circuit element and a light-emitting element. Referring to FIG. 4, each sub-pixel (SP1, SP2, SP3, SP4) can have a 2T (Transistor) 1C (Capacitor) structure including two transistors (DT, ST) and one capacitor (Cst), but is not necessarily limited thereto. Each sub-pixel (SP1, SP2, SP3, SP4) can further include a compensation circuit (CC), and in such a case, can have various structures such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C.

[0044] Each of the transistors (DT, ST) of each sub-pixel (SP1, SP2, SP3, SP4) includes a gate electrode, a source electrode, and a drain electrode. Since the source electrode and the drain electrode are not fixed and can be changed according to the voltage applied to the gate electrode and the direction of the current, either one of the source electrode and the drain electrode can be represented by a first electrode, and the remaining one can be represented by a second electrode. The transistors (DT, ST) of each sub-pixel (SP1, SP2, SP3, SP4) can use at least one of a polysilicon semiconductor, an amorphous silicon semiconductor, and an oxide semiconductor. The transistors (DT, ST) can be P-type or N-type, or can use a mixture of P-type and N-type.

[0045] The light-emitting element (ED) can include an anode electrode connected to the driving transistor (DT), a cathode electrode that receives the supply of a second power supply voltage (EVSS) from a second power supply line (VSSL), and a light-emitting layer between the anode electrode and the cathode electrode. The anode electrode is an independent electrode for each light-emitting element, but the cathode electrode can be a common electrode shared by the entire light-emitting element. When a driving current is supplied from the driving transistor (DT) to the light-emitting element (ED), electrons from the cathode electrode are injected into the light-emitting layer, holes from the anode electrode are injected into the light-emitting layer, and fluorescence or phosphorescence is emitted by recombination of electrons and holes in the light-emitting layer, thereby generating light with a brightness proportional to the current value of the driving current.

[0046] In each sub-pixel (SP1, SP2, SP3, SP4), the driving transistor (DT) is connected between the anode electrode of the light-emitting element (ED) and a first power supply line (VDDL) that supplies a driving voltage (EVDD). Here, the driving voltage (EVDD) is applied to the first electrode of the driving transistor (DT).

[0047] Such a driving transistor (DT) is a transistor that drives the light-emitting element (ED), is controlled by the voltage applied to the gate electrode, and supplies current to the light-emitting element (ED). Thereby, the light-emitting element (ED) is driven.

[0048] In each sub-pixel (SP1, SP2, SP3, SP4), the switching transistor (ST) is connected between the first node (N1) of the driving transistor (DT) and the data line (DL). The switching transistor (ST) is controlled by a scan signal (Scan) supplied from the scan line (SCANL), and applies a data voltage (Vdata) supplied from the data line (DL) to the first node (N1).

[0049] In each sub-pixel (SP1, SP2, SP3, SP4), the capacitor (Cst) is connected to the first node (N1) and charges the voltage applied to the first node (N1). The capacitor (Cst) can supply the charged driving voltage to the driving transistor (DT). The capacitor (Cst) is a storage capacitor.

[0050] The compensation circuit (CC) can be provided to compensate for the threshold voltage of the driving transistor (DT) and the like. The compensation circuit (CC) can be composed of one or more transistors. The compensation circuit (CC) can include one or more transistors and capacitors, and can be configured in various ways according to the compensation method. Pixels including the compensation circuit (CC) can have various structures such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc.

[0051] Hereinafter, with reference to FIG. 5, the configuration arranged in the non-transmissive region (NTA) and the transmissive region (TA) will be described more specifically.

[0052] Referring to FIG. 5, a display panel 110 according to an embodiment of the present specification includes a first substrate 111 and a second substrate 112 facing each other, and circuit elements, light-emitting elements (ED), a sealing layer 180, a color filter (CF), and a black matrix (BM) can be arranged between the first substrate 111 and the second substrate circuit 112.

[0053] Circuit elements are arranged separately for each sub-pixel (SP1, SP2, SP3, SP4) in the non-transmissive area (NTA), and can include various signal wirings, thin film transistors, capacitors, etc. The signal wirings can include a pixel power line, a common power line, a scan line, a data line, etc., and the thin film transistors can include a switching transistor and a driving transistor (DT). The switching transistor is switched by a scan signal supplied to the scan line and can charge a capacitor with a data voltage supplied from the data line.

[0054] The driving transistor (DT) is switched by the data voltage charged in the capacitor (Cst, Figure 4), generates a data current from the power supply supplied by the pixel power line (VDDL, Figure 4), and serves to supply it to the first electrode (E1) of the sub-pixels (SP1, SP2, SP3, SP4). Such a driving transistor (DT) can include an active layer (ACT), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE).

[0055] Specifically, a light-shielding layer (LS) can be provided on the first substrate 111. The light-shielding layer (LS) is provided so as to overlap the region where the driving transistor (DT) is formed, and can serve to block external light incident on the active layer (ACT) of the driving transistor (DT). The display panel 110 having a transmissive area (TA) can be widely used in an environment exposed to the outside from indoors. Since the display panel 110 is exposed to external light for a long time, the characteristics of circuit elements such as the driving transistor (DT) can be different. The display panel 110 may have a reduced brightness and a darker screen due to changes in the characteristics of the circuit elements.

[0056] According to an embodiment of the present specification, the display panel 110 can block external light from entering the driving transistor (DT) by disposing a light shielding layer (LS) below the driving transistor (DT). According to an embodiment of the present specification, the display panel 110 can prevent the characteristics of the driving transistor (DT) from changing and enable the sub-pixel to maintain high brightness.

[0057] Such a light shielding layer (LS) can be formed of a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0058] A buffer film 120 can be provided on the light shielding layer (LS). The buffer film 120 can protect the transistor (DT) from moisture that penetrates through the first substrate 111 that is vulnerable to moisture permeation. For this purpose, the buffer film 120 can be provided in a non-transmissive region (NTA) and a transmissive region (TA). Such a buffer film 120 can be formed of an inorganic film, such as a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.

[0059] An active layer (ACT) of the driving transistor (DT) can be provided on the buffer film 120. The active layer (ACT) of the driving transistor (DT) can be formed of a silicon-based semiconductor material or an oxide-based semiconductor material.

[0060] A gate insulating film 130 can be provided on the active layer (ACT) of the driving transistor (DT). The gate insulating film 130 can be provided in the non-transmissive region (NTA) and the transmissive region (TA). The gate insulating film 130 can be formed of an inorganic film, such as a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.

[0061] On the gate insulating film 130, a gate electrode (GE), a source electrode (SE), and a drain electrode (DE) of the driving transistor (DT) can be provided. The gate electrode (GE), the source electrode (SE), and the drain electrode (DE) of the driving transistor (DT) can be formed of the same material in the same layer as shown in FIG. 5, but are not necessarily limited thereto. In other embodiments, the source electrode (SE) and the drain electrode (DE) of the driving transistor (DT) can also be formed of different materials in different layers from the gate electrode (GE). The source electrode (SE) and the drain electrode (DE) can be connected to the active layer (ACT) through the first contact hole (CH1).

[0062] The gate electrode (GE), the source electrode (SE), and the drain electrode (DE) of the driving transistor (DT) can be formed of a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0063] On the gate electrode (GE), the source electrode (SE), and the drain electrode (DE) of the driving transistor (DT), a first interlayer insulating film 140 and a second interlayer insulating film 150 can be provided. The first interlayer insulating film 140 and the second interlayer insulating film 150 may be provided only in the non-transmissive region (NTA) in order to increase the light transmittance of the transmissive region (TA), and may not be provided in the transmissive region (TA). Each of the first interlayer insulating film 140 and the second interlayer insulating film 150 can be formed of an inorganic film, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer film thereof.

[0064] On the second interlayer insulating film 150, a planarization film 160 for flattening the step due to the driving transistor (DT) can be provided. The planarization film 160 can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin. The planarization film 160 is provided in the non-transmissive region (NTA) and may not be provided in at least a part of the transmissive region (TA). The display panel 110 according to an embodiment of the present specification can improve the light transmittance of the transmissive region (TA) by not providing the planarization film 160 in the transmissive region (TA).

[0065] On the planarization film 160, a light-emitting element (ED) including a first electrode (E1), a light-emitting layer (EL), and a second electrode (E2) and a bank 165 are provided.

[0066] The first electrode (E1) is provided on the planarization film 160 and can be electrically connected to the driving transistor (DT). Specifically, the first electrode (E1) can be connected to one of the source electrode (SE) and the drain electrode (DE) of the driving transistor (DT) through a second contact hole (CH2) penetrating the first interlayer insulating film 140, the second interlayer insulating film 150, and the planarization film 160.

[0067] Such a first electrode (E1) is provided for each sub-pixel (SP1, SP2, SP3, SP4) and may not be provided in the transmissive region (TA). A bank 165 is provided between the first electrodes (E1) adjacent to each other, whereby the first electrodes (E1) adjacent to each other can be electrically insulated.

[0068] The first electrode (E1) can be formed of a highly reflective metallic material such as a laminated structure of aluminum and titanium (Ti / Al / Ti), a laminated structure of aluminum and ITO (ITO / Al / ITO), an Ag alloy, a laminated structure of an Ag alloy and ITO (ITO / Ag alloy / ITO), a MoTi alloy, and a laminated structure of a MoTi alloy and ITO (ITO / MoTi alloy / ITO). The Ag alloy can be an alloy of silver (Ag), palladium (Pd), copper (Cu), etc. The MoTi alloy can be an alloy of molybdenum (Mo) and titanium (Ti). Such a first electrode (E1) can be an anode electrode.

[0069] The bank 165 can be provided on the planarization film 160. Further, the bank 165 can be formed to cover the end of the first electrode (E1) and expose a part of the first electrode (E1). Thereby, the bank 165 can prevent the problem that current concentrates at the end of the first electrode (E1) and the light emission efficiency decreases.

[0070] The bank 165 can define the respective light-emitting regions (EA) of the sub-pixels (SP1, SP2, SP3, SP4). Each light-emitting region (EA) of the sub-pixels (SP1, SP2, SP3, SP4) indicates a region where the first electrode (E1), the light-emitting layer (EL), and the second electrode (E2) are laminated in this order, and holes from the first electrode (E1) and electrons from the second electrode (E2) are combined with each other in the light-emitting layer (EL) to emit light. In this case, the region where the bank 165 is formed becomes a non-light-emitting region (NEA) because it does not emit light, and the region where the bank 165 is not formed and the first electrode (E1) is exposed can become the light-emitting region (EA). The bank 165 can be provided in the non-transmissive region (NTA) and may not be provided in at least a part of the transmissive region (TA).

[0071] Such a bank 165 can be formed of an organic film such as an acrylic-based material, an epoxy-based material, a phenol-based material, a polyamide-based material, a polyimide-based material, etc.

[0072] The light-emitting layer (EL) can be disposed on the first electrode (E1). The light-emitting layer (EL) can include a light-emitting material layer (Emission Material Layer; EML) containing a light-emitting material. The light-emitting material can include an organic material, an inorganic material, or a hybrid material. The light-emitting layer (EL) can have a multilayer structure. For example, the light-emitting layer (EL) can further include at least one of a hole injection layer (Hole Injection Layer; HIL), a hole transport layer (Hole Transport Layer; HTL), an electron transport layer (Electron Transport Layer; ETL), and an electron injection layer (Electron Injection Layer; EIL). In this case, when a voltage is applied to the first electrode (E1) and the second electrode (E2), holes and electrons move to the light-emitting material layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the light-emitting material layer to emit light.

[0073] In one embodiment, the light-emitting layer (EL) can be a common layer formed commonly for sub-pixels (SP1, SP2, SP3, SP4). Here, the light-emitting layer (EL) can be a white light-emitting layer that emits white light. In this case, the light-emitting layer (EL) can be formed not only in the sub-pixels (SP1, SP2, SP3, SP4) but also in a non-light-emitting region (NEA) between the sub-pixels (SP1, SP2, SP3, SP4). The light-emitting layer (EL) can be formed continuously in the sub-pixels (SP1, SP2, SP3, SP4) and between the sub-pixels (SP1, SP2, SP3, SP4). Also, the light-emitting layer (EL) can be provided not only in a non-transmissive region (NTA) including a light-emitting region (EA) and a non-light-emitting region (NEA) but also in a transmissive region (TA), but is not necessarily limited thereto. The light-emitting layer (EL) can also be pattern-formed only in a non-transmissive region (NTA) including a light-emitting region (EA) and a non-light-emitting region (NEA).

[0074] In other embodiments, the light-emitting layer (EL) can form a light-emitting material layer for each sub-pixel (SP1, SP2, SP3, SP4). As an example, a green light-emitting layer that emits green light is formed in the first sub-pixel (SP1), a red light-emitting layer that emits red light is formed in the second sub-pixel (SP2), a blue light-emitting layer that emits blue light is formed in the third sub-pixel (SP3), and a white light-emitting layer that emits white light can be formed in the fourth sub-pixel (SP4). In such a case, the light-emitting material layer in the light-emitting layer (EL) may not be formed in the transmission region (TA). However, the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL) excluding the light-emitting material layer can be commonly formed in the sub-pixels (SP1, SP2, SP3, SP4) and can also be formed in the transmission region (TA).

[0075] The second electrode (E2) can be disposed on the light-emitting layer (EL). The second electrode (E2) can be a common layer commonly formed in the sub-pixels (SP1, SP2, SP3, SP4). The second electrode (E2) can be formed not only in the light-emitting region (EA) of the sub-pixels (SP1, SP2, SP3, SP4) but also in the non-light-emitting region (NEA) between the sub-pixels (SP1, SP2, SP3, SP4). The second electrode (E2) can be continuously formed between the sub-pixels (SP1, SP2, SP3, SP4) and the sub-pixels (SP1, SP2, SP3, SP4).

[0076] The second electrode (E2) can be formed of a transparent metal material (TCO, Transparent Conductive Material) such as ITO or IZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the upper electrode (E2) is formed of a semi-transmissive conductive material, the light extraction efficiency can be increased by a micro cavity. Such a second electrode (E2) can be a cathode electrode.

[0077] On the light-emitting element (ED), a sealing layer 180 can be provided. The sealing layer 180 can be formed to cover the second electrode (E2) on the second electrode (E2). The sealing layer 180 serves to prevent oxygen or moisture from penetrating into the light-emitting layer (EL) and the second electrode (E2). For this purpose, the sealing layer 180 can include at least one inorganic film and at least one organic film. The sealing layer 180 can also have a structure in which the inorganic film and the organic film are alternately laminated, but is not necessarily limited to this.

[0078] On the sealing layer 180, a color filter (CF) can be provided. The color filter (CF) can be patterned for each sub-pixel (SP1, SP2, SP3, SP4). Specifically, the color filter (CF) can include a first color filter, a second color filter, a third color filter, and a fourth color filter. The first color filter can be arranged to correspond to the first sub-pixel (SP1) and, for example, can be a red color filter that transmits red light. The second color filter can be arranged to correspond to the second sub-pixel (SP2) and can be a green color filter that transmits green light. The third color filter (CF3) can be arranged to correspond to the third sub-pixel (SP3) and can be a blue color filter that transmits blue light. The fourth color filter can be arranged to correspond to the fourth sub-pixel (SP4) and can be a white color filter that transmits white light. The white color filter can be made of a transparent organic substance that transmits white light, but is not necessarily limited to this.

[0079] A black matrix (BM) can be provided between color filters (CF) formed with patterns for each sub-pixel (SP1, SP2, SP3, SP4). The black matrix (BM) is provided between the sub-pixels (SP1, SP2, SP3, SP4) and can prevent color mixing from occurring between adjacent sub-pixels (SP1, SP2, SP3, SP4). Further, the black matrix (BM) can prevent light incident from outside from reflecting off a plurality of signal lines provided between the sub-pixels (SP1, SP2, SP3, SP4).

[0080] In addition, the black matrix (BM) is provided between the transmission region (TA) and the plurality of sub-pixels (SP1, SP2, SP3, SP4), and can prevent the light emitted by each of the plurality of sub-pixels (SP1, SP2, SP3, SP4) from traveling to the transmission region (TA). Such a black matrix (BM) can include a light-absorbing substance, for example, a black dye that absorbs all light in the wavelength band of visible light.

[0081] The first substrate 111 provided with the color filter (CF) and the black matrix (BM) can be bonded to the second substrate 112 by a separate adhesive layer 190. Here, the adhesive layer 190 can be an optically clear resin layer (OCR) or an optically clear adhesive film (OCA).

[0082] FIG. 6 is a plan view schematically showing a power short bar and a bottleneck portion according to an embodiment of the present specification, FIG. 7 is an enlarged view of region A in FIG. 6, and FIG. 8 is a cross-sectional view showing an example of a stacked structure of a power short bar and a pixel power line. FIG. 9 is a diagram showing the flow of current in a power short bar and a bottleneck portion according to an embodiment of the present specification, FIG. 10 is a diagram showing the flow of current when the first power line and the second power line have a constant width, and FIG. 11 is a diagram showing an example of the flow of current in the first power line and the second power line according to an embodiment of the present specification. FIG. 12 is a diagram showing an example of the flow of current when the drawing portion of the bottleneck portion has a constant width, and FIG. 13 is a diagram showing an example of the flow of current in the drawing portion of the bottleneck portion according to an embodiment of the present specification.

[0083] A display panel 110 according to an embodiment of the present specification can be divided into a display area (DA) where pixels are formed to display an image as shown in FIG. 6 and a non-display area (NDA) disposed on the outer periphery of the display area (DA). The non-display area (NDA) can include a pad area (PA) where power pads are disposed. The power pads can include a first power pad (PAD1) to which a first power voltage (high-potential power voltage, EVDD) is applied and a second power pad (PAD2) to which a second power voltage (low-potential power voltage, EVSS) is applied. A flexible film 220 (FIG. 1) is attached on the first power pad (PAD1) and the second power pad (PAD2), and the supply of the first power voltage (high-potential power voltage, EVDD) and the second power voltage (low-potential power voltage, EVSS) from the outside can be received.

[0084] A display panel 110 according to an embodiment of the present specification can include a power short bar 610 and a bottleneck portion 620 in the non-display area (NDA).

[0085] The power short bar 610 can be arranged on one side of the display area (DA) of the non-display area (NDA). Specifically, the power short bar 610 can be arranged on the side where the pad area (PA) is arranged among the plurality of sides of the display area (DA). The power short bar 610 can be arranged between the display area (DA) and the pad area (PA).

[0086] The power short bar 610 can be formed long in the second direction (for example, the X-axis direction) between the display area (DA) and the pad area (PA). The power short bar 610 can be connected to a plurality of common power lines (VSSL) provided in the display area (DA) and supply a second power supply voltage (low potential power supply voltage, EVSS) to the plurality of common power lines (VSSL).

[0087] The plurality of common power lines (VSSL) can extend in the first direction (for example, the Y-axis direction) in the display area (DA). Each of the plurality of common power lines (VSSL) is arranged in the non-transmissive area (NTA, FIG. 3) and can be separated from each other. The plurality of common power lines (VSSL) can extend from the display area (DA) to the non-display area (NDA) and be connected to the power short bar 610 at one end. The plurality of common power lines (VSSL) can be formed on the same layer as the power short bar 610, but is not necessarily limited thereto. The plurality of common power lines (VSSL) can also be provided on a layer different from the power short bar 610. In such a case, they can be connected to the power short bar 610 through contact holes at one end.

[0088] The plurality of common power lines (VSSL) can be connected to a plurality of light-emitting elements (ED) in the display area (DA). The plurality of common power lines (VSSL) can supply the second power supply voltage (low potential power supply voltage, EVSS) supplied from the power short bar 610 to the cathode electrodes (E2) of the plurality of light-emitting elements (ED).

[0089] The bottleneck portion 620 is disposed between the power short bar 610 and the second power pad (PAD2), and connects the power shot bar 610 and the second power pad (PAD2). The bottleneck portion 620 can be in contact with the power short bar 610 on one side and the second power pad (PAD2) on the other side. The power short bar 610, the bottleneck portion 620, and the second power pad (PAD2) can be formed of the same material on the same layer. That is, the power short bar 610, the bottleneck portion 620, and the second power pad (PAD2) can be integrally formed.

[0090] The bottleneck portion 620 is formed to have a first width (W1) smaller than that of the power short bar 610, and a plurality of them can be arranged. Here, the first width (W1) can represent the length of the side in contact with the power short bar 610. The first width (W1) can be the width in the second direction (for example, the X-axis direction). The plurality of bottleneck portions 620 can be arranged at intervals from each other. Each of the plurality of bottleneck portions 620 is connected to each of the plurality of second power pads (PAD2), and can receive a second power voltage (low-potential power supply voltage, EVSS) from the outside through the plurality of second power pads (PAD2). The second power voltage (low-potential power supply voltage, EVSS) is applied to the power short bar 610 through the plurality of bottleneck portions 620, and can be applied to the plurality of common power lines (VSSL) in the display area (DA) through the power short bar 610.

[0091] In this way, when the second power voltage (low-potential power supply voltage, EVSS) is transmitted to the power short bar 610 and the bottleneck portion 620, current can flow from the power short bar 610 into the bottleneck portion 620. Here, since the bottleneck portion 620 has a first width (W1) smaller than that of the power short bar 610, current can gather in a part of the bottleneck portion 620. The bottleneck portion 620 can be damaged by generating a large amount of heat in the region where the current gathers.

[0092] According to an embodiment of the present specification, the display panel 110 can alleviate the phenomenon that current gathers in the bottleneck portion 620 by forming the power short bar 610 in a mesh structure.

[0093] Specifically, as shown in FIG. 7, the power short bar 610 can have a mesh structure in which a plurality of first power lines 612 extending in the first direction (for example, the Y-axis direction) and a plurality of second power lines 614 extending in the second direction (for example, the X-axis direction) are connected to each other. The plurality of first power lines 612 and the plurality of second power lines 614 can be integrally formed in the same layer. The plurality of first power lines 612 and the plurality of second power lines 614 can be provided with the same material in the same layer as the gate electrode (GE, FIG. 5) of the driving transistor (DT, FIG. 5).

[0094] The plurality of first power lines 612 can extend in the first direction (for example, the Y-axis direction) between the pad region (PA) and the display region (DA) and be arranged spaced apart from each other in the second direction (for example, the X-axis direction). Some of the plurality of first power lines 612 may be in contact with the bottleneck portion 620, and some other parts may not be in contact with the bottleneck portion 620. The plurality of first power lines 612 can include a first group (G1) that is in contact with the bottleneck portion 620 at one end and a second group (G2) that is not in contact with the bottleneck portion 620 at one end. The first power lines 612 included in the second group (G2) can be arranged spaced apart from the bottleneck portion 620.

[0095] The first power line 612 included in the second group (G2) can have a width different from at least one width of the first power line 612 included in the first group (G1). The first power line 612 included in the second group (G2) can have a width smaller than at least one width of the first power line 612 included in the first group (G1). At least one of the first power lines 612 included in the first group (G1) can have a second width. Among the first power lines 612 included in the first group (G1), the first power line 612 disposed in a region excluding the end region can have a second width. The first power line 612 included in the second group (G2) can have a third width smaller than the second width. That is, among the plurality of first power lines 612, the first power line 612 not in contact with the bottleneck portion 620 can be formed relatively thin. On the other hand, among the plurality of first power lines 612, most of the first power lines 612 in contact with the bottleneck portion 620 can be formed relatively thick.

[0096] Since the resistance is inversely proportional to the cross-sectional area, the resistance of the first power line 612 can be small when the cross-sectional area is large, and the resistance can be large when the cross-sectional area is small. Among the plurality of first power lines 612, most of the first power lines 612 in contact with the bottleneck portion 620 have a relatively large second width, so that a large cross-sectional area can be formed and the resistance can be small. Since the current is inversely proportional to the resistance, a relatively large amount of current can flow through the first power line 612 included in the first group (G1) as shown in FIG. 9.

[0097] On the other hand, among the plurality of first power lines 612, the first power line 612 not in contact with the bottleneck portion 620 has a small third width, so that a small cross-sectional area can be formed and the resistance can be large. As a result, a relatively small amount of current can flow through the first power line 612 included in the second group (G2) as compared with the first power line 612 included in the first group (G1) as shown in FIG. 9.

[0098] On one hand, at least a part of the first power line 612 included in the first group (G1) can have a width different from that of another part. Specifically, the first power line 612 included in the first group (G1) can include a first subgroup (G11) provided in the first region, a second subgroup (G12) provided in a second region arranged on one side of the first region, and a third subgroup (G13) provided in a third region arranged on the other side of the first region.

[0099] The second subgroup (G12) can include the first power line 612 arranged at the left outermost contour among the first power lines 612 included in the first group (G1). The second subgroup (G12) can include only one of the first power lines 612 arranged at the left outermost contour among the first power lines 612 included in the first group (G1), but is not necessarily limited thereto. The second subgroup (G12) can also include a plurality of first power lines 612 provided in the left end region among the first power lines 612 included in the first group (G1).

[0100] The third subgroup (G13) can include the first power line 612 arranged at the right outermost contour among the first power lines 612 included in the first group (G1). The third subgroup (G13) can include only one of the first power lines 612 arranged at the right outermost contour among the first power lines 612 included in the first group (G1), but is not necessarily limited thereto. The third subgroup (G13) can also include a plurality of first power lines 612 provided in the right end region among the first power lines 612 included in the first group (G1).

[0101] The first power line 612 included in the first subgroup (G11) can have a width different from the widths of the first power lines 612 included in the second subgroup (G12) and the third subgroup (G13). The first power lines 612 included in the second subgroup (G12) and the third subgroup (G13) can have a width smaller than the first power line 612 included in the first subgroup (G11).

[0102] The first power line 612 included in the first subgroup (G11) can have a second width. The first power lines 612 included in the second subgroup (G12) and the third subgroup (G13) can have a fourth width smaller than the second width. In one embodiment, the first power lines 612 included in the second subgroup (G12) and the third subgroup (G13) can have the same width as the first power lines 612 included in the second group (G2). That is, the fourth width of the first power lines 612 included in the second subgroup (G12) and the third subgroup (G13) can be the same as the third width of the first power lines 612 included in the second group (G2).

[0103] The plurality of second power lines 614 extend in a second direction (e.g., the X-axis direction) between the pad region (PA) and the display region (DA), and can be arranged spaced apart from each other in a first direction (e.g., the Y-axis direction). Among the plurality of second power lines 614, the uppermost second power line 614 may have some regions in contact with the bottleneck portion 620 and some other regions not in contact with the bottleneck portion 620.

[0104] The plurality of second power lines 614 can have widths that are different in some parts from other parts. The second power line 614 having a first separation distance from the bottleneck portion 620 can have a width different from the width of the second power line 614 having a second separation distance from the bottleneck portion 620. The first separation distance may be smaller than the second separation distance. In such a case, the second power line 614 having a first separation distance from the bottleneck portion 620 can have a fifth width. The second power line 614 having a second separation distance from the bottleneck portion 620 can have a sixth width (W5) larger than the fifth width. That is, the second power line 614 disposed closer to the bottleneck portion 620 can be formed thinner than the second power line 614 disposed farther from the bottleneck portion 620.

[0105] Since the second power line 614 disposed close to the bottleneck portion 620 has a fifth width, it can be formed with a small cross-sectional area and have a large resistance. As a result, a relatively small amount of current can flow through the second power line 614 disposed close to the bottleneck portion 620, as shown in FIG. 9.

[0106] On the other hand, since the second power line 614 disposed far from the bottleneck portion 620 has a relatively large sixth width, it can be formed with a large cross-sectional area and have a small resistance. Since current is inversely proportional to resistance, a relatively larger amount of current can flow through the second power line 614 disposed far from the bottleneck portion 620 than through the second power line 614 disposed close to the bottleneck portion 620, as shown in FIG. 9.

[0107] In one embodiment, as shown in FIG. 7, the plurality of second power lines 614 can gradually increase in width as they move away from the bottleneck portion 620. In such a case, the amount of current flowing through the plurality of second power lines 614 can gradually increase as they move away from the bottleneck portion 620.

[0108] According to an embodiment of the present specification, the display panel 110 forms the power short bar 610 in a mesh structure composed of a plurality of first power lines 612 and a plurality of second power lines 614, and the widths of the plurality of first power lines 612 and the plurality of second power lines 614 can be designed with differences.

[0109] According to an embodiment of the present specification, the widths of the plurality of first power lines 612 of the display panel 110 can be designed with differences. Specifically, according to an embodiment of the present specification, the display panel 110 forms the first power lines 612 that do not contact the bottleneck portion 620 among the plurality of first power lines 612 thinner, so that a relatively small amount of current can flow through the first power lines 612 that do not contact the bottleneck portion 620.

[0110] In addition, according to an embodiment of the present specification, the display panel 110 can form the outermost first power line 612 among the first power lines 612 in contact with the bottleneck portion 620 thinner. The current flowing through the first power lines 612 that do not contact the bottleneck portion 620 can flow into the first power lines 612 in contact with the bottleneck portion 620 through the second power lines 614. Here, when all the first power lines 612 in contact with the bottleneck portion 620 have the same thickness, as shown in FIG. 10, the current can gather in the outermost first power line 612 having the shortest distance.

[0111] According to an embodiment of the present specification, the display panel 110 can prevent the current from concentrating on the outermost first power line 612 by forming the outermost first power line 612 among the first power lines 612 in contact with the bottleneck portion 620 relatively thinner. According to an embodiment of the present specification, the display panel 110 can form the first power line 612 disposed in the central region among the first power lines 612 in contact with the bottleneck portion 620 relatively thicker, so as to guide the current to flow through the first power line 612 disposed in the central region.

[0112] In addition, the display panel 110 according to an embodiment of the present specification can design the widths of a plurality of second power lines 614 with different lengths. Specifically, in the display panel 110 according to an embodiment of the present specification, among the plurality of second power lines 614, the second power line 614 disposed near the bottleneck portion 620 can be formed thinner, and the second power line 614 disposed far from the bottleneck portion 620 can be formed thicker. Thereby, the display panel 110 according to an embodiment of the present specification can induce a relatively small amount of current to flow through the second power line 614 disposed near the bottleneck portion 620, and can induce a relatively large amount of current to flow through the second power line 614 disposed far from the bottleneck portion 620.

[0113] By designing the widths of the plurality of first power lines 612 and the plurality of second power lines 614 with different lengths as described above, the display panel 110 according to an embodiment of the present specification can disperse the current flowing into the bottleneck portion 620 from the plurality of first power lines 612 and the plurality of second power lines 614 as shown in FIG. 11.

[0114] Current has the characteristic of flowing to the place with the shortest distance at the same resistance. Therefore, when the widths of the plurality of first power lines 612 and the plurality of second power lines 614 are designed to be constant, as shown in FIG. 10, the current flowing through the power lines 612 and 614 that do not contact the bottleneck portion 620 can flow into the end region of the bottleneck portion 620 at the shortest distance. Thereby, a phenomenon in which current accumulates in the end region of the bottleneck portion 620 can occur.

[0115] In contrast, in the display panel 110 according to an embodiment of the present specification, by designing the widths of the plurality of first power lines 612 and the plurality of second power lines 614 to be different, the plurality of first power lines 612 and the plurality of second power lines 614 can have different resistances from each other. In the display panel 110 according to an embodiment of the present specification, the first power line 612 in contact with the central region of the bottleneck portion 620 and the second power line 614 disposed far from the bottleneck portion 620 have small resistances, so that, as shown in FIG. 11, among the currents flowing from the common power line (VSSL) to the power short bar 610, a relatively large amount of current can be induced to flow dispersedly into the central region of the bottleneck portion 620. Thereby, the display panel 110 according to an embodiment of the present specification can alleviate the occurrence of the phenomenon that current accumulates in the end region of the bottleneck portion 620.

[0116] On the one hand, according to an embodiment of the present specification, the display panel 110 can reduce metal stress by forming the power short bar 610 in a mesh structure, as compared with forming the power shot bar 610 as an electrode on a flat plate (or in a thin film shape). The power short bar 610 can overlap with the pixel power line (VDDL) in at least a part of the region. The pixel power line (VDDL) can extend from the display area (DA) to the pad area (PA) in the non-display area (NDA) and be connected to the first power pad (PAD1). The pixel power line (VDDL) can supply the first power voltage (high potential power voltage, EVDD) supplied from the first power pad (PAD1) to the anode electrode (E1) of a plurality of light emitting elements (ED) arranged in the display area (DA). Such a pixel power line (VDDL) can overlap with the power short bar 610 in at least a part of the region. Here, the pixel power line (VDDL) and the power short bar 610 can have a stacked structure as shown in FIG. 8. The power short bar 610 can be provided with the same material in the same layer as the gate electrode (GE, FIG. 5) of the driving transistor (DT, FIG. 5). And the pixel power line (VDDL) can be provided with the same material in the same layer as the light shielding layer (LS, FIG. 5). In such a case, a gate insulating film 130 and a buffer film 120 are provided between the power short bar 610 and the pixel power line (VDDL) to insulate the power shot bar 610 and the pixel power line (VDDL).

[0117] When the power short bar 610 is formed as an electrode on a flat plate (or in a thin film shape), the metal stress caused by the power short bar 610 increases. As a result, there is a limit to reducing the thickness of the insulating film between the power short bar 610 and the pixel power line (VDDL). If the thickness of the insulating film between the power short bar 610 and the pixel power line (VDDL) is formed thin, the power short bar 610 and the pixel power line (VDDL), as well as the surrounding insulating film, can be damaged due to metal stress. The display panel 110 according to an embodiment of the present specification can reduce the metal stress caused by the power short bar 610 and further prevent damage caused by the metal stress by forming the power short bar 610 in a mesh structure. Also, the display panel 110 according to an embodiment of the present specification can reduce the thickness of the insulating film between the power short bar 610 and the pixel power line (VDDL), thereby reducing the overall thickness of the display panel 110.

[0118] Also, in the display panel 110 according to an embodiment of the present specification, since the power short bar 610 has a mesh structure, the area where the power short bar 610 and the pixel power line (VDDL) overlap can be reduced. Thereby, it is possible to prevent the phenomenon that static electricity jumps between the power short bar 610 and the pixel power line (VDDL).

[0119] The bottleneck portion 620 is disposed between the power short bar 610 and the second power pad (PAD2) and connects the power short bar 610 and the second power pad (PAD2). The bottleneck portion 620 can be in contact with the power short bar 610 on one side and in contact with the second power pad (PAD2) on the other side. The bottleneck portions 620 can be arranged at intervals in the second direction (for example, the X-axis direction).

[0120] Each bottleneck portion 620 includes a drawing-in portion 622 in contact with the power short bar 610 through which current flows in, and a connection portion 624 connecting the second power pad (PAD2) to the drawing-in portion 622.

[0121] The lead-in part 622 can be in contact with the power short bar 610 on one side. The lead-in part 622 is in contact with a part of the plurality of first power lines 612, and current can flow in from the first power line 612 in contact. Also, the lead-in part 622 is in contact with a partial area of the uppermost second power line 614 among the plurality of second power lines 614, and current can flow in from the uppermost second power line 614 in contact.

[0122] Such a lead-in part 622 can be provided with a recess 623 formed in a concave shape so as to face the center line (CL) on at least one side. The lead-in part 622 can be provided with a recess 623 on at least one side provided between the side in contact with the power short bar 610 and the side in contact with the connection part 624.

[0123] As an example, the lead-in part 622 can be provided with a first recess 623a formed in a concave shape so as to face the center line (CL) at the left end, and a second recess 623b formed in a concave shape so as to face the center line (CL) at the right end. The first recess 623a and the second recess 623b can be formed in a round streamline shape or a curve shape. As an example, the first recess 623a and the second recess 623b can have a semi-circular shape.

[0124] The lead-in part 622 can include a first region (A1) whose width decreases as it goes from the side in contact with the power short bar 610 toward the second power pad (PAD2) due to the recess 623 being formed on at least one side. In one embodiment, the lead-in part 622 can further include a second region (A2) whose width widens as it goes from the first region (A1) toward the second power pad (PAD2).

[0125] According to an embodiment of the present specification, the display panel 110 includes a first region (A1) where the width of the drawing-in portion 622 is not constant and decreases toward the second power pad (PAD2) side in contact with the power short bar 610, so that the current flowing into the end region of the drawing-in portion 622 can be dispersed. Specifically, the drawing-in portion 622 of the bottleneck portion 620 can have a constant width as shown in FIG. 12. That is, the drawing-in portion 622 of the bottleneck portion 620 and the power short bar 610 can be in perpendicular contact. In such a case, the drawing-in portion 622 of the bottleneck portion 620 and the second power line 614 of the power short bar 610 can form a right angle. In such a case, the current flowing into the drawing-in portion 622 can gather at the end of the drawing-in portion 622.

[0126] For example, the current flowing in through the first power line 612a that does not contact the drawing-in portion 622 of the bottleneck portion 620 can flow along a path having the shortest distance to the second power pad (PAD2). Then, the current flowing in through the first power line 612a that does not contact the drawing-in portion 622 of the bottleneck portion 620 can flow to the connection portion 624 along the end of the drawing-in portion 622 or the recess 623.

[0127] In addition, among the first power lines 612 in contact with the drawing-in portion 622 of the bottleneck portion 620, the current flowing in through at least one of the first power lines 612b and 612c arranged in the end region can flow in a direction that is collinear with the first power lines 612b and 612c. However, since the drawing-in portion 622 is perpendicular to the power short bar 610, after the current flowing in through the first power lines 612b and 612c flows to the end on the side where the drawing-in portion 622 and the power short bar 610 are in contact, the first path that flows along the end of the drawing-in portion 622 can be at the same distance as the second path that flows in a direction collinear with the first power lines 612b and 612c. Thus, a part of the current flowing through at least one of the first power lines 612b and 612c arranged in the end region among the first power lines 612 in contact with the drawing-in portion 622 of the bottleneck portion 620 can flow along the second path, and the remaining part can flow along the first path as shown in FIG. 12. As a result, more current can gather at the end of the drawing-in portion 622 rather than in the central region, particularly at the end on the side where the drawing-in portion 622 and the power short bar 610 are in contact, thereby increasing the temperature and potentially damaging the drawing-in portion 622.

[0128] On the other hand, the display panel 110 according to an embodiment of the present specification can disperse the current in the end region of the drawing-in portion 622 by forming a recess 623 in a streamline form or a curved form in the drawing-in portion 622 of the bottleneck portion 620.

[0129] For example, the current flowing in through the first power line 612a that does not contact the drawing-in part 622 of the bottleneck part 620 flows along a path having the shortest distance to the second power pad (PAD2), and thus can flow to the connection part 624 along the end of the drawing-in part 622. However, the drawing-in part 622 according to an embodiment of the present specification has a concave part 623 of a curve. As a result, after the current flowing in through the first power lines 612b and 612c flows to the end on the side where the drawing-in part 622 contacts the power short bar 610, the first path flowing along the end of the drawing-in part 622 becomes larger than the second path flowing in a direction collinear with the first power lines 612b and 612c. Thereby, among the first power lines 612 in contact with the drawing-in part 622 of the bottleneck part 620, the current flowing in through at least one of the first power lines 612b and 612c arranged in the end region flows not through the first path but through the second path. As a result, the current can be dispersed without concentrating on the end on the side where the drawing-in part 622 contacts the power short bar 610.

Claims

1. A display area in which a plurality of pixels are arranged to display an image, A non-display area disposed on the outer periphery of the display area and including a pad area, A power short bar disposed on one side of the display area in the non-display area, A power pad disposed in the pad area, A bottleneck portion connecting the power short bar and the power pad, The display device, wherein the power short bar has a mesh structure in which a plurality of first power lines extending in a first direction and a plurality of second power lines extending in a second direction are connected to each other.

2. The display device according to claim 1, wherein the plurality of second power lines have different widths from each other.

3. The display device according to claim 2, wherein a second power line having a first separation distance from the bottleneck portion has a width smaller than the width of a second power line having a second separation distance from the bottleneck portion, and the first separation distance is smaller than the second separation distance.

4. The display device according to claim 2, wherein the plurality of second power lines increase in width as they are farther from the bottleneck portion.

5. The display device according to claim 1, wherein the bottleneck portion is in contact with a part of the plurality of first power lines and not in contact with the remaining part.

6. The plurality of first power lines include a first group in contact with the bottleneck portion at one end and a second group not in contact with the bottleneck portion at one end, The display device according to claim 1, wherein the first power lines included in the second group have a width different from the width of at least one of the first power lines included in the first group.

7. The display device according to claim 6, wherein the first power lines included in the second group have a width smaller than the width of at least one of the first power lines included in the first group.

8. The first power lines included in the first group include a first subgroup provided in a first area, a second subgroup provided in a second area disposed on one side of the first area, and a third subgroup provided in a third area disposed on the other side of the first area, The display device according to claim 6, wherein the first power lines included in the first subgroup have a width different from the widths of the first power lines included in the second subgroup and the third subgroup.

9. The second subgroup includes a first power line disposed at the left outermost periphery among the first power lines included in the first group, and the third subgroup includes a first power line disposed at the right outermost periphery among the first power lines included in the first group. The display device according to claim 8.

10. The first power line included in the first subgroup has a width greater than the width of the first power lines included in the second subgroup and the third subgroup. The display device according to claim 8.

11. The first power lines included in the second subgroup and the third subgroup have the same width as the first power lines included in the second group. The display device according to claim 8.

12. The bottleneck portion includes a drawing-in portion in contact with the power short bar and into which current flows. The display device according to claim 1.

13. The drawing-in portion is in contact with a part of the plurality of first power lines, and current flows into the drawing-in portion from the contacted first power line. The display device according to claim 12.

14. The drawing-in portion is in contact with a region of a part of the uppermost second power line among the plurality of second power lines, and current flows into the drawing-in portion from the contacted uppermost second power line. The display device according to claim 12.

15. The drawing-in portion includes a region where the width decreases as it goes in the direction of the power pad from the side in contact with the power short bar. The display device according to claim 12.

16. The drawing-in portion includes a recess formed in a concave shape so as to face the center line on at least one side. The display device according to claim 12.

17. The recess has a curve. The display device according to claim 16.

18. The display device according to claim 1 further includes a plurality of common power lines extending in the first direction from the display area to the non-display area, and one end of each of the plurality of common power lines is connected to the power short bar.

19. The display area includes a transmissive area through which external light passes and a non-transmissive area provided between adjacent transmissive areas. Each of the plurality of common power lines is disposed in the non-transmissive area. The display device according to claim 18.

20. The display device further includes a light-emitting element provided in the non-transmissive area and including an anode electrode, a light-emitting layer, and a cathode electrode. The common power line supplies a power voltage to the cathode electrode of the light-emitting element. The display device according to claim 19.

21. The display device according to claim 18, wherein each of the plurality of common power lines is connected to each of the plurality of first power lines of the power short bar.

22. The plurality of common power lines are provided in a layer different from the plurality of first power lines of the power short bar, The display device according to claim 21, wherein each of the plurality of common power lines is connected to each of the plurality of first power lines of the power short bar through contact holes.

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