Electronic circuit adapted for charging or reading floating-gate memory structure

Abstract

To provide an electronic circuit adapted to charge or read a floating-gate memory structure forming part of the electronic circuit.SOLUTION: Provided is an electronic circuit arranged to read and charge a floating-gate memory structure. The floating-gate memory structure includes: from a first input terminal (T) a first MOS type transistor (1) with a large floating gate (FG); and from a second input terminal (B) a second MOS type transistor (2) with a smaller floating gate (FG) than the first MOS transistor (1). The first MOS transistor (1) is connected in series via its floating gate (FG) to the floating gate (FG) of the second MOS transistor (2). The first MOS transistor operates directly as a read transistor of the floating-gate memory structure.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an electronic circuit adapted to charge or read a floating gate memory structure forming part of an electronic circuit.

Background Art

[0002] As schematically shown in FIG. 1, an electronic circuit includes at least one memory structure of the electrically erasable (EE) type. The memory structure may include at least one floating gate MOS transistor FG for defining a capacitor. However, the floating gate memory structure may instead be composed of a first MOS transistor 1 having a coupling capacitance Cc and a second MOS transistor 2 having a coupling capacitance Ct. Each MOS transistor is made on the same semiconductor substrate and can be of P-type or N-type. Generally, the two transistors 1 and 2 are made on the same P-type semiconductor substrate so as to define a PMOS transistor together with all other elements of the integrated electronic circuit. The two floating gate PMOS transistors 1 and 2 are connected in series with each other by a common floating gate FG.

[0003] In the memory structure of the electronic circuit shown in this Figure 1, a floating gate shown as FG is charged by the tunneling effect due to the coupling of a programming voltage applied to the first input terminal T of the first PMOS transistor 1 or the second input terminal B of the second PMOS transistor 2. Generally, the tunneling effect charging is applied via the second input terminal B of the second PMOS transistor 2 which is smaller than the first PMOS transistor 1. Therefore, the voltage programmed on the floating gate FG is then read by a PMOS read transistor (T_read) 3 whose gate is connected to the floating gate FG. The overall structure shown in Figure 1 in an asymmetric mode uses PMOS type transistors 1 and 2 to implement the first and second capacitors 1 and 2 having capacitances Cc and Ct. This structure is generally implemented in a differential mode. To maximize the coupling between the first terminal T and the floating gate FG, the PMOS read (read) transistor 3 (having parasitic capacitance) and the second PMOS tunneling effect transistor 2 having capacitance Ct are made as small as possible compared to the first PMOS coupling Cc transistor 1. As a result, if the size of the set of Cc - Ct - T_read is constant, the read offset which is the offset between the threshold voltage and the measured current is inversely proportional to the size of the PMOS read transistor. Since the stored voltage decreases over time, this large offset limits the memory retention time and adds statistical uncertainty to the stored voltage. This is a drawback of such a memory structure.

Summary of the Invention

[0004] For this purpose, the present invention relates to an electronic circuit having a floating gate memory structure by configuring, as described in independent claim 1, one of a plurality of MOS type transistors having coupling capacitances to be provided with a large floating gate in the form of a MOS type read transistor so as to avoid the use of other specific read transistors.

[0005] Specific embodiments of the electronic circuit having a floating gate memory structure are defined in dependent claims 2 to 13.

[0006] An advantage of the present invention is that the MOS transistor is configured to implement a large-capacity capacitor by the coupling capacitance of the floating gate memory structure. In this case, by using a plurality of protection transistors, it becomes easy to interconnect the MOS transistors in the read mode. This is because the parasitic capacitive charges of these protection transistors do not affect the coupling of the input terminal of the memory structure in the floating gate itself. Since the size of the MOS read transistor has increased (to implement a capacitor having a coupling capacitance Cc), the read offset is significantly reduced. Furthermore, by removing the small read transistors of the prior art, the capacitive coupling substantially increases according to a predetermined capacitance ratio of the two transistors implementing the two capacitors.

[0007] One advantage of the present invention is that the offset problem when reading an electrically erasable permanent memory structure in a single polysilicon substrate technology can be reduced.

Brief Description of the Drawings

[0008] The purpose, advantages and features of the electronic circuit adapted to charge or read the floating gate memory structure forming part of the electronic circuit will become apparent in the non-limiting description with reference to the following drawings.

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Embodiments for Carrying Out the Invention

[0010] In the electronic circuit having the floating - gate memory structure of the present invention, it is allowed to have an improved coupling for reading or charging the floating - gate memory structure. Further, during the operation of the circuit, it is observed that the offset problem when reading such a memory structure is reduced.

[0011] FIG. 2 mainly schematically shows a floating - gate memory structure of a simplified electronic circuit as compared with the prior art shown in FIG. 1 described herein. A first MOS transistor 1 having a large coupling capacitance Cc implements a first capacitor. In this way, protection transistors (not shown) are also used to facilitate the interconnection of this transistor in the read mode. This is because the parasitic capacitive charges of these protection transistors do not affect the coupling of the first input terminal T or the second input terminal B at the floating gate FG at all.

[0012] An electronic circuit having a floating gate memory structure is preferably integrated on a P-type silicon substrate. Thus, the first transistor 1 is a PMOS readout transistor for implementing a first capacitor. The source terminal and the substrate terminal of this first PMOS transistor 1 are connected to a first input terminal T, and the drain terminal is connected to a MOS-type readout transistor having a floating gate FG programmed to a predetermined voltage in advance for reading information. The programming of the floating gate FG is mainly performed via a second PMOS transistor 2 having a coupling capacitance Ct. The predetermined voltage can be programmed via the second PMOS transistor 2 with a small Ct by a programming voltage of up to approximately 8V or more. This programming is performed by the tunneling effect of the floating gate FG or by using the hot electron injection effect. In this case, instead of charging the common floating gate FG for the two PMOS transistors 1 and 2 implementing the two capacitors Cc and Ct, programming by the tunneling effect through at least one insulating layer is used.

[0013] Since the first PMOS readout transistor 1 is large, the readout offset is significantly reduced. The second small PMOS transistor 2 having a coupling capacitance Ct is connected to the floating gate FG of the first PMOS transistor 1 having a large coupling capacitance Cc within the same integrated circuit. The second PMOS transistor 2 is made such that its source and substrate are connected to a second input terminal B while its drain remains unconnected. Further, by eliminating the prior art conventional readout transistor, a differential readout pair is formed, so that the coupling at a given capacitance ratio Cc / Ct can be substantially increased.

[0014] That is, the first PMOS transistor 1 of the memory structure is directly a transistor for reading the charge state of the floating gate of the memory structure in order to avoid using the original read transistor shown in FIG. 1 having associated parasitic capacitance. Thereby, the coupling coefficient of the programming voltage (Vprog) is increased, and thus the value of the programming voltage (Vprog) required to obtain a given floating gate voltage (FG) is reduced.

[0015] For reference, several values can be given for the sizes of the PMOS transistors 1 and 2 used to implement two capacitors, and the different battery voltages Vbat, power supply voltages Vdd, and programming voltages Vprog of the floating gate memory structure FG. The first PMOS transistor 1 can be made, for example, over a width w equal to 2.24 μm and over a length l equal to 1.75 μm, in which case the surface area of the floating gate is 3.92 μm 2 to 2 a range approaching 4 μm. On the other hand, the second PMOS transistor 1 can be made, for example, over a width w equal to 0.65 μm and over a length l equal to 0.5 μm, in which case the surface area of the floating gate is 0.325 μm 2It falls within the range. Therefore, the surface ratio between the two PMOS transistors 1 and 2 implementing the two integrated capacitors Cc and Ct of the electronic circuit exceeds 10 times and, in this case, exceeds 12 times. This indicates a large dimensional difference between the first PMOS transistor and the second PMOS transistor. The supply voltage Vdd of the integrated electronic circuit equipped with all these components required to perform reading and charging on the floating gate memory structure forming part of the electronic circuit may be defined to be in the range of 1.2V, while the battery voltage Vbat used to bias some of the transistors connected to the first and second input terminals T and B of the memory structure may be defined to be in the range of 3.6V. The programming voltage Vprog of the memory structure, specifically the programming voltage Vprog via the second input terminal B by the second PMOS transistor 2, may be in the range of 7.4V or up to approximately 9V during a programming time of up to 100 ms per pulse during the programming phase. Of course, once programming is performed on the floating gate FG of the memory structure, the programming voltage terminal Vprog may remain floating. The battery voltage may be lowered to the same 1.2V as the supply voltage Vdd. In some cases, when the floating gate FG is charged, during the read phase of the floating gate voltage FG, the supply voltage Vdd may even temporarily reach the ground level Vss.

[0016] Also to be noted is that generally, when the programmed floating gate voltage becomes low enough (typically in the range of 1 mV), the tunnel effect current of the thin oxide becomes comparable to the tunnel effect current of the thick oxide at 1 V. When the read operation is performed quickly (by compensating by exposing the gate to VT for a very short read time, or similarly to -VT), the thin oxide device can be used for long-term retention purposes. At this time, a self-zeroing differential sense amplifier is required to correctly detect the very small voltage difference of the binary cell. The advantage is that the structure can be sufficiently programmed with a typical programming voltage of 5 V.

[0017] Figure 2 also shows, at the output of the PMOS read transistor 1, an NMOS transistor 3 having the power supply potential Vbat at the gate, and another NMOS transistor 4 connected to the first input terminal T of the new read transistor 1. These two transistors 3 and 4 may also be N DEMOS ("drain extended MOS") type transistors. Thanks to these DEMOS transistors, it becomes possible to protect the latch described in Figure 4 below and to access the power supply voltage Vdd from the programming voltage Vprog that can become high during the programming phase. To implement a cascode transistor, a special DEMOS transistor whose drain is surrounded by a well overlap of 0.3 μm Nwell is used. This increases the reverse breakdown and avoids the corresponding unwanted breakdown current from flowing to Vss, allowing a voltage Vprog of up to +9 V.

[0018] Figure 3 shows a first embodiment of an electronic circuit for reading or charging a floating gate memory structure forming part of the electronic circuit. The memory structure described with reference to Figure 2 is here clearly shown in relation to transistors cascode-connected from input terminals T and B. The two PMOS transistors 1 and 2 of the memory structure are shown in series between the two input terminals T and B. A first large PMOS transistor 1 having a coupling capacitance Cc and a second PMOS transistor 2 having a coupling capacitance Ct are connected via a common floating gate FG.

[0019] Generally, when using an integrated electronic circuit having a floating gate memory structure FG, first, there is a phase of memory structure programming, and after this memory structure programming, there are one or more successive read phases with a time shift of the read state of the floating gate memory structure FG in response to a request. In each read phase when the memory structure is programmed, the first large PMOS transistor 1 can function as a transistor for reading the charge stored in the floating gate. In this regard, the read unit 30 is connected to the drain of the PMOS transistor to determine the charge state of the floating gate memory structure. For the sake of simplicity, a complementary NMOS-type transistor 3' is shown such that its drain is connected to the drain of the first PMOS-type transistor 1. The first PMOS-type transistor 1 implements the first capacitor Cc in the charge read phase of the floating gate FG in the read unit 30. The transistor 3' may be of the same type as the DEMOS transistor 3 in Figure 2.

[0020] The electronic circuit shown in FIG. 3 will now be described together with all the transistors necessary for its operation, whether for programming the memory structure or for reading or charging the floating gate memory structure. As shown above, it is preferable to use a pair of transistors connected in cascode from the input terminals T and B of the floating gate capacitor FG. First, to program the floating gate FG, two PMOS transistors 21 and 22 connected in series are connected on the one hand to the programming voltage Vprog terminal and on the other hand to the second input terminal B of the floating gate memory structure. In this case, the programming of the floating gate FG can be performed via a second PMOS transistor 2 having a small capacitance Ct due to the tunneling effect. The first PMOS transistor 21 is connected to the programming terminal Vprog via the source and the substrate, while the drain of the first PMOS transistor 21 is connected to the source and the substrate of the second PMOS transistor 22 whose gate is biased by the battery voltage Vbat. The first PMOS transistor 21 functions as a switch connecting the programming terminal to the second input terminal B. When the voltage of the gate of the first PMOS transistor is at least equal to or lower than the battery voltage Vbat, this means that both the first PMOS transistor 21 and the second PMOS transistor 22 are conducting so that the programming of the floating gate FG of the memory structure can be executed via the second PMOS transistor 2 implementing the second capacitor of the memory structure.

[0021] Two other PMOS transistors 11 and 12 connected in series are connected on one hand to the programming voltage terminal Vprog and on the other hand to the first input terminal T of the floating gate memory structure. The first PMOS transistor 11 is connected to the programming terminal Vprog via the source and the substrate, while the drain of the first PMOS transistor 11 is connected to the source and the substrate of the second PMOS transistor 12 whose gate is biased by the battery voltage Vbat. The first PMOS transistor 11 is made non-conductive so as not to be connected to the programming voltage terminal Vprog, unlike the first PMOS transistor 21. The drain of the second PMOS transistor 12 is connected to the first input terminal T of the first PMOS transistor 1 implementing the first capacitor.

[0022] A pair of NMOS transistors connected in series is provided from the first input terminal T of the memory structure. The third NMOS transistor 13 is connected to the first input terminal T via its drain, while the source terminal is connected to the drain terminal of the fourth NMOS transistor 14, and the source terminal of the fourth NMOS transistor 14 is preferably directly connected to ground. The gate of the third NMOS transistor 13 is biased by the battery voltage Vbat, while the gate of the fourth NMOS transistor 14 is controlled by the first control signal W1.

[0023] Another pair of NMOS transistors connected in series is provided from the second input terminal B of the memory structure. The third NMOS transistor 23 is connected to the second input terminal B via its drain, while the source terminal is connected to the drain terminal of the fourth NMOS transistor 24, and the source terminal of the fourth NMOS transistor 24 is preferably directly connected to ground. The gate of the third NMOS transistor 23 is biased by the battery voltage Vbat, while the gate of the fourth NMOS transistor 24 is controlled by the second control signal W2.

[0024] Preferably, the third NMOS transistors 13 and 23 are DEMOS (Drain-Extended-MOS) type transistors.

[0025] FIG. 4 shows a second embodiment of an electronic circuit adapted to charge or read two floating gate memory structures FG and FG' connected in parallel and reverse to each other in the electronic circuit. The operating principle of this type of memory structure is based on the differential structure of the two floating gates FG and FG'. The two floating gates FG and FG' are each connected in series to two PMOS transistors. That is, a first PMOS transistor 1 having a large coupling capacitance Cc is connected to a first input terminal T, and a second PMOS transistor 2 having a small coupling capacitance Ct is adapted to program the first floating gate FG by tunneling through a second input terminal B. The first large PMOS transistor 1 can be directly adapted to function as a first PMOS type read transistor by connecting its drain terminal to the drain terminal of a first NMOS type transistor 31 of a read unit 30. Of course, the first NMOS transistor 31 may advantageously be a first DEMOS transistor.

[0026] Since a third PMOS transistor 42 having a large coupling capacitance Cc' is connected to the second input terminal B, it can be adapted to function as a second PMOS type read transistor by connecting its drain terminal to the drain terminal of a second NMOS type transistor 32 of the read unit 30. Of course, the second NMOS transistor 32 of the read unit 30 may advantageously be a second DEMOS transistor. Since a fourth PMOS transistor 41 having a small coupling capacitance Ct' is connected to the first input terminal T, it can be adapted to program the second floating gate FG' by tunneling through the first input terminal T.

[0027] The PMOS transistors 1, 2, 41, and 42 of the couplings Cc, Ct, Cc', and Ct' can preferably be manufactured as thick-oxide PMOS transistors (e.g., having a thickness in the range of 60 angstroms). For this purpose, source connections and gate connections are preferably used. This is because when the transistor is not used as a sense transistor, the drain connection is not used.

[0028] Also to be noted is that the unused drain terminals of the PMOS transistors forming the capacitors having the maximum coupling capacitances Cc and Cc' may be used to provide a large read transistor, and thus, very small standard read transistors as in the prior art can be eliminated. Further, by allowing the elimination of the parasitic charge of the original read transistor, the coupling function of the MOS transistor having the maximum capacitance is maximized. The larger the read transistor becomes, the lower the offset error of the electronic read circuit is reduced. This allows for a longer retention time of the memory in which the floating gate potentials FG and FG' slowly decrease over time due to leakage. Further, since the coupling of the programming pulse (the high voltage applied to the input terminals T or B) to the floating gate FG / FG' is improved, the program voltage is also maximized.

[0029] Also to be noted is that the pairs of PMOS, DEMOS, and NMOS transistors 11, 12, 13, 14, 21, 22, 23, and 24 are the same as those already described with reference to FIG. 3 and will not be described again with reference to FIG. 4.

[0030] As can be noticed in FIG. 4, the read unit 30 also includes a latch assembly that can output a signal shown as pol-bit-out that provides information regarding the programming state in each of the floating gates FG and FG' under the first and second transistors 31 and 32.

[0031] For this purpose, a third PMOS transistor 33 is provided. The source terminal and the substrate terminal of the third PMOS transistor 33 are connected to the source terminal of the first NMOS transistor or the DEMOS transistor 31, and the drain terminal of the third PMOS transistor 33 is connected to the drain terminal of the fifth NMOS transistor 35. The source terminal of the fifth transistor 35 is directly connected to ground. The gate terminals of the third transistor 33 and the fifth transistor 35 are connected to each other, thereby allowing the formation of the first inverter.

[0032] A fourth PMOS transistor 34 is also provided. The source terminal and the substrate terminal of the fourth PMOS transistor 34 are connected to the source terminal of the second NMOS transistor or the DEMOS transistor 32, and the drain terminal of the fourth PMOS transistor 34 is connected to the drain terminal of the sixth NMOS transistor 36. The source terminal of the sixth transistor 36 is directly connected to ground. The gate terminals of the fourth transistor 34 and the sixth transistor 36 are connected to each other, thereby allowing the formation of the second inverter.

[0033] It should also be noted that the gate terminal of the third transistor 33 and the gate terminal of the fifth transistor 35 are connected to the drain terminal of the fourth transistor 34 and the drain terminal of the sixth transistor 36, thereby allowing the output of at least one pol-bit-out output signal. Similarly, the gate terminal of the fourth transistor 34 and the gate terminal of the sixth transistor 36 are connected to the drain terminal of the third transistor 33 and the drain terminal of the fifth transistor 35.

[0034] It is also provided to connect the first NMOS transistor 37 in the stationary mode to the fifth NMOS transistor 35. The drain terminal of the first transistor 37 in the stationary mode with its source terminal connected to the ground is connected to the drain terminal of the fifth transistor 35. Similarly, it is provided to connect the second NMOS transistor 38 in the stationary mode to the drain terminal of the sixth NMOS transistor 36 via its drain terminal. The source terminal of the second NMOS transistor 38 is connected to the ground. In this way, when the stationary mode is desired, the gate terminals of the first and second transistors 37 and 38 are at a sufficient voltage supplied by the SAEb signal, so they become conductive and switch to the stationary mode.

[0035] It is also provided to connect a first NMOS transistor 51 between the supply voltage Vdd and the first input terminal T of the memory structure, connect the drain terminal to the supply voltage terminal Vdd via the drain terminal, and connect the source terminal to the drain terminal of a second DEMOS transistor 52 whose source terminal is connected to the first input terminal T via the source terminal. While the first transistor 51 is controlled by the SAE signal at its gate terminal, the gate terminal of the second transistor 52 is controlled by the battery voltage signal Vbat.

[0036] Similarly, it is also provided to connect a third NMOS transistor 53 between the supply voltage Vdd and the second input terminal B of the memory structure, connect the drain terminal to the supply voltage terminal Vdd via the drain terminal, and connect the source terminal to the drain terminal of a fourth DEMOS transistor 54 whose source terminal is connected to the second input terminal B via the source terminal. While the third transistor 53 is controlled by the SAE signal at its gate terminal, the gate terminal of the fourth transistor 54 is controlled by the battery voltage signal Vbat.

[0037] Some variations of the electronic circuit may be provided to enable charging or reading of the floating - gate memory structure forming part of the electronic circuit within the scope of the claims.

Claims

1. An electronic circuit having a floating gate memory structure, comprising a first transistor (1) provided with a large floating gate (FG) from a first input terminal (T), and a second transistor (2) provided with a floating gate (FG) smaller than the first transistor (1) from a second input terminal (B), wherein the first transistor (1) is connected in series to the floating gate (FG) of the second transistor (2) via its floating gate (FG), and the electronic circuit is arranged to read and load with respect to the floating gate memory structure, characterized in that the first transistor is converted into the form of a MOS transistor that directly functions as a transistor for reading with respect to the floating gate memory structure.

2. The features are that the electronic circuit is integrated with the floating gate memory structure on a P-type silicon substrate, and the first transistor (1) implementing the first capacitor of the memory structure is converted into a PMOS transistor having a source connected to the substrate connected to the first input terminal (T) of the memory structure and a drain connected to a read unit (30) to enable reading of the charge state of the memory structure. The electronic circuit according to claim 1.

3. The features are that the first transistor (1) having a large coupling capacitance (Cc) configured as a read transistor is allowed to be interconnected in the read mode by protection transistors, and the parasitic capacitive charges of these protection transistors do not affect the coupling of the first input terminal (T) or the second input terminal (B) at the floating gate (FG), and a significant reduction in the read offset is allowed by the size of the read transistor. The electronic circuit according to claim 2.

4. The first transistor (1) of the memory structure is directly converted into a PMOS transistor so as to become a transistor that reads the charge state of the floating gate of the memory structure, avoiding the use of the original read transistor having associated parasitic capacitance, increasing the coupling coefficient of the programming voltage (Vprog), and thus reducing the value of the programming voltage (Vprog) required to obtain a given floating gate voltage (FG). The electronic circuit according to claim 2, characterized in that.

5. The surface ratio between two PMOS transistors implementing the integrated first and second capacitors Cc and Ct of the electronic circuit exceeds 10 times. The electronic circuit according to claim 1, characterized in that.

6. The feature is The first PMOS transistor (1) is made to have a width w equal to 2.24 μm and a length l equal to 1.75 μm that give a surface area of the floating gate in the range of 3.92 μm ２ and, The surface area of the second PMOS transistor (2) is less than one twelfth of the surface area of the first PMOS transistor (1), and is 0.325 μm ２ made over a width w equal to 0.65 μm and over a length l equal to 0.5 μm, providing a surface area of the floating gate in the range of in the electronic circuit according to claim 5.

7. A read unit (30) is connected to the drain of the first PMOS transistor (1) to determine the charge state of the floating gate memory structure (FG). The electronic circuit according to claim 1, characterized in that.

8. The first NDEMOS transistor (3, 3') of the read unit (30) has a drain connected to the drain of the first PMOS transistor (1). The electronic circuit according to claim 7, characterized in that.

9. The feature is To program the floating gate (FG) of the memory structure, two PMOS transistors (21, 22) connected in series are connected to the programming voltage terminal (Vprog) on the one hand and to the second input terminal (B) of the floating gate memory structure (FG) to perform charging by the tunneling effect through the second PMOS transistor (2) having a small capacitance (Ct) on the other hand; The first PMOS transistor (21) is connected to the programming terminal (Vprog) via the source and the substrate, while the drain of the first PMOS transistor (21) is connected to the source and the substrate of the second PMOS transistor (22), and the gate of the second PMOS transistor (22) is biased by the battery voltage (Vbat); When the voltage of the gate of the first PMOS transistor (21) is at least a voltage equal to or lower than the battery voltage (Vbat) that is lower than the programming voltage (Vprog), the first PMOS transistor (21) functions as a switch that connects the programming terminal to the second input terminal (B). The electronic circuit according to claim 1, as set forth in **Claim 10** The features are that the electronic circuit includes two PMOS transistors (11, 12) connected in series, where one is connected to the programming voltage terminal (Vprog) and the other is connected to the first input terminal (T) of the floating gate memory structure (FG); the first PMOS transistor (11) is connected to the programming terminal (Vprog) by its source and substrate, while the drain of the first PMOS transistor (11) is connected to the source and substrate of the second PMOS transistor (12), and the gate of the second PMOS transistor (12) is biased by the battery voltage (Vbat); when the drain of the second PMOS transistor (12) is connected to the first input terminal (T) of the first PMOS transistor (1) having a high coupling capacitance, the first PMOS transistor (11) can be controlled to be conductive at its gate, or preferably to be non-conductive so as not to have a connection to the programming voltage terminal (Vprog). The electronic circuit according to claim 1, as set forth in **Claim 11** The features are that the electronic circuit includes two pairs of NMOS transistors (13, 14; 23, 24) connected in series by cascodes from each of the input terminals (T, B) and connected to the ground terminal (Vss); the first NMOS transistor (13, 23) of each pair is a DEMOS transistor biased by the battery voltage (Vbat) at its gate, while the second transistor (14, 24) of each pair is an NMOS transistor controlled by control signals (W1, W2) at its gate respectively. The electronic circuit according to claim 1, as set forth in **Claim 12** The features are that The electronic circuit includes two floating gate memory structures (FG, FG') connected in anti-parallel between the first input terminal (T) and the second input terminal (B). A large first floating gate (FG) is provided from the first input terminal (T) to the first PMOS transistor (1). A first floating gate (FG) smaller than the first capacitor (1) is provided from the second input terminal (B) to the second PMOS transistor (2). A large second floating gate (FG') is provided from the second input terminal (B) to the third PMOS transistor (42). A second floating gate (FG') smaller than the third PMOS transistor (42) is provided from the first input terminal (T) to the fourth PMOS transistor (41). The electronic circuit according to claim 1.

13. The features are The read unit (30) includes a first DEMOS transistor (31) and a second DEMOS transistor (32). The drain of the first DEMOS transistor (31) is connected to the drain of the first PMOS read transistor (1), and the drain of the second DEMOS transistor (31) is connected to the drain of the second PMOS read transistor (2) of the third capacitor (42). The read unit (30) is configured to output at least one signal (pol-bit-out) of the charging state of the floating gate. The electronic circuit according to claim 12.

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