Pixel circuit, display panel, and display device

Abstract

To provide a pixel circuit, display panel, and display device.SOLUTION: In more particular, the present invention relates to a pixel circuit capable of reducing the number of power lines and sufficiently securing the time for sampling a threshold voltage of a driving element in the pixel circuit, and to a display panel and a display device.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This embodiment relates to a pixel circuit, a display panel, and a display device.

Background Art

[0002] An organic electroluminescent display device includes an organic light emitting diode (OLED), and has advantages such as a fast response speed, high luminous efficiency, high luminance, and a large viewing angle.

[0003] Such an organic electroluminescent display device includes a pixel circuit for driving the OLED. Here, the pixel circuit may include a driving element for driving the OLED.

[0004] On the other hand, there may be variations in electrical characteristics among pixel circuits. Here, the electrical characteristics of the pixel circuit may include the threshold voltage of the driving element.

[0005] Such variations in the electrical characteristics of the pixel circuit may become larger as the driving time of the pixel circuit increases.

[0006] An internal compensation circuit may be added to the pixel circuit to compensate for variations in the electrical characteristics of the driving element among pixel circuits.

[0007] Here, the internal compensation circuit can be divided into a source follower method and a diode connection method.

[0008] The description provided in the background art should not be regarded as prior art only for the reason that it is mentioned in the background art or is related to the background art. The background art may include information explaining one or more of the features of the present invention.

Summary of the Invention

Problems to be Solved by the Invention

[0009] The inventors of the present invention newly recognized that the diode connection method has good compensation performance because of the low loss of the threshold voltage of the driving element. However, since the data voltage is addressed and the threshold voltage of the driving element is sampled during one horizontal period, the sampling time may be insufficient in the high-speed driving of a display device with a short horizontal period.

[0010] In addition, since a power supply line for setting the voltage of each node is added to the internal compensation circuit, the high-resolution design of the display device may be difficult.

[0011] The present invention provides a pixel circuit, a display panel, and a display device that can sufficiently secure the time for sampling the threshold voltage of a driving element in a pixel circuit and can reduce the number of power supply lines.

[0012] The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0013] This embodiment includes a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode and a second electrode connected to a second node to which a data voltage is applied, a light-emitting element including an anode electrode and a cathode electrode and emitting light by a current from the driving element, and a first switch element connected between the anode electrode and the cathode electrode and electrically connecting the anode electrode and the cathode electrode in response to a first gate signal.

[0014] The first switch element can be turned on until the light-emitting element emits light by the current and maintain the electrical connection between the anode electrode and the cathode electrode until the light-emitting element emits light.

[0015] The pixel circuit is driven in the order of an initialization period, a sampling period, a data writing period, and a light emission period. The first gate signal is a gate-on voltage during the initialization period, the sampling period, and the data writing period, and is a gate-off voltage during the light emission period. The first switch element is turned on in response to the gate-on voltage of the first gate signal to be electrically connected to the anode electrode and the cathode electrode, and can be turned off in response to the gate-off voltage of the first gate signal.

[0016] The pixel circuit further includes a first capacitor connected between a fourth node connected to the anode electrode and the second node, a second switch element connected between the first node and the second node and turned on in response to the gate-on voltage of the first gate signal to electrically connect the first node and the second node, a third switch element turned on in response to the gate-on voltage of a second gate signal to electrically connect a drive power line that supplies the pixel drive voltage to the first node, a fourth switch element turned on in response to the gate-on voltage of a third gate signal to electrically connect a third node connected to the second electrode of the drive element and an initialization power line that supplies an initialization voltage, a second capacitor connected between a data line to which a data voltage is applied and the second node, a fifth switch element turned on in response to the gate-on voltage of a fourth gate signal to electrically connect the data line and the second capacitor, and a sixth switch element turned on in response to the gate-on voltage of a fifth gate signal to electrically connect the third node to the fourth node.

[0017] The cathode voltage applied from the cathode electrode to the anode electrode is a voltage lower than the initialization voltage, and the pixel drive voltage can be a voltage higher than the initialization voltage.

[0018] The pixel circuit is driven in the order of an initialization period, a sampling period, a data writing period, and a light emitting period. During the initialization period, the first gate signal and the second gate signal are gate-on voltages, and the third gate signal, the fourth gate signal, and the fifth gate signal are gate-off voltages. During the sampling period, the first gate signal and the third gate signal are gate-on voltages, and the second gate signal, the fourth gate signal, and the fifth gate signal are gate-off voltages. During the data writing period, the first gate signal, the third gate signal, and the fourth gate signal are gate-on voltages, and the second gate signal and the fifth gate signal are gate-off voltages. During the light emitting period, the second gate signal and the fifth gate signal may be gate-on voltages, and the first gate signal, the third gate signal, and the fourth gate signal may be gate-off voltages.

[0019] The first switch element and the second switch element may be turned on during the initialization period, the sampling period, and the data writing period.

[0020] The third switch element is turned on during the initialization period and the light emitting period, and the fourth switch element may be turned on during the sampling period and the data writing period.

[0021] The fifth switch element is turned on during the data writing period, and the sixth switch element may be turned on during the light emitting period.

[0022] On the other hand, in this embodiment, a display panel is provided in which a plurality of data lines, a plurality of gate lines, a plurality of pixel circuits, a cathode power line for supplying a cathode voltage to the pixel circuits, a driving power line for supplying a pixel driving voltage to the pixel circuits, and an initialization power line for supplying an initialization voltage to the pixel circuits are arranged; a data driving circuit for outputting a data voltage of pixel data to the plurality of data lines; and a gate driving circuit for sequentially outputting gate signals to the plurality of gate lines. The pixel circuit includes a first electrode connected to a first node to which the pixel driving voltage is applied, a driving element including a gate electrode and a second electrode connected to a second node to which the data voltage is applied, a light emitting element including an anode electrode and a cathode electrode connected to the cathode power line and emitting light by a current from the driving element, and a first switch element connected between the anode electrode and the cathode electrode and electrically connecting the anode electrode and the cathode electrode in response to a first gate signal.

[0023] The pixel circuit may further include a second switch element connected between the first node and the second node and electrically connecting the first node and the second node in response to the first gate signal.

[0024] The pixel circuit is driven in the order of an initialization period, a sampling period, the data writing period, and the light emitting period. The first gate signal is a gate-on voltage during the initialization period, the sampling period, and the data writing period, and is a gate-off voltage during the light emitting period. The first switch element is turned on in response to the gate-on voltage of the first gate signal to electrically connect the anode electrode and the cathode electrode, and is turned off in response to the gate-off voltage of the first gate signal. The second switch element may be turned on in response to the gate-on voltage of the first gate signal to electrically connect the first node and the second node, and may be turned off in response to the gate-off voltage of the first gate signal.

[0025] The pixel circuit may further include a first capacitor connected between a fourth node connected to the anode electrode and the second node, a third switch element turned on in response to a gate-on voltage of a second gate signal to electrically connect the drive power line to the first node, a fourth switch element turned on in response to a gate-on voltage of a third gate signal to electrically connect a third node connected to a second electrode of the drive element and the initialization power line, a second capacitor connected between a data line to which a data voltage is applied and the second node, a fifth switch element turned on in response to a gate-on voltage of a fourth gate signal to electrically connect the data line and the second capacitor, and a sixth switch element turned on in response to a gate-on voltage of a fifth gate signal to electrically connect the third node to the fourth node.

[0026] The pixel circuit is driven in the order of an initialization period, a sampling period, the data writing period, and the light emitting period. During the initialization period, the first gate signal and the second gate signal are at gate-on voltages, and the third gate signal, the fourth gate signal, and the fifth gate signal are at gate-off voltages. During the sampling period, the first gate signal and the third gate signal are at gate-on voltages, and the second gate signal, the fourth gate signal, and the fifth gate signal are at gate-off voltages. During the data writing period, the first gate signal, the third gate signal, and the fourth gate signal are at gate-on voltages, and the second gate signal and the fifth gate signal are at gate-off voltages. During the light emitting period, the second gate signal and the fifth gate signal may be at gate-on voltages, and the first gate signal, the third gate signal, and the fourth gate signal may be at gate-off voltages.

[0027] On the other hand, this embodiment includes a display area where an input video is displayed, a non-display area outside the display area, a plurality of cathode power lines arranged in the display area, and a plurality of pixel circuits arranged in the display area. Each of the pixel circuits includes an anode electrode and a cathode electrode, a light-emitting element that emits light by current from a driving element, a first electrode connected to the anode electrode, a second electrode connected to the cathode electrode, and a first switching element including a gate electrode to which a scan signal is applied. The cathode electrode of the light-emitting element and the second electrode of the first switching element are connected to the corresponding cathode power line, providing a display panel.

[0028] The display panel may include a first short bar disposed on one side of the non-display area and connected to one end of the cathode power line, and a second short bar disposed on the other side of the non-display area and connected to the other end of the cathode power line.

[0029] The display panel further includes an insulating layer covering the first electrode, the second electrode, and the cathode power line of the first switching element, a first planarization layer covering the insulating layer, a first connection electrode contacting the cathode power line in the non-display area through a first contact hole penetrating the first planarization layer, a second connection electrode contacting the first electrode of the first switching element in the display area through a second contact hole penetrating the first planarization layer, a second planarization layer covering the first connection electrode and the second connection electrode, and a bank layer covering the second planarization layer. The anode electrode contacts the second connection electrode in the display area through a third contact hole penetrating the second planarization layer, and the cathode electrode may contact the first connection electrode through a fourth contact hole penetrating the bank layer and the second planarization layer.

[0030] On the other hand, this embodiment includes a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode and a second electrode connected to a second node to which a data voltage is applied, a light-emitting element including an anode electrode connected to a fourth node and a cathode electrode connected to a cathode power line, a first switching element including a first electrode connected to the fourth node, a gate electrode connected to a first gate line, and a second electrode connected to the gate electrode, a first capacitor connected between the fourth node and the second node, a second switching element including a first electrode connected to the first node, a gate electrode connected to a first gate line, and a second electrode connected to a second node, a third switching element including a first electrode connected to a driving power line for supplying a pixel driving voltage, a gate electrode connected to a second gate line, and a second electrode connected to the first node, a fourth switching element including a first electrode connected to an initialization power line for supplying an initialization voltage, a gate electrode connected to a third gate line, and a second electrode connected to the third node, a second capacitor connected between a data line to which a data voltage is applied and the second node, a fifth switching element including a first electrode connected to the data line, a gate electrode connected to a fourth gate line, and a second electrode connected to the second capacitor, and a sixth switching element including a first electrode connected to the third node, a gate electrode connected to a fifth gate line, and a second electrode connected to the fourth node.

[0031] As described above, according to this embodiment, the time for sampling the threshold voltage of the driving element in the pixel circuit is sufficiently ensured, and the number of power lines can be reduced, so that the high-speed driving and high-resolution design of the display device are facilitated.

[0032] The various and beneficial merits and effects of the present invention are not limited to the above-described content, and will be more easily understood in the process of describing the specific embodiments of the present invention.

Brief Description of the Drawings

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BEST MODE FOR CARRYING OUT THE INVENTION

[0034] Advantages and features of the present invention, and methods for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but is embodied in various different forms, and the embodiments are merely provided so that the disclosure of the present invention is complete and that those with ordinary knowledge in the technical field to which the present invention pertains are fully informed of the scope of the invention. The present invention is only defined by the scope of the claims.

[0035] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and thus the present invention is not limited to the matters shown in the drawings. The same reference numerals throughout the specification indicate substantially the same components. Further, when explaining the present invention, if it is determined that the specific description of related known technologies will obscure the gist of the present invention, the detailed description thereof will be omitted.

[0036] When terms such as "comprising", "including", "having", "consisting of", etc. are used in this specification, other parts can be added as long as "only" is not used. When a component is expressed in the singular, it can be interpreted as plural unless otherwise explicitly stated.

[0037] When interpreting a component, even without a separate explicit description, it is interpreted as including an error range.

[0038] When it comes to the description of the positional relationship, for example, when the positional relationship and the mutual connection relationship between two components are described such as "on", "above", "below", "beside", "connect or couple", "crossing", "intersecting", etc., one or more other components can be interposed between these components unless there is a reference such as "immediately" or "directly".

[0039] The first, second, etc. may be used to distinguish components, but the functions and structures of these components are not limited by the ordinal numbers attached to the components or the names of the components. Since the claims are described centering on essential components, the ordinal numbers attached to the names of the components in the claims may not match the ordinal numbers attached to the names of the components in the embodiments.

[0040] The following embodiments can be partially or entirely combined or combined with each other, and various linkages and drives are technically possible. Each embodiment can be implemented independently of each other or can be implemented together with a correlation relationship.

[0041] In the display device of the present invention, a display panel driving circuit, a pixel circuit, a level shifter, etc. may include a transistor. The transistor may be embodied as an oxide transistor including an oxide semiconductor, an LTPS transistor including low temperature poly silicon (LTPS), etc. Here, the transistor may be a thin film transistor (TFT).

[0042] A transistor is a three-electrode element including a gate, a source, and a drain. The source is a terminal that supplies a carrier to the transistor. In the transistor, the carrier flows out from the source. The drain is a terminal through which the carrier exits the transistor to the outside. In the transistor, the flow of the carrier flows from the source to the drain. In the case of an N-channel transistor, since the carrier is an electron, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an N-channel transistor, the direction of the current flows from the drain to the source side. In the case of a P-channel transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. Since holes flow from the source to the drain side in the P-channel transistor, the current flows from the source to the drain side. It should be noted that the drain and source of the transistor are not fixed. For example, the drain and source can be changed according to the applied voltage. Therefore, the invention is not limited by the drain and source of the transistor. In the following description, the drain and source of the transistor will be referred to as the first electrode and the second electrode.

[0043] The gate signal swings between a gate on voltage and a gate off voltage. The gate off voltage may be interpreted as a first voltage, and the gate on voltage may be interpreted as a second voltage. The transistor turns on in response to the gate on voltage and turns off in response to the gate off voltage. In the case of an N-channel transistor, the gate on voltage may be a gate high voltage VGH, and the gate off voltage may be a gate low voltage VGL. In the case of a P-channel transistor, the gate on voltage may be a gate low voltage VGL, and the gate off voltage may be a gate high voltage VGH.

[0044] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0045] FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a cross-sectional structure of the display panel shown in FIG. 1.

[0046] Referring to FIGS. 1 and 2, the display device according to an embodiment of the present invention may be an organic light emitting display device, but the present embodiment is not limited thereto. For example, the display device of the present embodiment may also be other types of display devices such as a micro-light emitting diode (micro-LED) display device. Such a display device may include a display panel 100, a display panel driving circuit for writing (Write) pixel data to the pixel circuit of the display panel 100, and a power supply circuit 140 that generates a power supply necessary for driving the pixel circuit and the display panel driving circuit.

[0047] The display panel 100 may be a panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction, but is not limited thereto. For example, the display panel 100 may be a panel having a rectangular structure with a length in the Y-axis direction and a width in the X-axis direction. As yet another example, the display panel 100 may be a panel having a structure of any shape such as a square, a circle, an ellipse, etc.

[0048] The display area AA of the display panel 100 includes a pixel array for displaying an image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the plurality of data lines 102, and pixel circuits 101 arranged in a matrix at points where the plurality of data lines 102 and the plurality of gate lines 103 intersect. The display panel 100 may further include a power line commonly connected to the pixel circuits 101. The power line is connected to the pixel circuits to supply a constant voltage required for driving the pixel circuits 101 to the pixel circuits 101.

[0049] The pixel circuit 101 may be divided into two or more sub-pixel circuits for color implementation. For example, three sub-pixel circuits sequentially arranged in the X-axis direction may be divided into a red sub-pixel circuit, a green sub-pixel circuit, and a blue sub-pixel circuit, but the present embodiment is not limited thereto.

[0050] Also, four sub-pixels sequentially arranged in the X-axis direction may also be divided into a red sub-pixel circuit, a green sub-pixel circuit, a blue sub-pixel circuit, and a white sub-pixel circuit.

[0051] Each of the pixel circuits 101 is connected to a data line, a gate line, and a power line.

[0052] The pixel array includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes a line of pixel circuits arranged along the line direction (X-axis direction) in the pixel array of the display panel 100. The pixel circuits arranged in one pixel line share the gate line 103. The pixel circuits arranged in the column direction (Y-axis direction) along the data line direction share the same data line 102. One horizontal period is the time obtained by dividing one frame period by the total number of the pixel lines L1 to Ln.

[0053] The display panel 100 can be embodied as a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device where an image is displayed on the screen and the real object in the background can be seen. The display panel 100 can also be embodied as a flexible display panel or a non-flexible display panel.

[0054] At least a part of the display panel 100 may include a transmissive pixel structure that overlaps with an optical element arranged at the lower part of the display panel 100. The optical element may include optical elements such as an image sensor (or camera), a proximity sensor, an illumination element, or an infrared sensor for face recognition.

[0055] The cross-sectional structure of such a display panel 100 is as follows.

[0056] FIG. 2 is a cross-sectional view showing the cross-sectional structure of the display panel shown in FIG. 1.

[0057] Referring to FIG. 2, it is a cross-sectional view including two switching thin-film transistors TFT1, TFT2 and one capacitor CST. The two switching thin-film transistors TFT1, TFT2 include a polycrystalline thin-film transistor TFT1 containing a polycrystalline semiconductor material such as LTPS (low-temperature poly-Si), and an oxide thin-film transistor TFT2 containing an oxide semiconductor material. However, the present embodiment is not limited thereto.

[0058] The polycrystalline thin film transistor TFT1 shown in FIG. 2 is an emission switching thin film transistor or a driving transistor connected to the light emitting element EL, and the oxide thin film transistor TFT2 is any one of the switching thin film transistors connected to the capacitor CST.

[0059] In FIG. 2, one pixel includes a light emitting element EL and a pixel driving circuit that applies a driving current to the light emitting element EL. The pixel driving circuit is disposed on the substrate 211, and the light emitting element EL is disposed on the pixel driving circuit. And a sealing layer 220 is disposed on the light emitting element EL. The sealing layer 220 protects the light emitting element EL.

[0060] The pixel driving circuit may refer to a pixel array portion including a driving thin film transistor, a switching thin film transistor, and a capacitor. And the light emitting element EL may refer to an array portion for light emission including an anode electrode, a cathode electrode, and a light emitting layer disposed therebetween.

[0061] In one embodiment, the driving thin film transistor and at least one switching thin film transistor use an oxide semiconductor as the active layer. A thin film transistor using an oxide semiconductor material as the active layer has an excellent leakage current blocking effect and is relatively inexpensive in manufacturing cost compared to a thin film transistor using a polycrystalline semiconductor material as the active layer. Therefore, in order to reduce power consumption and lower the manufacturing cost, the pixel driving circuit according to one embodiment includes a driving thin film transistor and at least one switching thin film transistor using an oxide semiconductor material.

[0062] All of the thin film transistors constituting the pixel driving circuit can be implemented using an oxide semiconductor material, or only some of the switching thin film transistors can be implemented using an oxide semiconductor material.

[0063] The substrate 211 can be embodied as a multi-layer in which an organic film and an inorganic film are alternately laminated. For example, the substrate 211 can be formed by alternately laminating an organic film such as polyimide and an inorganic film such as silicon oxide (SiO2).

[0064] Also, the substrate 211 may include glass, plastic, or a flexible polymer film. For example, the flexible polymer film can be made of any one of polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS), but this is merely an example and is not necessarily limited thereto.

[0065] On the substrate 211, a lower buffer layer 212a is formed. The lower buffer layer 212a is for blocking moisture and the like that can penetrate from the outside, and a silicon oxide (SiO2) film or the like can be laminated in multiple layers for use. An auxiliary buffer layer 212b can be further disposed on the lower buffer layer 212a to protect the element from moisture permeation.

[0066] On the substrate 211, a polycrystalline thin-film transistor TFT1 is formed. The polycrystalline thin-film transistor TFT1 can use a polycrystalline semiconductor as an active layer. The polycrystalline thin-film transistor TFT1 includes a first active layer ACT1 including a channel through which electrons or holes move, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2.

[0067] The first active layer ACT1 includes a first channel region, a first source region disposed on one side sandwiching the first channel region, and a first drain region disposed on the other side.

[0068] The first source region and the first drain region are regions that are made conductive by doping a genuine polycrystalline semiconductor material with impurity ions of Group 5 or Group 3, such as phosphorus (P) or boron (B), at a predetermined concentration. The first channel region is one in which the polycrystalline semiconductor material maintains a genuine state and provides a path for electrons and holes to move.

[0069] On the other hand, the polycrystalline thin-film transistor TFT1 includes a first gate electrode GE1 that overlaps with the first channel region in the first active layer ACT1. A first gate insulating layer 213 is disposed between the first gate electrode GE1 and the first active layer ACT1. The first gate insulating layer 213 can be formed by laminating inorganic layers such as a silicon oxide (SiO2) film and a silicon nitride (SiNx) film, either singly or in multiple layers.

[0070] In one embodiment, the polycrystalline thin-film transistor TFT1 can have a top-gate structure in which the first gate electrode GE1 is located above the first active layer ACT1. However, this embodiment is not limited thereto. For example, the polycrystalline thin-film transistor TFT1 can have a bottom-gate structure or a dual-gate structure. As a result, the first electrode CST1 included in the capacitor CST and the light-shielding layer LS included in the oxide thin-film transistor TFT2 can be formed of the same material as the first gate electrode GE1. By forming the first gate electrode GE1, the first electrode CST1, and the light-shielding layer LS through one mask process, the number of mask processes can be reduced. However, this is not limiting, and the light-shielding layer LS can also be formed through another mask process on the lower buffer layer 212a and the auxiliary buffer layer 212b. In this case, the light-shielding layer LS is not limited to the oxide thin-film transistor TFT2 and can be formed under all transistors. Also, the light-shielding layer LS can be disposed so as to overlap the bottom of the capacitor CST to form a double capacitor.

[0071] The first gate electrode GE1 is composed of a metallic substance. For example, the first gate electrode GE1 can be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0072] A first interlayer insulating layer 214 is disposed on the first gate electrode GE1. The first interlayer insulating layer 214 can be implemented with silicon oxide (SiO2), silicon nitride (SiNx), or the like.

[0073] The display panel 100 can further include an upper buffer layer 215, a second gate insulating layer 216, and a second interlayer insulating layer 217 that are sequentially disposed on the first interlayer insulating layer 214. The polycrystalline thin film transistor TFT1 is formed on the second interlayer insulating layer 217 and includes a first source electrode SD1 and a first drain electrode SD2 that are respectively connected to the first source region and the first drain region.

[0074] The first source electrode SD1 and the first drain electrode SD2 can be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0075] The upper buffer layer 215 separates the first active layer ACT1 made of a polycrystalline semiconductor material from the second active layer ACT2 of the oxide thin film transistor TFT2 made of an oxide semiconductor material, and provides a substrate on which the second active layer ACT2 can be formed.

[0076] The second gate insulating layer 216 covers the second active layer ACT2 of the oxide thin film transistor TFT2. Since the second gate insulating layer 216 is formed on the second active layer ACT2 made of an oxide semiconductor material, it is made of an inorganic film. For example, the second gate insulating layer 216 can be silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0077] The second gate electrode GE2 is composed of a metal material. For example, the second gate electrode GE2 can be a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0078] On the other hand, the oxide thin film transistor TFT2 is formed on the upper buffer layer 215 and includes a second active layer ACT2 made of an oxide semiconductor material, a second gate electrode GE2 disposed on the second gate insulating layer 216, a second source electrode SD3 and a second drain electrode SD4 disposed on the second interlayer insulating layer 217.

[0079] The second active layer ACT2 includes an intrinsic second channel region made of an oxide semiconductor material and not doped with impurities, and a second source region and a second drain region doped with impurities and made conductive.

[0080] The oxide thin film transistor TFT2 is located below the upper buffer layer 215 and further includes a light shielding layer LS that overlaps with the second active layer ACT2. The light shielding layer LS can block the light incident on the second active layer ACT2 and ensure the reliability of the oxide thin film transistor TFT2. The light shielding layer LS is formed of the same material as the first gate electrode GE1 and can be formed on the upper surface of the first gate insulating layer 213. The light shielding layer LS can also be electrically connected to the second gate electrode GE2 to form a dual gate.

[0081] The second source electrode SD3 and the second drain electrode SD4, together with the first source electrode SD1 and the first drain electrode SD2, can be simultaneously formed from the same material on the second interlayer insulating layer 217, thereby reducing the number of mask processes.

[0082] On the other hand, the second electrode CST2 can be disposed on the first interlayer insulating layer 214 so as to overlap the first electrode CST1, thereby implementing the capacitor CST. The second electrode CST2 can be, for example, a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0083] The capacitor CST stores the data voltage applied through the data line DL for a certain period and then provides it to the light-emitting element EL. The capacitor CST includes two electrodes corresponding to each other and a dielectric disposed therebetween. The first interlayer insulating layer 214 is located between the first electrode CST1 and the second electrode CST2.

[0084] Either the first electrode CST1 or the second electrode CST2 of the capacitor CST can be electrically connected to the oxide thin film transistor TFT2, the second source electrode SD3, or the second drain electrode SD4. However, it is not limited thereto, and the connection relationship of the capacitor CST can change according to the pixel driving circuit.

[0085] On the other hand, the first planarization layer 218 and the second planarization layer 219 are sequentially disposed on the pixel driving circuit to planarize the step caused by the pixel driving circuit. The first planarization layer 218 and the second planarization layer 219 can be organic films such as polyimide and acrylic resin.

[0086] Then, the light-emitting element EL is formed on the second planarization layer 219.

[0087] The light-emitting element EL includes an anode electrode ANO, a cathode electrode CAT, and a light-emitting layer LEL disposed between the anode electrode ANO and the cathode electrode CAT. When implemented with a pixel driving circuit that commonly uses a low-potential voltage connected to the cathode electrode CAT, the anode electrode ANO is disposed on a separate electrode for each sub-pixel. If implemented with a pixel driving circuit that commonly uses a high-potential voltage, the cathode electrode CAT can also be disposed on a separate electrode for each sub-pixel.

[0088] The light-emitting element EL is electrically connected to the driving element through an intermediate electrode CNE disposed on the first planarization layer 218. Specifically, the anode electrode ANO of the light-emitting element EL and the first source electrode SD1 of the polycrystalline thin-film transistor TFT1 constituting the pixel driving circuit are connected to each other by the intermediate electrode CNE.

[0089] The anode electrode ANO is connected to the exposed intermediate electrode CNE through a contact hole penetrating the second planarization layer 219. Also, the intermediate electrode CNE is connected to the exposed first source electrode SD1 through a contact hole penetrating the first planarization layer 218. However, the embodiments of the present invention are not limited thereto. For example, depending on the structure of the pixel driving circuit, the intermediate electrode CNE may be connected to the first drain electrode SD2, the second source electrode SD3, or the second drain electrode SD4.

[0090] The intermediate electrode CNE serves as a medium for connecting the first source electrode SD1 and the anode electrode ANO. The intermediate electrode CNE can be formed from a conductive material such as copper (Cu), silver (Ag), molybdenum (Mo), or titanium (Ti).

[0091] The anode electrode ANO can be formed in a multilayer structure including a transparent conductive film and an opaque conductive film with high reflection efficiency. The transparent conductive film is made of a material with a relatively large work function value, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The opaque conductive film can be composed of a single-layer or multilayer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or an alloy thereof. For example, the anode electrode ANO can be formed in a structure where a transparent conductive film, an opaque conductive film, and a transparent conductive film are sequentially laminated, or in a structure where a transparent conductive film and an opaque conductive film are sequentially laminated.

[0092] The light-emitting layer LEL is formed by laminating a hole-related layer, an organic light-emitting layer, and an electron-related layer in this order or in the reverse order on the anode electrode ANO.

[0093] The bank layer BNK can be a pixel-defining film that exposes the anode electrode ANO of each pixel. The bank layer BNK can also be formed from an opaque material (e.g., black) to prevent light interference between adjacent pixels. In this case, the bank layer BNK contains a light-shielding substance composed of at least one of a color pigment, organic black, and carbon. A spacer can be further disposed on the bank layer BNK.

[0094] The cathode electrode CAT faces the anode electrode ANO with the light-emitting layer LEL interposed therebetween and is formed on the upper surface and side surfaces of the light-emitting layer LEL. The cathode electrode CAT can be integrally formed over the entire display area AA. When applied to a front-emission type organic light-emitting display device, the cathode electrode CAT can be made of a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0095] A sealing layer 220 for suppressing the penetration of moisture can be further disposed on the cathode electrode CAT.

[0096] The encapsulation layer 220 can block the penetration of external moisture and oxygen into the light-emitting element EL that is vulnerable to external moisture and oxygen. For this purpose, the encapsulation layer 220 can include, but is not limited to, at least one inorganic encapsulation layer and at least one organic encapsulation layer. In the present invention, the structure of the encapsulation layer 220 in which the first encapsulation layer 221, the second encapsulation layer 222, and the third encapsulation layer 223 are sequentially laminated will be described as an example.

[0097] The first encapsulation layer 221 is formed on the substrate 211 on which the cathode electrode CAT is formed. The third encapsulation layer 223 is formed on the substrate 211 on which the second encapsulation layer 222 is formed, and can be formed so as to surround the upper surface, lower surface, and side surface of the second encapsulation layer 222 together with the first encapsulation layer 221. Such first encapsulation layer 221 and third encapsulation layer 223 can minimize or prevent the penetration of external moisture and oxygen into the light-emitting element EL. The first encapsulation layer 221 and the third encapsulation layer 223 can be formed of an inorganic insulating material capable of low-temperature deposition, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Since the first encapsulation layer 221 and the third encapsulation layer 223 are deposited in a low-temperature atmosphere, it is possible to prevent the light-emitting element EL, which is vulnerable to a high-temperature atmosphere, from being damaged during the deposition process of the first encapsulation layer 221 and the third encapsulation layer 223.

[0098] The second encapsulation layer 222 serves as a buffer to relieve the stress between layers due to the bending of the display device and can planarize the step between layers. This second encapsulation layer 222 can be formed on the substrate 211 on which the first encapsulation layer 221 is formed from a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and polyethylene or silicon oxycarbide (SiOC), or a photosensitive organic insulating material such as photoacrylic, but is not limited thereto. When the second encapsulation layer 222 is formed by an inkjet method, a dam DAM can be disposed to prevent the liquid-form second encapsulation layer 222 from spreading to the edge of the substrate 211. The dam DAM can be disposed closer to the edge of the substrate 211 than the second encapsulation layer 222. Such a dam DAM can prevent the second encapsulation layer 222 from spreading to the pad region where the conductive pads disposed on the outermost contour of the substrate 211 are located.

[0099] The dam DAM is designed to prevent the diffusion of the second encapsulation layer 222. However, if the second encapsulation layer 222 is formed to exceed the height of the dam DAM during the process, since the second encapsulation layer 222, which is an organic layer, may be exposed to the outside, moisture and the like may easily penetrate into the interior of the light-emitting element. Therefore, to prevent this, the dam DAM can be formed in at least 11 or more overlapping layers.

[0100] The dam DAM can be disposed on the second interlayer insulating layer 217 of the non-display area NDA.

[0101] Also, the dam DAM can be formed simultaneously with the first planarization layer 218 and the second planarization layer 219. When the first planarization layer 218 is formed, the lower layer of the dam DAM is formed together, and when the second planarization layer 219 is formed, the upper layer of the dam DAM is formed together and can be formed by being laminated in a double structure.

[0102] Therefore, the dam DAM can be composed of the same material as the first planarization layer 218 and the second planarization layer 219, but is not limited thereto.

[0103] The dam DAM can be formed to overlap with the cathode power line PL1. For example, in the non-display area NDA, the cathode power line PL1 can be formed in the lower layer of the area where the dam DAM is located.

[0104] The cathode power line PL1 and the gate drive circuit 120 configured in the GIP (Gate In Panel) form are formed in a form surrounding the outer contour of the display panel, and the cathode power line PL1 can be located outside the outer contour of the gate drive circuit 120. Also, the cathode power line PL1 is connected to the cathode electrode CAT and can apply a common voltage. The gate drive circuit 120 is simply represented in the plane and cross-sectional drawings, but can be configured using thin film transistors having the same structure as the thin film transistors in the display area AA.

[0105] The cathode power line PL1 is arranged outside the gate drive circuit 120. The cathode power line PL1 is arranged outside the gate drive circuit 120 and surrounds the display area AA. For example, the cathode power line PL1 can be made of the same material as the first gate electrode GE1, but is not limited thereto, and can be made of the same material as the second electrode CST2 or the first source and drain electrodes SD1, SD2, but is not limited thereto.

[0106] Also, the cathode power line PL1 can be electrically connected to the cathode electrode CAT. The cathode power line PL1 can supply the cathode voltage EVSS to the pixels in the display area AA.

[0107] A touch layer can be arranged on the sealing layer 220. In the touch layer, the touch buffer film 251 can be located between the touch sensor metal including the touch electrode connection lines 252, 254 and the touch electrodes 255, 256 and the cathode electrode CAT of the light emitting element EL.

[0108] The touch buffer film 251 can prevent a chemical solution (such as a developer or an etchant) or external moisture used during the manufacturing process of the touch sensor metal disposed on the touch buffer film 251 from penetrating into the light-emitting layer LEL containing organic substances. Thereby, the touch buffer film 251 can prevent damage to the light-emitting layer LEL vulnerable to the chemical solution or moisture.

[0109] The touch buffer film 251 can be formed at a certain temperature (e.g., a low temperature of 100 degrees Celsius (°C) or less) to prevent damage to the light-emitting layer LEL containing organic substances vulnerable to high temperatures, and is formed of an organic insulating material having a low dielectric constant of 1 to 3. For example, the touch buffer film 251 can be formed of a material of an acrylic series, an epoxy series, or a siloxane series. The touch buffer film 251 having planarization performance with an organic insulating material can prevent damage to the sealing layer 220 due to the bending of the organic light-emitting display device and the cracking phenomenon of the touch sensor metal formed on the touch buffer film 251.

[0110] According to the touch sensor structure of the mutual-capacitance method, touch electrodes 255 and 256 are disposed on the touch buffer film 251, and the touch electrodes 255 and 256 can be disposed to cross each other.

[0111] The touch electrode connection lines 252 and 254 can electrically connect between the touch electrodes 255 and 256. The touch electrode connection lines 252 and 254 and the touch electrodes 255 and 256 can be located in different layers with the touch insulating film 253 interposed therebetween.

[0112] The touch electrode connection lines 252 and 254 are disposed to overlap with the bank layer BNK, and can prevent a decrease in the aperture ratio.

[0113] On the other hand, for the touch electrodes 255 and 256, a part of the touch electrode connection line 252 can be electrically connected to a touch drive circuit (not shown) through the touch pad, passing through the upper and side surfaces of the sealing layer 220 and the upper and side surfaces of the dam DAM.

[0114] A part of the touch electrode connection line 252 can be supplied with a touch driving signal from the touch driving circuit and transmitted to the touch electrodes 255 and 256, and the touch sensing signals from the touch electrodes 255 and 256 can also be transmitted to the touch driving circuit.

[0115] A touch protection film 257 can be disposed on the touch electrodes 255 and 256. In the drawings, the touch protection film 257 is shown as being disposed only on the touch electrodes 255 and 256, but it is not limited thereto, and the touch protection film 257 can be extended to before or after the DAM and also disposed on the touch electrode connection line 252.

[0116] Then, a color filter (not shown) can be further disposed on the sealing layer 220. The color filter can be located on the touch layer or between the sealing layer 220 and the touch layer. FIG. 2 shows a detailed layer structure of the display panel, but this is provided merely by way of example, and it should be noted that the embodiments of the present invention are not limited thereto. For example, the layer structure of the display panel can be changed in various ways, and one or more of the buffer layer or the planarization layer can be omitted as necessary.

[0117] The power supply circuit 140 uses a DC-DC converter to generate the DC (or constant voltage) required for driving the pixel array of the display panel 100 and the display panel driving circuit. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply circuit 140 can adjust the level of the DC input voltage applied from a host system (not shown) to generate constant voltages such as the gamma reference voltage VGMA, the gate-on voltage VGH, the gate-off voltage VGL, the pixel driving voltage EVDD, the cathode voltage EVSS, and the initialization voltage Vinit. The gamma reference voltage VGMA is supplied to the data driving circuit 110. The gate-on voltage VGH and the gate-off voltage VGL are supplied to the level shifter 150 and the gate driving circuit 120. Constant voltages such as the pixel driving voltage EVDD, the cathode voltage EVSS, and the initialization voltage Vinit are supplied to the pixel circuit 101 through a power supply line commonly connected to the pixel circuit 101.

[0118] On the other hand, the pixel driving voltage EVDD can also be output from the main power supply of the host system 200 and supplied to the display panel 100. In this case, the power supply circuit 140 does not need to output the pixel driving voltage EVDD.

[0119] The display panel driving circuit writes pixel data of the input video into the pixel circuit of the display panel 100 under the control of the timing controller 130.

[0120] The display panel driving circuit includes a data driving circuit 110 and a gate driving circuit 120.

[0121] The display panel driving circuit may further include a touch sensor driving circuit (not shown) for driving the touch sensor. The data driving circuit 110 and the touch sensor driving circuit (not shown) may be integrated into one drive IC (Integrated Circuit). In mobile devices and wearable devices, the timing controller 130, the power supply circuit 140, the level shifter 150, the data driving circuit 110, the touch sensor driving circuit (not shown), etc. may be integrated into one drive IC.

[0122] The data driving circuit 110 receives the pixel data of the input video as a digital signal from the timing controller 130 and outputs a data voltage. The data driving circuit 110 uses a DAC (Digital to Analog Converter) to convert the pixel data of the input video into a gamma compensation voltage for each frame period and outputs a data voltage Vdata. The gamma reference voltage VGMA is divided into gamma compensation voltages for each gradation through a voltage dividing circuit. The gamma compensation voltages for each gradation are provided to the DAC of the data driving circuit 110. The data voltage Vdata is output from each channel of the data driving circuit 110 through an output buffer.

[0123] Such a data driving circuit 110 may be integrated into a source driver IC (SDIC: Source Driver Integrated Circuit). The source driver IC may be connected to the bonding pads of the display panel 100 by a tape automated bonding (TAB) method or a chip on glass (COG) method. Also, the source driver IC can be implemented by a chip on film (COF) method.

[0124] The gate driving circuit 120 can be formed in the circuit layer CIR on the display panel 100 together with the TFT array and wiring of the pixel array. The gate driving circuit 120 can be disposed on the bezel area which is the non-display area NA of the display panel 100, or can be dispersedly disposed within the pixel array where the input video is reproduced.

[0125] The gate driving circuit 120 can be disposed in the both-side bezel areas BZ of the display panel 100 sandwiching the display area of the display panel, and can supply gate pulses in a double feeding manner from both sides of the gate line 103. In other embodiments, the gate driving circuit 120 can be disposed on either one of the left and right side bezels of the display panel 100, and can supply a gate signal to the gate line 103 in a single feeding manner. The gate driving circuit 120 sequentially outputs pulses of the gate signal to the gate line under the control of the timing controller 130. The gate driving circuit 120 can use a shift register to shift the pulses of the gate signal, thereby sequentially supplying those signals to the gate line 103.

[0126] The gate driving circuit 120 may include a plurality of gate driving units that output pulses of gate signals. When the pixel circuit 101 is as shown in FIG. 4, the gate driving circuit 120, as shown in FIG. 3, includes a first gate driving unit 310 that sequentially outputs a first gate signal SCAN1, a second gate driving unit 320 that sequentially outputs a second gate signal EM1, a third gate driving unit 330 that sequentially outputs a third gate signal SCAN2, a fourth gate driving unit 340 that sequentially outputs a fourth gate signal SCAN3, and a fifth gate driving unit 350 that sequentially outputs a fifth gate signal EM2. Here, the plurality of gate driving units may be implemented by a shift register or an edge trigger. Some of the plurality of gate driving units may be implemented by a shift register, and the rest may be implemented by an edge trigger. In FIG. 3, the gate driving circuit 120 is illustrated as including first to fifth gate driving units, but embodiments of the present invention are not limited thereto, and the gate driving circuit 120 may include a greater or smaller number of gate driving units as needed.

[0127] Here, the second gate signal EM1 and the fifth gate signal EM2 may be emission signals, and the first gate signal SCAN1, the third gate signal SCAN2, and the fourth gate signal SCAN3 may be scan signals.

[0128] Between the fifth gate driving unit 350 that outputs the fifth gate signal EM2, which is an emission signal, and the second gate driving unit 320, the first gate driving unit 310 that outputs the first gate signal SCAN1, which is a scan signal, and the third gate driving unit 330 that outputs the third gate signal SCAN2 may be arranged.

[0129] And between the first gate driving unit 310 that outputs the first gate signal SCAN1, which is a scan signal, and the fourth gate driving unit 340 that outputs the fourth gate signal SCAN3, the second gate driving unit 320 that outputs the second gate signal EM1, which is an emission signal, may be arranged. However, the present invention is not necessarily limited thereto.

[0130] In one embodiment of the present invention, the fifth gate driving unit 350 can also be arranged on the outermost periphery of the gate driving circuit 120.

[0131] And in FIG. 3, the gate driving units 320 and 350 that output the light emission signal and the gate driving units 310, 330, and 340 that output the scan signal are shown to be arranged symmetrically with respect to the display area AA. However, the present invention is not limited thereto, and the gate driving units 320 and 350 that output the light emission signal and the gate driving units 310, 330, and 340 that output the scan signal can also be arranged asymmetrically with respect to the display area AA.

[0132] On the other hand, in FIG. 3, the fourth gate driving unit 340 can be connected to each of the odd-numbered pixel lines and the even-numbered pixel lines one by one, and the first gate driving unit 310, the second gate driving unit 320, the third gate driving unit 330, and the fifth gate driving unit 350 can be commonly connected to two pixel lines.

[0133] The timing controller 130 receives video data and a timing signal synchronized therewith from a host system (not shown). The video data received by the timing controller 130 is a digital signal. The timing controller 130 can switch the video data to a data format used by the data driving circuit 110 and transmit it to the data driving circuit 110. Here, the timing signal may include a vertical synchronization signal, a horizontal synchronization signal, a clock signal, a data enable signal, and the like. Since the vertical period and the horizontal period can be determined from the method of counting the data enable signal, the vertical synchronization signal and the horizontal synchronization signal can be omitted. The data enable signal has a period of one horizontal period (1H).

[0134] Based on the timing signal received from a host system (not shown), the timing controller 130 can generate a data timing control signal for controlling the operation timing of the data driving circuit 110, a gate timing control signal for controlling the operation timing of the gate driving circuit 120, and the like.

[0135] The gate timing control signal generated from the timing controller 130 can be input to the shift register of the gate driving circuit 120 through the level shifter 150. The level shifter 150 can generate a start pulse and a shift clock when the gate timing control signal is input, and provide them to the gate driving circuit 120.

[0136] As described above, the display device including the display panel 100, the display panel driving circuit, and the power supply circuit 140 can be a display device that sufficiently secures the threshold voltage sampling time of the driving element during internal compensation of the pixel circuit 101. Thereby, the display device can be driven at high speed.

[0137] Also, the display device can be a display device in which the number of power lines of the pixel circuit 101 is reduced. Thereby, the display device can be designed with high resolution.

[0138] As described above, in order to sufficiently secure the threshold voltage sampling time of the driving element during internal compensation of the pixel circuit 101 and reduce the number of power lines required during internal compensation, the pixel circuit 101 may include the following configuration.

[0139] FIG. 4 is a circuit diagram exemplarily showing a pixel circuit according to an embodiment of the present invention.

[0140] Referring to FIG. 4, the pixel circuit 101 may include a light emitting element EL, a driving element DT that drives the light emitting element EL, a first capacitor C1, a second capacitor C2, and a plurality of switch elements T1 to T6. Here, the driving element DT and the plurality of switch elements T1 to T6 may be N-channel transistors. And the N-channel transistor may be implemented with an oxide TFT.

[0141] The pixel circuit 101 is connected to a data line DL to which a data voltage Vdata is applied, and gate lines GL1 to GL4 to which gate signals SCAN1, SCAN2, SCAN3, EM1, and EM2 are applied.

[0142] The pixel circuit 101 is connected to a cathode power line PL1 that supplies a cathode voltage EVSS, a drive power line PL2 that supplies a pixel drive voltage EVDD, and an initialization power line PL3 that supplies an initialization voltage Vinit. On the display panel 100, the power lines PL1, PL2, and PL3 can be commonly connected to all pixels.

[0143] The pixel drive voltage EVDD is set to a voltage higher than the maximum voltage (Vdata White Max) of the data voltage Vdata and at which the drive element DT can operate in the saturation region. The initialization voltage Vinit can be set to a voltage lower than the minimum voltage (Vdata Black) of the data voltage Vdata and higher than the cathode voltage EVSS.

[0144] The gate-on voltage VGH can be set to a voltage higher than the pixel drive voltage EVDD, and the gate-off voltage VGL can be set to a voltage lower than the cathode voltage EVSS.

[0145] For example, if the maximum voltage (Vdata White Max) of the data voltage Vdata is 6 [V] and the minimum voltage (Vdata Black) is 1 [V], the pixel drive voltage EVDD can be set within a voltage range of 10 [V] to 16 [V]. The initialization voltage Vinit can be set within a voltage range of 0.5 [V] to 1 [V], and the cathode voltage EVSS can be set within a voltage range of -8 [V] to -0.5 [V].

[0146] The gate-on voltage VGH can be set within a voltage range of 8 [V] to 24 [V], and the gate-off voltage VGL can be set within a voltage range of -5 [V] to -16 [V].

[0147] That is, the magnitude of the voltage applied to the pixel circuit 101 can be such that the gate-on voltage VGH > the pixel driving voltage EVDD > the maximum voltage (Vdata White Max) > the minimum voltage (Vdata Black) > the initialization voltage Vinit > the cathode voltage EVSS > the gate-off voltage VGL.

[0148] The gate signals SCAN1, SCAN2, SCAN3, EM1, and EM2 include pulses that swing between the gate-on voltage VGH and the gate-off voltage VGL. The gate signals SCAN1, SCAN2, SCAN3, EM1, and EM2 include the first gate signal SCAN1, the second gate signal EM1, the third gate signal SCAN2, the fourth gate signal SCAN3, and the fifth gate signal EM2.

[0149] The driving period of the pixel circuit 101 is driven in the order of the initialization period INI, the sampling period SAM, the data writing period WR, and the light emission period EMI. The initialization period INI, the sampling period SAM, the data writing period WR, and the light emission period EMI can be determined by the waveforms of the gate signals SCAN1, SCAN2, SCAN3, EM1, and EM2 as shown in FIG. 5.

[0150] Specifically, during the initialization period INI, the voltages of the first gate signal SCAN1 and the second gate signal EM1 are the gate-on voltage. And the voltages of the third gate signal SCAN2, the fourth gate signal SCAN3, and the fifth gate signal EM2 are the gate-off voltage VGL.

[0151] During the sampling period SAM, the voltages of the first gate signal SCAN1 and the third gate signal SCAN2 are the gate-on voltage VGH. And the voltages of the second gate signal EM1, the fourth gate signal SCAN3, and the fifth gate signal EM2 are the gate-off voltage VGL.

[0152] During the data writing period WR, the voltages of the first gate signal SCAN1, the third gate signal SCAN2, and the fourth gate signal SCAN3 are the gate-on voltage VGH. And the voltages of the second gate signal EM1 and the fifth gate signal EM2 are the gate-off voltage VGL.

[0153] During the light emission period EMI, the voltages of the second gate signal EM1 and the fifth gate signal EM2 are the gate-on voltage VGH. And the voltages of the first gate signal SCAN1, the third gate signal SCAN2, and the fourth gate signal SCAN3 are the gate-off voltage VGL.

[0154] On the other hand, the driving element DT of the pixel circuit 101 generates a current according to the gate-source voltage Vgs to drive the light-emitting element EL. Such a driving element DT includes a first electrode connected to the first node N1, a gate electrode connected to the second node N2, and a second electrode connected to the third node N3. Here, the pixel driving voltage EVDD is applied to the first node N1, and the data voltage Vdata may be applied to the second node N2. Specifically, during the initialization period INI and the light emission period, the pixel driving voltage EVDD is applied to the first node N1, and during the data writing period WR, the data voltage Vdata may be applied to the second node N2.

[0155] The light-emitting element EL may be implemented as an OLED. The light-emitting element EL includes an anode electrode and a cathode electrode, and emits light by the current from the driving element DT. Here, the light-emitting element EL may further include an organic compound layer formed between the anode electrode and the cathode electrode.

[0156] The anode electrode of the light-emitting element EL is connected to the fourth node N4, and the cathode electrode is connected to a cathode power line PL1 that supplies the cathode voltage EVSS. Here, the fourth node N4 may be selectively connected to the third node N3 by turning on and off the sixth switching element T6.

[0157] The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode electrode and the cathode electrode of the light emitting element EL, holes that have passed through the hole transport layer HTL and electrons that have passed through the electron transport layer ETL move to the light emission layer EML, and excitons are formed. At this time, visible light is emitted from the light emission layer EML. The light emitting element EL can be embodied in a tandem structure in which a plurality of light emission layers are stacked. The light emitting element EL having a tandem structure can improve the luminance and lifespan of a pixel.

[0158] The first capacitor C1 is connected between the second node N2 and the fourth node N4, stores the threshold voltage Vth of the driven element DT sampled during the sampling period SAM, and maintains the gate-source voltage Vgs of the driven element DT during the emission period EMI.

[0159] The second capacitor C2 is connected between the data line DL to which the data voltage Vdata is applied and the second node N2. The second capacitor C2 stores the data voltage Vdata applied through the fifth switching element T5 during the data writing period WR and transmits it to the second node N2.

[0160] As a result, during the data writing period WR, the potential of the second node N2 becomes a voltage obtained by adding the voltage applied to the second node N2 during the sampling period SAM and the data voltage Vdata.

[0161] When there is no second capacitor C2 between the second node N2 and the fourth node N4, during the data writing period WR, the data voltage Vdata can be immediately transmitted to the second node N2, and the potential of the second node N2 can be reset to the data voltage Vdata.

[0162] That is, the second capacitor C2 can be a buffer capacitor that prevents the data voltage Vdata from being rapidly transmitted to the second node N2 during the transmission of the data voltage Vdata. Here, the capacitance of the second capacitor C2 may be smaller than the capacitance of the first capacitor C1. For example, the capacitance of the first capacitor C1 is 141 [fF (Femto - Farad)], and the capacitance of the second capacitor C2 may be 135 [fF].

[0163] On the other hand, the switch elements T1 to T6 of the pixel circuit 101 include a first switch element T1 and a second switch element T2 that are turned on in response to the gate - on voltage VGH of the first gate signal SCAN1, a third switch element T3 that is turned on in response to the gate - on voltage VGH of the second gate signal EM1, a fourth switch element T4 that is turned on in response to the gate - on voltage VGH of the third gate signal SCAN2, a fifth switch element T5 that is turned on in response to the gate - on voltage VGH of the fourth gate signal SCAN3, and a sixth switch element T6 that is turned on in response to the gate - on voltage VGH of the fifth gate signal EM2.

[0164] The first switch element T1 is connected between the anode electrode and the cathode electrode of the light - emitting element EL. That is, the first switch element T1 is connected between the fourth node N4 on the anode - electrode side and the cathode - power - supply line PL1 on the cathode - electrode side.

[0165] Specifically, the first electrode of the first switch element T1 is connected to the anode electrode of the light - emitting element EL, that is, the fourth node N4, and the second electrode is connected to the cathode electrode of the light - emitting element EL, that is, the cathode - power - supply line PL1. And the gate electrode is connected to the first gate line GL1, and the first gate signal SCAN1 is applied to the gate electrode.

[0166] The first switch element T1 electrically connects the anode electrode and the cathode electrode in response to the first gate signal SCAN1.

[0167] That is, the first switch element T1 is turned on in response to the gate-on voltage VGH of the first gate signal SCAN1, and applies the cathode voltage EVSS to the fourth node N4.

[0168] Here, the first switch element T1 is turned on until before the light emission period EMI, and the potential of the fourth node N4 is maintained at the cathode voltage EVSS until before the light emission period EMI.

[0169] That is, during the initialization period INI, the sampling period SAM, and the data writing period WR, since the voltage of the first gate signal SCAN1 is the gate-on voltage VGH, the first switch element T1 is turned on during the initialization period INI, the sampling period SAM, and the data writing period WR, and the potential of the fourth node N4 is maintained at the cathode voltage EVSS during the initialization period INI, the sampling period SAM, and the data writing period WR.

[0170] During the light emission period, since the voltage of the first gate signal SCAN1 is the gate-off voltage, during the light emission period, the first switch element T1 is turned off in response to the gate-off voltage.

[0171] The second switch element T2 is connected between the first node N1 and the second node N2.

[0172] Specifically, the first electrode of the second switch element T2 is connected to the first node N1, and the second electrode is connected to the second node N2. And the gate electrode is connected to the first gate line GL1, and the first gate signal SCAN1 is applied to the gate electrode.

[0173] That is, the second switch element T2 shares the first switch element T1 and the first gate signal SCAN1.

[0174] The second switch element T2 is turned on in response to the gate-on voltage VGH of the first gate signal SCAN1.

[0175] Here, the second switch element T2 is turned on until the light emission period EMI, and maintains the driving element DT in a diode connection state until the light emission period EMI.

[0176] That is, during the initialization period INI, the sampling period SAM, and the data writing period WR, since the voltage of the first gate signal SCAN1 is the gate-on voltage VGH, the second switch element T2 is turned on during the initialization period INI, the sampling period SAM, and the data writing period WR, and maintains the driving element DT in a diode connection state during the initialization period INI, the sampling period SAM, and the data writing period WR. Here, the diode connection means that the gate electrode and the first electrode of the driving element DT are connected.

[0177] During the light emission period, since the voltage of the first gate signal SCAN1 is the gate-off voltage, during the light emission period, the second switch element T2 is turned off according to the gate-off voltage.

[0178] The third switch element T3 is connected between the driving power line PL2 that supplies the pixel driving voltage EVDD and the first node N1.

[0179] Specifically, the first electrode of the third switch element T3 is connected to the driving power line PL2, and the second electrode is connected to the first node N1. And the gate electrode is connected to the second gate line GL2, and the second gate signal EM1 is applied to the gate electrode.

[0180] The third switch element T3 is turned on in response to the gate-on voltage VGH of the second gate signal EM1.

[0181] Here, during the initialization period INI and the light emission period EMI, since the voltage of the second gate signal EM1 is the gate-on voltage VGH, the third switch element T3 is turned on only during the initialization period INI and then turned on again during the light emission period EMI.

[0182] The fourth switch element T4 is connected between an initialization power supply line PL3 that supplies an initialization voltage and a third node N3.

[0183] Specifically, a first electrode of the fourth switch element T4 is connected to the initialization power supply line PL3, and a second electrode is connected to the third node N3. And the gate electrode is connected to a third gate line GL3, and a third gate signal SCAN2 is applied to the gate electrode.

[0184] The fourth switch element T4 is turned on in response to a gate-on voltage VGH of the third gate signal SCAN2.

[0185] Here, during a sampling period SAM and a data writing period WR, since the voltage of the third gate signal SCAN2 is the gate-on voltage VGH, the fourth switch element T4 is turned on between the sampling period SAM and the data writing period WR.

[0186] The fifth switch element T5 is connected between a data line DL and a second capacitor C2.

[0187] Specifically, a first electrode of the fifth switch element T5 is connected to the data line DL, and a second electrode is connected to the second capacitor C2. And the gate electrode is connected to a fourth gate line GL4, and a fourth gate signal SCAN3 is applied to the gate electrode.

[0188] The fifth switch element T5 is turned on in response to a gate-on voltage VGH of the fourth gate signal SCAN3.

[0189] Here, during the data writing period WR, since the voltage of the fourth gate signal SCAN3 is the gate-on voltage VGH, the fifth switch element T5 is turned on only during the data writing period WR.

[0190] The sixth switch element T6 is connected between the third node N3 and the fourth node N4.

[0191] Specifically, the first electrode of the sixth switch element T6 is connected to the third node N3, and the second electrode is connected to the fourth node N4. And the gate electrode is connected to the fifth gate line GL5, and the fifth gate signal EM2 is applied to the gate electrode.

[0192] The sixth switch element T6 is turned on in response to the gate-on voltage VGH of the fifth gate signal EM2.

[0193] Here, during the light emission period EMI, since the voltage of the fifth gate signal EM2 is the gate-on voltage VGH, the sixth switch element T6 is turned on only during the light emission period EMI to connect the third node N3 to the fourth node N4.

[0194] During the light emission period EMI, when the third node N3 and the fourth node N4 are connected, a current path is formed between the cathode power line PL1 and the drive power line PL2, and current can flow through the light emitting element EL.

[0195] Hereinafter, the operation of the pixel circuit 101 will be described step by step according to the driving period of the pixel circuit 101.

[0196] FIGS. 6 and 7 are diagrams showing the operation of the pixel circuit during the initialization period shown in FIG. 4. FIGS. 8 and 9 are diagrams showing the operation of the pixel circuit during the sampling period shown in FIG. 4. FIGS. 10 and 11 are diagrams showing the operation of the pixel circuit during the data writing period shown in FIG. 4. FIGS. 12 and 13 are diagrams showing the operation of the pixel circuit during the light emission period shown in FIG. 4.

[0197] Referring to FIGS. 6 and 7, during the initialization period INI, the main nodes of the pixel circuit 101 are initialized. During the initialization period INI, the voltages of the first gate signal SCAN1 and the second gate signal EM1 are the gate-on voltage VGH as shown in FIG. 6. During the initialization period INI, the voltages of the third gate signal SCAN2, the fourth gate signal SCAN3, and the fifth gate signal EM2 are the gate-off voltage VGL.

[0198] Therefore, during the initialization period INI, as shown in FIG. 7, the first switch element T1 and the second switch element T2 are turned on in response to the gate-on voltage VGH of the first gate signal SCAN1, and the third switch element T3 is turned on in response to the gate-on voltage VGH of the second gate signal EM1. Here, when the second switch element T2 is turned on, the driving element DT becomes in a diode-connected state during the initialization period INI.

[0199] On the other hand, the fourth switch element T4, the fifth switch element T5, and the sixth switch element T6 are turned off in response to the gate-off voltage VGL of the third gate signal SCAN2, the fourth gate signal SCAN3, and the fifth gate signal EM2. As a result, during the initialization period INI, the potentials of the first node N1 and the second node N2 are initialized with the pixel driving voltage EVDD, and the potential of the third node N3 becomes a voltage (EVDD - Vth) obtained by subtracting the threshold voltage Vth of the driving element DT from the pixel driving voltage EVDD.

[0200] And the potential of the fourth node N4 is initialized with the cathode voltage EVSS. When the voltage difference between the pixel driving voltage EVDD and the threshold voltage Vth of the driving element DT is higher than the threshold voltage Vth of the driving element DT, the driving element DT can be turned on during the initialization period INI. In an embodiment of the present invention, by applying the cathode voltage EVSS, which is a low voltage, to the anode electrode of the light-emitting element EL, that is, the fourth node N4, during the initialization period INI, it is possible to prevent the light-emitting element EL from emitting light when the second node N2 is initialized with the pixel driving voltage EVDD, which is a high voltage. Here, the reason for the light emission of the light-emitting element EL is due to the coupling phenomenon of the first capacitor C1 that occurs when the second node N2 is initialized with the pixel driving voltage EVDD.

[0201] Referring to FIGS. 8 and 9, during the sampling period SAM, the threshold voltage Vth of the driving element DT is sampled by the first capacitor C1.

[0202] During the sampling period SAM, the voltages of the first gate signal SCAN1 and the third gate signal SCAN2 are the gate-on voltage VGH as shown in FIG. 8. During the sampling period SAM, the voltages of the second gate signal EM1, the fourth gate signal SCAN3, and the fifth gate signal EM2 are the gate-off voltage VGL.

[0203] Therefore, during the sampling period SAM, as shown in FIG. 9, the first switching element T1 and the second switching element T2 maintain the on state in response to the gate-on voltage VGH of the first gate signal SCAN1, and the fourth switching element T4 is turned on in response to the gate-on voltage VGH of the third gate signal SCAN2. Here, due to the turn-on of the second switching element T2, the driving element DT maintains the diode-connected state during the sampling period SAM.

[0204] On the other hand, the third switching element T3, the fifth switching element T5, and the sixth switching element T6 are turned off in response to the gate-off voltage VGL of the second gate signal EM1, the fourth gate signal SCAN3, and the fifth gate signal EM2.

[0205] As a result, during the sampling period SAM, the potentials of the first node N1 and the second node N2 become the voltage (Vinit + Vth) obtained by adding the initialization voltage Vinit and the threshold voltage Vth of the driving element DT, and the potential of the third node N3 becomes the initialization voltage Vinit. And the potential of the fourth node becomes the cathode voltage EVSS.

[0206] In one embodiment of the present invention, by maintaining the potential of the fourth node N4 at the cathode voltage EVSS during the sampling period SAM, it is possible to prevent the voltage of the fourth node N4 from rising. Therefore, it is possible to prevent the voltage of the fourth node N4 from rising and the light-emitting element EL from emitting light during the sampling period SAM.

[0207] Referring to FIGS. 10 and 11, during the data write period WR, the data voltage Vdata of the pixel data is applied to the second node N2. Therefore, the data voltage Vdata compensated for the threshold voltage Vth of the driving element DT can be stored in the first capacitor C1.

[0208] During the data write period WR, the voltages of the first gate signal SCAN1, the third gate signal SCAN2, and the fourth gate signal SCAN3 are the gate-on voltage VGH as shown in FIG. 10. During the data write period WR, the voltages of the second gate signal EM1 and the fifth gate signal EM2 are the gate-off voltage VGL.

[0209] Therefore, during the data write period WR, the first switch element T1 and the second switch element T2 maintain the on state in response to the gate-on voltage VGH of the first gate signal SCAN1 as shown in FIG. 11, and the fourth switch element T4 maintains the on state in response to the gate-on voltage VGH of the third gate signal SCAN2. And the fifth switch element T5 is turned on in response to the gate-on voltage VGH of the fourth gate signal SCAN3. Here, when the second switch element T2 is turned on, during the data write period WR, the driving element DT maintains the diode-connected state.

[0210] On the other hand, the third switch element T3 and the sixth switch element T6 are turned off in response to the gate-off voltage VGL of the second gate signal EM1 and the fifth gate signal EM2.

[0211] As a result, during the data write period WR, the potential of the first node N1 becomes the voltage (Vinit + Vth) obtained by adding the initialization voltage Vinit and the threshold voltage Vth of the driving element DT, and the potential of the second node N2 becomes the voltage (Vinit + Vth + Vdata) obtained by adding the initialization voltage Vinit, the threshold voltage Vth of the driving element DT, and the data voltage Vdata. And the potential of the third node N3 becomes the initialization voltage Vinit, and the potential of the fourth node N4 becomes the cathode voltage EVSS.

[0212] In one embodiment of the present invention, during the data write period WR, by maintaining the potential of the fourth node N4 at the cathode voltage EVSS, it is possible to prevent the voltage of the fourth node N4 from rising. Therefore, during the data write period WR, it is possible to prevent the voltage of the fourth node N4 from rising and the light-emitting element EL from emitting light.

[0213] Referring to FIGS. 12 and 13, during the light emission period EMI, the voltages of the second gate signal EM1 and the fifth gate signal EM2 are the gate-on voltage VGH as shown in FIG. 12. During the light emission period EMI, the voltages of the first gate signal SCAN1, the third gate signal SCAN2, and the fourth gate signal SCAN3 are the gate-off voltage VGL.

[0214] Therefore, during the light emission period EMI, as shown in FIG. 13, the third switch element T3 is turned on in response to the gate-on voltage VGH of the second gate signal EM1, and the sixth switch element T6 is turned on in response to the gate-on voltage VGH of the fifth gate signal EM2.

[0215] On the other hand, the first switch element T1, the second switch element T2, the fourth switch element T4, and the fifth switch element T5 are turned off in response to the gate-off voltage VGL of the first gate signal SCAN1, the third gate signal SCAN2, and the fourth gate signal SCAN3.

[0216] According to the turn-on or turn-off of the switch elements as described above, during the light emission period EMI, a current path is formed between the cathode power line PL1 and the drive power line PL2, and the light-emitting element EL can emit light by the current flowing through the drive element DT. Here, the light-emitting element EL can emit light with a brightness corresponding to the gradation value of the pixel data.

[0217] On one hand, during the emission period EMI, the potential of the first node N1 becomes the pixel driving voltage EVDD, and the potential of the second node N2 becomes the voltage obtained by adding the initialization voltage Vinit, the threshold voltage Vth of the driving element DT, and the data voltage Vdata (Vinit + Vth + Vdata). Then, the potentials of the third node N3 and the fourth node N4 become the initialization voltage Vinit.

[0218] And, during the emission period EMI, the current I flowing through the light emitting element EL oled is determined by the following formula.

[0219]

Equation

[0220] Here, Vgs is the gate-source voltage of the driving element DT, and K means a constant value determined by the mobility and parasitic capacitance of the driving element DT. And, Vinit is the initialization voltage, Vdata is the data voltage, and Vth is the threshold voltage of the driving element DT, respectively.

[0221] During the emission period EMI, since the potential of the second node N2, which is the gate side node of the driving element DT, is Vinit + Vth + Vdata, and the potential of the third node N3 or the fourth node N4, which is the source side node, is Vinit, the gate-source voltage becomes Vinit + Vth + Vdata - Vinit.

[0222] As in Equation 1 above, the current I flowing through the light emitting element EL oled does not reflect the threshold voltage Vth of the driving element DT, and only the data voltage Vdata is reflected. That is, the current I flowing through the light emitting element EL oled is a current in which the threshold voltage Vth of the driving element DT is compensated.

[0223] On the other hand, during the light emission period EMI, one or more of the second gate signal EM1 and the fifth gate signal EM2 can be generated as PWM (Pulse Width Modulation) pulses. The duty ratio of the PWM pulses can vary according to the digital brightness value (DBV: Digital Brigthness Value).

[0224] As described above, in the pixel circuit 101 according to the embodiment of the present invention, the sampling period SAM and the data writing period WR are separated. Therefore, the sampling period SAM can be sufficiently ensured regardless of one horizontal period 1H corresponding to the data writing period WR.

[0225] Also, in the pixel circuit 101 according to an embodiment of the present invention, due to the first switch element T1, the potential of the anode electrode of the light emitting element EL, that is, the fourth node N4, is maintained at the cathode voltage EVSS until before the light emission period EM1. Therefore, another low voltage power supply line such as the reference voltage line VREF does not have to be arranged in the pixel circuit 101. Accordingly, the number of power supply lines required for the pixel circuit 101 can be reduced.

[0226] That is, when another low voltage power supply line such as the reference voltage line VREF is arranged in the pixel circuit, as shown in FIG. 14, the area occupied by the power supply line in the pixel circuit increases. Therefore, the size of the pixel circuit increases, making it difficult to design a high resolution display device. In FIG. 14, the power supply lines can be the cathode power supply line PL1, the drive power supply line PL2, the initialization power supply line PL3, and the reference voltage line PL4 arranged between the first data line DL1, the second data line DL2, and the third data line DL3.

[0227] On the other hand, if another low-voltage power supply line such as the reference voltage line PL4 is not arranged in the pixel circuit, as shown in FIG. 15, the area occupied by the power supply line in the pixel circuit will decrease. As a result, the size of the pixel circuit decreases, facilitating the design of a high-resolution display device. In FIG. 15, the power supply line can be the cathode power supply line PL1, the drive power supply line PL2, and the initialization power supply line PL3 arranged between the first data line DL1, the second data line DL2, and the third data line DL3.

[0228] The structure of the pixel circuit 101 shown in FIG. 4 and the driving timing of the pixel circuit 101 shown in FIG. 5 are provided merely by way of example, and the embodiments of the present invention are not limited thereto. For example, the pixel circuit may include more or fewer transistors and capacitors, and its driving method can be variously changed.

[0229] Hereinafter, in the pixel circuit 101 according to an embodiment of the present invention, a configuration in which the first switch element T1 is connected to the cathode power supply line PL1 will be described.

[0230] FIG. 16 is a diagram schematically showing a configuration in which a cathode power supply line is arranged on a display panel. FIGS. 17 and 18 are diagrams for explaining a configuration in which the first switch element of the pixel circuit according to an embodiment of the present invention is connected to the cathode power supply line.

[0231] Referring to FIG. 16, a first short bar 1622 may be arranged on one side of the substrate 1610 for forming the display panel 100, and a second short bar 1624 may be arranged on the other side of the substrate 1610. Here, one side and the other side of the substrate 1610 may correspond to the non-display area NA of the display panel 100. That is, a first short bar 1622 may be arranged on one side of the non-display area NA, and a second short bar 1624 may be arranged on the other side of the substrate 1610.

[0232] And a plurality of cathode power supply lines 1630 may be arranged between the first short bar 1622 and the second short bar 1624.

[0233] That is, one end of the cathode power line 1630 can be connected to the first short bar 1622, and the other end of the cathode power line 1630 can be connected to the second short bar 1624. Here, the cathode power line 1630 can be arranged in the display area AA of the display panel 100.

[0234] On the other hand, for the first switching element T1 of the pixel circuit 101, as shown in the dotted line portion of FIG. 17, the first electrode is connected to the cathode power line 1630, and the second electrode is connected to the fourth node N4, that is, the anode electrode of the light-emitting element EL.

[0235] In the cross-sectional structure of the display panel 100 as shown in FIG. 18, the first switching element T1 can be arranged in a plurality of insulating layers.

[0236] Specifically, the plurality of insulating layers may include a first insulating layer 1812 covering the multi-buffer layer 1802 laminated on the substrate 1610 of the display panel 100, a second insulating layer 1814 covering the first insulating layer 1812, and a third insulating layer 1816 covering the second insulating layer 1814. Here, the multi-buffer layer 1802 can block moisture and the like that can penetrate from the outside. The multi-buffer layer 1802 can be formed by laminating silicon oxide (SiOx) and silicon nitride (SiNx) in multiple layers, but is not necessarily limited thereto.

[0237] The multi-buffer layer 1802 may include a first buffer layer B1 and a second buffer layer B2. A first - 1 metal layer 1804 and a first - 2 metal layer 1805 may be formed on the first buffer layer B1. And a second - 1 metal layer 1806 and a second - 2 metal layer 1807 may be formed on the second buffer layer B2. The first - 1 metal layer 1804, the second - 1 metal layer 1806, and the first buffer layer B1 which is a dielectric arranged therebetween may form a first capacitor C1. And the second - 1 metal layer 1806, the second - 2 metal layer 1807, and the first buffer layer B1 which is a dielectric arranged therebetween may form a second capacitor C2.

[0238] Either one of the first metal layer 1804 and the second metal layer 1806 can be electrically connected to the second node N2, and the other one can be electrically connected to the fourth node N4.

[0239] Either one of the second metal layer 1806 and the second metal layer 1807 can be electrically connected to the second electrode of the fifth switching element T5, and the other one can be electrically connected to the second node N2.

[0240] The first electrode 1822 and the second electrode 1824 of the first switching element T1 can be disposed on the third insulating layer 1816. And the gate electrode 1826 of the first switching element T1 can be disposed on the second insulating layer 1814, and the semiconductor layer 1828 can be disposed on the first insulating layer 1812. Here, the semiconductor layer 1828 can be made of an oxide semiconductor. The oxide semiconductor material can include at least one or more of an IGZO (InGaZnO)-based oxide semiconductor material, an IZO (InZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, an FIZO (FeInZnO)-based oxide semiconductor material, a ZnO-based oxide semiconductor material, an SIZO (SiInZnO)-based oxide semiconductor material, and a ZnON (Zn-Oxynitride)-based oxide semiconductor material.

[0241] On the other hand, the first electrode 1822 and the second electrode 1824 disposed on the third insulating layer 1816 can be covered by a protective layer 1818 made of an insulating layer.

[0242] The first planarization layer 1832 can cover the protective layer 1818. And the second planarization layer 1834 can cover the first planarization layer 1832.

[0243] The first planarization layer 1832 can planarize the upper part of the first switching element T1 and protect the first switching element T1.

[0244] The second planarization layer 1834 can cover the first planarization layer 1832. And the light-emitting element EL can be disposed on the second planarization layer 1834. Here, the light-emitting element EL may include, but is not necessarily limited to, an anode electrode 1872, an organic compound layer 1874, a cathode electrode 1876, and a bank layer 1878.

[0245] Here, the bank layer 1878 can expose the anode electrode 1872. The bank layer 1878 can change the size and shape of the light-emitting region in each of the pixel circuits. The bank layer 1878 can be formed from a photosensitive organic insulating material or a material containing black, but is not limited thereto. The bank layer 1878 can be composed of at least one or more substances among inorganic insulating substances such as silicon nitride (SiNx) or silicon oxide (SiOx), or organic insulating substances such as BCB (BenzoCycloButene), acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. Such a bank layer 1878 can be disposed on the second planarization layer 1834 so as to cover the edge portion of the anode electrode 1872.

[0246] The organic compound layer 1874 including the light-emitting layer of the light-emitting element EL can cover the anode electrode 1872 and the bank layer 1878. The cathode electrode 1876 of the light-emitting element EL can be disposed on the organic compound layer 1874. The cathode electrode 1876 can be formed from a metal layer having an area the same as or similar to the area of the substrate 1610, and a plurality of pixel circuits can commonly use the cathode electrode 1876.

[0247] A sealing layer can be disposed on the cathode electrode 1876, and a touch sensor layer can be disposed on the sealing layer. Here, the sealing layer can be composed of insulating layers 1882, 1784, 1786 in which at least two or more inorganic films and organic films are laminated.

[0248] In the cross-sectional structure of the display panel 100 as described above, the cathode power line 1630 can be connected to the second electrode 1824 of the first switching element T1 on the third insulating layer 1816.

[0249] That is, the cathode power line 1630, the first electrode 1822 of the first switching element T1, and the second electrode 1824 can be arranged on the third insulating layer 1816. Then, the cathode power line 1630, the first electrode 1822, and the second electrode 1824 can be covered with a protective layer 1818 made of an insulating layer.

[0250] Here, the first electrode 1822 and the second electrode 1824 of the first switching element T1 can be located in the display area AA of the display panel 100.

[0251] And the cathode power line 1630 connected to the second electrode 1824 can be extended to the non-display area NA of the display panel 100.

[0252] In the non-display area NA, the cathode power line 1630 can be brought into contact with the first connection electrode 1852 through a first contact hole 1842 penetrating the first planarization layer 1832. Here, the first connection electrode 1852 is arranged on the first planarization layer 1832 and can be covered with a second planarization layer 1834.

[0253] The cathode electrode 1876 located in the non-display area NA can be brought into contact with the first connection electrode 1852 through a fourth contact hole 1848 penetrating the bank layer 1860 and the second planarization layer 1834.

[0254] Through the above configuration, the cathode power line 1630 connected to the second electrode 1824 can be connected to the cathode electrode 1876. That is, the second electrode 1824 and the cathode electrode 1876 can be connected through the above configuration. Here, the first short bar 1622 or the second short bar 1624 can be composed of the first contact hole 1842, the first connection electrode 1852, and the fourth contact hole 1848 located in the non-display area NA, etc.

[0255] On one hand, in the display area AA, the second connection electrode 1854 can be in contact with the first electrode 1822 of the first switch element T1 through the second contact hole 1844 penetrating the first planarization layer 1832. Here, the second connection electrode 1854 can be disposed on the first planarization layer 1832 and covered with the second planarization layer 1834.

[0256] In the display area AA, the anode electrode 1872 disposed on the second planarization layer 1834 can be in contact with the second connection electrode 1854 through the third contact hole 1846 penetrating the second planarization layer 1834.

[0257] Through the above configuration, the second electrode 1824 and the anode electrode 1872 can be connected. Here, the anode electrode 1872 can correspond to the fourth node N4.

[0258] On one hand, in one embodiment of the present invention, the switch elements T1 to T6 of the pixel circuit 101 have been described as being composed of N-channel transistors, but the present invention is not limited thereto.

[0259] That is, one or more of the switch elements T1 to T6 can also be composed of P-channel transistors.

[0260] For example, as shown in FIG. 19, the first switch element T1, the second switch element T2, the third switch element T3, the fourth switch element T4, and the sixth switch element T6 can be composed of P-channel transistors, and the fifth switch element T5 can be composed of an N-channel transistor.

[0261] In such a case, as shown in FIG. 20, the gate-on voltages of the first gate signal SCAN1, the second gate signal EM1, the third gate signal SCAN2, and the fifth gate signal EM2 can be the gate-low voltage VGL, and the gate-off voltage can be the gate-high voltage VGH.

[0262] As another example, as shown in FIG. 21, the first switch element T1, the second switch element T2, the third switch element T3, and the sixth switch element T6 may be composed of P-channel transistors, and the fourth switch element T4 and the fifth switch element T5 may be composed of N-channel transistors.

[0263] In such a case, as shown in FIG. 22, the gate-on voltages of the first gate signal SCAN1, the second gate signal EM1, and the fifth gate signal EM2 may be the gate-low voltage VGL, and the gate-off voltage may be the gate-high voltage VGH.

[0264] As yet another example, as shown in FIG. 23, the third switch element T3 and the sixth switch element T6 may be composed of P-channel transistors, and the first switch element T1, the second switch element T2, the fourth switch element T4, and the fifth switch element T5 may be composed of N-channel transistors.

[0265] In such a case, as shown in FIG. 24, the gate-on voltages of the second gate signal EM1 and the fifth gate signal EM2 may be the gate-low voltage VGL, and the gate-off voltage may be the gate-high voltage VGH.

[0266] Since the content of the specification describing the problems to be solved, the means for solving the problems, and the effects does not specify the essential features of the claims, the scope of the claims is not limited by the matters described in the content of the specification.

[0267] The embodiments of the present invention have been described in more detail above with reference to the accompanying drawings. However, the present invention is not necessarily limited to such embodiments, and various modifications can be made and implemented without departing from the technical idea of the present invention. Therefore, the embodiments disclosed in the present invention are not for limiting the technical idea of the present invention, but for explanatory purposes, and the scope of the technical idea of the present invention is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are exemplary in all aspects and not restrictive. The protection scope of the present invention should be interpreted by the scope of the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of the rights of the present invention.

Description of Reference Numerals

[0268] 100: Display panel 101: Pixel circuit 102: Data line 103: Gate line 110: Data driving circuit 120: Gate driving circuit 130: Timing controller 140: Power supply circuit 150: Level shifter 1610: Substrate 1630: Cathode power line 1810: Contact hole 1852: First connection electrode 1854: Second connection electrode 1872: Anode electrode

Claims

1. A driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node to which a data voltage is applied, and a second electrode; A light-emitting element including an anode electrode and a cathode electrode, and emitting light by a current from the driving element; A first switch element connected between the anode electrode and the cathode electrode, and electrically connecting the anode electrode and the cathode electrode in response to a first gate signal A pixel circuit including the above.

2. The pixel circuit according to claim 1, wherein the first switch element is turned on until the light-emitting element emits light by the current, and maintains the electrical connection between the anode electrode and the cathode electrode until the light-emitting element emits light.

3. The pixel circuit is driven in the order of an initialization period, a sampling period, a data writing period, and a light-emitting period, The first gate signal is a gate-on voltage during the initialization period, the sampling period, and the data writing period, and is a gate-off voltage during the light-emitting period, The pixel circuit according to claim 1, wherein the first switch element is turned on in response to the gate-on voltage of the first gate signal to electrically connect the anode electrode and the cathode electrode, and is turned off in response to the gate-off voltage of the first gate signal.

4. A first capacitor connected between a fourth node connected to the anode electrode and the second node; A second switch element connected between the first node and the second node, and turned on in response to the gate-on voltage of the first gate signal to electrically connect the first node and the second node; A third switch element turned on in response to the gate-on voltage of a second gate signal to electrically connect a driving power line supplying the pixel driving voltage to the first node; A fourth switch element turned on in response to the gate-on voltage of a third gate signal to electrically connect a third node connected to the second electrode of the driving element and an initialization power line supplying an initialization voltage; A second capacitor connected between a data line to which a data voltage is applied and the second node; A fifth switch element turned on in response to the gate-on voltage of a fourth gate signal to electrically connect the data line and the second capacitor; A sixth switching element that is turned on in response to the gate-on voltage of the fifth gate signal and electrically connects the third node to the fourth node The pixel circuit according to claim 1, further comprising. **Claim 5** The cathode voltage applied from the cathode electrode is a voltage lower than the initialization voltage, and the pixel driving voltage is a voltage higher than the initialization voltage. The pixel circuit according to claim 4. **Claim 6** The pixel circuit is driven in the order of an initialization period, a sampling period, a data writing period, and a light emitting period. During the initialization period, the first gate signal and the second gate signal are gate-on voltages, and the third gate signal, the fourth gate signal, and the fifth gate signal are gate-off voltages. During the sampling period, the first gate signal and the third gate signal are gate-on voltages, and the second gate signal, the fourth gate signal, and the fifth gate signal are gate-off voltages. During the data writing period, the first gate signal, the third gate signal, and the fourth gate signal are gate-on voltages, and the second gate signal and the fifth gate signal are gate-off voltages. During the light emitting period, the second gate signal and the fifth gate signal are gate-on voltages, and the first gate signal, the third gate signal, and the fourth gate signal are gate-off voltages. The pixel circuit according to claim 4. **Claim 7** The first switching element and the second switching element are turned on during the initialization period, the sampling period, and the data writing period. The pixel circuit according to claim 6. **Claim 8** The third switching element is turned on during the initialization period and the light emitting period, and the fourth switching element is turned on during the sampling period and the data writing period. The pixel circuit according to claim 6. **Claim 9** The fifth switching element is turned on during the data writing period, and the sixth switching element is turned on during the light emitting period. The pixel circuit according to claim 6. **Claim 10** A display panel in which a plurality of data lines, a plurality of gate lines, a plurality of pixel circuits, a cathode power line for supplying a cathode voltage to the pixel circuit, a driving power line for supplying a pixel driving voltage to the pixel circuit, and an initialization power line for supplying an initialization voltage to the pixel circuit are arranged. A data driving circuit that outputs data voltages of pixel data to the plurality of data lines, a gate driving circuit that sequentially outputs gate signals to the plurality of gate lines and the pixel circuit includes a driving element including a first electrode connected to a first node to which the pixel driving voltage is applied, a gate electrode and a second electrode connected to a second node to which the data voltage is applied, a light emitting element including an anode electrode and a cathode electrode connected to the cathode power line, and emitting light by a current from the driving element, and a first switch element connected between the anode electrode and the cathode electrode and electrically connecting the anode electrode and the cathode electrode in response to a first gate signal a display device. **Claim 11** The display device according to claim 10, further including a second switch element connected between the first node and the second node and electrically connecting the first node and the second node in response to the first gate signal. **Claim 12** The pixel circuit is driven in the order of an initialization period, a sampling period, a data writing period, and a light emitting period, the first gate signal is a gate-on voltage during the initialization period, the sampling period, and the data writing period, and is a gate-off voltage during the light emitting period, the first switch element is turned on in response to the gate-on voltage of the first gate signal to electrically connect the anode electrode and the cathode electrode, and is turned off in response to the gate-off voltage of the first gate signal, the second switch element is turned on in response to the gate-on voltage of the first gate signal to electrically connect the first node and the second node, and is turned off in response to the gate-off voltage of the first gate signal, according to the display device of claim 11. **Claim 13** a first capacitor connected between a fourth node connected to the anode electrode and the second node, a third switch element that is turned on in response to the gate-on voltage of a second gate signal and electrically connects the driving power line to the first node, a fourth switch element that is turned on in response to the gate-on voltage of a third gate signal and electrically connects a third node connected to the second electrode of the driving element and the initialization power line, a second capacitor connected between a data line to which a data voltage is applied and the second node A fifth switching element that is turned on in response to the gate-on voltage of the fourth gate signal and electrically connects the data line and the second capacitor; A sixth switching element that is turned on in response to the gate-on voltage of the fifth gate signal and electrically connects the third node to the fourth node, the display device according to claim 11.

14. The pixel circuit is driven in the order of an initialization period, a sampling period, a data writing period, and the light emitting period. In the initialization period, the first gate signal and the second gate signal are gate-on voltages, and the third gate signal, the fourth gate signal, and the fifth gate signal are gate-off voltages. In the sampling period, the first gate signal and the third gate signal are gate-on voltages, and the second gate signal, the fourth gate signal, and the fifth gate signal are gate-off voltages. In the data writing period, the first gate signal, the third gate signal, and the fourth gate signal are gate-on voltages, and the second gate signal and the fifth gate signal are gate-off voltages. In the light emitting period, the second gate signal and the fifth gate signal are gate-on voltages, and the first gate signal, the third gate signal, and the fourth gate signal are gate-off voltages, the display device according to claim 13.

15. A display area where an input video is displayed; A non-display area outside the display area; A plurality of cathode power lines arranged in the display area; A plurality of pixel circuits arranged in the display area including Each of the pixel circuits includes a light emitting element that includes an anode electrode and a cathode electrode and emits light by current from a driving element; A first switching element including a first electrode connected to the anode electrode, a second electrode connected to the cathode electrode, and a gate electrode to which a scan signal is applied including A display panel in which the cathode electrode of the light emitting element and the second electrode of the first switching element are connected to the corresponding cathode power line.

16. A first short bar disposed on one side of the non-display area and connected to one end of each of the cathode power lines; A second short bar disposed on the other side of the non-display area and connected to the other end of each of the cathode power lines; The display panel according to claim 15, further comprising.

17. An insulating layer covering the first electrode, the second electrode of the first switch element, and the cathode power line; A first planarization layer covering the insulating layer; A first connection electrode that contacts the cathode power line in the non-display region through a first contact hole penetrating the first planarization layer; A second connection electrode that contacts the first electrode of the first switch element in the display region through a second contact hole penetrating the first planarization layer; A second planarization layer covering the first connection electrode and the second connection electrode; A bank layer covering the second planarization layer; Further comprising; The anode electrode contacts the second connection electrode in the display region through a third contact hole penetrating the second planarization layer; The cathode electrode contacts the first connection electrode through a fourth contact hole penetrating the bank layer and the second planarization layer, the display panel according to claim 15.

18. A driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node to which a data voltage is applied, and a second electrode; A light-emitting element including an anode electrode connected to a fourth node and a cathode electrode connected to a cathode power line; A first switch element including a first electrode connected to the fourth node, a gate electrode connected to a first gate line, and a second electrode connected to the gate electrode; A first capacitor connected between the fourth node and the second node; A second switch element including a first electrode connected to the first node, a gate electrode connected to the first gate line, and a second electrode connected to the second node; A third switch element including a first electrode connected to a driving power line for supplying the pixel driving voltage, a gate electrode connected to a second gate line, and a second electrode connected to the first node; A fourth switch element including a first electrode connected to an initialization power line for supplying an initialization voltage, a gate electrode connected to a third gate line, and a second electrode connected to a third node; A second capacitor connected between a data line to which a data voltage is applied and the second node; A fifth switch element including a first electrode connected to the data line, a gate electrode connected to a fourth gate line, and a second electrode connected to the second capacitor; A sixth switch element including a first electrode connected to the third node, a gate electrode connected to the fifth gate line, and a second electrode connected to the fourth node, and A pixel circuit including the same.

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