Image sensor

Abstract

To provide an image sensor.SOLUTION: An image sensor according to the present invention comprises: a top layer that includes a first FD wiring structure coupled with a floating diffusion node, and a first shield structure that is arranged on the first FD wiring structure side; an intermediate layer that is bonded to and below the top layer, and includes a source follower gate, a source follower source region, a second FD wiring structure coupled with the first FD wiring structure and the source follower gate, a second shield structure coupled with the first shield structure and the source follower source region, and a source follower landing pad arranged interposed between the second shield structure and the source follower source region, and spaced apart from the source follower gate; and a bottom layer that is bonded to and below the intermediate layer. The bottom layer includes: a third substrate; and transistors that are arranged on the third substrate.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to an image sensor, and more particularly, to an image sensor capable of improving conversion gain.

Background Art

[0002] Image sensors that capture images and convert them into electrical signals are used not only in general consumer electronic devices such as digital cameras, mobile phone cameras, and portable camcorders, but also in cameras mounted on automobiles, security devices, and robots. In image sensors, pixels are gradually becoming smaller, and as the pixels are miniaturized, the capacitance of the floating diffusion increases. Therefore, it is necessary to improve the phenomenon that the conversion gain becomes smaller.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The problem to be solved by the present invention is to provide an image sensor capable of improving conversion gain.

Means for Solving the Problems

[0004] To solve the above-described problems, an image sensor according to an embodiment of the technical idea of the present invention includes: a top layer including a first substrate, a floating diffusion node disposed in the first substrate, a first FD wiring structure connected to the floating diffusion node, and a first shield structure disposed on the first FD wiring structure side; a second substrate, a source follower gate disposed on the second substrate, a source follower source region disposed in the second substrate, a second FD wiring structure connected to the first FD wiring structure and the source follower gate, a second shield structure connected to the first shield structure and the source follower source region, and a source follower landing pad interposed between the second shield structure and the source follower source region and disposed at a distance from the source follower gate; an intermediate layer bonded to the top layer below the top layer; and a bottom layer bonded to the intermediate layer below the intermediate layer. The bottom layer may include a third substrate and a transistor disposed on the third substrate.

[0005] An image sensor according to an embodiment of the technical idea of the present invention includes: a top layer including a first substrate, a floating diffusion node disposed in the first substrate, a first FD wiring structure connected to the floating diffusion node, and a first shield structure disposed on the first FD wiring structure side; an intermediate layer bonded to the top layer below the top layer, including a second substrate having a second front surface and a second back surface corresponding to the second front surface, a source follower gate disposed on the second front surface of the second substrate, a source follower source region disposed in the second substrate, a second FD wiring structure connected to the first FD wiring structure and the source follower gate, and a second shield structure connected to the first shield structure and the source follower source region; a bottom layer bonded to the intermediate layer below the intermediate layer, including a third substrate and a transistor disposed on the third substrate, wherein the second shield structure may include a second shield bonding pad bonded to a first shield bonding pad included in the first shield structure, and an impurity region disposed in the second substrate and connected to the second shield bonding pad.

[0006] An image sensor according to an embodiment of the technical idea of the present invention includes a first substrate, a pixel isolation layer disposed in the first substrate to define pixels, a photodiode disposed in the first substrate to form pixels, a transmission transistor for sending an electrical signal generated by the photodiode, a floating diffusion node disposed in the first substrate and connected to the transmission transistor, a first FD wiring structure connected to the floating diffusion node, and a first shield structure disposed on the side of the first FD wiring structure, and a top layer including a first wiring layer disposed at a distance from the first FD wiring structure and the first shield structure; a second substrate, a source follower gate disposed on the second substrate, a source follower source region disposed in the second substrate, a second FD wiring structure connected to the first FD wiring structure and the source follower gate, a second shield structure connected to the first shield structure and the source follower source region, and a source follower landing pad interposed between the second shield structure and the source follower source region and surrounding the source follower gate, and a second wiring layer disposed at a distance from the second FD wiring structure and the second shield structure, an intermediate layer bonded to the top layer below the top layer; a bottom layer bonded to the intermediate layer below the intermediate layer; and the bottom layer may include a third substrate, a transistor disposed on the third substrate, a third wiring layer connected to the transistor, and a third via plug disposed between the transistor and the third wiring layer.

Brief Description of the Drawings

[0007]

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Embodiments for Carrying Out the Invention

[0008] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments of the present invention can be embodied by any one of them or by a combination of one or more. Therefore, the technical idea of the present invention should not be construed as being limited to one embodiment.

[0009] In this specification, the singular form of a component may include a plurality of forms unless otherwise clearly indicated in the context. In this specification, the drawings are exaggerated for illustrative purposes to explain the invention more clearly. In this specification, the order such as first, second, etc. is for convenience of explanation and is not limited thereto.

[0010] FIG. 1 is a block diagram showing an image sensor according to an embodiment of the technical idea of the present invention.

[0011] Specifically, the image sensor 100 may include a pixel array 110, a row driver 120, a lamp signal generator 130, a counting code generator 140, an analog-digital conversion circuit 150 (hereinafter referred to as an ADC circuit), a data output circuit 180, and a timing controller 190. The image sensor 100 may further include a signal processing unit 195. The configuration including the ADC circuit 150 and the data output circuit 180 may be referred to as a lead-out circuit.

[0012] The pixel array 110 may include a plurality of row lines RL and a plurality of column lines CL. The pixel array 110 may be connected to the plurality of row lines RL and the plurality of column lines CL and include a plurality of pixels PX arranged in a matrix. The plurality of pixels PX are also APS (active pixel sensors).

[0013] Each of the plurality of pixels PX includes at least one photoelectric conversion element. The pixel PX can sense light using the photoelectric conversion element and output an image signal that is an electrical signal converted from the sensed light. For example, the photoelectric conversion element may include a photo diode, a phototransistor, a photogate, or a pinned photo diode, etc.

[0014] Each of the plurality of pixels PX can sense light in a specific spectral region. For example, among the plurality of pixels PX, some can convert light in the red spectral region into an electrical signal, convert light in the green spectral region into an electrical signal, or convert light in the blue spectral region into an electrical signal. However, it is not limited thereto, and at least some of the plurality of pixels can convert light in the white spectral region into an electrical signal.

[0015] As another example, at least some of the plurality of pixels PX can convert light in other color spectral regions into electrical signals. For example, at least some of the plurality of pixels PX can convert light in any one spectral region of yellow, cyan, or magenta into an electrical signal.

[0016] On top of each of the plurality of pixels PX, a color filter for transmitting light in a specific spectral region may be arranged. The hue that the pixel PX can perceive may be determined by the color filter. However, the present disclosure is not limited thereto. In some embodiments, a specific photoelectric conversion element can also convert light in a specific wavelength band into an electrical signal according to the level of the electrical signal applied to the photoelectric conversion element.

[0017] In some embodiments, each of the plurality of pixels PX has a dual conversion gain. The dual conversion gain includes a low conversion gain and a high conversion gain. Here, the conversion gain means the ratio at which the charge accumulated in the floating diffusion node (or floating diffusion region) is converted into a voltage. The charge generated by the photoelectric conversion element is transmitted to and accumulated in the floating diffusion node FD, and the charge accumulated in the floating diffusion node FD can be converted into a voltage by the conversion gain. At this time, the conversion gain is variable according to the capacitance of the floating diffusion node FD. If the capacitance increases, the conversion gain decreases, and if the capacitance decreases, the conversion gain may increase.

[0018] The row driver 120 drives the pixel array 110 in row units. The row driver 120 can decode the row control signal (e.g., address signal) received from the timing controller 190. The load driver 120 can select at least one of the plurality of row lines RL constituting the pixel array 110 in response to the decoded row control signal.

[0019] For example, the row driver 120 can generate a selection signal for selecting one of a plurality of rows. The selection signal can be transmitted to the pixel array 110 via the row line RL. The pixel array 110 outputs pixel signals (e.g., pixel voltages) from the row selected by the selection signal provided from the row driver 120. The pixel signals can include a reset signal and an image signal. The row driver 120 can transmit a control signal to the pixel array 110. The control signal is also a signal for outputting the pixel signals. The pixel PX can output the pixel signals by operating in response to the control signal.

[0020] The ramp signal generator 130 can generate a ramp signal (e.g., ramp voltage) whose level rises or falls at a predetermined gradient under the control of the timing controller 190. The ramp signal RAMP can be provided to each of a plurality of correlated double sampling (CDS) circuits 160 provided in the ADC circuit 150.

[0021] The counting code generator 140 can generate a counting code CCD under the control of the timing controller 190. The counting code CCD can be provided to each of a plurality of counter circuits 170. In some embodiments, the counting code generator 140 can be implemented by a gray code generator. The counting code generator 140 can generate a plurality of code values with a resolution according to the set number of bits as the counting code CCD. For example, when a 10-bit code is set, the counting code generator 140 can generate a counting code CCD including 1024 code values that sequentially increase or decrease.

[0022] The ADC circuit 150 may include a plurality of CDS circuits 160 and a plurality of counter circuits 170. The ADC circuit 150 can convert a pixel signal input from the pixel array 110 into a pixel value which is a digital signal. Each pixel signal received via each of the plurality of column lines CL is converted into a pixel value which is a digital signal by the CDS circuit 160 and the counter circuit 170.

[0023] The CDS circuit 160 can compare a pixel signal received via a column line CL with a ramp signal RAMP and output a comparison result as a comparison result signal. The CDS circuit 160 can output a comparison signal that transitions from a first level (e.g., logic high) to a second level (e.g., logic low) when the level of the ramp signal RAMP is the same as the level of the pixel signal. The time point at which the level of the comparison signal transitions can be determined by the level of the pixel signal.

[0024] The CDS circuit 160 can sample a pixel signal provided from a pixel PX by a Correlated Double Sampling method. The CDS circuit 160 can sample a reset signal received as a pixel signal, compare the reset signal with the ramp signal RAMP, and generate a comparison signal based on the reset signal. Thereafter, the CDS circuit 160 can sample an image signal correlated with the reset signal, compare the image signal with the ramp signal RAMP, and generate a comparison signal based on the image signal.

[0025] The counter circuit 170 can count the time point of the level transition of the comparison result signal output from the CDS circuit 160 and output a count value. In some embodiments, the counter circuit 170 may include a latch circuit and an arithmetic circuit. The latch circuit can receive a counting code CCD from the counting code generator 140 and a comparison signal from the CDS circuit 160, and latch the code value of the counting code CCD when the level of the comparison signal transitions.

[0026] The latch circuit can latch the code value corresponding to the reset signal. For example, the latch circuit can latch the reset value and the code value corresponding to the image signal respectively. For example, the latch circuit can latch the image signal value. The arithmetic circuit can perform an operation on the reset value and the image signal value to generate an image signal value with the reset level of pixel PX removed. The counter circuit 170 can output the image signal value with the reset level removed as a pixel value.

[0027] In this embodiment, the image sensor 100 includes a counting code generator 140, and the counter circuit 170 has been described as including a circuit that latches the code value of the counting code CCD received from the counting code generator 140, but it is not limited thereto.

[0028] In some embodiments, the image sensor 100 does not include a separate counting code generator 140, and the counter circuit 170 can also be implemented by an up-counter, an arithmetic circuit, an up / down counter, or a bit-wise inversion counter in which the count value sequentially increases based on the counting clock signal provided by the timing controller 190.

[0029] The data output circuit 180 can temporarily store the pixel value output from the ADC circuit 150 and then output it. The data output circuit 180 can include a plurality of column memories 181 and a column decoder 182. The column memory 181 stores the pixel value received from the counter circuit 170. In some embodiments, each of the plurality of column memories 181 can be provided in the counter circuit 170. The plurality of pixel values stored in the plurality of column memories 181 can be output as image data IDT under the control of the column memory 181.

[0030] The timing controller 190 outputs control signals to the loud driver 120, the lamp signal generator 130, the counting code generator 140, the ADC circuit 150, and the data output circuit 180 respectively, and can control the operations or timings of the loud driver 120, the lamp signal generator 130, the counting code generator 140, the ADC circuit 150, and the data output circuit 180.

[0031] The signal processing unit 195 can perform noise reduction processing, gain adjustment, waveform shaping processing, interpolation processing, white balance processing, gamma processing, edge enhancement processing, binning, etc. on the image data. In some embodiments, the signal processing unit 195 can also be provided in an external processor of the image sensor 100.

[0032] FIG. 2 is a circuit diagram of an image sensor according to an embodiment of the technical idea of the present invention.

[0033] Referring to FIG. 2, the image sensor 100 may include a plurality of photodiodes PD, a plurality of transmission transistors TX, a floating diffusion node FD, a conversion gain transistor DCG, a reset transistor RX, a source follower transistor SF, and a selection transistor SEL.

[0034] Each of the transmission transistor TX, the conversion gain transistor DCG, the reset transistor RX, the source follower transistor SF, and the selection transistor SEL may include a transmission gate TG, a conversion gain gate, a reset gate, a source follower gate SFG, and a selection gate.

[0035] In some embodiments, the transmission gate TG is also a vertical gate. In some embodiments, each of the conversion gain gate, the reset gate, the source follower gate SFG, and the selection gate is also a planar gate.

[0036] The photodiode PD can generate charges in proportion to the amount of incident light. The photodiode PD can generate electrons, which are negative charges, and holes, which are positive charges, in response to the incident light.

[0037] In some embodiments, eight photodiodes PD can be provided. The eight photodiodes PD can share one floating diffusion node FD, a reset transistor RX, a conversion gain transistor DCG, a source follower transistor SF, and a selection transistor SEL. However, the provision of eight photodiodes PD is only one example, and the number of photodiodes PD is not limited thereto.

[0038] The transmission gate TG is disposed between the photodiode PD and the floating diffusion node FD, and can transmit the charges generated by the photodiode PD to the floating diffusion node FD. The transmission transistor TX can include the transmission gate TG, a drain region connected to the photodiode PD, and a source region connected to the floating diffusion node FD.

[0039] The conversion gain transistor DCG can include a conversion gain gate, a source region connected to the drain region of the reset transistor RX, and a source region connected to the floating diffusion node FD.

[0040] The conversion gain transistor DCG can change the capacitance of the floating diffusion node FD by a conversion gain signal. When the conversion gain transistor DCG is turned on, the capacitance increases, so the image sensor 100 can operate in a low conversion gain mode. Conversely, when the conversion gain transistor DCG is turned off, the capacitance decreases, so the image sensor 100 can operate with a high conversion gain.

[0041] The reset transistor RX may include a reset gate, a source region connected to the power supply voltage Vpix, and a drain region connected to the source region of the conversion gain transistor DCG. When the reset transistor RX is turned on by a reset control signal and the conversion gain transistor DCG is turned on by a conversion gain signal, the floating diffusion node FD can be reset based on the power supply voltage Vpix. Specifically, the charge accumulated in the floating diffusion node FD can be discharged and the floating diffusion node FD can be reset. At this time, a reset signal corresponding to the voltage level of the floating diffusion node FD can be output.

[0042] The source follower transistor SF may include a source follower gate SFG to which the floating diffusion node FD is connected, a source follower source region SFS connected to the source region of the selection transistor SEL, and a drain region to which the power supply voltage Vpix is connected.

[0043] The potential of the floating diffusion node FD changes according to the amount of charge accumulated in the floating diffusion node FD, and the source follower transistor SF can amplify the potential change at the floating diffusion node FD and output it to the source follower source region SFS.

[0044] A gate-source capacitance Cgs can be formed between the source follower transistor SF and the floating diffusion node FD. The gate-source capacitance Cgs is distinguished from the parasitic capacitance applied to the floating diffusion node FD. The gate-source capacitance Cgs can reduce the value of the parasitic capacitance applied to the floating diffusion node FD. As a result, the conversion gain can be increased by the gate-source capacitance Cgs.

[0045] The selection transistor SEL may include a selection gate, a source region connected to the source of the source follower transistor SF, and a drain region to which the output voltage line Vout is connected.

[0046] FIG. 3 is a schematic cross-sectional view for explaining the structure of an image sensor according to an embodiment of the technical idea of the present invention.

[0047] Specifically, the image sensor EX1 is also an embodiment in which the image sensor 100 of FIG. 1 is embodied. The image sensor EX1 may include the pixel PX of FIG. 1. The image sensor EX1 may include a top layer 200, an intermediate layer 300, and a bottom layer 400.

[0048] In the image sensor EX1, the intermediate layer 300 and the top layer 200 may be stacked on the bottom layer 400. The image sensor EX1 may be composed of three layers in which the intermediate layer 300 and the top layer 200 are stacked on the bottom layer 400. The image sensor EX1 may be composed of three layers in which the bottom layer 400, the intermediate layer 300, and the top layer 200 are bonded to each other. The image sensor EX1 may include a floating diffusion wiring structure (hereinafter, FD wiring structure) FLS and a shield structure SHS.

[0049] Hereinafter, the transistors to be described may include planar transistors, MBC (multi bridge channel) transistors, GAA (gate all around) transistors, or Fin FET transistors (field effect transistors).

[0050] The top layer 200 may include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first floating diffusion wiring structure (hereinafter, first FD wiring structure) 210, and a first shield structure 220.

[0051] The first substrate 201 is also a semiconductor substrate or a SOI (Silicon on insulator) substrate. The semiconductor substrate may include, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first substrate 201 may include a first front surface 201f and a first back surface 201b corresponding to the first front surface 201f. A photodiode (PD in FIG. 2, not shown in FIG. 3) may be disposed on the first substrate 201.

[0052] In some embodiments, one photodiode (PD in FIG. 2) may be disposed corresponding to one color filter 217 and one lens 219. In some embodiments, a plurality of photodiodes (PD in FIG. 2) may be disposed corresponding to one color filter 217 and one lens 219.

[0053] The color filter 217 and the lens 219 may be disposed on the first back surface 201b of the first substrate 201. The color filter 217 and the lens 219 may be sequentially stacked on the first back surface 201b of the first substrate 201.

[0054] A pixel isolation layer 215 may be disposed in the first substrate 201. The pixel isolation layer 215 can perform a function of separating a plurality of pixels PX in FIG. 1 from each other. The pixel isolation layer 215 may include two or more substances. The pixel isolation layer 215 may include, for example, a semiconductor substance and an insulating substance having a refractive index different from that of the first substrate 201. The semiconductor substance may include, for example, a polysilicon film doped with impurities or a silicon-germanium film. The impurities doped in the polysilicon or the silicon-germanium film are, for example, one of boron, phosphorus, and arsenic. The insulating substance may include, for example, silicon oxide. The pixel isolation layer 215 may include a metal film instead of the semiconductor substance.

[0055] The first transistor 203 can be arranged on the first front surface 201f. For example, the first transistor 203 can include, but is not limited to, a transmission transistor (TX in FIG. 2). When the first transistor 203 corresponds to the transmission transistor (TX in FIG. 2), a part of the first source and drain regions constituting the first transistor 203 is also a floating diffusion node FD. The other part of the first source and drain regions is omitted for the sake of convenience.

[0056] In this specification, the first horizontal direction D1 is in a direction parallel to the first front surface 201f of the first substrate 201, the second horizontal direction D2 is parallel to the first front surface 201f of the first substrate 201 and in a direction intersecting the first horizontal direction D1, and the vertical direction Z is defined in a direction perpendicular to the first front surface 201f of the first substrate 201.

[0057] The first contact plug 206 and the first wiring layer 205 can be connected to the first transistor 203. The first contact plug 206 and the first wiring layer 205 can be arranged on the first front surface 201f of the first substrate 201. A plurality of the first wiring layers 205 can be provided. Among the plurality of first wiring layers 205, two different first wiring layers 205 can be located at different vertical levels. That is, the plurality of first wiring layers 205 can form a multilayer structure.

[0058] In this specification, the "vertical level" is defined as the height in the vertical direction Z from an arbitrary point to a specific point. For example, the vertical level of the first wiring layer 205 is also the height in the vertical direction Z from the third back surface 401b of the third substrate 401 to the first wiring layer 205.

[0059] In this specification, the expression "is connected to" corresponds to a concept that not only means that a configuration is in direct contact with a different configuration, but also includes being indirectly connected through other configurations. Further, the expression "is connected to" corresponds to a concept that includes the electrical connection between one configuration and another configuration.

[0060] The first contact plug 206 can connect at least two first wiring layers 205 at different vertical levels to each other. The first contact plug 206 can connect the first wiring layer 205 and the first front bonding pad 204 to each other. The first front bonding pad 204 can be disposed below the uppermost layer 200. The first front bonding pad 204 can be connected to the second front bonding pad 304. The first wiring layer 205 and the first contact plug 206 can be connected to the second front bonding pad 304 via the first front bonding pad 204. The first wiring layer 205, the first contact plug 206, and the first front bonding pad 204 can include a metal, for example, copper (Cu) or tungsten (W).

[0061] The floating diffusion node FD can be disposed in the first substrate 201. The floating diffusion node FD can correspond to the floating diffusion node FD in FIG. 2. The floating diffusion node FD is also a region doped with impurities in the first substrate 201. The impurities can include a P-type or N-type conductivity type.

[0062] The first via plug 213 can be connected to the floating diffusion node FD. The first via plug 213 can be disposed on the first front surface 201f of the first substrate 201. The first via plug 213 can include a metal, for example, copper or tungsten.

[0063] The first FD wiring structure 210 can be connected to the first via plug 213. The first FD wiring structure 210 can be disposed on the first front surface 201f of the first substrate 201. The first FD wiring structure 210 can be connected to the floating diffusion node FD via the first via plug 213. The first FD wiring structure 210 can be connected to the floating diffusion node FD.

[0064] The first FD wiring structure 210 may include a first FD wiring layer 207, a first FD plug 208, and a first FD bonding pad 209. A plurality of the first FD wiring layers 207 may be provided. Among the plurality of first FD wiring layers 207, two different first FD wiring layers 207 may be located at different vertical levels from each other. That is, the plurality of first FD wiring layers 207 may form a multilayer structure. At least one layer among the plurality of first FD wiring layers 207 and at least one layer among the plurality of first wiring layers 205 may be located at the same vertical level as each other.

[0065] The first FD plug 208 may connect at least two layers of the first FD wiring layer 207 at different vertical levels to each other. The first FD plug 208 may connect the first FD wiring layer 207 and the first FD bonding pad 209 to each other. The first FD bonding pad 209 may be disposed below the uppermost layer 200. The first FD wiring layer 207 and the first FD plug 208 may be connected to the second FD bonding pad 309 via the first FD bonding pad 209. The first FD wiring layer 207, the first FD plug 208, and the first FD bonding pad 209 may include a metal, for example, copper or tungsten.

[0066] FIG. 4 is a plan view seen along the line X-X' of FIG. 3.

[0067] Referring to FIGS. 3 and 4, the first shield structure 220 may be disposed on the first front surface 201f of the first substrate 201. The first shield structure 220 may include a first shield wiring layer 221, a first shield plug 222, and a first shield bonding pad 223.

[0068] A plurality of first shield wiring layers 221 can be provided. Among the plurality of first shield wiring layers 221, two different first shield wiring layers 221 can be located at different vertical levels. That is, the plurality of first shield wiring layers 221 can form a multilayer structure. At least one of the plurality of first shield wiring layers 221 and at least one of the plurality of first wiring layers 205 can be located at the same vertical level.

[0069] The first shield plug 222 can connect at least two layers of first shield wiring layers 221 at different vertical levels to each other. The first shield plug 222 can connect the first shield wiring layer 221 and the first shield bonding pad 223 to each other. The first shield bonding pad 223 can be disposed below the uppermost layer 200. The first shield wiring layer 221 and the first shield plug 222 can be connected to the second shield bonding pad 323 via the first shield bonding pad 223. The first shield wiring layer 221, the first shield plug 222, and the first shield bonding pad 223 can include a metal, for example, copper or tungsten.

[0070] The first shield structure 220 can be separated from the first FD wiring structure 210 in the first horizontal direction D1 and the second horizontal direction D2. The first shield structure 220 can be separated from the first wiring layer 205 and the first contact plug 206 in the first horizontal direction D1 and the second horizontal direction D2. The first shield structure 220 can surround the floating diffusion node FD and the first FD wiring structure 210. Specifically, the first shield wiring layer 221 can surround a first FD wiring layer 207 at a vertical level such as the first shield wiring layer 221. The plurality of first shield wiring layers 221 can be respectively disposed at all vertical levels where the plurality of first FD wiring layers 207 are respectively disposed. Therefore, all of the plurality of first FD wiring layers 207 can be surrounded by at least one first shield wiring layer 221.

[0071] Referring to FIG. 3, a first insulating layer 211 may be disposed on a first front surface 201f of the first substrate 201. A first wiring layer 205, a first contact plug 206, a first FD wiring structure 210, a first shield structure 220, and a first via plug 213 may be disposed within the first insulating layer 211. However, the first insulating layer 211 does not cover the lower surfaces of the first front bonding pad 204, the first FD bonding pad 209, and the first shield bonding pad 223. The first insulating layer 211 may have a single-layer or multi-layer structure. The first insulating layer 211 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0072] The intermediate layer 300 may include a second substrate 301, a plurality of second transistors 303, a source follower gate SFG, a source follower source region SFS, a source follower via SFV, a back bonding through via 330, a second wiring layer 305, a second contact plug 306, a second front bonding pad 304, a second via plug 313, a second floating diffusion wiring structure (hereinafter, second FD wiring structure) 310, a second shield structure 320, and a second insulating layer 311.

[0073] The first front bonding pad 204 included in the topmost layer 200 may be bonded to the second front bonding pad 304 included in the intermediate layer 300. The first FD bonding pad 209 included in the topmost layer 200 may be bonded to the second FD bonding pad 309 included in the intermediate layer 300. The first shield bonding pad 223 included in the topmost layer 200 may be bonded to the second shield bonding pad 323 included in the intermediate layer 300. The first insulating layer 211 included in the topmost layer 200 may be bonded to the second insulating layer 311 included in the intermediate layer 300. The topmost layer 200 and the intermediate layer 300 may have a boundary surface F-F where the front surface F and the front surface F are bonded.

[0074] The second substrate 301 is also a semiconductor substrate or an SOI (Silicon on insulator) substrate. The semiconductor substrate may include, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The second substrate 301 may include a second front surface 301f and a second back surface 301b corresponding to the second front surface 301f. A second transistor 303 may be formed on the second front surface 301f.

[0075] A second transistor 303 may be disposed on the second front surface 301f. The second transistor 303 may include any one of the transistors described in FIG. 2, excluding the source follower transistor (SF in FIG. 2). For example, the second transistor 303 may include any one of a conversion gain transistor (DCG in FIG. 2), a reset transistor (RX in FIG. 2), or a selection transistor (SEL in FIG. 2). In FIG. 3, the second source and drain regions constituting the second transistor 303 are disposed within the second substrate 301, but are omitted for convenience.

[0076] A source follower gate SFG constituting a source follower transistor (SF in FIG. 2) may be disposed on the second front surface 301f. A source follower source region SFG constituting the source follower transistor (SF in FIG. 2) may be disposed within the second substrate 301. The source follower source region SFG is also a region doped with impurities within the second substrate 301. The impurities may include P-type or N-type conductivity types.

[0077] A back bonding through via 330 may be disposed within a through via hole VHO penetrating the second substrate 301. The back bonding through via 330 may be separated from the second substrate 301 with the second insulating layer 311 interposed therebetween.

[0078] The second contact plug 306 and the second wiring layer 305 can be connected to the second transistor 303 via the second via plug 313. The second contact plug 306, the second wiring layer 305, and the second via plug 313 can be disposed on the second front surface 301f of the second substrate 301. The second wiring layer 305 can be provided with a plurality of layers. Among the plurality of second wiring layers 305, two different second wiring layers 305 from each other can be located at different vertical levels. That is, the plurality of second wiring layers 305 can form a multilayer structure.

[0079] The second contact plug 306 can connect at least two layers of the second wiring layer 305 at different vertical levels to each other. The second contact plug 306 can connect the second wiring layer 305 and the second front bonding pad 304 to each other. The second front bonding pad 304 can be disposed on the upper part of the intermediate layer 300. The second front bonding pad 304 can be connected to the first front bonding pad 204. The second wiring layer 305 and the second contact plug 306 can be connected to the first front bonding pad 204 via the second front bonding pad 304. The second wiring layer 305, the second contact plug 306, the second via plug 313, and the second front bonding pad 304 can include a metal, for example, copper or tungsten.

[0080] The second FD wiring structure 310 can be connected to the second via plug 313. The second FD wiring structure 310 can be disposed on the second front surface 301f of the second substrate 301. The second FD wiring structure 310 can be connected to the source follower gate SFG via the second via plug 313. The second FD wiring structure 310 can be connected to the source follower gate SFG.

[0081] The second FD wiring structure 310 may include a second FD wiring layer 307, a second FD plug 308, and a second FD bonding pad 309. The second FD wiring layer 307 may be provided in multiple layers. Among the multiple second FD wiring layers 307, two different second FD wiring layers 307 may be located at different vertical levels. That is, the multiple second FD wiring layers 307 may form a multilayer structure. At least one layer among the multiple second FD wiring layers 307 and at least one layer among the multiple second wiring layers 305 may be located at the same vertical level.

[0082] The second FD plug 308 can connect at least two second FD wiring layers 307 at different vertical levels to each other. The second FD plug 308 can connect the second FD wiring layer 307 and the second FD bonding pad 309 to each other. The second FD bonding pad 309 may be disposed on the upper part of the intermediate layer 300. The second FD bonding pad 309 can connect the second FD wiring layer 307 and the second FD plug 308 to the first FD bonding pad 209. The second FD wiring layer 307, the second FD plug 308, and the second FD bonding pad 309 may include a metal, for example, copper or tungsten.

[0083] Referring to FIGS. 3 and 4, the second shield structure 320 may be disposed on the second front surface 301f of the second substrate 301. The second shield structure 320 may include a second shield wiring layer 321, a second shield plug 322, and a second shield bonding pad 323.

[0084] The second shield wiring layer 321 may be provided in multiple layers. Among the multiple second shield wiring layers 321, two different second shield wiring layers 321 may be located at different vertical levels. That is, the multiple second shield wiring layers 321 may form a multilayer structure. At least one layer among the multiple second shield wiring layers 321 and at least one layer among the multiple second wiring layers 305 may be located at the same vertical level.

[0085] The second shield plug 322 can connect at least two second shield wiring layers 321 at different vertical levels to each other. The second shield plug 322 can connect the second shield wiring layer 321 and the second shield bonding pad 323 to each other. The second shield bonding pad 323 can be disposed on the upper part of the intermediate layer 300. The second shield wiring layer 321 and the second shield plug 322 can be connected to the first shield bonding pad 223 via the second shield bonding pad 323. The second shield wiring layer 321, the second shield plug 322, and the second shield bonding pad 323 can include a metal, for example, copper or tungsten.

[0086] The second shield structure 320 can be separated from the second FD wiring structure 310 in the first horizontal direction D1 and the second horizontal direction D2. The second shield structure 320 can be separated from the second wiring layer 305 and the second contact plug 306 in the first horizontal direction D1 and the second horizontal direction D2. The second shield structure 320 can surround the second FD wiring structure 310. Specifically, the second shield wiring layer 321 can surround a second FD wiring layer 307 at a vertical level such as the second shield wiring layer 321. The plurality of second shield wiring layers 321 can be respectively disposed at all vertical levels where the plurality of second FD wiring layers 307 are respectively disposed. Accordingly, all of the plurality of second FD wiring layers 307 can be surrounded by at least one second shield wiring layer 321.

[0087] The second shield structure 320 can be connected to the source follower source region SFS via the source follower via SFV. The second shield structure 320 can be connected to the source follower source region SFS.

[0088] Referring to FIG. 3, a second insulating layer 311 can be disposed on the second front surface 301f of the second substrate 301. The second insulating layer 311 can also be interposed between the back bonding through-via 330 and the second substrate 301. A second wiring layer 305, a second contact plug 306, a second FD wiring structure 310, a second shield structure 320, and a second via plug 313 can be disposed within the second insulating layer 311. However, the second insulating layer 311 does not cover the upper surfaces of the second front bonding pads 304, the second FD bonding pads 309, and the second shield bonding pads 323. The second insulating layer 311 can have a single-layer or multi-layer structure. The second insulating layer 311 can include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0089] Referring to FIGS. 3 and 4, the first FD wiring structure 210 and the second FD wiring structure 310 can together constitute an FD wiring structure FLS. The first shield structure 220 and the second shield structure 320 can together constitute a shield structure SHS.

[0090] The FD wiring structure FLS can be connected to a floating diffusion node FD and a source follower gate SFG. The shield structure SHS can be connected to a source follower source region SFS. The shield structure SHS can surround the floating diffusion node FD and the FD wiring structure FLS. In a plan view, the floating diffusion node FD0 and the FD wiring structure FLS can be disposed within the shield structure SHS.

[0091] Referring to FIG. 3 again, the bottom layer 400 can include a third substrate 401, a plurality of third transistors 403, a third wiring layer 405, a third contact plug 406, a third front bonding pad 409, a third via plug 413, and a third insulating layer 411.

[0092] The back bonding through-via 330 included in the intermediate layer 300 can be bonded to the third front bonding pad 409 included in the bottommost layer 400. The second substrate 301 and the second insulating layer 311 included in the intermediate layer 300 can be bonded to the third insulating layer 411 included in the bottommost layer 400. The intermediate layer 300 and the bottommost layer 400 can have an interface B-F where the back surface B and the front surface F are bonded.

[0093] The third substrate 401 is also a semiconductor substrate or an SOI (Silicon on insulator) substrate. The semiconductor substrate can include, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The third substrate 401 can include a third front surface 401f and a third back surface 301b corresponding to the third front surface 401f. The third transistor 403 can be disposed on the third front surface 401f. In FIG. 3, the fourth source and drain regions constituting the third transistor 403 are disposed within the third substrate 401, but are omitted here for the sake of convenience.

[0094] The third contact plug 406 and the third wiring layer 405 can be connected to the third transistor 403 via the third via plug 413. The third wiring layer 405 can be connected to the third front bonding pad 409 via the third contact plug 406. The third contact plug 406 and the third wiring layer 405 can be connected to the third front bonding pad 409. The third front bonding pad 409, the third wiring layer 405, the third contact plug 406, and the third via plug 413 can include a metal, for example, copper or tungsten.

[0095] The third insulating layer 411 can be disposed on the third front surface 401f of the third substrate 401. The third wiring layer 405, the third contact plug 406, and the third via plug 413 can be disposed within the third insulating layer 411. However, the third insulating layer 411 does not cover the upper surface of the third front bonding pad 409. The third insulating layer 411 can have a single-layer or multi-layer structure. The third insulating layer 411 can include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0096] The image sensor EX1 according to the technical idea of the present invention may include a floating diffusion node FD, an FD wiring structure FLS connected to the floating diffusion node FD and a source follower gate SFG, and a shield structure SHS connected to a source follower source region SFS. The shield structure SHS may be separated from the floating diffusion node FD and the FD wiring structure FLS in a first horizontal direction D1 and a second horizontal direction D2. The shield structure SHS may surround the floating diffusion node FD and the FD wiring structure FLS. Thereby, capacitance may be formed between the FD wiring structure FLS and the shield structure SHS. The capacitance may correspond to the gate-source capacitance Cgs described with reference to FIG. 2. By forming the gate-source capacitance Cgs of FIG. 2 between the FD wiring structure FLS and the shield structure SHS, the conversion gain may be improved.

[0097] FIG. 5 is a plan view seen along the line X-X' of FIG. 3. Hereinafter, the arrangement of the shield structure SHS will be described based on FIGS. 3 and 5. Hereinafter, only the content different from the content described with reference to FIGS. 3 and 4 will be described, and the remaining overlapping content will be omitted.

[0098] Referring to FIGS. 3 and 5, the shield structure SHS does not surround the floating diffusion node FD and the FD wiring structure FLS. The first shield structure 220 included in the shield structure SHS is disposed on both side surfaces of the FD wiring structure FLS and extends in the second horizontal direction D2. Alternatively, the first shield structure 220 included in the shield structure SHS is disposed on both side surfaces of the FD wiring structure FLS and extends in the first horizontal direction D1.

[0099] The second shield structure 320 included in the shield structure SHS is disposed on both side surfaces of the FD wiring structure FLS and extends in the second horizontal direction D2. Or, the second shield structure 320 included in the shield structure SHS is disposed on both side surfaces of the FD wiring structure FLS and extends in the first horizontal direction D1. The first shield structure 220 and the second shield structure 320 may or may not overlap in the vertical direction Z. However, the first shield structure 220 and the second shield structure 320 can be connected to each other.

[0100] Alternatively, each of the first shield structure 220 and the second shield structure 320 is disposed only on one of the side surfaces of the FD wiring structure FLS and extends in the first horizontal direction D1 or the second horizontal direction D2. Even in that case, capacitance can be formed between the shield structure FLS including the first shield structure 220 and the second shield structure 320 and the FD wiring structure FLS.

[0101] Although not shown, the first shield structures 220 disposed on both sides of the FD wiring structure FLS can be connected to each other. Although not shown, the second shield structures 220 disposed on both sides of the FD wiring structure FLS can be connected to each other.

[0102] In the image sensor EX1 according to the technical idea of the present invention, the shield structure SHS does not surround the FD wiring structure FLS. Each of the first and second shield structures 220 and 320 of the shield structure SHS can be disposed only on both side surfaces or one of the side surfaces of the FD wiring structure FLS. Therefore, the area occupied by the shield structure SHS in the image sensor EX1 is reduced. And even in that case, capacitance is formed between the shield structure SHS and the FD wiring structure FLS, and the conversion gain can be improved. For the reasons as above, the integration degree and the conversion gain of the image sensor EX1 can be improved.

[0103] FIG. 6 is a schematic cross-sectional view for explaining the structure of an image sensor according to an embodiment of the technical idea of the present invention.

[0104] Specifically, the image sensor EX2 is also an embodiment that implements the image sensor 100 in FIG. 1. The image sensor EX2 may include the pixel PX in FIG. 1. When the image sensor EX2 is compared with the image sensor EX1 in FIG. 3, it is substantially the same except that the top layer 200 is different. In FIG. 6, the content described in FIGS. 3 and 4 will be briefly described or omitted.

[0105] The image sensor EX2 may include a top layer 200, an intermediate layer 300, and a bottom layer 400. The image sensor EX2 may be composed of three layers in which the bottom layer 400, the intermediate layer 300, and the top layer 200 are bonded to each other.

[0106] The top layer 200 may include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shield structure 220.

[0107] The first FD wiring structure 210 may include a first FD wiring layer 207, a first FD plug 208, and a first FD bonding pad 209. The first FD wiring layer 207 may be provided with a plurality of layers. Among the plurality of first FD wiring layers 207, two different first FD wiring layers 207 may be located at different vertical levels. That is, the plurality of first FD wiring layers 207 may form a multilayer structure.

[0108] For example, any one of the plurality of first FD wiring layers 207 may be arranged at the first vertical level LV1, and any other one of them may be arranged at the second vertical level LV2. The first vertical level LV1 and the second vertical level LV2 may be located between the first front surface 201f of the first substrate 201 and the bottom surface of the top layer 200. The second vertical level LV2 may be different from the first vertical level LV1. For example, the second vertical level LV2 may be lower than the first vertical level LV1.

[0109] Any one of the plurality of first wiring layers 205 may be disposed at the first vertical level LV1, and any other one may be disposed at the second vertical level LV2. Although not shown, there may be other vertical levels where the first FD wiring layer 207 and the first wiring layer 205 are disposed, in addition to the first vertical level LV1 and the second vertical level LV2. This may vary depending on the design of the image sensor EX2 to be fabricated.

[0110] The first shield structure 220 may include a first shield wiring layer 221, a first shield plug 222, and a first shield bonding pad 223. The first shield wiring layer 221 is disposed in some but not all of the vertical levels where the first FD wiring layer 207 is disposed. For example, as shown in FIG. 6, the first shield wiring layer 221 is disposed at the first vertical level LV1 and not at the second vertical level LV2. The first shield bonding pad 223 and the first shield wiring layer 221 disposed at the first vertical level LV1 may be connected via the first shield plug 222. The first shield wiring layer 221 disposed at the first vertical level LV1 may surround the first FD wiring structure 210.

[0111] In FIG. 6, only the arrangement of the first shield wiring layer 221 constituting the top layer 200 is shown, but the description regarding the first shield wiring layer 221 can be similarly applied to the second shield wiring layer 321 constituting the intermediate layer 300. That is, the second shield wiring layer 321 is disposed in some but not all of the vertical levels where the second FD wiring layer 307 is disposed. This may vary depending on the design of the image sensor EX2 to be fabricated. However, for the sake of simplicity of explanation, detailed description of the second shield wiring layer 321 and the second FD wiring layer 307 is omitted.

[0112] The first shield wiring layer 221 of the image sensor EX2 according to the technical idea of the present invention is disposed in a part of the vertical level where the first FD wiring layer 207 is disposed, and is not disposed in another part. For example, the first shield wiring layer 221 is disposed in the first vertical level LV1 and is not disposed in the second vertical level LV2. On the other hand, the first shield wiring layer 221 may be omitted at a specific vertical level. Thus, whether to omit the first shield wiring layer 221 can be determined by the integration degree of a plurality of wirings disposed in each vertical level. Even in that case, capacitance can be formed between the shield structure SHS and the FD wiring structure FLS. Therefore, while improving the conversion gain of the image sensor EX2, the wiring freedom can be increased at the same time.

[0113] FIG. 7 is a schematic cross-sectional view for explaining the structure of an image sensor according to an embodiment of the technical idea of the present invention.

[0114] Specifically, the image sensor EX3 is also an embodiment in which the image sensor 100 of FIG. 1 is embodied. The image sensor EX3 may include the pixel PX of FIG. 1. When the image sensor EX3 is compared with the image sensor EX1 of FIG. 3, it is substantially the same except that the uppermost layer 200 and the intermediate layer 300 are different. In FIG. 7, the contents described in FIGS. 3 and 4 are briefly described or omitted.

[0115] Referring to FIG. 7, the image sensor EX3 may include an uppermost layer 200, an intermediate layer 300, and a lowermost layer 400. The image sensor EX3 may be composed of three layers in which the lowermost layer 400, the intermediate layer 300, and the uppermost layer 200 are bonded to each other.

[0116] The uppermost layer 200 may include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel separation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shield structure 220.

[0117] The first FD wiring structure 210 may include a first FD wiring layer 207, a first FD plug 208, and a first FD bonding pad 209. The first FD wiring layer 207 may be provided in a plurality of layers. Among the plurality of first FD wiring layers 207, two different first FD wiring layers 207 may be located at different vertical levels. That is, the plurality of first FD wiring layers 207 may form a multilayer structure.

[0118] For example, any one of the plurality of first FD wiring layers 207 may be disposed at a first vertical level LV1, and any other one of them may be disposed at a second vertical level LV2. The first vertical level LV1 and the second vertical level LV2 may be located between the first front surface 201f of the first substrate 201 and the lowermost surface of the uppermost layer 200. The second vertical level LV2 may be different from the first vertical level LV1. For example, the second vertical level LV2 may be lower than the first vertical level LV1.

[0119] Any one of the plurality of first wiring layers 205 may be disposed at a first vertical level LV1, and any other one of them may be disposed at a second vertical level LV2. Although not shown, in addition to the first vertical level LV1 and the second vertical level LV2, there may be other vertical levels at which the first FD wiring layer 207 and the first wiring layer 205 are disposed. This may vary depending on the design of the image sensor EX2 to be fabricated.

[0120] The first shield structure 220 may include a first shield wiring layer 221, a first shield plug 222, and a first shield bonding pad 223. The first shield wiring layer 221 may be provided in a plurality of layers. Any one of the first shield wiring layers 221 may be disposed at a first vertical level LV1, and any other one of them may be disposed at a second vertical level LV2.

[0121] The horizontal width of the first shield wiring layer 221 disposed at the first vertical level LV1 may be different from the horizontal width of the first shield wiring layer 221 disposed at the second vertical level LV2. The horizontal width of the first shield wiring layer 221 means the width of the first shield wiring layer 221 in the first horizontal direction D1 or the second horizontal direction D2.

[0122] In FIG. 7, although it is illustrated that the horizontal widths of the first shield wiring layers 221 at different vertical levels are different from each other, the horizontal widths of the first shield wiring layers 221 at the same vertical level are also different from each other.

[0123] The intermediate layer 300 may include a second substrate 301, a plurality of second transistors 303, a source follower gate SFG, a source follower source region SFS, a source follower via SFV, a back bonding through via 330, a second wiring layer 305, a second contact plug 306, a second front bonding pad 304, a second via plug 313, a second FD wiring structure 310, a second shield structure 320, and a second insulating layer 311.

[0124] The second FD wiring structure 310 may include a second FD wiring layer 307, a second FD plug 308, and a second FD bonding pad 309. Multiple layers of the second FD wiring layer 307 may be provided. Among the multiple second FD wiring layers 307, two different second FD wiring layers 307 may be located at different vertical levels from each other. That is, the multiple second FD wiring layers 307 may form a multilayer structure.

[0125] For example, any one of the multiple second FD wiring layers 307 may be arranged at the third vertical level LV3, and any other one of them may be arranged at the fourth vertical level LV4. The third vertical level LV3 and the fourth vertical level LV4 may be located between the topmost surface of the intermediate layer 300 and the second front surface 301f of the second substrate 301. The third vertical level LV3 may be different from the fourth vertical level LV4. For example, the fourth vertical level LV4 may be lower than the third vertical level LV3.

[0126] Any one of the plurality of second wiring layers 305 may be arranged at the third vertical level LV3, and any other one of them may be arranged at the fourth vertical level LV4. Although not shown, there may be other vertical levels where the second FD wiring layer 307 and the second wiring layer 305 are arranged, in addition to the third vertical level LV3 and the fourth vertical level LV4. This may vary depending on the design of the image sensor EX3 to be fabricated.

[0127] The second shield structure 320 may include a second shield wiring layer 321, a second shield plug 322, and a second shield bonding pad 323. A plurality of layers of the second shield wiring layer 321 may be provided. Any one of the second shield wiring layers 321 may be arranged at the third vertical level LV3, and any other one of them may be arranged at the fourth vertical level LV4.

[0128] The minimum distance between the second FD wiring layer 307 arranged at the third vertical level LV3 and the second shield wiring layer 321 arranged at the third vertical level LV3 is also the first distance L1. The first distance L1 is also the distance in the first horizontal direction D1 or the second horizontal direction D2. The maximum distance between the second FD wiring layer 307 arranged at the third vertical level LV3 and the second shield wiring layer 321 arranged at the third vertical level LV3 is also the second distance L2. The second distance L2 is also the distance in the first horizontal direction D1 or the second horizontal direction D2.

[0129] The horizontal distance between the second FD wiring layer 307 arranged at the fourth vertical level LV4 and the second shield wiring layer 321 arranged at the third vertical level LV3 is also the third distance L3. The third distance L3 is also the distance in the first horizontal direction D10 or the second horizontal direction D2. The third distance L3 is also variable.

[0130] The first distance L1 and the second distance L2 can be different from each other. That is, at the same vertical level, the horizontal distance between the second FD wiring layer 307 and the second shield wiring layer 321 can also be variable. Also, the third distance L3 can be different from the first distance L1 and the second distance L2. That is, at other vertical levels, the horizontal distance between the second FD wiring layer 307 and the second shield wiring layer 321 can also be variable. On the other hand, the horizontal distance between the FD wiring structure FLS and the shield structure SHS can also be variable.

[0131] The image sensor EX3 according to the technical idea of the present invention can include an FD wiring structure FLS and a shield structure SHS. The horizontal distance between the FD wiring structure FLS and the shield structure SHS can also be variable. Even in that case, capacitance can be formed between the shield structure SHS and the FD wiring structure FLS. Therefore, the conversion gain of the image sensor EX3 can be improved, and the wiring degree of freedom can be increased.

[0132] FIG. 8 is a schematic cross-sectional view for explaining the structure of an image sensor according to an embodiment of the technical idea of the present invention. FIG. 9 is a plan view seen along the Y-Y' line of FIG. 8.

[0133] Specifically, the image sensor EX4 is also an embodiment in which the image sensor 100 of FIG. 1 is implemented. The image sensor EX4 can include the pixel PX of FIG. 1. When the image sensor EX4 is compared with the image sensor EX1 of FIG. 3, it is substantially the same except that the intermediate layer 300 is different. In FIGS. 8 and 9, the content described in FIGS. 3 and 4 will be briefly described or omitted.

[0134] Referring to FIGS. 8 and 9, the image sensor EX4 can include a top layer 200, an intermediate layer 300, and a bottom layer 400. The image sensor EX4 can be composed of three layers in which the bottom layer 400, the intermediate layer 300, and the top layer 200 are bonded to each other.

[0135] The uppermost layer 200 may include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shield structure 220.

[0136] The intermediate layer 300 may include a second substrate 301, a plurality of second transistors 303, a source follower gate SFG, a source follower source region SFS, a source follower via SFV, a source follower landing pad SLP, a back bonding through via 330, a second wiring layer 305, a second contact plug 306, a second front bonding pad 304, a second via plug 313, a second FD wiring structure 310, a second shield structure 320, and a second insulating layer 311.

[0137] The source follower landing pad SLP may be interposed between the source follower source region SFS and the source follower via SFV. The source follower landing pad SLP may connect the source follower source region SFS and the source follower via SFV. At least a part of the source follower landing pad SLP may be inserted into the source follower source region SFS. The shield structure SHS may be connected to the source follower source region SFS via the source follower via SFV and the source follower landing pad SLP. The shield structure SHS may be connected to the source follower source region SFS.

[0138] The vertical level of the upper surface of the source follower landing pad SLP is also substantially the same as the vertical level of the upper surface of the second transistor 303 and the vertical level of the upper surface of the source follower gate SFG. In this specification, the expression "substantially the same" means, of course, not mathematically the same, but also a concept including the error range in the process. The upper surface of the source follower landing pad SLP may be coplanar with the upper surface of the second transistor 303 and the upper surface of the source follower gate SFG.

[0139] In a plan view, the source follower landing pad SLP can surround the source follower gate SFG. The source follower landing pad SLP can include various shapes such as a polygon, a circle, or an ellipse in a plan view. The source follower landing pad SLP can be separated from the source follower gate SFG in a first horizontal direction D1 and a second horizontal direction D2.

[0140] The source follower landing pad SLP can include the same material as the material included in the source follower gate SFG. The source follower landing pad SLP and the source follower gate SFG can include the same material as each other. The source follower landing pad SLP can include a conductive material. For example, the source follower landing pad SLP can include polycrystalline silicon doped with impurities.

[0141] The image sensor EX4 according to the technical idea of the present invention can include a source follower landing pad SLP interposed between a source follower source region SFS and a source follower via SFV. The source follower landing pad SLP can connect the shield structure SHS and the source follower source region SFS. In a plan view, the source follower landing pad SLP can surround the source follower gate SFG. Therefore, capacitance can also be formed between the source follower gate SFG and the source follower landing pad SLP, and between the source follower gate SFG and the shield structure SHS. As a result, the capacitance formed between the shield structure SHS and the FD wiring structure FLS becomes even larger. Therefore, the conversion gain of the image sensor EX4 can be further improved.

[0142] FIG. 10 is a schematic cross-sectional view for explaining the structure of an image sensor according to an embodiment of the technical idea of the present invention.

[0143] Specifically, the image sensor EX5 is an embodiment that implements the image sensor 100 of FIG. 1. The image sensor EX5 may include the pixel PX of FIG. 1. When compared with the image sensor EX5 of FIG. 10, the image sensor EX5 is substantially the same except that the intermediate layer 300 is different. In FIG. 10, the content described in FIGS. 8 and 9 will be briefly described or omitted.

[0144] Referring to FIG. 10, the top layer 200 may include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shield structure 220.

[0145] The intermediate layer 300 may include a second substrate 301, an element isolation film STI, a plurality of second transistors 303, a source follower gate SFG, a source follower source region SFS, a source follower via SFV, a source follower landing pad SLP, a back bonding through via 330, a second wiring layer 305, a second contact plug 306, a second front bonding pad 304, a second via plug 313, a second FD wiring structure 310, a second shield structure 320, and a second insulating layer 311.

[0146] The element isolation film STI may be disposed within the second substrate 301. The element isolation film STI enables electrical insulation between the plurality of second transistors 303. In one embodiment, the element isolation film STI may be disposed in contact with the source follower source region SFS. The element isolation film STI may be inserted downward in the vertical direction Z from the second front surface 301f of the second substrate 301.

[0147] A source follower landing pad SLP can be interposed between a source follower source region SFS and a source follower via SFV. The source follower landing pad SLP can connect the source follower source region SFS and the source follower via SFV. At least a part of the source follower landing pad SLP can be inserted into the source follower source region SFS. At least another part of the source follower landing pad SLP can be inserted into the element isolation film STI. The source follower landing pad SLP can be disposed on the source follower source region SFS and on the element isolation film STI. The source follower landing pad SLP can contact the source follower source region SFS and the element isolation film STI simultaneously.

[0148] FIG. 11 is a schematic cross-sectional view for explaining the structure of an image sensor according to an embodiment of the technical idea of the present invention.

[0149] Specifically, the image sensor EX6 is an embodiment in which the image sensor 100 of FIG. 1 is embodied. The image sensor EX6 can include the pixel PX of FIG. 1. When the image sensor EX6 is compared with the image sensor EX1 of FIG. 3, it is substantially the same except that the uppermost layer 200 is different. In FIG. 11, the contents described in FIGS. 3 and 4 will be briefly described or omitted.

[0150] Referring to FIG. 11, the image sensor EX6 can include an uppermost layer 200, an intermediate layer 300, and a lowermost layer 400. The image sensor EX6 can be composed of three layers in which the lowermost layer 400, the intermediate layer 300, and the uppermost layer 200 are bonded to each other.

[0151] The uppermost layer 200 can include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shield structure 220.

[0152] The first FD wiring structure 210 may include a first FD wiring layer 207, a first FD plug 208, and a first FD bonding pad 209. A plurality of first FD wiring layers 207 may be provided. Among the plurality of first FD wiring layers 207, two different first FD wiring layers 207 may be located at different vertical levels from each other. That is, the plurality of first FD wiring layers 207 may form a multilayer structure.

[0153] For example, any one of the plurality of first FD wiring layers 207 may be disposed at the first vertical level LV1, and any other one of them may be disposed at the second vertical level LV2. The first vertical level LV1 and the second vertical level LV2 may be located between the first front surface 201f of the first substrate 201 and the lowermost surface of the uppermost layer 200. The second vertical level LV2 may be different from the first vertical level LV1. For example, the second vertical level LV2 may be lower than the first vertical level LV1.

[0154] Any one of the plurality of first wiring layers 205 may be disposed at the first vertical level LV1, and any other one of them may be disposed at the second vertical level LV2. Although not shown, in addition to the first vertical level LV1 and the second vertical level LV2, there may be other vertical levels where the first FD wiring layer 207 and the first wiring layer 205 are disposed. This may vary depending on the design of the image sensor EX6 to be fabricated.

[0155] Unlike the image sensor EX1 in FIG. 3, the first shield structure 220 of the image sensor EX6 in FIG. 6 does not include a first shield wiring layer (221 in FIG. 3) and a first shield plug (222 in FIG. 3). Therefore, the first shield wiring layer (221 in FIG. 3) may be omitted at the first vertical level LV1 and the second vertical level LV2. The first shield structure 220 may include only the first shield bonding pad 223.

[0156] Even when the first shield structure 220 includes only the first shield bonding pad 223, a capacitance can be formed between the shield structure SHS and the FD wiring structure FLS. Therefore, the conversion gain of the image sensor EX6 can be improved, and the wiring freedom of the image sensor EX6 can be increased.

[0157] FIG. 12 is a schematic cross-sectional view for explaining the structure of an image sensor according to an embodiment of the technical idea of the present invention.

[0158] Specifically, the image sensor EX7 is an embodiment in which the image sensor 100 of FIG. 1 is implemented. The image sensor EX7 may include the pixel PX of FIG. 1. When the image sensor EX7 is compared with the image sensor EX1 of FIG. 3, it is substantially the same except that the uppermost layer 200 and the intermediate layer 300 are different. In FIG. 12, the content described in FIGS. 3 and 4 will be briefly described or omitted.

[0159] Referring to FIG. 12, the image sensor EX7 may include an uppermost layer 200, an intermediate layer 300, and a lowermost layer 400. The image sensor EX7 may be composed of three layers in which the lowermost layer 400, the intermediate layer 300, and the uppermost layer 200 are bonded to each other.

[0160] The uppermost layer 200 may include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shield structure 220.

[0161] The intermediate layer 300 may include a second substrate 301, a plurality of second transistors 303, a source follower gate SFG, a source follower source region SFS, a source follower via SFV, a back bonding pad 332, a second wiring layer 305, a second contact plug 306, a second front bonding pad 304, a second via plug 313, a second FD wiring structure 310, a second shield structure 320, a second connection via plug 340, and a second insulating layer 311.

[0162] The first front bonding pad 204 included in the topmost layer 200 may be bonded to the back bonding pad 332 included in the intermediate layer 300. The first insulating layer 211 included in the topmost layer 200 may be bonded to the second insulating layer 311 included in the intermediate layer 300. The topmost layer 200 and the intermediate layer 300 may have an interface F-B where the front F and the back B are bonded.

[0163] The second substrate 301 may include a second front surface 301f and a second back surface 301b corresponding to the second front surface 301f. The second transistors 303 and the source follower gate SFG may be arranged on the second front surface 301f. In FIG. 12, the second source and drain regions constituting the second transistors 303 may be arranged in the second substrate 301, but are omitted for convenience.

[0164] The second wiring layer 305 and the second contact plug 306 may be connected to the second transistors 303 via the second via plug 313. The second wiring layer 305 and the second contact plug 306 may be connected to the second front bonding pad 304. The second wiring layer 305 and the second contact plug 306 may be connected to the back bonding pad 332 via the second connection via plug 340. The second connection via plug 340 may be arranged in a through via hole VHO' penetrating the second substrate 301.

[0165] The back bonding pad 332 can be disposed adjacent to the second back surface 301b of the second substrate 301. The back bonding pad 332 can be disposed within the upper portion of the intermediate layer 300. The back bonding pad 332 can be connected to the first front bonding pad 204.

[0166] The second FD wiring structure 310 can further include a first connection via plug 314 that penetrates the second substrate 301. The first connection via plug 314 can be spaced apart from the second substrate 301 with the second insulating layer 311 interposed therebetween. The second FD bonding pad 309 can be connected to the second FD wiring layer 307 and the second FD plug 308 via the first connection via plug 314. The first connection via plug 314 can be connected to the source follower gate SFG via the second FD wiring layer 307 and the second FD plug 308.

[0167] The second shield structure 320 can further include a shield via plug 324 that penetrates the second substrate 301. Different from the second shield structure 320 in FIG. 12, the second shield structure 320 in FIG. 3 does not include a second shield plug (322 in FIG. 3). The shield via plug 324 can be spaced apart from the second substrate 301 with the second insulating layer 311 interposed therebetween. The second shield bonding pad 323 can be connected to the second shield wiring layer 321 and the source follower via SFV via the shield via plug 324. The shield via plug 324 can be connected to the source follower source region SFS via the second shield wiring layer 321 and the source follower via SFV. Although not shown, the first shield structure 220 and the second shield structure 320 can be connected to each other.

[0168] The first connection via plug 314 is even longer in the vertical direction than the second FD plug 308. The second connection via plug 340 is even longer in the vertical direction than the second contact plug 306. The shield via plug 324 is even longer in the vertical direction than the source follower via SFV. The first connection via plug 314, the second connection via plug 340, and the shield via plug 324 can include a metal, for example, copper or tungsten.

[0169] The second insulating layer 311 can be disposed on the second back surface 301b of the second substrate 302 and on the second front surface 301f. The second insulating layer 311 can be composed of a single layer or multiple layers. The second insulating layer 311 does not cover the upper surface of the second FD bonding pad 309, the upper surface of the second shield bonding pad 323, the upper surface of the back bonding pad 332, and the lower surface of the second front bonding pad 304.

[0170] FIG. 13 is a schematic cross-sectional view for explaining the structure of an image sensor according to an embodiment of the technical idea of the present invention.

[0171] Specifically, the image sensor EX8 is also an embodiment in which the image sensor 100 of FIG. 1 is embodied. The image sensor EX8 can include the pixel PX of FIG. 1. When the image sensor EX8 is compared with the image sensor EX7 of FIG. 12, it is substantially the same except that the intermediate layer 300 is different. In FIG. 13, the content described in FIG. 12 will be briefly described or omitted.

[0172] Referring to FIG. 13, a source follower landing pad SLP can be interposed between the source follower source region SFS and the source follower via SFV. The source follower source region SFS and the source follower via SFV can be connected to each other via the source follower landing pad SLP. The lower surface of the source follower landing pad SLP can be coplanar with the lower surface of the source follower gate SFG and the lower surface of the second transistor 303.

[0173] At least a part of the source follower landing pad SLP can be inserted into the source follower source region SFS. The shield structure SHS can be connected to the source follower source region SFS via the source follower via SFV and the source follower landing pad SLP. The shield structure SHS can be connected to the source follower source region SFS.

[0174] In a plan view, the source follower landing pad SLP can surround the source follower gate SFG, similar to FIG. 9. The source follower landing pad SLP can include various shapes such as a polygon, a circle, or an ellipse in a plan view. The source follower landing pad SLP can be separated from the source follower gate SFG in a first horizontal direction D1 and a second horizontal direction D2.

[0175] The source follower landing pad SLP can include a conductive material. For example, the source follower landing pad SLP can include polycrystalline silicon doped with impurities.

[0176] FIG. 14 is a schematic cross-sectional view for explaining the structure of an image sensor according to an embodiment of the technical idea of the present invention.

[0177] Specifically, the image sensor EX9 is an embodiment in which the image sensor 100 of FIG. 1 is embodied. The image sensor EX9 can include the pixel PX of FIG. 1. When the image sensor EX9 is compared with the image sensor EX1 of FIG. 3, it is substantially the same except that the intermediate layer 300 is different. In FIG. 14, the content described in FIG. 3 will be briefly described or omitted.

[0178] Referring to FIG. 14, the image sensor EX9 can include a top layer 200, an intermediate layer 300, and a bottom layer 400. The image sensor EX9 can be composed of three layers in which the bottom layer 400, the intermediate layer 300, and the top layer 200 are bonded to each other.

[0179] The top layer 200 can include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shield structure 220.

[0180] The intermediate layer 300 may include a second substrate 301, a plurality of second transistors 303, a source follower gate SFG, a source follower source region SFS, a source follower via SFV, a source follower landing pad SLP, a back bonding pad 332, a second wiring layer 305, a second contact plug 306, a second front bonding pad 304, a second via plug 313, a second FD wiring structure 310, a second shield structure 320, a second connection via plug 340, and a second insulating layer 311.

[0181] The first front bonding pad 204 included in the topmost layer 200 may be bonded to the back bonding pad 332 included in the intermediate layer 300. The first insulating layer 211 included in the topmost layer 200 may be bonded to the second insulating layer 311 included in the intermediate layer 300. The topmost layer 200 and the intermediate layer 300 may have an interface F-B where the front F and the back B are bonded.

[0182] The second substrate 301 may include a second front surface 301f and a second back surface 301b corresponding to the second front surface 301f. The second transistor 303 and the source follower gate SFG may be disposed on the second front surface 301f. In FIG. 14, the second source and drain regions constituting the second transistor 303 are disposed in the second substrate 301, but are omitted for convenience.

[0183] The second wiring layer 305 and the second contact plug 306 may be connected to the second transistor 303 via the second via plug 313. The second wiring layer 305 and the second contact plug 306 may be connected to the second front bonding pad 304. The second wiring layer 305 and the second contact plug 306 may be connected to the back bonding pad 332 via the second connection via plug 340. The second connection via plug 340 may be disposed in a through via hole VHO' penetrating the second substrate 301.

[0184] The back bonding pad 332 can be disposed adjacent to the second back surface 301b of the second substrate 301. The back bonding pad 332 can be disposed within the upper portion of the intermediate layer 300. The back bonding pad 332 can be connected to the first front bonding pad 204.

[0185] The second FD wiring structure 310 can further include a first connection via plug 314 that penetrates the second substrate 301. The first connection via plug 314 can be spaced apart from the second substrate 301 with the second insulating layer 311 interposed therebetween.

[0186] The second FD bonding pad 309 can be connected to the second FD wiring layer 307 and the second FD plug 308 via the first connection via plug 314. Although not illustrated in FIG. 14, the second FD wiring layer 307 connected to the first connection via plug 314 can be connected to the second FD plug 308 connected to the source follower gate SFG. The first connection via plug 314 can be connected to the source follower gate SFG via the second FD wiring layer 307 and the second FD plug 308.

[0187] The first connection via plug 314 is even longer in the vertical direction than the second FD plug 308. The second connection via plug 340 is even longer in the vertical direction than the second contact plug 306. The first connection via plug 314 and the second connection via plug 340 can include a metal, such as copper or tungsten.

[0188] The second insulating layer 311 can be disposed on the second back surface 301b of the second substrate 302 and on the second front surface 301f. The second insulating layer 311 can be composed of a single layer or multiple layers. The second insulating layer 311 does not cover the upper surface of the second FD bonding pad 309, the upper surface of the second shield bonding pad 323, the upper surface of the back bonding pad 332, and the lower surface of the second front bonding pad 304.

[0189] The second shield structure 320 may further include an impurity region 350 disposed in the second substrate 301 and a shield connection plug 352 that connects the impurity region 350 and the second shield wiring layer 321. The impurity region 350 is also a region in the second substrate 301 doped with impurities. The impurities can have a P-type or N-type conductivity type.

[0190] The impurity region 350 may be connected to the second shield bonding pad 323 via the second shield plug 322. The impurity region 350 may be connected to the second shield wiring layer 321 via the shield connection plug 352. In plan view, the impurity region 350 can have an annular shape.

[0191] The second shield wiring layer 321 may be connected to the source follower source region SFS via the source follower via SFV and the source follower landing pad SLP. The shield connection plug 352 may include a metal, such as copper or tungsten.

[0192] A source follower landing pad SLP may be interposed between the source follower source region SFS and the source follower via SFV. The source follower source region SFS and the source follower via SFV may be connected to each other via the source follower landing pad SLP. The lower surface of the source follower landing pad SLP may be coplanar with the lower surface of the source follower gate SFG and the lower surface of the second transistor 303.

[0193] At least a part of the source follower landing pad SLP may be inserted into the source follower source region SFS. The shield structure SHS may be connected to the source follower source region SFS via the source follower via SFV and the source follower landing pad SLP. The shield structure SHS may be connected to the source follower source region SFS.

[0194] In plan view, the source follower landing pad SLP can surround the source follower gate SFG, similar to FIG. 9. The source follower landing pad SLP can include various shapes such as a polygon, a circle, or an ellipse in plan view. The source follower landing pad SLP can be separated from the source follower gate SFG in the first horizontal direction D1 and the second horizontal direction D2.

[0195] The source follower landing pad SLP can include a conductive material. For example, the source follower landing pad SLP can include polycrystalline silicon doped with impurities.

[0196] FIGS. 15A and 15B are cross-sectional views for explaining a method of manufacturing the image sensor of FIG. 3 according to an embodiment of the present invention.

[0197] Specifically, in FIGS. 15A and 15B, the content described in FIG. 3 will be briefly explained or omitted. Referring to FIG. 15A, the top layer 200 is prepared. The top layer 200 can include a first substrate 201, a plurality of first transistors 203, a first wiring layer 205, a first contact plug 206, a first front bonding pad 204, a first via plug 213, a first insulating layer 211, a pixel isolation layer 215, a color filter 217, a lens 219, a first FD wiring structure 210, and a first shield structure 220. The first substrate 201 can include a first front surface 201f and a first back surface 201b corresponding to the first front surface 201f.

[0198] The intermediate layer 300 is prepared. The intermediate layer 300 can include a second substrate 301, a plurality of second transistors 303, a source follower gate SFG, a source follower source region SFS, a source follower via SFV, a back bonding through via 330, a second wiring layer 305, a second contact plug 306, a second front bonding pad 304, a second via plug 313, a second FD wiring structure 310, a second shield structure 320, and a second insulating layer 311.

[0199] The second substrate 301 may include a second front surface 301f and a second back surface 301b corresponding to the second front surface 301f. Through vias VHO penetrating the second front surface 301f and the second back surface 301b may be formed in the second substrate 301. Back-bonding through vias 330 insulated by a second insulating layer 311 may be formed in the through vias VHO.

[0200] The first front bonding pads 204 constituting the topmost layer 200 are bonded in the arrow direction to the second front bonding pads 304 constituting the intermediate layer 300. The first insulating layer 211 constituting the topmost layer 200 is bonded in the arrow direction to the second insulating layer 311 constituting the intermediate layer 300. When the first front bonding pads 204 and the second front bonding pads 304 are formed of a copper layer, the copper pads may be bonded to each other. At this time, the first FD bonding pads 209 and the second FD bonding pads 309 may be bonded, and the first shield bonding pads 223 and the second shield bonding pads 323 may be bonded.

[0201] Referring to FIG. 15B, as described in FIG. 15A, the bonded topmost layer 200 and intermediate layer 300 are prepared. Then, the bottommost layer 400 is prepared. The bottommost layer 400 may include a third substrate 401, a plurality of third transistors 403, a third wiring layer 405, third contact plugs 406, third front bonding pads 409, third via plugs 413, and a third insulating layer 411.

[0202] The second insulating layer 311 and the second substrate 301 constituting the intermediate layer 300 are bonded in the arrow direction to the third insulating layer 411 constituting the bottommost layer 400. The back-bonding through vias 330 and the third front bonding pads 409 may be bonded. When the back-bonding through vias 330 and the third front bonding pads 409 are formed of a copper layer, the copper vias and the copper pads may be bonded to each other. Through such a process, the image sensor EX1 of FIG. 3 may be manufactured.

[0203] FIG. 16A and FIG. 16D are cross-sectional views for explaining a method of manufacturing the image sensor of FIG. 8 according to an embodiment of the present invention. Specifically, FIGS. 16A and 16D are cross-sectional views for explaining a method of manufacturing an intermediate layer 300 of the image sensor EX4 of FIG. 8.

[0204] Referring to FIG. 16A, a second substrate 301 is prepared. The second substrate 301 may include a second front surface 301f and a second back surface 301b corresponding to the second front surface 301f. An impurity implantation process may be advanced in the second substrate 301 to form a source follower source region SFS.

[0205] After forming a photomask film (not shown) on the second front surface 301f of the second substrate 301, an exposure and development process is advanced for the photomask film. A photomask pattern PM may be formed from the photomask film by the exposure and development process. The photomask pattern PM may include an opening OP that exposes a part of the source follower source region SFS.

[0206] An etching process may be advanced for the second substrate 301 using the photomask pattern PM as an etching mask. While a part of the source follower source region SFS exposed through the opening OP is being etched, a recess RS may be formed downward in the vertical direction Z from the second front surface 301f of the second substrate 301.

[0207] Referring to FIG. 16B, the photomask pattern PM may be removed. Next, a preliminary conductive film GL covering the second front surface 301f of the second substrate 301 may be formed. The preliminary conductive film GL may include, for example, polycrystalline silicon or metal. The preliminary conductive film GL may fill the recess RS.

[0208] Referring to FIG. 16C, the preliminary conductive film GL in FIG. 16B can be patterned to form the second transistor 303, the source follower gate SFG, and the source follower landing pad SLP. Specifically, the second transistor 303 formed by patterning the preliminary conductive film GL means the transistor gate of the second transistor 303. The second transistor 303, the source follower gate SFG, and the source follower landing pad SLP can be formed simultaneously from the preliminary conductive film GL.

[0209] Referring to FIG. 16D, then, the second via plug 313, the second wiring layer 305, the second contact plug 306, the second FD wiring structure 310, the second shield structure 320, the second front bonding pad 304, and the back bonding through via 330 can be formed. Thereby, the intermediate layer 300 of the image sensor EX4 in FIG. 8 can be manufactured.

[0210] Next, in the same manner as described in FIGS. 15A and 15B, the uppermost layer 200 and the lowermost layer 400 can be prepared, and the uppermost layer 200 and the intermediate layer 300 can be bonded, and the intermediate layer 300 and the lowermost layer 400 can be bonded. Thereby, the image sensor EX4 in FIG. 8 can be manufactured.

[0211] As described above, the present invention has been described based on the embodiments illustrated in the drawings, but this is merely exemplary, and those having ordinary knowledge in the technical field will understand that various modifications, substitutions, and equivalent other embodiments are possible from them. It must be understood that the foregoing embodiments are exemplary in all respects and not restrictive. The true technical protection scope of the present invention must be determined by the technical idea of the claims.

Description of Reference Numerals

[0212] 200 Uppermost layer 201 First substrate 201b First back surface 201f First front surface 203 First transistor 204 First front bonding pad 205 First wiring layer 206 First contact plug 207 First FD wiring layer 208 First FD plug 209 First FD bonding pad 210 First floating diffusion wiring structure 211 First insulating layer 213 First via plug 215 Pixel isolation layer 217 Color filter 219 Lens 220 First shield structure 221 First shield wiring layer 222 First shield plug 223 First shield bonding pad 300 Intermediate layer 301 Second substrate 303 Second transistor 304 Second front bonding pad 305 Second wiring layer 306 Second contact plug 307 Second FD wiring layer 308 Second FD plug 309 Second FD bonding pad 310 Second floating diffusion wiring structure 311 Second insulating layer 313 Second via plug 320 Second shield structure 321 Second shield wiring layer 322 Second shield plug 323 Second shield bonding pad 330 Back bonding through via 400 Lowermost layer 401 Third substrate 403 Third transistor 405 Third wiring layer 406 Third contact plug 409 Third front bonding pad 411 Third insulating layer 413 Third via plug EX1 Image sensor SFG Source follower gate SFS Source follower source region SFV Source follower via

Claims

1. The topmost layer includes a first substrate, a floating diffusion node disposed within the first substrate, a first FD wiring structure connected to the floating diffusion node, and a first shield structure disposed on the side of the first FD wiring structure, a second substrate, a source follower gate disposed on the second substrate, a source follower source region disposed within the second substrate, a second FD wiring structure connected to the first FD wiring structure and the source follower gate, a second shield structure connected to the first shield structure and the source follower source region, and a source follower landing pad interposed between the second shield structure and the source follower source region and disposed at a distance from the source follower gate, and an intermediate layer bonded to the topmost layer below the topmost layer, a bottommost layer bonded to the intermediate layer below the intermediate layer, wherein the bottommost layer includes a third substrate and a transistor disposed on the third substrate, an image sensor.

2. The first shield structure is horizontally spaced from the first FD wiring structure and surrounds the first FD wiring structure, The second shield structure is horizontally spaced from the second FD wiring structure and surrounds the second FD wiring structure, the image sensor according to claim 1.

3. The first FD wiring structure includes a first FD wiring layer disposed at a first vertical level and a second FD wiring layer disposed at a second vertical level different from the first vertical level, The first shield structure includes a first shield wiring layer only at either the first vertical level or the second vertical level, the image sensor according to claim 1.

4. The first shield structure includes a first shield wiring layer disposed at a first vertical level and a second shield wiring layer disposed at a second vertical level different from the first vertical level, The horizontal distance from the first FD wiring structure to the first shield wiring layer is different from the horizontal distance from the first FD wiring structure to the second shield wiring layer, the image sensor according to claim 1.

5. The intermediate layer is disposed within the second substrate and further includes an element isolation film in contact with the source follower source region, The image sensor according to claim 1, wherein at least a part of the source follower landing pad contacts the element isolation film.

6. The image sensor according to claim 1, wherein the second FD wiring structure includes a second FD bonding pad bonded to a first FD bonding pad included in the first FD wiring structure, and a first connection via plug that is connected to the second FD bonding pad and penetrates the second substrate.

7. The image sensor according to claim 1, wherein the source follower landing pad surrounds the source follower gate.

8. An uppermost layer including a first substrate, a floating diffusion node disposed in the first substrate, a first FD wiring structure connected to the floating diffusion node, and a first shield structure disposed on the first FD wiring structure side, An intermediate layer bonded to the uppermost layer below the uppermost layer, including a second substrate having a second front surface and a second back surface corresponding to the second front surface, a source follower gate disposed on the second front surface of the second substrate, a source follower source region disposed in the second substrate, a second FD wiring structure connected to the first FD wiring structure and the source follower gate, and a second shield structure connected to the first shield structure and the source follower source region, A lowermost layer bonded to the intermediate layer below the intermediate layer, including a third substrate and a transistor disposed on the third substrate, The image sensor, wherein the second shield structure includes a second shield bonding pad bonded to a first shield bonding pad included in the first shield structure, and an impurity region disposed in the second substrate and connected to the second shield bonding pad.

9. The image sensor according to claim 8, wherein the second shield structure further includes a second shield wiring layer disposed apart from the second substrate, a second shield plug connecting the impurity region and the second shield bonding pad, and a shield connection plug connecting the impurity region and the second shield wiring layer.

10. The intermediate layer further includes a source follower landing pad interposed between the source follower source region and the second shield plug. The image sensor according to claim 9, wherein at least a part of the source follower landing pad is surrounded by the source follower source region.

Images