Manufacturing method of memory device

Abstract

To provide a reliable memory device.SOLUTION: A manufacturing method of a memory device includes the steps of: forming a first insulator on a substrate; forming a second insulator on the first insulator; forming a third insulator on the second insulator; forming an opening penetrating the first insulator, the second insulator, and the third insulator; forming a fourth insulator inside a side face of the first insulator, a side face of the second insulator, and a side face of the third insulator in the opening; forming an oxide semiconductor inside the fourth insulator; removing the second insulator; and forming an electric conductor between the first insulator and the third insulator. The fourth insulator is formed by performing a cycle multiple times, the cycle including a first step of supplying a gas containing silicon and an oxidizing gas to the chamber in which the substrate is arranged, and a second step of stopping the supply of the gas containing silicon to the chamber, and a third step of generating plasma containing the oxidizing gas in the chamber.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method of manufacturing the same.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] Note that in this specification and the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. In addition, a display device, a light-emitting device, a lighting device, an electro-optical device, a memory device, an imaging device, a communication device, an information processing device, and an electronic device may include semiconductor elements or semiconductor circuits. Further, a display device, a light-emitting device, a lighting device, an electro-optical device, a memory device, an imaging device, a communication device, and an electronic device may also be referred to as a semiconductor device. One aspect of the present invention particularly relates to a memory device and a method of manufacturing the same.

Background Art

[0004] In recent years, with the increase in the amount of data to be processed, semiconductor devices having a larger storage capacity have been demanded. In order to increase the storage capacity per unit area, it is effective to stack memory cells (see Patent Document 1 and Patent Document 2). By stacking and providing memory cells, the storage capacity per unit area can be increased according to the number of stacked memory cells. Patent Document 3 and Patent Document 4 disclose memory devices using an oxide semiconductor. Patent Document 5 discloses a semiconductor memory using an oxide semiconductor as a charge storage layer.

[0005] In addition, Non-Patent Document 1 discloses CAAC-IGZO as a crystalline oxide semiconductor. Non-Patent Document 1 also discloses the growth mechanism of CAAC-IGZO and the like.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Non-Patent Documents

[0007]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] In Patent Document 1 and Patent Document 2, a plurality of memory elements (also referred to as memory cells) are stacked, and these are connected in series to form a three-dimensional memory cell array (also referred to as a memory string).

[0009] In Patent Document 1, a columnar semiconductor is in contact with an insulator having a charge storage layer. In Patent Document 2, a columnar semiconductor is in contact with an insulator that functions as a tunnel dielectric. In both Patent Document 1 and Patent Document 2, writing information into a memory cell is performed by extracting and injecting charges through the insulator. In this case, a trap center may be formed at the interface where the semiconductor and the insulator are in contact. The trap center may capture electrons and vary the threshold voltage of the transistor. Also, due to the extraction and injection of charges, one or both of the inside of the insulator and the interface where the semiconductor and the insulator are in contact may deteriorate, and the charges held in the charge storage layer may leak and disappear. Therefore, there is a risk of adversely affecting the reliability of the memory device.

[0010] Therefore, one of the problems of one embodiment of the present invention is to provide an insulator in which the formation of a trap center is suppressed at the interface with a semiconductor, and a method for forming the same. Another problem of one embodiment of the present invention is to provide a memory device capable of extracting and injecting charges without passing through an insulator when writing information into a memory cell, and a method for forming the same.

[0011] Another problem of one embodiment of the present invention is to provide a highly reliable memory device. Another problem of one embodiment of the present invention is to provide a memory device having a large storage capacity. Another problem of one embodiment of the present invention is to provide a memory device having a small occupied area. Another problem of one embodiment of the present invention is to provide a memory device with a low manufacturing cost. Another problem of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another problem of one embodiment of the present invention is to provide a semiconductor device with a low manufacturing cost. Another problem of one embodiment of the present invention is to provide a novel semiconductor device.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0013] One aspect of the present invention includes a step of forming a first insulator on a substrate, a step of forming a second insulator on the first insulator, a step of forming a third insulator on the second insulator, a step of forming an opening penetrating the first insulator, the second insulator, and the third insulator, a step of forming a fourth insulator covering the side surfaces of the first insulator, the second insulator, and the third insulator in the opening, a step of forming an oxide semiconductor adjacent to the fourth insulator, a step of removing the second insulator, and a step of forming a conductor between the first insulator and the third insulator. The fourth insulator is formed by performing a cycle including a first step of supplying a gas containing silicon and an oxidizing gas to a chamber in which the substrate is disposed, a second step of stopping the supply of the gas containing silicon to the chamber, and a third step of generating a plasma containing the oxidizing gas in the chamber, a plurality of times. It is a method for manufacturing a memory device.

[0014] In the above, the gas containing silicon is preferably SiH4.

[0015] In the above, the oxidizing gas is preferably N2O.

[0016] In the above first step, it is preferable to supply He to the chamber.

[0017] In the above, the oxide semiconductor preferably contains indium, element M (element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0018] In the above, the oxide semiconductor preferably has crystallinity.

[0019] In the above, the c-axis of the oxide semiconductor preferably has a region that is oriented in the normal direction of the side surface of the conductor within the opening.

[0020] In the above, the fourth insulator preferably has a region where the nitrogen concentration is 3×10 19 atoms / cm 3 or more and 1×10 21 atoms / cm 3 or less.

[0021] In the above, the fourth insulator preferably has a region where the carbon concentration is 1×10 18 atoms / cm 3 or more and 5×10 20 atoms / cm 3 or less.

[0022] One aspect of the present invention is a method for manufacturing a memory device, including: a step of forming a first insulator on a substrate; a step of forming a first conductor on the first insulator; a step of forming a second insulator on the first conductor; a step of forming a third insulator on the second insulator; a step of forming a fourth insulator on the third insulator; a step of forming an opening that penetrates the first insulator, the first conductor, the second insulator, the third insulator, and the fourth insulator; a step of forming a fifth insulator that covers the side surfaces of the first insulator, the first conductor, the second insulator, the third insulator, and the fourth insulator within the opening; a step of forming an oxide semiconductor adjacent to the fifth insulator; a step of removing the third insulator; and a step of forming a second conductor between the second insulator and the fourth insulator. The fifth insulator is formed by performing a plurality of cycles including: a first step of supplying a gas containing silicon and an oxidizing gas to a chamber in which the substrate is disposed; a second step of stopping the supply of the gas containing silicon to the chamber; and a third step of generating a plasma containing the oxidizing gas in the chamber.

[0023] In the above, the gas containing silicon is preferably SiH4.

[0024] In the above, the oxidizing gas is preferably N2O.

[0025] In the above first step, it is preferable to supply He to the chamber.

[0026] In the above, the oxide semiconductor preferably contains indium, element M (element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0027] In the above, the oxide semiconductor preferably has crystallinity.

[0028] In the above, the c-axis of the oxide semiconductor preferably has a region in the opening that is oriented in the normal direction of at least one side surface of the first conductor and the second conductor.

[0029] In the above, the fifth insulator has a region where the nitrogen concentration is 3×10 19 atoms / cm 3 or more and 1×10 21 atoms / cm 3 or less.

[0030] In the above, the fifth insulator has a region where the carbon concentration is 1×10 18 atoms / cm 3 or more and 5×10 20 atoms / cm 3 or less.

[0031] One aspect of the present invention includes a first insulator having a first opening, a conductor on the first insulator having a second opening, a second insulator on the conductor having a third opening, a third insulator on the side surfaces of the first opening, the second opening, and the third opening, and an oxide semiconductor provided via the third insulator on the side surfaces of the first opening, the second opening, and the third opening. The third insulator has a region where the nitrogen concentration is 3×10 19 atoms / cm 3 or more and 1×10 21 atoms / cm 3 or less. The third insulator has a region where the carbon concentration is 1×10 18 atoms / cm 3 or more and 5×10 20 atoms / cm 3 or less. It is a memory device.

[0032] In the above, the oxide semiconductor preferably contains indium, element M (element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0033] In the above, the third insulator preferably has a region where the indium concentration is 1.0×10 19 atoms / cm 3 or less.

[0034] In the above, the oxide semiconductor preferably has crystallinity.

[0035] In the above, the c-axis of the oxide semiconductor preferably has a region in the second opening that is oriented in the normal direction of the side surface of the conductor.

[0036] In the above, the diameter of the second opening is preferably larger than the diameter of the first opening and the diameter of the third opening.

[0037] In the above, the diameter of the second opening is preferably smaller than the diameter of the first opening and the diameter of the third opening.

Advantages of the Invention

[0038] In the fabrication of a memory cell array having a three-dimensional structure in which a plurality of memory elements are stacked and these are connected in series, the total number of steps is preferably less than the product of the number of memory elements to be stacked and the number of steps for fabricating one memory element. That is, the fabrication process of the memory cell array is not proportional to the number of memory elements to be stacked. For example, when comparing the number of fabrication steps of a memory cell array A having 4 layers of memory elements and a memory cell array B having 32 layers of memory elements, although the number of stacked memory elements is 8 times, the number of fabrication steps of the memory cell array B can be significantly less than 8 times the number of fabrication steps of the memory cell array A.

[0039] According to one aspect of the present invention, a highly reliable memory device can be provided. Further, according to one aspect of the present invention, a memory device with a large memory capacity can be provided. According to one aspect of the present invention, a memory device with a small occupied area can be provided. Further, according to one aspect of the present invention, a memory device with a low manufacturing cost can be provided. Further, according to one aspect of the present invention, a highly reliable semiconductor device can be provided. Further, according to one aspect of the present invention, a semiconductor device with a low manufacturing cost can be provided. Further, according to one aspect of the present invention, a novel semiconductor device can be provided.

[0040] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be naturally apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0041]

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Embodiments for Carrying Out the Invention

[0042] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used among different drawings for the same part or parts having the same or similar functions, and the repeated description thereof will be omitted.

[0043] In addition, in the drawings and the like, the positions, sizes, ranges, etc. of each configuration shown may not represent the actual positions, sizes, ranges, etc. in order to facilitate the understanding of the invention. For this reason, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. For example, in an actual manufacturing process, a resist mask or the like may be unintentionally reduced in size due to a process such as etching, but this may not be reflected in the drawing for the sake of easy understanding.

[0044] In addition, in the drawings and the like, for the sake of easy understanding of the description, the description of some components may be omitted.

[0045] In addition, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0046] In addition, in this specification and the like, the "terminal" in an electric circuit refers to a part where current input or output, voltage input or output, or signal reception or transmission is performed. Therefore, a part of a wiring or an electrode may function as a terminal.

[0047] Note that in this specification and the like, terms such as "above" and "below" do not limit the positional relationship of components to be directly above or below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be formed directly on insulating layer A in contact therewith, and those including other components between insulating layer A and electrode B are not excluded.

[0048] In addition, in this specification and the like, terms such as "overlap" do not limit the state such as the stacking order of components. For example, in the expression "electrode B overlapping insulating layer A", it is not limited to the state where "electrode B is formed on insulating layer A", and states such as "electrode B is formed under insulating layer A" or "electrode B is formed on the right side (or left side) of insulating layer A" are not excluded.

[0049] In addition, in this specification and the like, terms such as "adjacent" and "proximate" do not limit components to be in direct contact. For example, in the expression "electrode B adjacent to insulating layer A", it is not necessary for insulating layer A and electrode B to be formed in direct contact therewith, and those including other components between insulating layer A and electrode B are not excluded.

[0050] In addition, since the functions of the source and the drain are interchanged with each other depending on operating conditions such as when transistors of different polarities are employed or when the direction of current changes in circuit operation, it is difficult to limit which is the source or the drain. For this reason, in this specification, the terms source and drain can be used interchangeably.

[0051] In addition, in this specification and the like, "electrically connected" includes both the case of direct connection and the case of being connected via "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the exchange of electrical signals between the connection targets. Therefore, even when expressed as "electrically connect", in an actual circuit, there may be a case where there is no physical connection part and only wiring extends.

[0052] In addition, in this specification and the like, "parallel" refers to, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" and "orthogonal" refer to, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0053] In addition, in this specification and the like, regarding numerical values and measured values, or regarding things, methods, and events that can be converted into numerical values or measured values, when using terms such as "identical", "the same", "equal", or "uniform", unless otherwise specified, it shall include an error of plus or minus 20%.

[0054] In addition, voltage often indicates the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and the like, unless otherwise specified, voltage and potential can be used interchangeably.

[0055] Note that even when expressed as "semiconductor", for example, when the conductivity is sufficiently low, it has the characteristics of an "insulator". Therefore, it is also possible to replace "semiconductor" with "insulator" and use it. In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "insulator" described in this specification may be able to be read as each other in some cases.

[0056] Also, even when described as a "semiconductor", for example, when the conductivity is sufficiently high, it has the characteristics of a "conductor". Therefore, it is also possible to use it by replacing "semiconductor" with "conductor". In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "conductor" described in this specification may be interchangeable with each other.

[0057] Note that ordinal numbers such as "first" and "second" in this specification and the like are attached to avoid confusion of components, and do not indicate any order or rank such as process order or stacking order. Also, even for terms without ordinal numbers in this specification and the like, ordinal numbers may be attached in the claims to avoid confusion of components. Also, even for terms with ordinal numbers in this specification and the like, different ordinal numbers may be attached in the claims. Also, even for terms with ordinal numbers in this specification and the like, ordinal numbers may be omitted in the claims and the like.

[0058] Note that in this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically short-circuited (also referred to as the "conducting state"). Also, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically disconnected (also referred to as the "non-conducting state").

[0059] Also, in this specification and the like, "on-current" may refer to the current flowing between the source and drain when the transistor is in the on state. Also, "off-current" may refer to the current flowing between the source and drain when the transistor is in the off state.

[0060] In this specification and the like, the high power supply potential VDD (hereinafter also simply referred to as "VDD", "H potential", or "H") indicates a power supply potential with a potential higher than the low power supply potential VSS (hereinafter also simply referred to as "VSS", "L potential", or "L"). Further, VSS indicates a power supply potential with a potential lower than VDD. Also, the ground potential (hereinafter also simply referred to as "GND" or "GND potential") can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0061] Also, unless otherwise specified, the transistors shown in this specification and the like are enhancement-type (normally-off type) n-channel field-effect transistors. Therefore, its threshold voltage (also referred to as "Vth") is greater than 0V. Also, unless otherwise specified, "supplying an H potential to the gate of the transistor" may be synonymous with "turning on the transistor". Also, unless otherwise specified, "supplying an L potential to the gate of the transistor" may be synonymous with "turning off the transistor".

[0062] In this specification and the like, the gate refers to a part or all of the gate electrode and the gate wiring. The gate wiring refers to the wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0063] In this specification and the like, the source refers to a part or all of the source region, the source electrode, and the source wiring. The source region refers to a region in the semiconductor layer where the resistivity is below a certain value. The source electrode refers to the conductive layer connected to the source region. The source wiring refers to the wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0064] In addition, in this specification and the like, "drain" refers to part or all of a drain region, a drain electrode, and a drain wiring. The drain region refers to a region in the semiconductor layer where the resistivity is equal to or less than a certain value. The drain electrode refers to a conductive layer at a portion connected to the drain region. The drain wiring refers to a wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0065] In addition, in drawings and the like, in order to make the potentials of wirings and electrodes, etc. easy to understand, "H" indicating an H potential or "L" indicating an L potential may be appended adjacent to the wirings and electrodes, etc. Further, for wirings and electrodes, etc. where a potential change has occurred, "H" or "L" may be appended in enclosed characters. Further, when a transistor is in an off state, an "×" symbol may be appended over the transistor.

[0066] Generally, a "capacitor" has a configuration in which two electrodes face each other with an insulator (dielectric) in between. In this specification and the like, "capacitor element" includes the case of the aforementioned "capacitor". That is, in this specification and the like, "capacitor element" includes those having a configuration in which two electrodes face each other with an insulator in between, those having a configuration in which two wirings face each other with an insulator in between, or those in which two wirings are arranged with an insulator in between.

[0067] In addition, in this specification and the like, when the same reference numerals are used for a plurality of elements, when it is particularly necessary to distinguish them, identification symbols such as "_1", "_2", "[n]", "[m,n]", etc. may be appended to the reference numerals for description. For example, the second conductor WWL may be described as conductor WWL[2].

[0068] (Embodiment 1) FIG. 1 shows a perspective view of a memory device 100 according to an aspect of the present invention. The memory device 100 is a memory device having a three-dimensional stacked structure. FIG. 2 is a cross-sectional view of the portion A1 - A2 indicated by the dashed-dotted line in FIG. 1 and the connection portion of the conductor SEL and the wiring. In FIG. 1 and the like, arrows indicating the X direction, the Y direction, and the Z direction may be attached. The X direction, the Y direction, and the Z direction are directions orthogonal to each other. In this specification and the like, one of the X direction, the Y direction, or the Z direction may be referred to as the "first direction" or the "first direction", another one may be referred to as the "second direction" or the "second direction", and the remaining one may be referred to as the "third direction" or the "third direction". In the present embodiment and the like, the direction in which the conductor 130 described later extends is defined as the Z direction.

[0069] FIG. 2 shows a cross-section of the X - Z plane. As described above, for the sake of clarity of explanation, in FIG. 1, FIG. 2, and the like, some of the components may be omitted.

[0070] <Configuration example of the memory device> A memory device 100 according to an aspect of the present invention includes a memory cell array 110. The memory cell array 110 includes a plurality of memory strings 120. The memory strings 120 extend in the Z direction and are arranged in a matrix on the XY plane.

[0071] FIG. 3 shows a cross-sectional configuration example of a memory string 120 according to an aspect of the present invention. The memory string 120 has a configuration in which a plurality of memory elements MC (also referred to as "memory cells") are connected in series. In the present embodiment, the case where five memory elements MC are connected in series is shown, but the number of memory elements MC included in the memory string 120 is not limited to five. If the number of memory elements MC included in the memory string 120 is n, n may be an integer of 2 or more.

[0072] The memory string 120 also includes a plurality of conductors WWL, a plurality of conductors RWL, a conductor SG, and a conductor SEL. The plurality of conductors WWL and the plurality of conductors RWL are alternately stacked via an insulator 123. The conductor SG is provided below the plurality of conductors WWL and the plurality of conductors RWL. The conductor SEL is provided above the plurality of conductors WWL and the plurality of conductors RWL.

[0073] In FIG. 3, five memory elements MC are shown as memory elements MC[1] to memory element MC[5]. When describing matters common to the memory elements MC[1] to MC[5], they are simply referred to as "memory element MC". The same applies to other components such as the conductor WWL, the conductor RWL, and the insulator 123.

[0074] The memory string 120 includes a transistor STr1 connected to the memory element MC[1] and a transistor STr2 connected to the memory element MC[5].

[0075] The conductor WWL, the conductor RWL, the conductor SG, and the conductor SEL extend beyond the memory cell array 110. Also, the conductor WWL, the conductor RWL, the conductor SG, and the conductor SEL are stacked stepwise outside the memory cell array 110 (see FIGS. 1 and 2).

[0076] FIG. 4A shows a cross-section of the portion B1 - B2 shown by the dashed line in FIG. 3 as viewed from the Z direction. FIG. 4B shows a cross-section of the portion C1 - C2 shown by the dashed line in FIG. 3 as viewed from the Z direction. FIG. 5A shows an enlarged view of the region 105 shown by the double-dashed line in FIG. 3. FIG. 5A corresponds to a cross-sectional view of the memory element MC.

[0077] The memory string 120 has a conductor 122 on a substrate 121. As the substrate 121, for example, an insulator may be used. Also, on the conductor 122, there are an insulator 123[1], a conductor SG, an insulator 123[2], a conductor RWL[1], an insulator 123[3], a conductor WWL[1], an insulator 123[4], a conductor RWL[2], an insulator 123[5], a conductor WWL[2], an insulator 123[6], a conductor RWL[3], an insulator 123[7], a conductor WWL[3], an insulator 123[8], a conductor RWL[4], an insulator 123[9], a conductor WWL[4], an insulator 123

[10] , a conductor RWL[5], an insulator 123

[11] , a conductor WWL[5], an insulator 123

[12] , and a conductor SEL (see FIG. 3).

[0078] Also, the memory string 120 has an opening 141 in which a part of each of the insulator 123[1], the conductor SG, the insulator 123[2], the conductor RWL[1], the insulator 123[3], the conductor WWL[1], the insulator 123[4], the conductor RWL[2], the insulator 123[5], the conductor WWL[2], the insulator 123[6], the conductor RWL[3], the insulator 123[7], the conductor WWL[3], the insulator 123[8], the conductor RWL[4], the insulator 123[9], the conductor WWL[4], the insulator 123

[10] , the conductor RWL[5], the insulator 123

[11] , the conductor WWL[5], the insulator 123

[12] , and the conductor SEL is removed.

[0079] The opening 141 extends in the Z direction and reaches the conductor 122. Also, in the opening 141, the diameter of the region 142 overlapping with the conductor RWL is larger than the diameter of the region 143 overlapping with the conductor WWL. Therefore, the side surface of the opening 141 has an uneven shape.

[0080] Also, along the side surface of the opening 141, an insulator 124 and a semiconductor 125 are provided. Also, in the region of the opening 141 that overlaps with the conductor RWL, a conductor 128 is provided between the insulator 124 and the semiconductor 125. The semiconductor 125 has a region that overlaps with the side surface of the opening 141 via the insulator 124.

[0081] Further, the memory string 120 has a conductor 130 extending in the Z direction. The conductor 130 is provided at or near the center of the opening 141. Also, an insulator 129, a semiconductor 127, and an insulator 126 are provided in a region overlapping with the side surface of the opening 141 of the conductor 130. The semiconductor 127 has a region overlapping with the side surface of the conductor 130 via the insulator 129. The insulator 126 has a region overlapping with the side surface of the conductor 130 via the insulator 129 and the semiconductor 127. Also, at the bottom of the opening 141, the semiconductor 125 and the semiconductor 127 have a region electrically connected to the conductor 122. Also, at the bottom of the opening 141, the conductor 130 has a region overlapping with the conductor 122 via the insulator 129 and the semiconductor 127.

[0082] Between the conductor WWL and the conductor 130, an insulator 181, an insulator 124, a semiconductor 125, an insulator 126, a semiconductor 127, and an insulator 129 are provided in this order from the conductor WWL side (see FIG. 4A). Between the conductor RWL and the conductor 130, an insulator 124, a conductor 128, a semiconductor 125, an insulator 126, a semiconductor 127, and an insulator 129 are provided in this order from the conductor RWL side (see FIG. 4B).

[0083] The memory element MC has a transistor WTr and a transistor RTr (see FIG. 5A). The region where the conductor WWL and the conductor 130 overlap functions as the transistor WTr. The conductor WWL functions as the gate electrode of the transistor WTr, and the conductor 130 functions as the back gate electrode of the transistor WTr. Also, a part of the semiconductor 125 functions as a semiconductor layer in which the channel of the transistor WTr is formed. The semiconductor layer in which the channel of the transistor WTr is formed overlaps with the gate electrode (conductor WWL) via a part of the insulator 124. In the present embodiment and the like, an example in which a part of the conductor WWL functions as a gate electrode is shown, but the gate electrode and the conductor WWL may be provided independently and electrically connected to each other.

[0084] The region where the conductor 128, the conductor RWL, and the conductor 130 overlap functions as a transistor RTr. The conductor RWL functions as the gate electrode of the transistor RTr. Also, the conductor 130 functions as the back gate electrode of the transistor RTr. A part of the semiconductor 127 functions as the semiconductor layer in which the channel of the transistor RTr is formed. The semiconductor layer in which the channel of the transistor RTr is formed overlaps with the gate electrode (conductor RWL) through a part of each of the insulator 126, the semiconductor 125, the conductor 128, and the insulator 124. The semiconductor layer in which the channel of the transistor RTr is formed overlaps with the back gate electrode (conductor 130) through a part of the insulator 129.

[0085] The transistor STr1 has a conductor SG, a semiconductor 125, and a semiconductor 127. Also, the transistor STr2 has a conductor SEL, a semiconductor 125, and a semiconductor 127.

[0086] Here, the back gate will be explained. The gate and the back gate are arranged so as to overlap through the channel formation region of the semiconductor layer. The back gate can function in the same way as the gate. Also, by changing the potential of the back gate, the threshold voltage of the transistor can be changed. One of the gate or the back gate may be called the "first gate" or "the first gate", and the other may be called the "second gate" or "the second gate".

[0087] Since the gate and the back gate are formed of a conductive layer or a semiconductor layer with a low resistivity, etc., they have a function (especially an electrostatic shielding function against static electricity) to prevent the electric field generated outside the transistor from acting on the semiconductor layer in which the channel is formed. That is, it is possible to prevent the electrical characteristics of the transistor from fluctuating due to the influence of an external electric field such as static electricity.

[0088] Also, by controlling the potential of the back gate, the threshold voltage of the transistor can be controlled. The potential of the back gate may be the same as the potential of the gate, or may be the ground potential (GND potential) or an arbitrary potential.

[0089] The semiconductor layer in which the channels of the transistor WTr and the transistor RTr are formed can be used singly or in combination, such as a single-crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor. As the semiconductor material, for example, silicon, germanium, etc. can be used. Also, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may be used. The same applies to the transistors STr1 and STr2.

[0090] Note that the semiconductor layers used for the transistors may be laminated. When laminating the semiconductor layers, semiconductors having different crystal states may be used, or different semiconductor materials may be used.

[0091] The semiconductor layers used for the transistor WTr, the transistor RTr, the transistor STr1, and the transistor STr2 are preferably oxide semiconductors having a metal oxide. A transistor using a metal oxide for the semiconductor layer can obtain a higher field-effect mobility compared to a transistor using amorphous silicon for the semiconductor layer. Also, in a transistor using polycrystalline silicon for the semiconductor layer, there is a possibility that grain boundaries may occur in the semiconductor layer. At grain boundaries, carriers are captured, which is likely to cause a decrease in the on-current of the transistor and a decrease in the field-effect mobility. On the other hand, although details will be described later, in an oxide semiconductor, a crystal structure in which distinct grain boundaries are not confirmed or a crystal structure in which the grain boundaries are extremely few can be realized. Using such an oxide semiconductor for the semiconductor layer is suitable because it can realize a transistor having good electrical characteristics such as a high on-current and a high field-effect mobility.

[0092] In this embodiment, as the oxide semiconductor, an oxide having a composition of In:Ga:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof, a composition of In:Ga:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof, a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or in the vicinity thereof, or a composition of In:Ga:Zn = 1:1:0.5 [atomic ratio] or in the vicinity thereof is used.

[0093] Further, in a CAAC-IGZO which is an oxide semiconductor, particularly a crystalline oxide semiconductor, it has a characteristic structure in which nanoclusters of several nm (for example, 1 to 3 nm) with the c-axis oriented in a direction perpendicular to the surface to be formed are connected to each other. Therefore, even in an opening extending in the Z direction, it is possible to form a crystal structure in which distinct crystal grain boundaries are not confirmed.

[0094] In particular, the transistor WTr is preferably a transistor (also referred to as an "OS transistor") using an oxide semiconductor which is a kind of metal oxide for the semiconductor layer in which the channel is formed. Since the oxide semiconductor has a bandgap of 2 eV or more, the off-current is extremely small. When an OS transistor is used for the transistor WTr, the charge written in the node ND described later can be retained for a long period. When an OS transistor is used for the transistor constituting the memory element MC, the memory element MC can be referred to as an "OS memory". Further, the memory string 120 including the memory element MC can also be referred to as an "OS memory". Also, the memory device 100 can also be referred to as an "OS memory".

[0095] The OS memory can retain the information written for a period of one year or more, and further ten years or more even when the power supply is stopped. Therefore, the OS memory can also be regarded as a non-volatile memory.

[0096] Further, since the amount of charge written in the OS memory hardly changes over a long period, the OS memory can retain not only binary (1-bit) but also multi-valued (multi-bit) information.

[0097] In addition, since the OS memory writes charges to the node via transistors, the high voltage required for conventional flash memory is not necessary, and a high-speed write operation can also be achieved. Further, the erasure operation before data rewriting performed in flash memory is not necessary in the OS memory. Also, since charge injection and extraction into / from the floating gate or charge trapping layer are not performed, the OS memory can substantially perform an unlimited number of data writes and reads. The OS memory has less degradation compared to conventional flash memory and provides high reliability.

[0098] Here, the insulators 124, 126, and 129 of the OS memory according to one aspect of the present invention are insulators with a sufficiently reduced concentration of nitrogen and carbon, and generation of trap centers at the interfaces with the adjacent semiconductors 125 or 127 is suppressed. Therefore, fluctuations in the threshold voltage are suppressed, and a memory device with good reliability can be provided. This also obtains a similar effect even when the OS memory according to one aspect of the present invention is a floating gate type or charge trapping type memory element. Although details will be described later, by using the above insulators as the insulator 126 adjacent to the semiconductor 127 and the insulator 129, generation of trap centers at the interfaces between the semiconductor 127 and the insulator 126 and between the semiconductor 127 and the insulator 129 is suppressed.

[0099] The carbon concentration of the insulator 124, the insulator 126, and the insulator 129 is preferably 1×10 18 atoms / cm 3 or more and 5×10 20 atoms / cm 3 or less, more preferably 5×10 18 atoms / cm 3 or more and 1×10 20 atoms / cm 3 or less as analyzed by SIMS. Further, the insulator contains nitrogen, and its nitrogen concentration is preferably 3×10 19 atoms / cm 3 or more and 1×10 21 atoms / cm 3 or less, more preferably 1×1019 atoms / cm 3 2×10 or more 20 atoms / cm 3 is below.

[0100] Also, it is preferable that the In concentration in the insulators 124, 126, and 129 is reduced as much as possible. Metallic In in the insulator may capture negative charges and affect transistor characteristics and their variations, such as a positive shift in the threshold voltage of the transistor and an increase in the S value. For example, when the threshold voltage of the transistor shifts positively and becomes normally-off characteristics, the transistor requires a higher drive voltage and it becomes difficult to drive at a low voltage. In this case, the power consumption of the transistor and the electronic device having the same increases.

[0101] Therefore, the In concentration contained in the insulator is 1.0×10 19 atoms / cm 3 or less, preferably 1.0×10 18 atoms / cm 3 or less, more preferably 1.0×10 17 atoms / cm 3 or less, and is preferably so.

[0102] When the insulators 124, 126, and 129 are in contact with one or both of the semiconductors 125 and 127, the carbon concentration, nitrogen concentration, and In concentration in the insulator may be the concentrations in a region 1 nm or more away from the interface with the semiconductor 125 or semiconductor 127.

[0103] Also, the OS memory does not involve a structural change at the atomic level during the rewriting of the memory, such as a magnetic resistance memory (MRAM) or a resistive random access memory (ReRAM). Therefore, the OS memory is more resistant to rewriting than the magnetic resistance memory and the resistive random access memory.

[0104] In addition, the OS transistor has almost no increase in the off-current even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range from room temperature to 200°C. Also, the on-current is less likely to decrease even in a high-temperature environment. A memory device including the OS memory operates stably even in a high-temperature environment and can provide high reliability. Further, the OS transistor has a high breakdown voltage between the source and the drain. By using the OS transistor in the transistors constituting the semiconductor device, a semiconductor device that operates stably and has good reliability can be realized even in a high-temperature environment.

[0105] The semiconductor 127 is preferably an n-type semiconductor. Also, the region overlapping with the conductor WWL of the semiconductor 125 is preferably an i-type or substantially i-type semiconductor. In this case, the transistor WTr becomes an enhancement-type (normally-off type) transistor, and the transistor RTr becomes a depletion-type (normally-on type) transistor.

[0106] Note that the semiconductor 125 and the semiconductor 127 may have the same material or different materials. For example, the semiconductor 125 and the semiconductor 127 may each be an oxide semiconductor. Also, the semiconductor 125 and the semiconductor 127 may each be a semiconductor having silicon. Further, the semiconductor 125 may be an oxide semiconductor and the semiconductor 127 may be a semiconductor having silicon. Alternatively, the semiconductor 125 may be a semiconductor having silicon and the semiconductor 127 may be an oxide semiconductor.

[0107] Note that FIG. 4A corresponds to the X - Y plane at or near the center of transistor WTr, and FIG. 4B corresponds to the X - Y plane at or near the center of transistor RTr. In FIGS. 4A and 4B, when the cross - sectional shape of conductor 130 is circular, insulator 129 is provided concentrically outside conductor 130, semiconductor 127 is provided concentrically outside insulator 129, insulator 126 is provided concentrically outside semiconductor 127, semiconductor 125 is provided concentrically outside insulator 126, and insulator 124 is provided concentrically outside semiconductor 125. Also, conductor 128 is provided concentrically between semiconductor 125 and insulator 124.

[0108] Also, the cross - sectional shape of conductor 130 is not limited to circular. The cross - sectional shape of conductor 130 may be rectangular. Also, the cross - sectional shape of conductor 130 may be triangular.

[0109] In the above, an example where memory element MC has two layers of semiconductor 125 and semiconductor 127 is shown, but the present invention is not limited to this. FIG. 5B shows an example where memory element MC has semiconductor 127 and conductor 128 that functions as a floating gate.

[0110] The region where conductor WL and conductor 130 overlap functions as memory element MC. Conductor WL functions as the control gate electrode of memory element MC, and conductor 130 functions as the back - gate electrode of memory element MC. Also, a part of semiconductor 127 functions as the semiconductor layer in which the channel of memory element MC is formed. The semiconductor layer in which the channel of memory element MC is formed overlaps conductor WL through a part of insulator 124. Also, conductor 128 is provided between the semiconductor layer in which the channel of memory element MC is formed and conductor WL, insulator 124 is provided between conductor WL and conductor 128, and insulator 126 that functions as a tunnel insulating film is provided between conductor 128 and the semiconductor layer in which the channel of memory element MC is formed.

[0111] Conductor 128 has a recess with respect to insulator 123. Inside the recess, conductor 128 is provided through insulator 124.

[0112] Further, as shown in FIG. 6A, an insulator 133 functioning as a charge storage layer may be provided instead of the conductor 128 functioning as a floating gate.

[0113] The region where the conductor WL and the conductor 130 overlap functions as a memory element MC. The conductor WL functions as a control gate electrode of the memory element MC, and the conductor 130 functions as a back gate electrode of the memory element MC. Further, a part of the semiconductor 127 functions as a semiconductor layer in which a channel of the memory element MC is formed. The semiconductor layer in which the channel of the memory element MC is formed overlaps the conductor WL via a part of the insulator 124. Further, a part of the insulator 133 is provided between the semiconductor layer in which the channel of the memory element MC is formed and the conductor WL and functions as a charge storage layer. Further, an insulator 124 is provided between the conductor WL and the insulator 133, and an insulator 126 functioning as a tunnel insulating film is provided between the insulator 133 and the semiconductor layer in which the channel of the memory element MC is formed.

[0114] The insulator 133 functioning as a charge storage layer is preferably an insulator containing silicon nitride.

[0115] Further, as shown in FIG. 6B, in the Z-axis direction, a conductor 128 may be provided so as to be in contact with the semiconductor 127 located between adjacent memory elements MC.

[0116] The insulator 123 has a concave portion with respect to the conductor 128. A conductor 128 in contact with the semiconductor 127 is provided in the concave portion. Providing the conductor 128 is preferable because the resistance between the channels of adjacent memory elements MC in the Z-axis direction is reduced.

[0117] In the memory element MC shown in FIGS. 5B, 6A, and 6B, since writing and reading are performed using a common conductor WL, the conductors WWL and RWL are unnecessary. Note that the conductor WL can be made of a material that can be used for the conductor WWL or the conductor RWL, and the same formation method as that for the conductor WWL or the conductor RWL can be used. Also, known methods can be used for the writing operation, reading operation, and erasing operation.

[0118] In the above, the insulators 124 and 126 in contact with the semiconductor 127 have sufficiently reduced impurities such as nitrogen and carbon, and generation of trap centers at the interface between the insulator and the semiconductor 127 is suppressed. Therefore, fluctuations in the threshold voltage are suppressed, and a memory device with good reliability can be provided.

[0119] Note that the memory string 120 can also be referred to as a memory device, and the memory element MC can also be referred to as a memory device.

[0120] To form insulators with reduced impurities such as nitrogen and carbon, such as the insulators 124, 126, and 129, it is preferable to use a silicon-containing gas 401 (precursor) and an oxidizing gas 402 (reactant) and form them by the ALD (Atomic Layer Deposition) method. Also, a noble gas such as helium, neon, argon, krypton, or xenon may be added to the oxidizing gas 402.

[0121] Examples of the ALD method include a thermal ALD (Thermal Atomic Layer Deposition) method in which the reaction of the precursor and the reactant is performed only with thermal energy, and a PEALD (Plasma Enhanced Atomic Layer Deposition) method that uses a plasma-excited reactant.

[0122] In addition, the ALD method utilizes the self-regulating property of atoms and can deposit atoms one by one, enabling extremely thin film formation, film formation on structures with a high aspect ratio, film formation with few defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. In the PEALD method, plasma is utilized, which may be preferable as it enables film formation at lower temperatures. Note that some of the precursors used in the ALD method contain carbon and the like. Therefore, the film formed by the ALD method may contain more impurities such as carbon compared to the film formed by other film formation methods. The quantification of impurities can be performed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0123] In this embodiment, the PEALD method is used. As gases containing silicon and not containing hydrocarbons, SiH4, Si2H6, SiF4, SiCl4, SiBr4, SiH2Cl2, SiH2I2, etc. can be used. As oxidizing gases, O2, O3, N2O, NO 2、 H2O, etc. can be used. In this embodiment, SiH4 is used as the gas 401 containing silicon and not containing hydrocarbons, and N2O is used as the oxidizing gas 402.

[0124] FIG. 7 shows a process flow for forming an insulator that can be used for the insulator 124, insulator 126, insulator 129, etc. by the PEALD method using SiH4 as the gas 401 containing silicon and N2O as the oxidizing gas 402, and FIG. 8A shows the film formation sequence thereof.

[0125] First, SiH4 and N2O are introduced into the reaction chamber, and the pressure in the reaction chamber is kept constant (step S01). Here, noble gases such as helium, neon, argon, krypton, and xenon may be introduced into the reaction chamber. When the flow rate ratio of SiH4 to N2O is such that the SiH4 flow rate is 1, N2O is set to be 10 or more and 3000 or less, preferably 10 or more and 800 or less, and more preferably 50 or more and 400 or less. Also, the pressure in the reaction chamber is set to be 200 Pa or more and 1200 Pa or less, preferably 400 Pa or more and 1000 Pa or less, and even more preferably 600 Pa or more and 800 Pa or less. Further, the substrate temperature is 100 °C or more and 500 °C or less, preferably 200 °C or more and 400 °C. Also, the substrate may not be heated, and film formation may be performed at room temperature.

[0126] Next, the introduction of SiH4 is stopped, and N2O is continuously introduced to purge the SiH4 remaining in the reaction chamber (step S02).

[0127] Next, high-frequency power 403 is supplied to the reaction chamber to generate N2O plasma. The frequency of the high frequency is set to be 13.56 MHz or more and 60 MHz or less. By oxidizing SiH adsorbed on the substrate in step S01 by the N2O plasma, x it is possible to form approximately a monolayer of silicon oxide (step S03). Note that nitrogen injected by the N2O plasma may be contained in the silicon oxide. Also, silicon oxide containing nitrogen may be called silicon oxynitride in some cases.

[0128] Next, the supply of the high-frequency power 403 is stopped (step S04).

[0129] Regarding the above steps S01 to S04 as one cycle, it is determined whether the number of cycles has reached a preset value (step S05). If not, the process returns to step S01. If it has reached, the process ends. By repeating the above cycle until the preset number of cycles is reached so as to obtain a desired film thickness, an insulator is formed. Also, as shown in FIG. 8B, in step S02, SiH 4、And stop introducing N2O and evacuate the SiH remaining in the reaction chamber 4、 A vacuum evacuation step of evacuating SiH and N2O may be inserted. At this time, the introduction of SiH4 、 And the introduction of N2O may be stopped simultaneously, or the introduction of N2O may be stopped after the introduction of SiH4 、 It is preferable to resume the introduction of N2O before the start of step S03.

[0130] The silicon oxide that becomes the insulator 124, the insulator 126, and the insulator 129 formed as described above is SiH 4、 And using N2O, a better insulator with a reduced hydrogen concentration and carbon concentration can be formed than the silicon oxide formed by the PECVD (PECVD: Plasma Enhanced CVD) method.

[0131] SiH 4、 The PECVD method using N2O applies high-frequency power in a state where SiH 4、 And N2O are introduced to generate plasma, so SiH4 is decomposed in the plasma, a large amount of hydrogen radicals are generated, and hydrogen is mixed into the silicon oxide. Further, since the insulator 124, the insulator 126, and the insulator 129 are in contact with one or both of the semiconductor 125 and the semiconductor 127, oxygen in the semiconductor 125 or the semiconductor 127 is extracted by the reduction reaction of hydrogen radicals and V O When H is formed, the hydrogen concentration in the semiconductor 125 or the semiconductor 127 becomes high.

[0132] On the other hand, in the PEALD method using SiH 4、 And N2O according to one aspect of the present invention, during the introduction of SiH 4、 And N2O in step 01, high-frequency power is not applied. In step 02, after purging the remaining SiH4, in step 03, plasma is generated by applying high-frequency power in a state where only N2O is introduced, so the generation of hydrogen radicals can be suppressed. Therefore, the mixing of hydrogen into the silicon oxide, the semiconductor 125, or the semiconductor 127 can be suppressed. Also, SiH4、 In the PEALD method using SiH4 and N2O as precursors, since a precursor containing impurities such as carbon, for example, an organic precursor having a CH group, is not used, it is possible to suppress the incorporation of impurities such as carbon and hydrocarbons into the silicon oxide. Since the silicon oxide formed in this way has a reduced impurity concentration and is a denser film, it is possible to prevent the diffusion of In from the semiconductor 125 or the semiconductor 127 into the silicon oxide.

[0133] The carbon concentration of the silicon oxide is preferably 1×10 18 atoms / cm 3 or more and 5×10 20 atoms / cm 3 or less, more preferably 5×10 18 atoms / cm 3 or more and 1×10 20 atoms / cm 3 or less, as determined by SIMS analysis. Further, the silicon oxide contains nitrogen, and the nitrogen concentration thereof is preferably 3×10 19 atoms / cm 3 or more and 1×10 21 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or more and 2×10 20 atoms / cm 3 or less, as determined by SIMS analysis.

[0134] As described above, by using a gas (precursor) containing silicon and not containing hydrocarbons and an oxidizing gas (reactant) according to one aspect of the present invention, and forming silicon oxide that becomes the insulator 124, the insulator 126, the insulator 129, etc. by the PEALD method, it is possible to obtain a transistor having excellent electrical characteristics and high reliability.

[0135] In addition, silicon oxide such as insulator 124, insulator 126, and insulator 129 preferably has an In concentration reduced as much as possible. Metal In in the silicon oxide may capture negative charges and affect transistor characteristics and their variations, such as a positive shift in the threshold voltage of the transistor and an increase in the S value. For example, when the threshold voltage of the transistor shifts to a positive value and becomes a normally-off characteristic, the transistor requires a higher drive voltage, making it difficult to drive at a low voltage. In this case, the power consumption of the transistor and the electronic device having the same increases.

[0136] Therefore, the In concentration contained in the silicon oxide is preferably 1.0×10 19 atoms / cm 3 or less, preferably 1.0×10 18 atoms / cm 3 or less, and more preferably 1.0×10 17 atoms / cm 3 or less.

[0137] [Constituent Materials of Semiconductor Device] Subsequently, constituent materials that can be used for the memory device 100 will be described.

[0138] [Substrate] The memory device 100 can be provided on a substrate. As the substrate, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as yttria-stabilized zirconia substrate), a resin substrate, and the like. Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, such as a SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, and the like. Or, there is a substrate having a metal nitride, a substrate having a metal oxide, and the like. Furthermore, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Or, those with elements provided on these substrates may also be used. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0139] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitroxides, metal oxides, metal oxynitrides, metal nitroxides, etc. that have insulating properties.

[0140] In this specification and the like, "oxynitride" refers to a material in which the oxygen content is higher than the nitrogen content as the main component. For example, "silicon oxynitride" refers to a material containing silicon, nitrogen, and oxygen in which the oxygen content is higher than the nitrogen content. Also, in this specification and the like, "nitroxide" refers to a material in which the nitrogen content is higher than the oxygen content as the main component. For example, "aluminum nitroxide" refers to a material containing aluminum, nitrogen, and oxygen in which the nitrogen content is higher than the oxygen content.

[0141] For example, as the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it becomes possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, for the insulator that functions as the interlayer film, by using a material with a low relative permittivity, the parasitic capacitance generated between the wirings can be reduced. Therefore, materials may be selected according to the function of the insulator.

[0142] In addition, examples of insulators with a high relative permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0143] In addition, examples of insulators with a low relative permittivity include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or resin.

[0144] In addition, the OS transistor can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a laminate. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0145] In addition, when an oxide semiconductor is used for the semiconductor 125 and / or the semiconductor 127, the insulator that functions as the gate insulator preferably is an insulator having a region containing oxygen that desorbs upon heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that desorbs upon heating is in contact with the semiconductor 125 and / or the semiconductor 127, the oxygen deficiency of the semiconductor 125 and / or the semiconductor 127 can be compensated.

[0146] In addition, it is preferable to provide an insulator 181 to suppress the oxidation of the conductor 182 that functions as the conductor WWL and the conductor 183 that functions as the conductor SEL. As the insulator 181, it is preferable to use the above materials having a barrier property against oxygen and hydrogen. The insulator 181 is preferably provided so as to be in contact with the lower surface, upper surface, and side surfaces of the conductor 182 and the conductor 183.

[0147] As the insulators 124, 126, and 129 that are in contact with one or both of the semiconductors 125 and 127, it is preferable to use insulators with reduced impurities such as nitrogen and carbon. To form such an insulator, it is preferable to use the ALD method. In particular, it is preferable to use the PEALD method that utilizes plasma.

[0148] The carbon concentration of the insulators 124, 126, and 129 is preferably 1×10 18 atoms / cm 3 or more and 5×10 20 atoms / cm 3 or less, more preferably 5×10 18 atoms / cm 3 or more and 1×10 20 atoms / cm 3 or less by SIMS analysis. Also, the insulators 124, 126, and 129 contain nitrogen, and the nitrogen concentration is preferably 3×10 19 atoms / cm 3 or more and 1×10 21 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or more and 2×10 20 atoms / cm 3 or less by SIMS analysis.

[0149] Also, the In concentration contained in the insulators 124, 126, and 129 is 1.0×10 19 atoms / cm 3 or less, preferably 1.0×10 18 atoms / cm 3 or less, more preferably 1.0×10 17 atoms / cm 3 or less, and it is preferable that it is so.

[0150] The ALD method utilizes the self - controllability of precursor molecules or atoms contained in the precursors, enabling the deposition of atoms layer by layer. As a result, it is possible to form extremely thin films, deposit films onto structures with a high aspect ratio, form films with few defects such as pinholes, form films with excellent coverage, and form films at low temperatures, among other effects. Also, by using plasma ALD method, film deposition at even lower temperatures becomes possible, which is preferable. On the other hand, an ALD method (sometimes referred to as thermal ALD method) in which the reactions of precursors and reactants are carried out using thermal energy may also be used.

[0151] [Conductor] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above - mentioned metal elements as components, or an alloy combining the above - mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Also, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Further, semiconductors with high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may also be used.

[0152] Also, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure combining the material containing the above-described metal element and the conductive material containing oxygen may be used. Further, a laminated structure combining the material containing the above-described metal element and the conductive material containing nitrogen may be used. Further, a laminated structure combining the material containing the above-described metal element, the conductive material containing oxygen, and the conductive material containing nitrogen may be used.

[0153] In addition, when an oxide semiconductor, which is a kind of metal oxide, is used for the channel formation region of the transistor, it is preferable to use a laminated structure combining the material containing the above-described metal element and the conductive material containing oxygen as the conductor functioning as the gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0154] In particular, as the conductor functioning as the gate electrode, it is preferable to use a conductive material containing the metal element and oxygen contained in the oxide semiconductor in which the channel is formed. Further, the conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the oxide semiconductor in which the channel is formed may be captured. Alternatively, hydrogen mixed from an external insulator or the like may be captured.

[0155] [Oxide semiconductor] As the semiconductor 125 and the semiconductor 127, it is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor. Hereinafter, the oxide semiconductors applicable to the semiconductor 125 and the semiconductor 127 will be described.

[0156] The oxide semiconductor preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0157] Here, consider the case where the oxide semiconductor is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is one or more selected from aluminum, gallium, yttrium, and tin. Applicable elements for other element Ms include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. However, there may be cases where a plurality of the aforementioned elements may be combined as element M.

[0158] Note that in this specification and the like, a metal oxide having nitrogen may also be generically referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0159] 〔Classification of crystal structure〕 First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 9A. FIG. 9A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0160] As shown in FIG. 9A, oxide semiconductors are roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "Amorphous" includes completely amorphous. Also, "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Also, "Crystal" includes single crystal and poly crystal.

[0161] Note that the structure within the thick frame shown in FIG. 9A is an intermediate state between "Amorphous" and "Crystal", and belongs to a new boundary region (New crystalline phase). That is, the structure can be paraphrased as a structure that is energetically unstable "Amorphous" or completely different from "Crystal".

[0162] Note that the crystal structure of a film or a substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, FIG. 9B shows the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of a CAAC-IGZO film classified as "Crystalline". Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 9B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in FIG. 9B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in FIG. 9B is 500 nm.

[0163] As shown in FIG. 9B, in the XRD spectrum of the CAAC-IGZO film, peaks indicating distinct crystallinity are detected. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected near 2θ = 31°. As shown in FIG. 9B, the peak near 2θ = 31° is asymmetric about the angle at which the peak intensity was detected.

[0164] Also, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 9C. FIG. 9C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in FIG. 9C is near In:Ga:Zn = 4:2:3 [atomic ratio]. Also, in the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0165] As shown in FIG. 9C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0166] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from FIG. 9A. For example, oxide semiconductors can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Also, non-single-crystalline oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

[0167] Subsequently, details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0168] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the plurality of crystal regions have their c-axes oriented in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. The strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in the region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor with c-axis orientation and no clear orientation in the a-b plane direction.

[0169] Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0170] Also, in an In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer) are laminated. Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0171] When performing a structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in an out-of-plane XRD measurement using a θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting CAAC-OS.

[0172] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0173] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0174] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers and are likely to cause a decrease in the on-current of a transistor and a decrease in the field-effect mobility due to the capture of carriers. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that for forming CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0175] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct crystal grain boundaries. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to crystal grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to impurity incorporation or defect generation, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0176] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Note that since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nano-crystals. Also, nc-OS has no regularity in crystal orientation among different nano-crystals. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scan. Also, when electron beam diffraction (also referred to as restricted field electron beam diffraction) using an electron beam with a probe diameter larger than the nano-crystals (for example, 50 nm or more) is performed on an nc-OS film, a diffraction pattern like a halo pattern is observed. On the other hand, when electron beam diffraction (also referred to as nano-beam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than the nano-crystals (for example, 1 nm or more and 30 nm or less) is performed on an nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be obtained.

[0177] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared to the nc-OS and the CAAC-OS.

[0178] [Constitution of Oxide Semiconductor] Next, the details of the above-described CAC-OS will be described. Note that the CAC-OS relates to the material constitution.

[0179] [CAC-OS] The CAC-OS is, for example, a configuration of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. Hereinafter, in the metal oxide, one or more metal elements are unevenly distributed, and a region having the metal element is in a state of being mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof, which is also referred to as a mosaic state or a patch state.

[0180] Furthermore, the CAC-OS is a configuration in which the material is separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter, also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.

[0181] Here, the atomic number ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0182] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0183] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0184] For example, in the CAC-OS in the In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0185] When CAC-OS is used in a transistor, the conductivity resulting from the first region and the insulating property resulting from the second region act complementarily, enabling the function of switching (the function of turning on / off) to be imparted to the CAC-OS. That is, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on )、high field-effect mobility (μ), and good switching operation can be realized.

[0186] Oxide semiconductors have various structures, each having different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0187] [Transistor having an oxide semiconductor] Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0188] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0189] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is preferably 1×10 18 cm -3 or less, more preferably 1×10 17 cm -3 or less, even more preferably 1×10 16 cm -3 or less, even more preferably 1×10 13 cm -3 or less, even more preferably 1×10 12 cm-3 It is more preferable that it is less than that. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as highly pure intrinsic or substantially highly pure intrinsic. In some cases, an oxide semiconductor with a low carrier concentration is referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. In some cases, being highly pure intrinsic or substantially highly pure intrinsic is referred to as type i or substantially type i.

[0190] In addition, since an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0191] In addition, the charge trapped in the trap levels of the oxide semiconductor takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0192] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0193] 〔Impurities〕 Here, the influence of each impurity in the oxide semiconductor will be described.

[0194] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is included, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon near the interface with the channel formation region of the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0195] In addition, when an alkali metal or an alkaline earth metal is included in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0196] In addition, in an oxide semiconductor, when nitrogen is included, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, when nitrogen is included in the oxide semiconductor, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm3 Make it as follows.

[0197] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, carriers such as electrons may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate carriers such as electrons. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the channel formation region of the oxide semiconductor is reduced as much as possible. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 less than, preferably less than 5×10 19 atoms / cm 3 less than, more preferably less than 1×10 19 atoms / cm 3 less than, still more preferably less than 5×10 18 atoms / cm 3 less than, still more preferably less than 1×10 18 atoms / cm 3 Make it less than.

[0198] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0199] 〔Other semiconductor materials〕 The semiconductor materials that can be used for semiconductor 125 and semiconductor 127 are not limited to the above-described oxide semiconductors. As semiconductor 125 and semiconductor 127, a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, a single-element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, or a layer material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, etc.) may be used as the semiconductor material. In particular, it is preferable to use a layer material that functions as a semiconductor as the semiconductor material.

[0200] In this specification and the like, the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via a bond weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0201] Examples of the layered material include graphene, silicene, and chalcogenides. A chalcogenide is a compound containing a chalcogen. Further, chalcogen is a general term for elements belonging to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0202] As the semiconductor 125 and the semiconductor 127, for example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor. Specific examples of transition metal chalcogenides applicable as the semiconductor 125 and the semiconductor 127 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), and the like.

[0203] <Example of manufacturing method of memory device> Next, an example of a method for manufacturing a memory device according to the present invention will be described with reference to FIGS. 10 to 19. Each of FIGS. 10 to 19 shows a cross section in the X-Z plane and is a cross-sectional view seen from the Y direction. In this manufacturing method, an example of manufacturing three memory strings 120 each having five (also referred to as "five stages") memory elements MC is shown, but the present embodiment is not limited to this. The memory string 120 may have two or more stages of memory elements MC. For example, the memory string 120 may have four stages of memory elements MC. Further, it is preferable that the memory string 120 has 32 or more stages, preferably 64 or more stages, more preferably 128 or more stages, and still more preferably 256 or more stages of memory elements MC. Further, by using one aspect of the present embodiment, two or more memory strings 120 can be manufactured simultaneously.

[0204] First, a conductor 122 is formed on a substrate 121 having an insulating surface, and an insulator 132 is formed around the conductor 122 (see FIG. 10).

[0205] Specifically, a conductive film is formed, the conductive film is processed using a lithography method to form the conductor 122. Next, an insulating film is formed on the substrate 121 so as to cover the conductor 122. Next, it is preferable to perform a planarization process on the insulating film. In the planarization process, it is preferable to polish the insulating film until the surface of the conductor 122 is exposed. By the above method, the insulator 132 can be formed. However, the formation methods of the conductor 122 and the insulator 132 are not limited to this. The insulator 132 may be formed on the substrate 121, unnecessary portions of the insulator 132 may be removed to form grooves and openings, and the conductor 122 may be formed so as to be embedded in the grooves and the openings. Such a method of forming a conductor is sometimes referred to as a damascene method (single damascene method, dual damascene method). By the above method, the structure shown in FIG. 10 can be obtained.

[0206] The formation of the conductor 122 and the insulator 132 can be performed using a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0207] Note that the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method that uses plasma, a thermal CVD (TCVD: Thermal CVD) method that uses heat, a photo CVD method that uses light, and the like. Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method depending on the source gas used.

[0208] In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Also, since the thermal CVD method does not use plasma, it is a film-forming method capable of reducing plasma damage to the object to be processed. For example, wirings, electrodes, elements (such as transistors and capacitor elements) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged by the accumulated charges. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Also, in the thermal CVD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

[0209] Also, the ALD method is also a film-forming method capable of reducing plasma damage to the object to be processed. Also, since plasma damage does not occur during film formation in the ALD method, a film with few defects can be obtained.

[0210] Unlike film deposition methods in which particles emitted from a target or the like are deposited, the CVD method and the ALD method are film deposition methods in which a film is formed by a gas-phase reaction on the surface of an object to be processed. Therefore, it is a film deposition method that is less affected by the shape of the object to be processed and has good step coverage. In particular, since the ALD method has excellent step coverage and excellent thickness uniformity, it is suitable for covering the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film deposition rate, it may be preferable to use it in combination with other film deposition methods such as the CVD method with a high film deposition rate.

[0211] In addition, in the CVD method, a film with an arbitrary composition can be formed by the flow rate ratio of the source gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while depositing the film. When depositing a film while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened by the time required for transportation and pressure adjustment compared to the case of using a plurality of film deposition chambers. Therefore, the productivity of semiconductor devices may be increased.

[0212] In addition, in the ALD method, a film with an arbitrary composition can be formed by simultaneously introducing a plurality of precursors with different compositions or by controlling the number of cycles of each precursor for a plurality of precursors with different compositions.

[0213] In the lithography method, first, a resist is exposed through a photomask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, by performing an etching process through the resist mask, conductors, semiconductors, insulators, etc. can be processed into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Also, a liquid immersion technique can be used, where a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Instead of the light described above, an electron beam or an ion beam can also be used. Note that when using an electron beam or an ion beam, a photomask is not required. For removing the resist mask, dry etching treatment such as ashing, wet etching treatment, wet etching treatment after dry etching treatment, or dry etching treatment after wet etching treatment can be performed.

[0214] Alternatively, a hard mask made of an insulator or a conductor can be used instead of the resist mask. When using a hard mask, an insulating film or a conductive film serving as a hard mask material is formed on the conductive film, a resist mask is formed thereon, and a hard mask having a desired shape can be formed by etching the hard mask material.

[0215] The above processing can use a dry etching method or a wet etching method. Processing by the dry etching method is suitable for microfabrication.

[0216] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency power source to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency power sources to one of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency power sources of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency power sources of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0217] When using a hard mask for etching the conductive film, the etching process may be performed after removing the resist mask used for forming the hard mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the etching of the conductive film. On the other hand, if the material of the hard mask has no influence on the subsequent process or can be used in the subsequent process, it is not necessarily required to remove the hard mask.

[0218] The conductive film serving as the conductor 122 is preferably formed of a conductive film containing a metal element by using a sputtering method. It can also be formed by using a CVD method.

[0219] The surface of the insulator 132 is preferably subjected to a planarization process as required. For the planarization process, a chemical mechanical polishing (CMP) method or a reflow method can be used.

[0220] An insulating film 123A, an insulating film 135A, and a conductive film 136A are alternately laminated on the conductor 122 and the insulator 132. In the present embodiment, an example is shown in which the insulating film 123A is formed on the insulator 132, the insulating film 135A is formed on the insulating film 123A, the insulating film 123A is formed on the insulating film 135A, and the conductive film 136A is formed on the insulating film 123A (see FIG. 10). For the formation of the insulating film 135A, the conductive film 136A, and the insulating film 123A, the CVD method can be used. Also, the sputtering method may be used.

[0221] As the conductor 122 and the conductive film 136A, a conductive material such as silicon doped with impurities or a metal can be used. Since the conductive film 136A needs to be selectively etched with respect to the conductor 122 and the insulating film 135A in a subsequent process, it is preferably a material capable of selective etching with respect to the conductor 122 and the insulating film 135A. When silicon is used as the conductor 122 or the conductive film 136A, amorphous silicon or polysilicon can be used. Also, in order to impart conductivity to silicon, a p-type impurity or an n-type impurity may be added. Further, as the conductive material containing silicon, a silicide containing titanium, cobalt, or nickel can be used as the conductor 122 or the conductive film 136A. Also, when a metal material is used for the conductor 122 or the conductive film 136A, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used.

[0222] As the insulator 132, the insulating film 135A, and the insulating film 123A, oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. having insulating properties can be used. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores or resin, aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium or nitrides having silicon and hafnium, etc. can be used.

[0223] In the subsequent process, since the insulating film 135A needs to be selectively etched with respect to the insulator 132 and the insulating film 123A, it is preferably a material capable of selective etching with respect to the insulator 132 and the insulating film 123A. For example, it is preferable that the insulator 132 and the insulating film 123A are made of silicon oxide or silicon oxynitride, and the insulating film 135A is made of silicon nitride or silicon nitride oxide.

[0224] In addition, in this embodiment, an example in which 12 layers of the insulating film 123A, 6 layers of the insulating film 135A, and 5 layers of the conductive film 136A are formed is shown, but the number of stacked layers is not limited to this. They can be formed respectively according to the required performance of the semiconductor device. Here, if the number of stacked layers of the insulating film 135A is m (m is an integer of 2 or more), the number of stacked layers of the insulating film 123A is 2×m, and the number of stacked layers of the conductive film 136A is m - 1. For example, m can be 33 or more, preferably 65 or more, more preferably 129 or more, and still more preferably 257 or more.

[0225] An insulating film 137A is formed on the uppermost insulating film 123A, and an insulating film 138A is formed on the insulating film 137A. The insulating film 137A can be formed of the same material using the same method as the insulating film 135A. Also, the insulating film 138A can be formed of the same material using the same method as the insulating film 123A. Further, a mask 140A is formed on the insulating film 138A.

[0226] Next, using the mask 140A, the insulating film 138A, the insulating film 137A, the insulating film 123A, the insulating film 135A, and the conductive film 136A are processed to form a first opening so as to expose the conductor 122 (see FIG. 11). By this processing, the mask 140A may be etched to become a mask 140B.

[0227] Next, anisotropic etching is performed on the conductive film 136A to increase the diameter of the opening of the conductive film 136A (see FIG. 12). By this treatment, the diameter of the opening of the conductive film 136A becomes larger than the diameters of the openings of the insulating film 138A, the insulating film 137A, the insulating film 123A, and the insulating film 135A. Also, it can be said that the conductive film 136A has recesses with respect to the side surfaces of the insulating film 138A, the insulating film 137A, the insulating film 123A, or the insulating film 135A located above or below. For such processing, anisotropic etching by dry etching using a gas, radical, plasma, etc., or anisotropic etching by wet etching using a liquid can be used. The liquid used for wet etching is sometimes called an etchant. When performing anisotropic etching using dry etching, a gas, radical, plasma, etc. containing at least one of chlorine, bromine, and fluorine can be used. Anisotropic etching is preferably performed without removing the mask used for the formation of the first opening. The first opening obtained by the above treatment corresponds to the opening 141 shown in FIG. 3.

[0228] Next, an insulating film 124A and a conductive film 128A are formed on the insulating film 138A, the mask 140B, and inside the first opening (see FIG. 12). Although not shown, the insulating film 124A may have a laminated structure. The insulating film 124A can be formed using a CVD method or an ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio, which is preferable.

[0229] Also, by using the PEALD method, the insulating film 124A can be formed at a lower temperature compared to the thermal ALD method, which is preferable. For example, it is preferable to form the insulating film 124A using the PEALD method with a gas containing silicon as a precursor and an oxidizing gas as a reactant. As the gas containing silicon, SiH4, SiF4, SiH2Cl2, SiCl4, etc. can be used. In particular, it is preferable to use SiH4. As the oxidizing gas, O2, O3, N2O, NO2, etc. can be used. In particular, it is preferable to use N2O. Also, as a reactant, a noble gas such as helium, neon, argon, krypton, or xenon may be added to the above oxidizing gas. When the insulating film 124A has a laminated structure, each insulating film may be formed by the same film-forming apparatus or different film-forming apparatuses. Also, the insulating film 124A may be formed by combining the ALD method and the CVD method.

[0230] The insulating film 124A formed by the above method has good coverage, and the insulating film 124A can be formed even for the recesses of the conductive film 136A. That is, the insulating film 124A can be formed so as to be in contact not only with the side surfaces of the insulating film 123A, the insulating film 135A, and the conductive film 136A, but also with a part of the upper surface and a part of the lower surface of the insulating film 123A.

[0231] Also, the carbon concentration of the insulating film 124A is preferably 1×10 18 atoms / cm 3 or more and 5×10 20 atoms / cm 3 or less, more preferably 5×1018 atoms / cm 3 1 × 10 or more 20 atoms / cm 3 is below. Further, the insulating film 124A contains nitrogen, and the nitrogen concentration thereof is preferably 3 × 10 19 atoms / cm 3 1 × 10 or more 21 atoms / cm 3 and below, more preferably 1 × 10 19 atoms / cm 3 2 × 10 or more 20 atoms / cm 3 is below.

[0232] Further, the In concentration contained in the insulating film 124A is 1.0 × 10 19 atoms / cm 3 and below, preferably 1.0 × 10 18 atoms / cm 3 and below, more preferably 1.0 × 10 17 atoms / cm 3 is preferably below.

[0233] The conductive film 128A only needs to be formed so as to fill at least the concave portion of the conductive film 136A via the insulating film 124A, and it is not necessarily required to fill all of the inside of the first opening. The conductive film 128A can be formed using a CVD method or an ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio, which is preferable. Alternatively, the conductive film 128A may be formed by combining the ALD method and the CVD method.

[0234] Next, the conductive film 128A is processed to form the conductor 128 (see FIG. 13). Isotropic etching or anisotropic etching can be used for processing the conductive film 128A. In the formation of the conductive film 128A, as shown in FIG. 12, when the conductive film 128A fills the concave portion and the first opening is not completely filled, it is preferable to use isotropic etching for processing the conductive film 128A. On the other hand, when the conductive film 128A is formed so as to fill the concave portion and the first opening, it is preferable to use anisotropic etching. Through the above processing, the conductor 128 can be formed inside the concave portion.

[0235] Next, the insulating film 124A formed at the bottom of the first opening is removed to obtain the insulator 124. It is preferable to use anisotropic etching for removing the insulating film 124A. At this time, since the insulating film 124A on the insulating film 138A and the mask 140B is also removed, the insulator 124 is provided only on the side wall of the first opening (see FIG. 13). By removing the insulating film 124A at the bottom of the first opening, the conductor 122 is exposed again.

[0236] Next, a semiconductor film 125A is formed inside the first opening so as to be in contact with the conductor 122 (see FIG. 13). The semiconductor film 125A can be formed using a CVD method or an ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio, which is preferable. Also, by using the PEALD method, the semiconductor film 125A can be formed at a lower temperature compared to the thermal ALD method, which is preferable. Alternatively, the semiconductor film 125A may be formed by combining the ALD method and the CVD method. The semiconductor film 125A is preferably an oxide semiconductor having a CAAC structure. When the semiconductor film 125A is an oxide semiconductor having a CAAC structure, the c-axis of the semiconductor film 125A is oriented in the normal direction of the formation surface inside the first opening. At this time, via the insulator 124, the c-axis of the semiconductor film 125A located on the side surfaces of the insulating film 138A, the insulating film 137A, the insulating film 123A, the insulating film 135A, and the conductive film 136A is oriented from the formation surface toward the axis 185 shown in FIG. 13. Note that the axis 185 can be referred to as the central axis of the first opening. Thereby, the c-axis of the semiconductor 125 located above is oriented from the formation surface toward the axis 185.

[0237] Here, when forming a metal oxide using the ALD method as the semiconductor film 125A, it is preferable to form an In-Ga-Zn oxide using a precursor containing indium, a precursor containing gallium, and a precursor containing zinc. Alternatively, an In-Ga-Zn oxide may be formed using a precursor containing indium and gallium and a precursor containing zinc.

[0238] As precursors containing indium, triethylindium, trimethylindium, tris(2,2,6,6 - tetramethyl - 3,5 - heptanedionato)indium, cyclopentadienylindium, indium(III) chloride, etc. can be used. Also, as precursors containing gallium, trimethylgallium, triethylgallium, tris(dimethylamide)gallium, gallium(III) acetylacetonate, tris(2,2,6,6 - tetramethyl - 3,5 - heptanedionato)gallium, dimethylchlorogallium, diethylchlorogallium, gallium(III) chloride, etc. can be used. Further, as precursors containing zinc, dimethylzinc, diethylzinc, bis(2,2,6,6 - tetramethyl - 3,5 - heptanedionato)zinc, zinc chloride, etc. can be used.

[0239] Next, an insulating film 126A is formed inside the semiconductor film 125A (see Fig. 13).

[0240] The insulating film 126A can be formed using the CVD method or the ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio, which is preferable. Also, by using the PEALD method, the insulating film 126A can be formed at a lower temperature compared to the thermal ALD method, which is preferable. Alternatively, the insulating film 126A may be formed by combining the ALD method and the CVD method. For example, the insulating film 126A can be formed in the same manner as the insulating film 124A. For example, it is preferable to form the insulating film 126A using the PEALD method with a gas containing silicon as a precursor and an oxidizing gas as a reactant. As the gas containing silicon, SiH4, SiF4, SiH2Cl2, etc. can be used. In particular, it is preferable to use SiH4. As the oxidizing gas, O2, O3, N2O, NO2, etc. can be used. In particular, it is preferable to use N2O. Also, a noble gas such as helium, neon, argon, krypton, or xenon may be added to the reactant.

[0241] Also, the carbon concentration of the insulating film 126A is preferably 1×10 18 atoms / cm 3 or more and 5×10 20 atoms / cm 3 or less, more preferably 5×10 18 atoms / cm 3 or more and 1×10 20 atoms / cm 3 or less. Also, the insulating film 126A contains nitrogen, and its nitrogen concentration is preferably 3×10 19 atoms / cm 3 or more and 1×10 21 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or more and 2×10 20 atoms / cm 3 or less.

[0242] Also, the In concentration contained in the insulating film 126A is preferably 1.0×10 19 atoms / cm 3 or less, preferably 1.0×10 18 atoms / cm 3 or less, more preferably 1.0×10 17 atoms / cm 3 or less.

[0243] Next, an insulator 131A is formed on the upper surface of the insulating film 126A. The insulator 131A is preferably selectively formed so as not to be formed inside the first opening. Alternatively, the insulator 131A may be formed on the upper surface of the insulating film 126A and inside the first opening, a mask may be formed on the upper surface of the insulating film 126A via the insulator 131A, and the insulator 131A inside the first opening may be selectively removed. As the insulator 131A, silicon nitride is preferably used. To selectively form the insulator 131A on the upper surface of the insulating film 126A, it is preferable to use the PECVD method. Further, by using a mixed gas containing SiH4 and N2 as the film-forming gas, the formation of the insulator 131A inside the first opening is suppressed, which is preferable. Further, when NH3 is contained in the mixed gas, the insulator 131A is likely to be formed inside the first opening, so it is preferable that the mixed gas does not contain NH3. Further, when the mixed gas contains N2 and NH3, the mixing ratio of NH3 is preferably 10% or less, preferably 5% or less, more preferably 1% or less of the mixing ratio of N2. Further, in the mixed gas, when the ratio (flow rate ratio) of N2 to SiH4 is low, the amount of nitrogen contained in the insulator 131A decreases, and amorphous silicon may be formed. Therefore, it is preferable to set the ratio (flow rate ratio) of N2 to SiH4 to 100 or more.

[0244] Next, a part of the semiconductor film 125A is made to have a high resistance to form a high-resistance region (type I region). As a method for forming the high-resistance region, the semiconductor film 125A may be irradiated with microwaves to remove hydrogen contained in the semiconductor film 125A. Further, it is preferable to perform the microwave irradiation in an atmosphere containing oxygen because oxygen is supplied to the semiconductor film 125A. In the present embodiment, the semiconductor film 125A is irradiated with microwaves in an atmosphere containing oxygen and argon to make the semiconductor film 125A have a high resistance. At this time, in the region where the semiconductor film 125A is in contact with the conductor 128, the resistance value may remain low.

[0245] In microwave treatment, thermal energy may be directly transferred to the semiconductor film 125A due to the electromagnetic interaction between microwaves and the molecules in the semiconductor film 125A. The semiconductor film 125A may be heated by this thermal energy. Such a heat treatment may be called microwave annealing. By performing the microwave treatment in an atmosphere containing oxygen, an effect equivalent to oxygen annealing may be obtained. Further, when hydrogen is contained in the semiconductor film 125A, it is considered that this thermal energy is transmitted to the hydrogen in the semiconductor film 125A, and the activated hydrogen is released from the semiconductor film 125A.

[0246] Here, heat treatment may be performed. The heat treatment is preferably performed in an atmosphere containing nitrogen at 200°C or higher and 500°C or lower, and more preferably 300°C or higher and 400°C or lower. The atmosphere for performing the heat treatment is not limited to the above, and may be performed in an atmosphere containing at least one of nitrogen, oxygen, and argon. Further, the heat treatment may be performed in a reduced-pressure atmosphere or in an atmospheric-pressure atmosphere.

[0247] By the heat treatment, the semiconductor film 125A in contact with the conductor 128 can be made to have a lower resistance and a low-resistance region (N-type region) can be formed. When the heat treatment is performed in a state where the semiconductor film 125A and the conductor 128 are in contact, a metal compound layer containing the metal elements of the conductor 128 and the components of the semiconductor film 125A may be formed at the interface between the conductor 128 and the semiconductor film 125A. The formation of the metal compound layer is preferable because the resistance of the semiconductor film 125A is reduced in the region in contact with the conductor 128. Further, the oxygen contained in the semiconductor film 125A may be absorbed by the conductor 128. When the heat treatment is performed in a state where the semiconductor film 125A and the conductor 128 are in contact, the semiconductor film 125A has a lower resistance. Further, by the heat treatment, the semiconductor film 125A may become CAAC-OS or nc-OS. Further, the crystallinity of the semiconductor film 125A may be improved. The heat treatment may be performed before the microwave treatment. On the other hand, the above-mentioned microwave treatment, that is, microwave annealing, may also serve as the heat treatment. When the semiconductor film 125A and the like are sufficiently heated by microwave annealing, the heat treatment may not be performed.

[0248] The carrier concentration of the semiconductor film 125A after the above microwave treatment and heat treatment is less than 1×10 18 / cm 3 and preferably less than 1×10 17 / cm 3 and more preferably less than 1×10 16 / cm 3 It is preferable that it is as follows. Further, the carrier concentration in the region where the semiconductor film 125A is in contact with the conductor 128 is 1×10 18 / cm 3 or more, preferably 1×10 19 / cm 3 or more, and more preferably 1×10 20 / cm 3 or more.

[0249] Note that, in the above, an example in which the high-resistance treatment of the semiconductor film 125A is performed after the formation of the insulating film 126A is shown, but the present embodiment is not limited to this. The high-resistance treatment may be performed before the formation of the insulating film 126A.

[0250] Next, the semiconductor film 125A and the insulating film 126A formed at the bottom of the first opening are removed to obtain a semiconductor 125B and an insulator 126B. For removing the semiconductor film 125A and the insulating film 126A, it is preferable to use anisotropic etching using the insulator 131A as a mask. At this time, the semiconductor film 125A and the insulating film 126A on the insulating film 138A and the mask 140B are not removed because they are covered with the insulator 131A (see FIG. 14). By removing the semiconductor film 125A and the insulating film 126A at the bottom of the first opening, the conductor 122 is exposed again.

[0251] Next, a semiconductor film 127A is formed inside the first opening so as to be in contact with the conductor 122 (see FIG. 14). At this time, the semiconductor film 127A is preferably formed so as to be in contact with the semiconductor 125B at the bottom of the first opening. The semiconductor film 127A can be formed using a CVD method or an ALD method. In particular, using the ALD method is preferable because a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio. Also, using the PEALD method is preferable because the semiconductor film 127A can be formed at a lower temperature compared to the thermal ALD method. Alternatively, the semiconductor film 127A may be formed by combining the ALD method and the CVD method. Also, the semiconductor film 127A is preferably an oxide semiconductor having a CAAC structure. When the semiconductor film 127A is an oxide semiconductor having a CAAC structure, the c-axis of the semiconductor film 127A is oriented in the normal direction of the surface to be formed inside the first opening. At this time, the c-axis of the semiconductor film 127A located on the side surface of the first opening is oriented from the surface to be formed toward the axis 185 shown in FIG. 14. Thereby, the c-axis of the semiconductor 127 located above is oriented from the surface to be formed toward the axis 185.

[0252] Here, when forming a metal oxide using the ALD method as the semiconductor film 127A, it is preferable to form an In-Ga-Zn oxide using a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.

[0253] As precursors containing indium, triethylindium, indium tris(2,2,6,6-tetramethyl-3,5-heptanedionate), cyclopentadienylindium, indium(III) chloride, etc. can be used. Further, as precursors containing gallium, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium, gallium(III) acetylacetonate, gallium tris(2,2,6,6-tetramethyl-3,5-heptanedionate), dimethylchlorogallium, diethylchlorogallium, gallium(III) chloride, etc. can be used. Further, as precursors containing zinc, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0254] Next, an insulating film 129A is formed inside the semiconductor film 127A, and a conductive film 130A is formed inside the insulating film 129A (see FIG. 14). The semiconductor film 127A, the insulating film 129A, and the conductive film 130A can be formed using a CVD method or an ALD method. By using the CVD method or the ALD method, a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio, which is preferable. Alternatively, they may be formed by combining the ALD method and the CVD method. Also, different film formation methods and film formation apparatuses may be used for each film to be formed. For example, it is preferable to use the ALD method for forming the semiconductor film 127A.

[0255] Further, for forming the insulating film 129A, it is preferable to use the PEALD method because the insulating film 129A can be formed at a lower temperature compared to the thermal ALD method. Also, for forming the conductive film 130A, it is preferable to use the CVD method. Alternatively, when the conductive film 130A has a laminated structure, the first layer of the conductive film 130A may be formed using the ALD method, and the second layer of the conductive film 130A may be formed using the CVD method.

[0256] For example, the insulating film 129A can be formed in the same manner as the insulating film 124A. For example, it is preferable to form the insulating film 129A using the PEALD method with a gas containing silicon as a precursor and an oxidizing gas as a reactant. As the gas containing silicon, SiH4, SiF4, SiH2Cl2, etc. can be used. In particular, it is preferable to use SiH4. As the oxidizing gas, O2, O3, N2O, NO2, etc. can be used. In particular, it is preferable to use N2O. Also, a noble gas such as helium, neon, argon, krypton, or xenon may be added to the reactant.

[0257] In addition, the carbon concentration of the insulating film 129A is preferably 1×10 18 atoms / cm 3 or more and 5×10 20 atoms / cm 3 or less, more preferably 5×10 18 atoms / cm 3 or more and 1×10 20 atoms / cm 3 or less, as determined by SIMS analysis. Also, the insulating film 129A contains nitrogen, and its nitrogen concentration is preferably 3×10 19 atoms / cm 3 or more and 1×10 21 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or more and 2×10 20 atoms / cm 3 or less, as determined by SIMS analysis.

[0258] In addition, the In concentration contained in the insulating film 129A is 1.0×10 19 atoms / cm 3 or less, preferably 1.0×10 18 atoms / cm 3 or less, more preferably 1.0×10 17 atoms / cm 3 or less, and is preferably such.

[0259] Here, a high-resistance treatment similar to that performed on the semiconductor film 125A may be performed on the semiconductor film 127A. When performing a high-resistance treatment on the semiconductor film 127A, it is preferable to perform the high-resistance treatment before the formation of the conductive film 130A or before the formation of the insulating film 129A. Further, when the high-resistance treatment of the semiconductor film 127A can also perform the high-resistance treatment of the semiconductor film 125A, the high-resistance treatment in the previous step may be omitted.

[0260] Next, a heat treatment is performed. The heat treatment is preferably performed at 200°C or higher and 500°C or lower, more preferably 300°C or higher and 400°C or lower, in an atmosphere containing nitrogen. The atmosphere for performing the heat treatment is not limited to the above, and may be performed in an atmosphere containing at least one of nitrogen, oxygen, and argon. Further, the heat treatment may be performed in a reduced-pressure atmosphere or in an atmospheric-pressure atmosphere. Further, the semiconductor film 127A may become CAAC-OS or nc-OS by the heat treatment. Further, the crystallinity of the semiconductor film 127A may be improved. The heat treatment may be performed by microwave annealing.

[0261] Microwave treatment can be used for the above high-resistance treatment and heat treatment.

[0262] Next, the conductive film 130A, the insulating film 129A, the semiconductor film 127A, the insulator 131A, the insulator 126B, the semiconductor 125B, and the mask 140B are processed to obtain the conductor 130, the insulator 129, the semiconductor 127, the insulator 131, the insulator 126, the semiconductor 125, and the mask 140 (see FIG. 15). The processing can use a dry etching method or a wet etching method. The processing by the dry etching method is suitable for microfabrication. In this processing, the conductive film 130A is processed, and after the processing of the conductive film 130A, the insulating film 129A and the semiconductor film 127A are processed. After the processing of the insulating film 129A and the semiconductor film 127A, the insulator 131A, the insulator 126B, the semiconductor 125B, and the mask 140B may be processed. In such a processing step, different masks may be formed in each processing step. Also, as the first processing, the conductive film 130A, the insulating film 129A, the semiconductor film 127A, the insulator 131A, the insulator 126B, the semiconductor 125B, and the mask 140B are processed using a mask, and then, as the second processing, the conductive film 130A, the insulating film 129A, and the semiconductor film 127A are processed again, and further, as the third processing, the conductive film 130A may be processed again. The masks used for the second processing and the third processing may be the masks used in the first processing after being processed, or different masks may be formed.

[0263] Next, an insulator 139 is formed on the insulating film 138A so as to cover the conductor 130, the insulator 129, the semiconductor 127, the insulator 131, the insulator 126, the semiconductor 125, and the mask 140. The insulator 139 can be formed by a method that can be used for forming the insulator 132, and a material that can be used for the insulator 132 can be used.

[0264] Next, the insulator 139, the insulating film 138A, the insulating film 137A, the insulating film 123A, the insulating film 135A, and the conductive film 136A are processed to form stepped insulators 139, 138, 137, 123, 135, and a conductor 136 as shown in FIG. 16. In the processing of the insulator 139, the insulating film 138A, the insulating film 137A, the insulating film 123A, the insulating film 135A, and the conductive film 136A, by alternately performing etching of the insulator 139, the insulating film 138A, the insulating film 137A, the insulating film 123A, the insulating film 135A, and the conductive film 136A and slimming of the mask, the stepped insulators 139, 138, 137, 123, 135, and the conductor 136 can be formed.

[0265] Next, an insulator 150 is formed (see FIG. 16). The insulator 150 can be formed using a CVD method. The insulator 150 is preferably planarized using a CMP method or a reflow method.

[0266] Next, in order to separate the memory strings 120 arranged in the Y direction, the insulator 150, the insulator 139, the insulator 138, the insulator 137, the insulator 123, the insulator 135, and the conductor 136 are processed to form a slit. Note that the slit is not shown because it is formed in the Y direction of the cross section shown in FIG. 16. Further, the slit is formed so as to extend in the X direction. Further, the slit is preferably formed between each of the memory strings 120 arranged in the Y direction.

[0267] Next, the insulator 137 and the insulator 135 are removed (see FIG. 17). For the removal of the insulator 137 and the insulator 135, wet etching or dry etching can be used. The etchant used for wet etching or the gas used for dry etching is introduced from the slit, and the insulator 137 and the insulator 135 are removed by isotropic etching. As the etching gas for the insulator 137 and the insulator 135, at least one of CH3F, CH2F2, and CHF3 can be used. Also, a mixed gas containing at least one of the above gases can be used. Examples of the mixed gas include a mixed gas containing at least one of the above gases and one gas selected from He, Ne, Ar, Kr, Xe, and Rn. Further, phosphoric acid can be used as the etchant for the insulator 137 and the insulator 135. When wet etching is used for the removal of the insulator 137 and the insulator 135, the etching rate of the insulator 137 and the insulator 135 can be controlled by adjusting the temperature of the etchant. It is preferable to heat the phosphoric acid to etch the insulator 137 and the insulator 135.

[0268] By removing the insulator 137 and the insulator 135, a layer with a cavity is formed between the upper and lower insulators 123.

[0269] Conductors 182 and 183 are formed in the regions where insulators 137 and 135 are removed (see Fig. 18). These conductors can be formed using the CVD method or the ALD method. In particular, using the ALD method is preferable because a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio. Also, as the conductor, a material that can be used for conductor 122 or conductive film 136A can be used. The conductor may contain the same material as conductor 122 or conductive film 136A, or a different material. Also, in order to suppress oxidation of the conductor, it is preferable to form insulator 181 before forming the conductor. Insulator 181 preferably has barrier properties against oxygen. Insulator 181 can be formed using the ALD method. By using the ALD method, insulator 181 can be formed on the upper surface of insulator 123, the lower surface of insulator 123, the side surfaces of insulator 124, and the side surfaces of insulator 150.

[0270] Next, anisotropic etching is performed on the conductor located within the slit formed in the previous step to obtain conductors 182 and 183 (see Fig. 18). Here, the conductor formed in the region where insulator 135 was provided is defined as conductor 182, and the conductor formed in the region where insulator 137 was provided is defined as conductor 183. Conductors 182 and 183 are covered by insulator 181 all around except for the surface located on the slit side, that is, the surface orthogonal to the Y direction.

[0271] Next, an insulator is formed so as to fill the portion removed by the above processing, that is, the slit portion. The insulator can be formed using the CVD method or the ALD method. In particular, using the ALD method is preferable because a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio. Alternatively, the insulator may be formed by combining the ALD method and the CVD method. The insulator is preferably planarized using the CMP method or the reflow method.

[0272] Next, insulators 150, 139, 129, 131, 126, 138, and 181 are processed using a lithography method to form a second opening so as to expose conductors 182, 136, 130, 183, semiconductor 125, and semiconductor 127. The second opening is formed for each of the stepped conductors 182 and 136 (see FIG. 19).

[0273] Next, conductors 161 electrically connected to conductor 182, conductor 162 electrically connected to conductor 136, conductor 164 electrically connected to conductor 183, conductor 165 electrically connected to semiconductor 125, and conductor 166 electrically connected to semiconductor 127 are formed so as to be embedded in the second opening (see FIG. 19). Conductors 161, 162, 164, 165, and 166 can be formed using a CVD method or an ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio, which is preferable. Alternatively, the above conductors may be formed by combining the ALD method and the CVD method. Further, conductors 161, 162, 164, 165, and 166 may have a laminated structure composed of a plurality of layers. Conductors 161, 162, 164, 165, and 166 can be formed by forming a conductive film on insulator 150 and inside the second opening and removing the unnecessary conductive film using CMP or the like.

[0274] Next, conductors 171 electrically connected to conductor 161, conductor 172 electrically connected to conductor 162, conductor 174 electrically connected to conductor 164, conductor 175 electrically connected to conductor 165, and conductor 176 electrically connected to conductor 166 are formed (see FIG. 19). Conductors 171, 172, 174, 175, and 176 can be formed by forming a conductive film on insulator 150 and processing it using a lithography method. The processing can use a dry etching method or a wet etching method. Processing by the dry etching method is suitable for microfabrication.

[0275] The conductor 171, the conductor 161, and the conductor 182 function as the conductor SG or the conductor WWL. The conductor 172, the conductor 162, and the conductor 136 function as the conductor RWL. The conductor 174, the conductor 164, and the conductor 183 function as the conductor SEL. The conductor 175 and the conductor 165 function as the conductor WBL. The conductor 176 and the conductor 166 function as the conductor RBL.

[0276] Next, an insulator 156 is formed to cover the insulator 150, the insulator formed to embed the slit, the conductor 171, the conductor 172, the conductor 174, the conductor 175, and the conductor 176 (see FIG. 19). The insulator 156 can be formed using a CVD method, an ALD method, a sputtering method, or the like.

[0277] Next, the insulator 156, the insulator 150, and the insulator 139 are processed using a lithography method to form a third opening so as to expose the conductor 130 (see FIG. 19).

[0278] Next, a conductor 163 electrically connected to the conductor 130 is formed so as to be embedded in the third opening (see FIG. 19). The conductor 163 can be formed using a CVD method or an ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio, which is preferable. Alternatively, the conductor may be formed by combining the ALD method and the CVD method. Further, the conductor 163 may have a laminated structure composed of a plurality of layers. The conductor 163 can be formed by forming a conductive film on the insulator 156 and inside the third opening and removing the unnecessary conductive film using CMP or the like.

[0279] Next, a conductor 173 that is electrically connected to the conductor 163 is formed (see FIG. 19). The conductor 173 can be formed by forming a conductive film on the insulator 156 and processing it using a lithography method. The processing can use a dry etching method or a wet etching method. Processing by the dry etching method is suitable for microfabrication.

[0280] The conductor 173, the conductor 163, and the conductor 130 function as a conductor BG. Through the above steps, a transistor STr1 having a semiconductor 127 that functions as a channel formation region and a conductor 182 that functions as a gate, a semiconductor 125 that functions as a channel formation region, and the semiconductor 127, and a transistor STr2 having a conductor 183 that functions as a gate, a transistor WTr having a semiconductor 125 that functions as a channel formation region and a conductor 182 that functions as a gate, and a transistor RTr having a semiconductor 127 that functions as a channel formation region, a conductor 136 that functions as a gate, a conductor 130 that functions as a back gate, and a conductor 128 between the semiconductor 127 and the conductor 136 can be fabricated. Also, a memory device having the transistors STr1, STr2, WTr, and RTr can be fabricated.

[0281] <Configuration Example of Film Deposition Apparatus> Here, as an example of an apparatus capable of film deposition using the ALD method, the configuration of a film deposition apparatus 4000 will be described with reference to FIGS. 20A and 20B. FIG. 20A is a schematic diagram of a multi-chamber type film deposition apparatus 4000, and FIG. 20B is a cross-sectional view of an ALD apparatus that can be used in the film deposition apparatus 4000.

[0282] The film forming apparatus 4000 includes a loading / unloading chamber 4002, a loading / unloading chamber 4004, a transfer chamber 4006, a film forming chamber 4008, a film forming chamber 4009, a film forming chamber 4010, and a transfer arm 4014. Here, the loading / unloading chamber 4002, the loading / unloading chamber 4004, and the film forming chambers 4008 to 4010 are each independently connected to the transfer chamber 4006. Thereby, continuous film formation can be performed without exposing the film forming chambers 4008 to 4010 to the atmosphere, and it is possible to prevent impurities from being mixed into the film. In addition, contamination at the interface between the substrate and the film and at the interface of each film is reduced, and a clean interface can be obtained.

[0283] Note that the loading / unloading chamber 4002, the loading / unloading chamber 4004, the transfer chamber 4006, and the film forming chambers 4008 to 4010 are preferably filled with an inert gas (such as nitrogen gas) with a controlled dew point to prevent moisture adhesion and the like, and it is desirable to maintain a reduced pressure.

[0284] In addition, an ALD apparatus can be used in the film forming chambers 4008 to 4010. Also, a configuration may be adopted in which a film forming apparatus other than the ALD apparatus is used in any one of the film forming chambers 4008 to 4010. Examples of the film forming apparatus that can be used in the film forming chambers 4008 to 4010 include a sputtering apparatus, a plasma CVD (PECVD: Plasma Enhanced CVD) apparatus, a thermal CVD (TCVD: Thermal CVD) apparatus, a photo CVD apparatus, a metal CVD (MCVD: Metal CVD) apparatus, a metal organic CVD (MOCVD: Metal Organic CVD) apparatus, and the like. Further, a device having a function other than the film forming apparatus may be provided in any one or more of the film forming chambers 4008 to 4010. Examples of such a device include a heating device (typically, a vacuum heating device), a plasma generating device (typically, a microwave plasma generating device), and the like.

[0285] For example, when the film formation chamber 4008 is an ALD apparatus, the film formation chamber 4009 is a PECVD apparatus, and the film formation chamber 4010 is a metal CVD apparatus, a metal oxide can be formed in the film formation chamber 4008, an insulating film that functions as a gate insulating film can be formed in the film formation chamber 4009, and a conductive film that functions as a gate electrode can be formed in the film formation chamber 4010. At this time, the metal oxide, the insulating film thereon, and the conductive film thereon can be continuously formed without exposing them to the atmosphere.

[0286] Further, although the film forming apparatus 4000 is configured to include the loading / unloading chamber 4002, the loading / unloading chamber 4004, and the film formation chambers 4008 to 4010, the present invention is not limited thereto. The film forming apparatus 4000 may be configured to have four or more film formation chambers. Further, the film forming apparatus 4000 may be a single wafer type or a batch type in which a plurality of substrates are film-formed at once.

[0287] <ALD apparatus> Next, the configuration of the ALD apparatus that can be used in the film forming apparatus 4000 will be described with reference to FIG. 20B. The ALD apparatus includes a film formation chamber (chamber 4020), a raw material supply unit 4021 (raw material supply units 4021a and 4021b), a raw material supply unit 4031, high-speed valves 4022a and 4022b that are introduction amount controllers, raw material inlets 4023 (raw material inlets 4023a and 4023b), a raw material inlet 4033, a raw material outlet 4024, and an exhaust device 4025. The raw material inlets 4023a, 4023b, and 4033 installed in the chamber 4020 are respectively connected to the raw material supply units 4021a, 4021b, and 4031 via supply pipes and valves, and the raw material outlet 4024 is connected to the exhaust device 4025 via a discharge pipe, a valve, and a pressure regulator.

[0288] Also, by connecting a plasma generator 4028 to the chamber 4020 as shown in FIG. 20B, in addition to the thermal ALD method, film formation can be performed by the plasma ALD method. The plasma generator 4028 is preferably an ICP type plasma generator using a coil 4029 connected to a high-frequency power supply. The high-frequency power supply can output power having a frequency of 10 kHz or more and 100 MHz or less, preferably 1 MHz or more and 60 MHz or less, more preferably 10 MHz or more and 60 MHz or less. For example, it can output power having frequencies of 13.56 MHz and 60 MHz. In the plasma ALD method, since film formation can be performed without reducing the film formation rate even at low temperatures, it is preferably used in a single-wafer film formation apparatus with low film formation efficiency.

[0289] There is a substrate holder 4026 inside the chamber, and the substrate 4030 is placed on the substrate holder 4026. The substrate holder 4026 may be provided with a mechanism for applying a constant potential or high frequency. Alternatively, the substrate holder 4026 may be floating or grounded. Further, a heater 4027 is provided on the outer wall of the chamber, and the temperature inside the chamber 4020, the substrate holder 4026, and the surface of the substrate 4030 can be controlled. The heater 4027 preferably can control the temperature of the surface of the substrate 4030 to 100°C or more and 500°C or less, preferably 200°C or more and 400°C or less, and the temperature of the heater 4027 itself is preferably set to 100°C or more and 500°C or less.

[0290] In the raw material supply units 4021a, 4021b, and 4031, raw material gas is formed from solid raw materials or liquid raw materials by vaporizers, heating means, etc. Or, the raw material supply units 4021a, 4021b, and 4031 may be configured to supply gaseous raw material gas.

[0291] In addition, in FIG. 20B, an example is shown in which two raw material supply units 4021 and one raw material supply unit 4031 are provided, but the present embodiment is not limited to this. One or three or more raw material supply units 4021 may be provided. Also, two or more raw material supply units 4031 may be provided. Further, the high-speed valves 4022a and 4022b can be precisely controlled by time, and are configured to control the supply of the raw material gas supplied from the raw material supply unit 4021a and the raw material gas supplied from the raw material supply unit 4021b.

[0292] In the film forming apparatus shown in FIG. 20B, after the substrate 4030 is carried onto the substrate holder 4026 and the chamber 4020 is sealed, the substrate 4030 is heated to a desired temperature (for example, 100° C. or higher and 500° C. or lower, preferably 200° C. or higher and 400° C. or lower) by the heater 4027, and the supply of the raw material gas supplied from the raw material supply unit 4021a, the exhaust by the exhaust device 4025, the supply of the raw material gas supplied from the raw material supply unit 4031, and the exhaust by the exhaust device 4025 are repeated to form a thin film on the substrate surface. Further, in the formation of the thin film, the supply of the raw material gas supplied from the raw material supply unit 4021b and the exhaust by the exhaust device 4025 may be further performed. The temperature of the heater 4027 may be appropriately determined according to the film type to be formed, the raw material gas, the desired film quality, the substrate, and the heat resistance of the film and elements provided thereon. For example, the film may be formed by setting the temperature of the heater 4027 to 200° C. or higher and 300° C. or lower, or may be formed by setting the temperature to 300° C. or higher and 500° C. or lower.

[0293] By forming the film while heating the substrate 4030 using the heater 4027, the heat treatment of the substrate 4030 required in the subsequent process can be omitted. That is, by using the chamber 4020 provided with the heater 4027 or the film forming apparatus 4000, the formation of the film on the substrate 4030 and the heat treatment of the substrate 4030 can be combined.

[0294] In the film forming apparatus shown in FIG. 20B, metal oxides can be formed by appropriately selecting the raw materials (such as volatile organic metal compounds) used in the raw material supply unit 4021 and the raw material supply unit 4031.

[0295] When forming an In-Ga-Zn oxide containing indium, gallium, and zinc as a metal oxide, it is preferable to use a film forming apparatus provided with at least three raw material supply units 4021 in addition to the raw material supply unit 4031. That is, it is preferable that a precursor containing indium is supplied from the first raw material supply unit 4021, a precursor containing gallium is supplied from the second raw material supply unit 4021, and a precursor containing zinc is supplied from the third raw material supply unit 4021.

[0296] When using precursors containing gallium and zinc for the formation of the metal oxide, at least two raw material supply units 4021 may be provided. As the precursor containing indium, the precursor containing gallium, and the precursor containing zinc, the aforementioned precursors can be used respectively.

[0297] In addition, a reactant is supplied from the raw material supply unit 4031. As the reactant, an oxidizing agent containing at least one of ozone, oxygen, and water can be used.

[0298] In addition, by appropriately selecting the raw materials (such as volatile organic metal compounds) used in the raw material supply units 4021a, 4021b, and 4031, an insulating layer composed of an oxide (including composite oxides) containing one or more elements selected from hafnium, aluminum, tantalum, zirconium, etc. can be formed. Specifically, an insulating layer composed of hafnium oxide, an insulating layer composed of aluminum oxide, an insulating layer composed of hafnium silicate, or an insulating layer composed of aluminum silicate, etc. can be formed. Also, by appropriately selecting the raw materials (such as volatile organic metal compounds) used in the raw material supply units 4021a, 4021b, and 4031, thin films such as a metal layer such as a tungsten layer or a titanium layer, and a nitride layer such as a titanium nitride layer can also be formed.

[0299] For example, when forming a hafnium oxide layer by an ALD apparatus, a first source gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (such as hafnium alkoxide or hafnium amide such as tetrakis(dimethylamide)hafnium (TDMAHf)) and a second source gas of ozone (O3) and oxygen (O2) as an oxidizing agent are used. In this case, the first source gas supplied from the source supply unit 4021a is TDMAHf, and the second source gas supplied from the source supply unit 4031 is ozone and oxygen. The chemical formula of tetrakis(dimethylamide)hafnium is Hf[N(CH3)2]4. Further, as other material liquids, there are tetrakis(ethylmethylamide)hafnium and the like. Also, water can be used as the second source gas.

[0300] When forming an aluminum oxide layer by an ALD apparatus, a first source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as TMA: trimethylaluminum) and a second source gas containing ozone (O3) and oxygen (O2) as an oxidizing agent are used. In this case, the first source gas supplied from the source supply unit 4021a is TMA, and the second source gas supplied from the source supply unit 4031 is ozone and oxygen. The chemical formula of trimethylaluminum is Al(CH3)3. Further, as other material liquids, there are tris(dimethylamide)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), and the like. Also, water can be used as the second source gas.

[0301] FIG. 21 illustrates different configurations of an ALD apparatus that can be used in the film forming apparatus 4000. Note that detailed descriptions of the configurations and functions similar to those of the ALD apparatus shown in FIG. 20B may be omitted.

[0302] FIG. 21A is a schematic diagram showing one aspect of a plasma ALD apparatus. The plasma ALD apparatus 4100 has a reaction chamber 4120 and a plasma generation chamber 4111 provided above the reaction chamber 4120. The reaction chamber 4120 can be called a chamber. Alternatively, the reaction chamber 4120 and the plasma generation chamber 4111 together can be called a chamber. The reaction chamber 4120 has a raw material inlet 4123 and a raw material outlet 4124, and the plasma generation chamber 4111 has a raw material inlet 4133. Further, a high-frequency wave such as RF or a microwave can be applied by the plasma generation device 4128 to the gas introduced into the plasma generation chamber 4111 to generate plasma 4131 in the plasma generation chamber 4111. When generating plasma 4131 using a microwave, typically a microwave with a frequency of 2.45 GHz is used. Plasma generated using a microwave is sometimes called ECR (Electron Cyclotron Resonance) plasma. Further, the reaction chamber 4120 has a substrate holder 4126, and a substrate 4130 is disposed thereon. The raw material gas introduced from the raw material inlet 4123 is decomposed by the heat from a heater provided in the reaction chamber 4120 and deposited on the substrate 4130. Further, the raw material gas introduced from the raw material inlet 4133 becomes a plasma state by the plasma generation device 4128. The raw material gas in a plasma state recombines with electrons and other molecules before reaching the surface of the substrate 4130 and becomes a radical state and reaches the substrate 4130. Thus, an ALD apparatus that forms a film using radicals is sometimes called a radical ALD (Radical-Enhanced ALD) apparatus. Further, in the plasma ALD apparatus 4100, a configuration in which the plasma generation chamber 4111 is provided above the reaction chamber 4120 is shown, but the present embodiment is not limited to this. The plasma generation chamber 4111 may be provided adjacent to the side surface of the reaction chamber 4120.

[0303] FIG. 21B is a schematic diagram showing one aspect of a plasma ALD apparatus. The plasma ALD apparatus 4200 has a chamber 4220. The chamber 4220 has an electrode 4213, a raw material discharge port 4224, and a substrate holder 4226, on which a substrate 4230 is disposed. The electrode 4213 has a raw material introduction port 4223 and a shower head 4214 for supplying the introduced raw material gas into the chamber 4220. A power source 4215 capable of applying a high frequency through a capacitor 4217 is connected to the electrode 4213. The substrate holder 4226 may be provided with a mechanism for applying a constant potential or a high frequency. Alternatively, the substrate holder 4226 may be floating or grounded. The electrode 4213 and the substrate holder 4226 function as an upper electrode and a lower electrode for generating plasma 4231, respectively. The raw material gas introduced from the raw material introduction port 4223 is decomposed by heat from a heater provided in the chamber 4220 and deposited on the substrate 4230. Alternatively, the raw material gas introduced from the raw material introduction port 4223 becomes a plasma state between the electrode 4213 and the substrate holder 4226. The raw material gas in the plasma state is incident on the substrate 4230 due to the potential difference (also referred to as an ion sheath) generated between the plasma 4231 and the substrate 4230.

[0304] FIG. 21C is a schematic diagram showing an embodiment of a plasma ALD apparatus different from that of FIG. 21B. The plasma ALD apparatus 4300 has a chamber 4320. The chamber 4320 has an electrode 4313, a raw material discharge port 4324, and a substrate holder 4326, on which a substrate 4330 is disposed. The electrode 4313 has a raw material introduction port 4323 and a shower head 4314 for supplying the introduced raw material gas into the chamber 4320. Further, a power source 4315 capable of applying a high frequency via a capacitor 4317 is connected to the electrode 4313. The substrate holder 4326 may be provided with a mechanism for applying a constant potential or a high frequency. Alternatively, the substrate holder 4326 may be floating or grounded. The electrode 4313 and the substrate holder 4326 function as an upper electrode and a lower electrode for generating plasma 4331, respectively. The plasma ALD apparatus 4300 is different from the plasma ALD apparatus 4200 in that it has a mesh 4319 to which a power source 4321 capable of applying a high frequency via a capacitor 4322 is connected between the electrode 4313 and the substrate holder 4326. By providing the mesh 4319, the plasma 4231 can be separated from the substrate 4130. The raw material gas introduced from the raw material introduction port 4323 is decomposed by the heat from a heater provided in the chamber 4320 and deposited on the substrate 4330. Alternatively, the raw material gas introduced from the raw material introduction port 4323 becomes a plasma state between the electrode 4313 and the substrate holder 4326. The raw material gas in the plasma state has its charge removed by the mesh 4319 and reaches the substrate 4130 in an electrically neutral state such as a radical. Therefore, film formation with suppressed ion incidence and plasma damage can be performed.

[0305] By forming the semiconductor 125 or the semiconductor 127 using the ALD method, a metal oxide having a CAAC structure in which the c-axis is oriented substantially parallel to the normal direction of the film formation surface may be formed.

[0306] <Microwave processing apparatus> Hereinafter, a microwave processing apparatus that can be used in the method for manufacturing the semiconductor device will be described.

[0307] First, the configuration of a manufacturing apparatus with less impurity contamination during the manufacture of semiconductor devices and the like will be described with reference to FIGS. 22, 23, and 24.

[0308] FIG. 22 schematically shows a top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmospheric-side substrate supply chamber 2701 having a cassette port 2761 for accommodating a substrate and an alignment port 2762 for aligning the substrate, an atmospheric-side substrate transfer chamber 2702 for transferring the substrate from the atmospheric-side substrate supply chamber 2701, a load lock chamber 2703a for loading the substrate and switching the pressure in the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703b for unloading the substrate and switching the pressure in the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring the substrate in a vacuum, and chambers 2706a, 2706b, 2706c, and 2706d.

[0309] The atmospheric-side substrate transfer chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b. The load lock chamber 2703a and the unload lock chamber 2703b are connected to the transfer chamber 2704. The transfer chamber 2704 is connected to the chambers 2706a, 2706b, 2706c, and 2706d.

[0310] A gate valve GV is provided at the connection portion of each chamber, and each chamber can be independently maintained in a vacuum state except for the atmospheric-side substrate supply chamber 2701 and the atmospheric-side substrate transfer chamber 2702. A transfer robot 2763a is provided in the atmospheric-side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. The substrate can be transferred within the manufacturing apparatus 2700 by the transfer robot 2763a and the transfer robot 2763b.

[0311] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Pa or less, preferably 3×10-5 Below Pa, more preferably 1×10 -5 Below Pa. Also, the partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Below Pa, preferably 1×10 -5 Below Pa, more preferably 3×10 -6 Below Pa. Also, the partial pressure of gas molecules (atoms) with an m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Below Pa, preferably 1×10 -5 Below Pa, more preferably 3×10 -6 Below Pa. Also, the partial pressure of gas molecules (atoms) with an m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Below Pa, preferably 1×10 -5 Below Pa, more preferably 3×10 -6 Below Pa.

[0312] Note that the total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using a mass spectrometer. For example, the quadrupole mass spectrometer (also referred to as Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. may be used.

[0313] Also, it is desirable that the transfer chamber 2704 and each chamber have a configuration with little external or internal leakage. For example, the leak rate of the transfer chamber 2704 and each chamber is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. Also, for example, the leak rate of gas molecules (atoms) with an m / z of 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m 3 / s or less. Also, for example, the leak rate of gas molecules (atoms) with an m / z of 28 is 1×10 -5 Pa·m 3 / s or less, preferably 1×10 -6Pa·m 3 shall be below / s. Also, for example, the leak rate of gas molecules (atoms) with m / z of 44 is 3×10 -6 Pa·m 3 / s or below, preferably 1×10 -6 Pa·m 3 / s or below.

[0314] Note that the leak rate may be derived from the total pressure and partial pressure measured using the mass spectrometer described above. The leak rate depends on external leaks and internal leaks. An external leak is the inflow of gas from outside the vacuum system due to a minute hole or poor sealing. An internal leak is caused by leakage from a partition such as a valve inside the vacuum system or the released gas from internal members. In order to make the leak rate below the above values, it is necessary to take measures against both external leaks and internal leaks.

[0315] For example, the opening and closing parts of the transfer chamber 2704 and each chamber may be sealed with a metal gasket. It is preferable to use a metal coated with iron fluoride, aluminum oxide, or chromium oxide for the metal gasket. The metal gasket has higher adhesion compared to an O-ring and can reduce external leaks. Also, by using the passivation of the metal coated with iron fluoride, aluminum oxide, chromium oxide, etc., the released gas containing impurities released from the metal gasket can be suppressed, and internal leaks can be reduced.

[0316] Also, as the members constituting the manufacturing apparatus 2700, use aluminum, chromium, titanium, zirconium, nickel, or vanadium that emits less released gas containing impurities. Also, the above-mentioned metal that emits less released gas containing impurities may be used after being coated with an alloy containing iron, chromium, nickel, etc. Alloys containing iron, chromium, nickel, etc. are rigid, heat-resistant, and suitable for processing. Here, if the surface unevenness of the member is reduced by polishing or the like in order to reduce the surface area, the released gas can be reduced.

[0317] Alternatively, the members of the aforementioned manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0318] The members of the manufacturing apparatus 2700 are preferably composed of only metal as much as possible. For example, when installing a viewing window composed of quartz or the like, the surface may be thinly coated with iron fluoride, aluminum oxide, chromium oxide, or the like in order to suppress the released gas.

[0319] The adsorbed substances present in the transfer chamber 2704 and each chamber do not affect the pressure in the transfer chamber 2704 and each chamber because they are adsorbed on the inner wall or the like, but they cause gas release when the transfer chamber 2704 and each chamber are evacuated. Therefore, although there is no correlation between the leak rate and the evacuation speed, it is important to use a pump with a high evacuation capacity to desorb the adsorbed substances present in the transfer chamber 2704 and each chamber as much as possible and evacuate them in advance. In addition, in order to promote the desorption of the adsorbed substances, the transfer chamber 2704 and each chamber may be baked. By baking, the desorption rate of the adsorbed substances can be increased by about 10 times. Baking may be performed at 100°C or higher and 450°C or lower. At this time, when removing the adsorbed substances while introducing an inert gas into the transfer chamber 2704 and each chamber, the desorption rate of water or the like that is difficult to desorb by evacuation alone can be further increased. In addition, by heating the introduced inert gas to about the same temperature as the baking temperature, the desorption rate of the adsorbed substances can be further increased. Here, it is preferable to use a noble gas as the inert gas.

[0320] Alternatively, it is preferable to increase the pressure in the transfer chamber 2704 and each chamber by introducing an inert gas such as heated rare gas or oxygen, and then evacuate the transfer chamber 2704 and each chamber again after a certain period of time. By introducing the heated gas, the adsorbed substances in the transfer chamber 2704 and each chamber can be desorbed, and the impurities present in the transfer chamber 2704 and each chamber can be reduced. This treatment is effectively repeated in the range of 2 to 30 times, preferably 5 to 15 times. Specifically, by introducing an inert gas or oxygen with a temperature of 40°C or higher and 400°C or lower, preferably 50°C or higher and 200°C or lower, the pressure in the transfer chamber 2704 and each chamber is set to 0.1 Pa or higher and 10 kPa or lower, preferably 1 Pa or higher and 1 kPa or lower, more preferably 5 Pa or higher and 100 Pa or lower, and the period for maintaining the pressure is set to 1 minute or longer and 300 minutes or shorter, preferably 5 minutes or longer and 120 minutes or shorter. Then, the transfer chamber 2704 and each chamber are evacuated for a period of 5 minutes or longer and 300 minutes or shorter, preferably 10 minutes or longer and 120 minutes or shorter.

[0321] Next, the chambers 2706b and 2706c will be described using the cross-sectional schematic diagram shown in FIG. 23.

[0322] The chambers 2706b and 2706c are chambers capable of performing microwave treatment on the object to be processed, for example. Note that the only difference between chamber 2706b and chamber 2706c is the atmosphere during the microwave treatment. Since the other configurations are common, they will be described together below.

[0323] Chambers 2706b and 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Also, outside Chambers 2706b and 2706c, etc., there are provided a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818.

[0324] The high-frequency generator 2803 is connected to the mode converter 2805 via the waveguide 2804. The mode converter 2805 is connected to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is arranged in contact with the dielectric plate 2809. Also, the gas supply source 2801 is connected to the mode converter 2805 via the valve 2802. Then, gas is sent to Chambers 2706b and 2706c by the mode converter 2805, the waveguide 2807, and the gas pipe 2806 passing through the dielectric plate 2809. Also, the vacuum pump 2817 has a function of exhausting gas, etc., from Chambers 2706b and 2706c via the valve 2818 and the exhaust port 2819. Also, the high-frequency power supply 2816 is connected to the substrate holder 2812 via the matching box 2815.

[0325] The substrate holder 2812 has a function of holding the substrate 2811. For example, it has a function of electrostatically chucking or mechanically chucking the substrate 2811. Also, it has a function as an electrode to which power is supplied from the high-frequency power supply 2816. Also, it has a heating mechanism 2813 inside and has a function of heating the substrate 2811.

[0326] As the vacuum pump 2817, for example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump can be used. Further, in addition to the vacuum pump 2817, a cryotrap may be used. Using a cryopump and a cryotrap is particularly preferable because water can be efficiently exhausted.

[0327] As the heating mechanism 2813, for example, a heating mechanism that heats using a resistance heating element or the like may be used. Alternatively, it may be a heating mechanism that heats by heat conduction or heat radiation from a medium such as a heated gas. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs a heat treatment using a high-temperature gas. As the gas, an inert gas is used.

[0328] Further, the gas supply source 2801 may be connected to the purification machine via a mass flow controller. As the gas, a gas having a dew point of -80°C or lower, preferably -100°C or lower is preferably used. For example, oxygen gas, nitrogen gas, and noble gas (such as argon gas) may be used.

[0329] As the dielectric plate 2809, for example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria) may be used. Further, another protective layer may be formed on the surface of the dielectric plate 2809. As the protective layer, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide may be used. Since the dielectric plate 2809 is to be exposed to a particularly high-density region of the high-density plasma 2810 described later, damage can be mitigated by providing a protective layer. As a result, an increase in particles during processing can be suppressed.

[0330] The high-frequency generator 2803 has a function of generating microwaves, for example, in the range of 0.3 GHz or higher and 6.0 GHz or lower. For example, microwaves in the range of 0.7 GHz or higher and 1.1 GHz or lower, or 2.2 GHz or higher and 2.8 GHz or lower, or 5.0 GHz or higher and 6.0 GHz or lower can be generated. The microwaves generated by the high-frequency generator 2803 are transmitted to the mode converter 2805 through the waveguide 2804. In the mode converter 2805, the microwaves transmitted in the TE mode are converted to the TEM mode. Then, the microwaves are transmitted to the slot antenna plate 2808 through the waveguide 2807. The slot antenna plate 2808 is provided with a plurality of slot holes, and the microwaves pass through the slot holes and the dielectric plate 2809. Then, an electric field is generated below the dielectric plate 2809, and high-density plasma 2810 can be generated. The high-density plasma 2810 contains ions and radicals corresponding to the gas species supplied from the gas supply source 2801. For example, oxygen radicals exist.

[0331] At this time, the substrate 2811 can be modified, such as the film on the substrate 2811, by the ions and radicals generated by the high-density plasma 2810. It is sometimes preferable to apply a bias to the substrate 2811 side using the high-frequency power supply 2816. For the high-frequency power supply 2816, for example, an RF (Radio Frequency) power supply with a frequency such as 13.56 MHz or 27.12 MHz can be used. By applying a bias to the substrate side, the ions in the high-density plasma 2810 can efficiently reach the depth of the openings such as the film on the substrate 2811.

[0332] For example, in the chamber 2706b or the chamber 2706c, oxygen can be introduced from the gas supply source 2801 to perform oxygen radical treatment using the high-density plasma 2810.

[0333] Next, the chambers 2706a and 2706d will be described with reference to the cross-sectional schematic diagram shown in FIG. 24.

[0334] Chambers 2706a and 2706d are chambers that can irradiate an object to be processed with electromagnetic waves, for example. The only difference between chamber 2706a and chamber 2706d is the type of electromagnetic wave. Since there are many common parts in other configurations, they will be described together below.

[0335] Chambers 2706a and 2706d have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. Further, outside chambers 2706a and 2706d, etc., a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0336] The gas supply source 2821 is connected to the gas inlet 2823 via the valve 2822. The vacuum pump 2828 is connected to the exhaust port 2830 via the valve 2829. The lamp 2820 is disposed facing the substrate holder 2825. The substrate holder 2825 has a function of holding the substrate 2824. Further, the substrate holder 2825 has a heating mechanism 2826 inside and has a function of heating the substrate 2824.

[0337] As the lamp 2820, for example, a light source having a function of emitting electromagnetic waves such as visible light or ultraviolet light may be used. For example, a light source having a function of emitting electromagnetic waves having a peak at a wavelength of 10 nm or more and 2500 nm or less, 500 nm or more and 2000 nm or less, or 40 nm or more and 340 nm or less may be used.

[0338] For example, as the lamp 2820, a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp may be used.

[0339] For example, some or all of the electromagnetic waves radiated from the lamp 2820 can be absorbed by the substrate 2824, thereby modifying a film or the like on the substrate 2824. For example, generation or reduction of defects, or removal of impurities can be achieved. Note that when performing the process while heating the substrate 2824, generation or reduction of defects, or removal of impurities can be achieved efficiently.

[0340] Alternatively, for example, the electromagnetic waves radiated from the lamp 2820 may heat the substrate holder 2825 to heat the substrate 2824. In that case, the heating mechanism 2826 does not have to be provided inside the substrate holder 2825.

[0341] For the vacuum pump 2828, refer to the description of the vacuum pump 2817. Also, for the heating mechanism 2826, refer to the description of the heating mechanism 2813. Also, for the gas supply source 2821, refer to the description of the gas supply source 2801.

[0342] The microwave processing apparatus that can be used in the present embodiment is not limited to the above. The microwave processing apparatus 2900 shown in FIG. 25 can be used. The microwave processing apparatus 2900 includes a quartz tube 2901, an exhaust port 2819, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a gas tube 2806, a vacuum pump 2817, and a valve 2818. Further, the microwave processing apparatus 2900 includes a substrate holder 2902 that holds a plurality of substrates 2811 (2811_1 to 2811_n, where n is an integer of 2 or more) inside the quartz tube 2901. Further, the microwave processing apparatus 2900 may include heating means 2903 outside the quartz tube 2901.

[0343] The microwave generated by the high-frequency generator 2803 is irradiated onto the substrate provided in the quartz tube 2901 via the waveguide 2804. The vacuum pump 2817 is connected to the exhaust port 2819 via the valve 2818, and can adjust the pressure inside the quartz tube 2901. Further, the gas supply source 2801 is connected to the gas pipe 2806 via the valve 2802, and can introduce a desired gas into the quartz tube 2901. Further, the substrate 2811 in the quartz tube 2901 can be heated to a desired temperature by the heating means 2903. Alternatively, the gas supplied from the gas supply source 2801 may be heated by the heating means 2903. The microwave processing apparatus 2900 can simultaneously perform a heat treatment and a microwave treatment on the substrate 2811. Further, after heating the substrate 2811, a microwave treatment can be performed. Further, after performing a microwave treatment on the substrate 2811, a heat treatment can be performed.

[0344] The substrates 2811_1 to 2811_n may all be processing substrates for forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates. For example, the substrates 2811_1 and 2811_n may be dummy substrates, and the substrates 2811_2 to 2811_n-1 may be processing substrates. Further, the substrates 2811_1, 2811_2, 2811_n-1, and 2811_n may be dummy substrates, and the substrates 2811_3 to 2811_n-2 may be processing substrates. Using dummy substrates is preferable because during microwave processing or heat treatment, a plurality of processing substrates are uniformly processed, and variations between the processing substrates can be reduced. For example, it is preferable to arrange a dummy substrate on the processing substrate closest to the high-frequency generator 2803 and the waveguide 2804 because this can prevent the processing substrate from being directly exposed to microwaves.

[0345] By using the above manufacturing apparatus, it is possible to suppress the mixing of impurities into the object to be processed and to modify the film.

[0346] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0347] (Embodiment 2) In this embodiment, the circuit configuration and operation of the memory string 120, which is a memory device, will be described. FIG. 26 shows an example of the circuit configuration of the memory string 120. Also, FIG. 27 shows an equivalent circuit diagram of the memory element MC.

[0348] Also, in the drawings and the like, in order to make the potential of wiring, electrodes, or conductors, etc. easier to understand, an "H" indicating the H potential or an "L" indicating the L potential may be added adjacent to the wiring, electrodes, or conductors, etc. Also, for wiring, electrodes, or conductors, etc. where a potential change has occurred, an "H" or "L" may be added in surrounded characters. Also, when a transistor is in the off state, an "×" symbol may be added over the transistor.

[0349] <Example of Circuit Configuration of Memory String> FIG. 26 shows an example of the circuit configuration of the memory string 120 including five memory elements MC. The memory element MC has a transistor WTr and a transistor RTr. In FIG. 26, the transistor WTr included in the memory element MC[1] is shown as the transistor WTr[1], and the transistor RTr included in the memory element MC[1] is shown as the transistor RTr[1]. Therefore, the memory string 120 shown in FIG. 26 has transistors WTr[1] to WTr[5] and transistors RTr[1] to RTr[5]. Also, the memory string 120 shown in FIG. 26 has transistors STr1, STr2, and STr3. The memory string 120 is a NAND-type memory device.

[0350] In an equivalent circuit diagram or the like, in order to indicate that a transistor is an OS transistor, "OS" may be appended to the circuit symbol of the transistor. Similarly, in order to indicate that a transistor is a Si transistor (a transistor using silicon for the semiconductor layer in which a channel is formed), "Si" may be appended to the circuit symbol of the transistor. In FIG. 26, it shows that the transistor WTr and the transistor RTr are OS transistors.

[0351] A NAND type memory device including an OS memory is also referred to as an "OS NAND type" or an "OS NAND type memory device". Further, an OS NAND type memory device having a configuration in which a plurality of OS memories are stacked in the Z direction is also referred to as a "3D OS NAND type" or a "3D OS NAND type memory device".

[0352] The transistor WTr is a normally-off type transistor. The transistor RTr is a normally-on type transistor. Also, as described in the above embodiment, the transistor RTr includes a conductor 128 between the gate and the semiconductor layer. The conductor 128 can function as a floating gate of the transistor RTr. For example, the conductor 128 included in the transistor RTr[1] is referred to as the conductor 128[1].

[0353] Also, a contact point where the conductor 128 and one of the source or drain of the transistor WTr are electrically connected is defined as the node ND. For example, a contact point where the conductor 128[1] and one of the source or drain of the transistor WTr[1] are electrically connected is referred to as the node ND[1].

[0354] One of the source or drain of transistor RTr[1] is electrically connected to one of the source or drain of transistor STr1, and the other is electrically connected to one of the source or drain of transistor RTr[2]. The gate of transistor RTr[1] is electrically connected to conductor RWL[1]. The back gate of transistor RTr[1] is electrically connected to conductor BG. One of the source or drain of transistor WTr[1] is electrically connected to conductor 128[1], and the other is electrically connected to conductor 128[2]. The gate of transistor WTr[1] is electrically connected to conductor WWL[1]. Also, the other of the source or drain of transistor STr1 is electrically connected to conductor 122, and the gate is electrically connected to conductor SG.

[0355] Here, as shown in FIG. 27, transistor RTr can be represented by replacing it with capacitor Cs and transistor Tr. The gate of transistor Tr is electrically connected to conductor RWL via capacitor Cs.

[0356] Also, one of the source or drain of transistor RTr[5] is electrically connected to the other of the source or drain of transistor RTr[4], and the other is electrically connected to one of the source or drain of transistor STr2. The gate of transistor RTr[5] is electrically connected to conductor RWL[5]. The back gate of transistor RTr[5] is electrically connected to conductor BG. One of the source or drain of transistor WTr[5] is electrically connected to conductor 128[5], and the other is electrically connected to one of the source or drain of transistor STr3. The gate of transistor WTr[5] is electrically connected to conductor WWL[5]. Also, the other of the source or drain of transistor STr2 is electrically connected to conductor RBL, and the gate is electrically connected to conductor RSEL. Also, the other of the source or drain of transistor STr3 is electrically connected to conductor WBL, and the gate is electrically connected to conductor WSEL.

[0357] When the memory string 120 includes n (n is an integer greater than or equal to 1) memory cells MC, in the i-th (i is an integer greater than or equal to 1 and less than or equal to n) memory cell MC[i] excluding the first and n-th memory cells MC, one of the source or drain of the transistor RTr[i] is electrically connected to the other of the source or drain of the transistor RTr[i - 1], and the other is electrically connected to one of the source or drain of the transistor RTr[i + 1]. The gate of the transistor RTr[i] is electrically connected to the conductor RWL[i]. The back gate of the transistor RTr[i] is electrically connected to the conductor BG. One of the source or drain of the transistor WTr[i] is electrically connected to the conductor 128[i], and the other is electrically connected to the conductor 128[i - 1]. The gate of the transistor WTr[i] is electrically connected to the conductor WWL[i].

[0358] The transistors STr1 and STr2 may be, for example, OS transistors or Si transistors. One of the transistors STr1 and STr2 may be an OS transistor and the other may be a Si transistor. When both the transistor WTr and the transistor RTr are formed of OS transistors, it is preferable that the transistors STr1 and STr2 are also formed of OS transistors. By using the same semiconductor material for the transistors, the productivity of the semiconductor device can be improved.

[0359] Alternatively, an OS transistor may be used for the transistor WTr and a Si transistor may be used for the transistor RTr. The equivalent circuit diagram of the memory string 120 when an OS transistor is used for the transistor WTr and a Si transistor is used for the transistor RTr is shown in FIG. 28.

[0360] When the transistor RTr is formed of a Si transistor, for example, polycrystalline silicon may be used for the semiconductor 125. When the transistor WTr is formed of an OS transistor, for example, CAAC-IGZO may be used for the semiconductor 127.

[0361] Note that, as shown in FIG. 29, depending on the purpose, application, etc., an Si transistor may be used as the transistor WTr, and an OS transistor may be used as the transistor RTr. Further, as shown in FIG. 30, depending on the purpose, application, etc., Si transistors may be used for both the transistor WTr and the transistor RTr. When Si transistors are used for both the transistor WTr and the transistor RTr, it is preferable to use Si transistors also for the transistors STr1 and STr2.

[0362] <Operation Example of Memory String> Next, an operation example of the memory string 120 shown in FIG. 26 will be described.

[0363] 〔Writing Operation〕 In the present embodiment, an operation example in the case where an H potential is written to the memory elements MC[1] and MC[3], and an L potential is written to the other memory elements MC will be described. FIG. 31 is a timing chart for explaining the writing operation. FIGS. 32A to 36B are circuit diagrams for explaining the writing operation.

[0364] As an initial state, it is assumed that L potentials are written to the memory elements MC[1] to MC[5]. Further, it is assumed that L potentials are supplied to the conductors WWL[1] to WWL[5], the conductors RWL[1] to RWL[5], the conductor WSEL, the conductor RSEL, the conductor BG, the conductor WBL, the conductor RBL, the conductor SG, and the conductor 122. Note that the conductor BG can control the threshold value of the transistor RTr. The potential supplied to the conductor BG may be appropriately adjusted so that the transistor RTr becomes a desired normally-on type transistor. Note that although the conductor WSEL and the conductor RSEL are described as being a common conductor, they may be different conductors.

[0365] [Period T1] During period T1, an H potential is supplied to the conductors WWL[1] to WWL[5], the conductor WBL, and the conductors WSEL (and RSEL) (see Fig. 32A). Then, the potentials of the nodes ND[1] to ND[5] become the H potential.

[0366] [Period T2] During period T2, an L potential is supplied to the conductor WWL[1] (see Fig. 32B). Then, the transistor WTr[1] turns off, and the charge written in the node ND[1] is retained. Here, the charge corresponding to the H potential is retained.

[0367] [Period T3] During period T3, an L potential is supplied to the conductor WBL (see Fig. 33A). Then, the potentials of the nodes ND[2] to ND[5] become the L potential. At this time, although the conductors 128[2] to 128[5] also become the L potential, since the transistor RTr is a normally-on type transistor, the transistors RTr[2] to RTr[5] do not turn off.

[0368] [Period T4] During period T4, an L potential is supplied to the conductor WWL[2] (see Fig. 33B). Then, the transistor WTr[2] turns off, and the charge written in the node ND[2] is retained. Here, the charge corresponding to the L potential is retained.

[0369] [Period T5] During period T5, an H potential is supplied to the conductor WBL (see Fig. 34A). Then, the potentials of the nodes [3] to [5] become the H potential.

[0370] [Period T6] During period T6, an L potential is supplied to the conductor WWL[3] (see Fig. 34B). Then, the transistor WTr[3] turns off, and the charge written in the node ND[3] is retained. Here, the charge corresponding to the H potential is retained.

[0371] [Period T7] During period T7, supply an L potential to the conductor WBL (see Fig. 35A). Then, the potentials of node ND[4] and node ND[5] become the L potential.

[0372] [Period T8] During period T8, supply an L potential to the conductor WWL[4] (see Fig. 35B). Then, the transistor WTr[4] turns off, and the charge written in node ND[4] is retained. Here, the charge corresponding to the L potential is retained.

[0373] [Period T9] During period T9, keep the conductor WBL at the L potential (see Fig. 36A). Thus, the potential of node ND[5] also remains at the L potential.

[0374] [Period T10] During period T10, supply an L potential to the conductor WWL[5] (see Fig. 36B). Then, the transistor WTr[5] turns off, and the charge written in node ND[5] is retained. Here, the charge corresponding to the L potential is retained. Also, supply an L potential to the conductor WSEL (and the conductor RSEL).

[0375] In this way, information can be written into the memory element MC.

[0376] When writing information into the i-th (excluding i = 1) memory element MC among a plurality of memory elements MC, the information writing operation for the memory elements MC up to the (i - 1)-th can be omitted. For example, when wanting to write information into the memory element MC[4], the information writing operations for the memory elements MC[1] to MC[3] do not have to be performed. In other words, the writing operations from period T1 to period T6 shown in this embodiment can be omitted. Thus, the time and power consumption related to the writing operation of the memory device can be reduced.

[0377] 〔Read operation〕 An example of the read operation of the memory string 120 with the above circuit configuration will be described. As an initial state, assume that the H potential is held in the memory element MC[1] and the memory element MC[3]. Also, assume that the L potential is supplied to the conductors WWL[1] to WWL[5], the conductors RWL[1] to RWL[5], the conductor WSEL, the conductor RSEL, the conductor BG, the conductor WBL, the conductor RBL, the conductor SG, and the conductor 122. FIGS. 37A and 37B are timing charts for explaining the read operation. FIGS. 38A to 39B are circuit diagrams for explaining the read operation.

[0378] <When the holding potential is the H potential> First, the read operation of the memory element MC[3] in which the H potential is held will be described.

[0379] [Period T11] In period T11, an H potential is supplied to the conductors RWL[1] to RWL[5] and the conductor RSEL (and the conductor WSEL) (see FIG. 38A). Then, the transistor STr2 (and the transistor STr3) is turned on, and the semiconductor 127 included in the transistor RTr is electrically connected to the conductor RBL. In this state, the H potential is pre-charged to the conductor RBL and the semiconductor 127, and both are set to a floating state.

[0380] Here, the Id-Vg characteristics of the transistor will be described. FIGS. 40A and 40B are diagrams for explaining the Id-Vg characteristics of the transistor. The horizontal axis in FIGS. 40A and 40B represents the gate voltage (Vg), and the vertical axis represents the drain current (Id). FIG. 40A shows the Id-Vg characteristics of a normally-off transistor, and FIG. 40B shows the Id-Vg characteristics of a normally-on transistor.

[0381] The H potential is higher than the L potential. If the L potential is set to 0V, the H potential is a positive voltage. In a normally-off type transistor, when Vg is at the L potential (0V), the channel resistance value (the resistance value between the source and the drain) is extremely large and almost no Id flows. Also, when Vg becomes the H potential, the channel resistance value decreases and Id increases (see Fig. 40A).

[0382] In a normally-on type transistor, even when Vg is at the L potential, the channel resistance value is small and more Id flows compared to a normally-off type transistor. Also, when Vg becomes the H potential, the channel resistance value becomes even smaller and Id further increases (see Fig. 40B).

[0383] Since the transistor RTr is a normally-on type transistor, precharging to the semiconductor 127 is possible even if the potential of the conductor RWL remains at the L potential. However, by supplying the H potential to the conductor RWL, the on-resistance of the transistor RTr decreases, so the time and power consumption required for precharging can be reduced.

[0384] [Period T12] During period T12, a L potential is supplied to the conductor RWL[3] (see Fig. 38B). Since the H potential is held at the node ND[3], even when the potential of the conductor RWL[3] becomes the L potential, the channel resistance value of the transistor RTr[3] remains small.

[0385] [Period T13] During period T13, an H potential is supplied to the conductor SG to turn on the transistor ST r1 (see Fig. 39A). Then, the conductor RBL and the conductor 122 are electrically connected. At this time, since an H potential is supplied to the conductors RWL[1], RWL[2], RWL[4], and RWL[5], the channel resistance values of the transistors RTr[1], RTr[2], RTr[4], and RTr[5] are small regardless of the potential of the node ND. Although an L potential is supplied to the conductor RWL[3], the channel resistance value of the transistor RTr[3] is also small because an H potential is held at the node ND[3]. Therefore, the potential of the floating conductor RBL changes rapidly from the H potential to the L potential (see Fig. 37A).

[0386] [Period T14] During period T14, an L potential is supplied to the conductor RSEL (and the conductor WSEL), the conductor RWL, and the conductor SG (see Fig. 39B).

[0387] <When the holding potential is the L potential> Next, the read operation of the memory element MC[2] holding the L potential will be described. When reading the information (potential) held in the memory element MC[2], the potential of the conductor RWL[2] is set to the L potential in period T12 (see Fig. 37B). At this time, since the L potential is held at the node ND[2], the channel resistance value of the transistor RTr[2] remains large.

[0388] Subsequently, in period T13, an H potential is supplied to the conductor SG to connect the conductor RBL and the conductor 122. At this time, since the channel resistance value of the transistor RTr[2] is large, the potential change of the conductor RBL from the H potential to the L potential becomes gentle.

[0389] In this way, in period T13, by setting the potential of the conductor RWL corresponding to the memory element MC to be read to the L potential, the information held in the memory element MC can be known.

[0390] <Modification Example> FIG. 41 shows a circuit configuration example of a memory string 120A, which is a modification of the memory string 120. The memory string 120A has a circuit configuration in which a transistor STr3 is added to the memory string 120.

[0391] In the memory string 120A shown in FIG. 41, the other of the source or drain of the transistor WTr[5] is not connected to one of the source or drain of the transistor STr2, but is electrically connected to one of the source or drain of the transistor STr3. Also, the other of the source or drain of the transistor STr3 is electrically connected to the conductor BL. Also, the gate of the transistor STr2 is electrically connected to the conductor RSEL, and the gate of the transistor STr3 is electrically connected to the conductor WSEL.

[0392] During the write operation, the transistor STr3 is turned on and the transistor STr2 is turned off. During the read operation, the transistor STr3 is turned off and the transistor STr2 is turned on. When writing or reading information via the conductor BL, the information transfer path can be switched by dedicated transistors respectively. Therefore, the operation of the memory device is stabilized and the reliability of the memory device can be improved.

[0393] Also, as in the memory string 120B shown in FIG. 42, the transistors STr2 and STr3 may be shared. In this case, the other of the source or drain of the transistor STr2 may be electrically connected to the conductor BL. The write operation and the read operation write and read information via the conductor BL. By providing a common conductor BL for each of the write operation and the read operation, the number of wirings can be reduced.

[0394] The memory string 120C shown in FIG. 43 has a circuit configuration in which a transistor STr4 is added to the memory string 120. One of the source or drain of the transistor STr4 is electrically connected to one of the source or drain of the transistor WTr[1], and the other is electrically connected to the conductor WBL[2]. The gate of the transistor STr4 is electrically connected to the conductor WSEL[2].

[0395] Also, in the memory string 120B, the gate of the transistor STr3 is electrically connected to the conductor WSEL[1], and the other of the source or drain of the transistor STr3 is electrically connected to the conductor WBL[1]. Note that, as shown in FIG. 41, the circuit configuration may be such that the transistors STr2 and STr3 are electrically connected to the conductor BL.

[0396] The memory string 120B can write information from both the conductors WBL[1] and WBL[2]. Therefore, the information writing speed can be increased. Also, the supply of charges corresponding to the information to be written can be more reliably performed.

[0397] Also, when writing information to the i-th memory element MC, when i is close to n, by writing information from the conductor WBL[1] side, the information writing operations of the memory elements MC from the 1st to the i-1th can be omitted. Also, when i is close to 1, by writing information from the conductor WBL[2] side, the information writing operations of the memory elements MC from the i+1th to the nth can be omitted. In the memory string 120B, the time related to the writing operation and the power consumption can be further reduced.

[0398] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0399] (Embodiment 3) In this embodiment, a configuration example of the semiconductor device 200 including the memory device 100 will be described.

[0400] FIG. 44 shows a block diagram illustrating a configuration example of a semiconductor device 200 according to one aspect of the present invention. The semiconductor device 200 shown in FIG. 44 includes a drive circuit 210 and a memory array 220. The memory array 220 includes one or more storage devices 100. FIG. 44 shows an example in which the memory array 220 includes a plurality of storage devices 100 arranged in a matrix.

[0401] The drive circuit 210 includes a PSW241 (power switch), a PSW242, and a peripheral circuit 215. The peripheral circuit 215 includes a peripheral circuit 211, a control circuit 212 (Control Circuit), and a voltage generation circuit 228. Note that the semiconductor device 200 includes elements or circuits having various functions such as the memory array 220, the PSW241, the PSW242, the peripheral circuit 211, the control circuit 212, and the voltage generation circuit 228. Therefore, the semiconductor device 200 may be referred to as a system or a subsystem.

[0402] In the semiconductor device 200, each circuit, each signal, and each voltage can be appropriately selected or discarded as necessary. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside. Signal CLK is a clock signal.

[0403] In addition, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 212.

[0404] The control circuit 212 is a logic circuit having a function of controlling the overall operation of the semiconductor device 200. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 200. Alternatively, the control circuit 212 generates a control signal for the peripheral circuit 211 so that this operation mode is executed.

[0405] The voltage generation circuit 228 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 228. For example, when a signal of H level is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 228, and the voltage generation circuit 228 generates a negative voltage.

[0406] The peripheral circuit 211 is a circuit for writing and reading data to and from the storage device 100. The peripheral circuit 211 includes a row decoder 221, a column decoder 222, a row driver 223, a column driver 224, an input circuit 225, an output circuit 226, and a sense amplifier 227.

[0407] The row decoder 221 and the column decoder 222 have a function of decoding the signal ADDR. The row decoder 221 is a circuit for designating the row to be accessed, and the column decoder 222 is a circuit for designating the column to be accessed. The row driver 223 has a function of selecting the conductor WL designated by the row decoder 221. The column driver 224 has functions such as writing data to the storage device 100, reading data from the storage device 100, and holding the read data.

[0408] The input circuit 225 has a function of holding the signal WDA. The data held by the input circuit 225 is output to the column driver 224. The output data of the input circuit 225 is the data (Din) to be written into the storage device 100. The data (Dout) read by the column driver 224 from the storage device 100 is output to the output circuit 226. The output circuit 226 has a function of holding Dout. Also, the output circuit 226 has a function of outputting Dout to the outside of the semiconductor device 200. The data output from the output circuit 226 is the signal RDA.

[0409] PSW241 has a function of controlling the supply of VDD to the peripheral circuit 215. PSW242 has a function of controlling the supply of VHM to the row driver 223. Here, the high power supply voltage of the semiconductor device 200 is VDD, and the low power supply voltage is GND (ground potential). Also, VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of PSW241 is controlled by the signal PON1, and the on / off of PSW242 is controlled by the signal PON2. In FIG. 44, in the peripheral circuit 215, the number of power supply domains to which VDD is supplied is set to 1, but it can also be made plural. In this case, a power switch may be provided for each power supply domain.

[0410] The drive circuit 210 and the memory array 220 may be provided on the same plane. Also, as shown in FIG. 45A, the drive circuit 210 and the memory array 220 may be provided in an overlapping manner. By providing the drive circuit 210 and the memory array 220 in an overlapping manner, the signal propagation distance can be shortened. Also, as shown in FIG. 45B, a plurality of memory arrays 220 may be provided in layers on the drive circuit 210.

[0411] Further, as shown in FIG. 45C, a memory array 220 may be provided in the upper layer and the lower layer of the drive circuit 210. FIG. 45C shows an example in which one layer of the memory array 220 is provided in each of the upper layer and the lower layer of the drive circuit 210. By arranging a plurality of memory arrays 220 so as to sandwich the drive circuit 210, the signal propagation distance can be further shortened. Note that the number of layers of the memory array 220 stacked on the upper layer of the drive circuit 210 and the number of layers of the memory array 220 stacked on the lower layer of the drive circuit 210 may each be one or more. It is preferable that the number of the memory arrays 220 stacked on the upper layer of the drive circuit 210 is equal to the number of the memory arrays 220 stacked on the lower layer of the drive circuit 210.

[0412] <Cross-sectional configuration example of semiconductor device 200> FIG. 46 shows a cross-sectional configuration example of the semiconductor device 200 shown in FIG. 45A. FIG. 46 shows a part of the semiconductor device 200 shown in FIG. 45A.

[0413] FIG. 46 shows transistors 301, 302, and 303 included in the drive circuit 210. Note that transistors 301 and 302 function as part of the sense amplifier 227. Also, transistor 303 functions as a column selection switch. Specifically, the conductor BL included in the memory array 220 is electrically connected to one of the source and drain of transistor 301, the gate of transistor 301 is electrically connected to one of the source and drain of transistor 302, and the gate of transistor 302 is electrically connected to the other of the source and drain of transistor 301. Also, one of the source and drain of transistor 301 and the other of the source and drain of transistor 302 are electrically connected to one of the source and drain of transistor 303 that functions as a column selection switch. Thereby, the layout area of the semiconductor device 200 can be reduced. Note that FIG. 46 shows an example in which seven memory cells MC are provided per one memory string. However, the number of memory cells MC provided in one memory string is not limited to this. For example, the number of memory cells MC provided in one memory string may be 32, 64, 128, or 200 or more.

[0414] The conductor BL of the memory array 220 is electrically connected to the sense amplifier 227 and the transistor 303 that functions as a column selection switch via a conductor 752 formed so as to be embedded in conductors 715, 714, 705, insulators 726, 722, etc. Note that the circuits and transistors included in the drive circuit 210 are an example, and are not limited to the circuit configuration and transistor structure. In addition to the above, appropriate circuits and transistors can be provided according to the configuration of the semiconductor device 200 and its driving method, such as a control circuit, a row decoder, a row driver, a source line driver, and an input / output circuit.

[0415] Transistors 301, 302, and 303 are provided on substrate 311 and each have a semiconductor region 313 (a part of substrate 311) that forms a channel and has a convex shape, a conductor 316, an insulator 315, a low-resistance region 314a and a low-resistance region 314b that function as a source region or a drain region. Note that, as shown in FIG. 46, one low-resistance region may be shared as one of the source regions or drain regions of transistors 301 and 302 and the other source region or drain region.

[0416] Transistors 301, 302, and 303 each have a semiconductor region 313 (a part of substrate 311) where a channel is formed and has a convex shape. Also, the side surface and the upper surface of semiconductor region 313 are covered with conductor 316 via insulator 315. Note that conductor 316 may use a material for adjusting the work function. Since transistors 301, 302, and 303 use the convex portions of the semiconductor substrate, they are also called FIN-type transistors. Note that an insulator that functions as a mask for forming the convex portions may be provided in contact with the upper portions of the convex portions. Here, a case where a part of the semiconductor substrate is processed to form the convex portions has been shown, but an SOI substrate may be processed to form a semiconductor film having a convex shape.

[0417] Transistors 301, 302, and 303 may each be either a p-channel type or an n-channel type, but it is preferable that transistors 301 and 302 are transistors having different polarities.

[0418] In regions where the channel of the semiconductor region 313 is formed, regions in the vicinity thereof, source regions, or drain regions, such as the low-resistance regions 314a and 314b, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice spacing may also be used. Alternatively, by using GaAs, GaAlAs, etc., the transistors 301, 302, and 303 may be HEMTs (High Electron Mobility Transistors).

[0419] The low-resistance regions 314a and 314b include, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity such as arsenic and phosphorus, or elements that impart p-type conductivity such as boron.

[0420] The insulator 315 functions as a gate insulating film for the transistors 301, 302, and 303.

[0421] As the conductor 316 that functions as a gate electrode, a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material that includes an element that imparts n-type conductivity such as arsenic and phosphorus, or an element that imparts p-type conductivity such as boron can be used.

[0422] Note that since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embedding properties, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

[0423] Further, it is preferable that an insulator 317 functioning as an etch stopper is provided above the conductor 316. Also, it is preferable that an insulator 318 functioning as a spacer is provided on the side surface of the insulator 315. By providing the insulator 317 and the insulator 318, the low resistance regions 314a and 314b and the region where the conductor 328 is electrically connected can be self-alignedly determined. Therefore, even if an alignment deviation occurs when forming an opening for exposing a part of the low resistance region 314a and the low resistance region 314b, an opening for exposing the intended region can be formed. By forming the conductor 328 in the opening thus formed, a good contact with reduced contact resistance can be obtained between the low resistance region 314a, the low resistance region 314b, and the conductor 328. The contact between the low resistance region 314a and the low resistance region 314b and the conductor 328 formed in this way may be referred to as a self-aligned contact. Further, a conductor 329 electrically connected to the conductor 316 may be provided so as to be embedded in the insulator 317 and the insulator 322.

[0424] Over the transistors 301, 302, and 303, insulators 320, 322, 324, 326, and 327 are sequentially stacked and provided.

[0425] As the insulators 320, 322, 324, 326, and 327, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0426] The insulator 322 may have a function as a planarization film that planarizes the step formed by the transistor 301 provided therebelow, etc. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0427] In addition, for the insulator 324, it is preferable to use a film having a barrier property that prevents hydrogen and impurities from diffusing into the region where the memory array 220 is provided, such as the substrate 311 or the transistor 301.

[0428] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by PEALD method or CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the memory element MC, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the memory element MC and the transistor 301 or the like. Specifically, the film that suppresses the diffusion of hydrogen is a film having a small amount of hydrogen desorption.

[0429] The amount of hydrogen desorption can be analyzed, for example, using temperature programmed desorption gas analysis method (TDS). For example, the amount of hydrogen desorption of the insulator 324 is such that in the TDS analysis, in the range where the surface temperature of the film is from 50°C to 500°C, the desorption amount converted to hydrogen atoms, when converted per unit area of the insulator 324, is 10×10 15 atoms / cm 2 Hereinafter, preferably 5×10 15 atoms / cm 2 or less is sufficient.

[0430] Note that the insulators 326 and 327 preferably have a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulators 326 and 327 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of the insulators 326 and 327 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0431] In addition, conductors 328, 329, and 330, etc. that are electrically connected to the memory array 220 are embedded in the insulators 320, 322, 324, 326, and 327. Note that the conductors 328, 329, and 330 have functions as plugs or wirings. Also, conductors having functions as plugs or wirings may be given the same reference numeral when a plurality of structures are grouped together. In this specification, etc., a wiring and a plug electrically connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0432] As materials for each plug and wiring (such as conductors 328, 329, and 330), conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used alone or in a laminated manner. It is preferable to use high melting point materials such as tungsten and molybdenum that achieve both heat resistance and conductivity, and it is more preferable to use tungsten. Alternatively, it is preferable to form them with low-resistance conductive materials such as aluminum and copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0433] A wiring layer may be provided on the insulator 327 and the conductor 330. For example, in FIG. 46, the insulators 350, 352, and 354 are sequentially laminated and provided. Also, a conductor 356 is formed in the insulators 350, 352, and 354. The conductor 356 has functions as a plug or a wiring. Note that the conductor 356 can be provided using the same material as the conductors 328, 329, and 330.

[0434] Note that, for example, as with insulator 324, it is preferable to use an insulator having a barrier property against hydrogen for insulator 350. Further, conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 301 or the like and the memory element MC can be separated by a barrier layer, and diffusion of hydrogen from the transistor 301 or the like to the memory element MC can be suppressed.

[0435] Note that, as the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 301 or the like can be suppressed while maintaining the conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.

[0436] A wiring layer may be provided on insulator 354 and conductor 356. For example, in FIG. 46, insulators 360, 362, and 364 are laminated and provided in this order. Further, a conductor 366 is formed in insulators 360, 362, and 364. Conductor 366 has a function as a plug or a wiring. Note that conductor 366 can be provided using the same material as conductors 328, 329, and 330.

[0437] Note that, for example, as with insulator 324, it is preferable to use an insulator having a barrier property against hydrogen for insulator 360. Further, conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of insulator 360 having a barrier property against hydrogen. With this configuration, the transistor 301 or the like and the memory element MC can be separated by a barrier layer, and diffusion of hydrogen from the transistor 301 or the like to the memory element MC can be suppressed.

[0438] An insulator 722 is provided on the insulator 364 and the conductor 366, and a memory array 220 is provided above the insulator 722. A barrier film made of the same material as the insulator 324 may be provided between the insulator 364 and the insulator 722.

[0439] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0440] (Embodiment 4) In this embodiment, an application example of the semiconductor device according to one aspect of the present invention to an information processing device will be described.

[0441] Generally, a computer has components such as a processor, a main memory, and a storage on a motherboard as components, and each component is electrically connected by, for example, bus wiring. For this reason, the longer the bus wiring is, the greater the parasitic resistance becomes, and thus the power consumption required for signal transmission also increases.

[0442] Specifically, as a computer, for example, it has a configuration as shown in FIG. 47A. The computer has a motherboard BD, and on the motherboard BD, an arithmetic processing unit (processor, CPU, etc.) 10, a main memory (DRAM (Dynamic Random Access Memory), etc.) 30, a storage (three-dimensional structure NAND-type storage device, 3D OS NAND-type storage device, etc.) 40, an interface 60, etc. are provided. In addition, in FIG. 47, an SRAM (Static Random Access Memory) 20 that also functions as a main memory is also shown, but it does not necessarily have to be provided on the motherboard BD.

[0443] Note that FIG. 47 shows a configuration in which the arithmetic processing unit 10 has a register 11.

[0444] In FIG. 47A, the arithmetic processing unit 10 is electrically connected to the SRAM 20, the main memory 30, the storage 40, and the interface 60. Further, the main memory 30 is electrically connected to the SRAM 20 and the storage 40.

[0445] Note that each component of the computer in FIG. 47A is electrically connected by the bus wiring BSH. That is, as the number of components of the computer increases or as the motherboard BD becomes larger, the length of the routed bus wiring BSH increases, so the power consumption required for signal transmission increases.

[0446] Incidentally, the computer in FIG. 47A may integrate each component of the computer into one chip and form a monolithic IC (Integrated Circuit). Further, at this time, the information processing apparatus described in the above embodiment can be applied as the main memory 30 and the storage 40. Thus, FIG. 47B shows the computer in FIG. 47A as a monolithic IC.

[0447] The monolithic IC in FIG. 47B has a circuit layer LGC on a semiconductor substrate having Si. Further, a storage layer STR is provided above the circuit layer LGC, and a circuit layer OSC is provided above the storage layer STR.

[0448] The circuit layer LGC includes, for example, a plurality of circuits including Si transistors formed on a semiconductor substrate SBT having Si. As a part of the plurality of circuits, for example, in FIG. 47A, the arithmetic processing unit 10, the SRAM 20, etc. can be used. Further, when the information processing apparatus is applied as the main memory 30 and the storage 40, as a part of the plurality of circuits, it can be the controller 1197 included in the information processing apparatus 50 described later.

[0449] In particular, as an example, the SRAM 20 can increase the driving frequency of the SRAM by using Si transistors.

[0450] The memory layer STR functions as a memory unit having Si transistors and / or OS transistors. As the memory layer STR, for example, a three-dimensional NAND-type memory circuit, a 3D OS NAND-type memory circuit, etc. can be used. Therefore, the memory layer STR has a memory unit 1196 in the information processing apparatus, a storage 40 in FIG. 47A, etc.

[0451] Note that by using a 3D OS NAND-type memory circuit, the power consumption of the monolithic IC in FIG. 47B can be reduced.

[0452] The circuit layer OSC has, for example, a plurality of circuits including OS transistors. As a part of the plurality of circuits, for example, it can be a circuit different from the circuits included in the circuit layer LGC such as the arithmetic processing unit 10 and the SRAM 20.

[0453] In the monolithic IC of FIG. 47B, since no bus wiring BSH for routing on the motherboard is provided, the wiring for electrically connecting the respective components becomes short. Therefore, the power consumption required for signal transmission can be reduced.

[0454] Also, the monolithic IC of FIG. 47B has an information processing apparatus 50. Therefore, the information processing apparatus 50 functions as the roles of the storage 40 and the main memory 30 in FIG. 47A. Therefore, in the monolithic IC of FIG. 47B, the memory unit 1196 of the memory layer STR can have the function of the main memory 30.

[0455] Due to the point of not providing the bus wiring BSH and the point of using the memory unit 1196 as an alternative to the main memory 30, the monolithic IC of FIG. 47B can reduce the circuit area compared to the computer of FIG. 47A.

[0456] Next, an example of the memory hierarchy of the computer in FIG. 47A and the monolithic IC in FIG. 47B is shown in FIGS. 48A and 48B, respectively.

[0457] Generally, for the memory hierarchy, the memory device located in the upper layer is required to have a faster operating speed, and the memory device located in the lower layer is required to have a larger memory capacity and a higher recording density. In FIG. 48A, as an example, from the top layer in order, there are a register included in the CPU (arithmetic processing unit 10), SRAM, DRAM included in the main memory 30, and a three-dimensional NAND-type memory circuit included in the storage 40.

[0458] The register included in the arithmetic processing unit 10 and the SRAM are used for temporarily storing calculation results, etc., so the access frequency from the arithmetic processing unit 10 is high. Therefore, a faster operating speed is required than the memory capacity. Also, the register has a function of holding setting information of the arithmetic processing unit, etc.

[0459] DRAM included in the main memory 30 has a function of holding programs and data read from the storage 40, for example. The recording density of DRAM is approximately 0.1 Gbit / mm 2 to 0.3 Gbit / mm 2 is.

[0460] The storage 40 has a function of holding data that needs to be stored long-term, various programs used in the arithmetic processing unit, etc. Therefore, the storage 40 is required to have a larger memory capacity and a higher recording density than the operating speed. The recording density of the memory device used for the storage 40 is approximately 0.6 Gbit / mm 2 to 6.0 Gbit / mm 2 is. For this reason, as the storage 40, a three-dimensional NAND-type memory circuit, a hard disk drive (HDD), etc. are used.

[0461] By the way, since the monolithic IC in FIG. 47B has the roles of the storage 40 and the main memory 30 in FIG. 47A, the memory hierarchy of the monolithic IC in FIG. 47B is as shown in FIG. 48B.

[0462] That is, in the monolithic IC of FIG. 47B, the memory cells included in the storage unit of the information processing apparatus 50 can be regarded not only as the cache memory of the storage unit but also as the main memory 30 in the computer of FIG. 47A. Therefore, in the monolithic IC of FIG. 47B, there is no need to provide a main memory 30 such as a DRAM, so that the circuit area of the monolithic IC of FIG. 47B can be reduced, and the power consumption required to operate the main memory 30 such as a DRAM can also be reduced.

[0463] Note that the configuration of the monolithic IC shown in FIG. 47B is an example and is not limited to one aspect of the present invention. The configuration of the monolithic IC shown in FIG. 47B may be changed according to the situation. For example, in the monolithic IC of FIG. 47B, when a high-speed memory of 1 GHz or more is required as an SRAM, for example, the SRAM may be mounted on the arithmetic processing unit.

[0464] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0465] (Embodiment 5) In this embodiment, an example of a chip 1200, which is a type of semiconductor device in which the storage device of the present invention is mounted, is shown using FIGS. 49A and 49B. A plurality of circuits (systems) are mounted on the chip 1200. In this way, the technology of integrating a plurality of circuits (systems) on one chip is sometimes called a System on Chip (SoC).

[0466] As shown in FIG. 49A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0467] The chip 1200 is provided with bumps (not shown) and is connected to the first surface of a Printed Circuit Board (PCB) 1201 as shown in FIG. 49B. Also, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to a motherboard 1203.

[0468] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. As the flash memory 1222, it is preferable to use the semiconductor device shown in the previous embodiment. By using the semiconductor device shown in the previous embodiment for the flash memory 1222, the storage capacity of the flash memory 1222 can be increased.

[0469] The CPU 1211 preferably has a plurality of CPU cores. Also, the GPU 1212 preferably has a plurality of GPU cores. Also, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a common memory for the CPU 1211 and the GPU 1212 may be provided on the chip 1200. Also, the GPU 1212 is suitable for parallel calculation of a large number of data and can be used for image processing and multiplication-accumulation operations. By providing an image processing circuit and a multiplication-accumulation circuit in the GPU 1212, it becomes possible to execute image processing and multiplication-accumulation operations with low power consumption.

[0470] Also, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, and transfer of the calculation result from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed at high speed.

[0471] The analog arithmetic unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Also, the above-mentioned product-sum arithmetic circuit may be provided in the analog arithmetic unit 1213.

[0472] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.

[0473] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0474] The network circuit 1216 has a network circuit for connecting to a LAN (Local Area Network), etc. Also, it may have a circuit for network security.

[0475] The above-mentioned circuits (systems) can be formed on the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0476] The PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 can be called a GPU module 1204.

[0477] Since the GPU module 1204 has the chip 1200 using SoC technology, its size can be reduced. Also, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles. Further, since the multiplication-accumulation circuit using the GPU 1212 can execute methods such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0478] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments and the like.

[0479] (Embodiment 6) In this embodiment, an application example of a semiconductor device using the storage device shown in the previous embodiment will be described. The storage device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives). Some configuration examples of the removable storage device are schematically shown in FIGS. 50A to 50E. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0480] FIG. 50A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The storage device or semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like.

[0481] FIG. 50B is a schematic diagram of the appearance of an SD card, and FIG. 50C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing the memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Also, a wireless chip having a wireless communication function may be provided on the substrate 1113. Thereby, data can be read from and written to the memory chip 1114 by wireless communication between the host device and the SD card 1110. A storage device or a semiconductor device shown in the previous embodiments can be incorporated into the memory chip 1114 or the like.

[0482] FIG. 50D is a schematic diagram of the appearance of an SSD, and FIG. 50E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 also on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. A storage device or a semiconductor device shown in the previous embodiments can be incorporated into the memory chip 1154 or the like.

[0483] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0484] (Embodiment 7) FIGS. 51A to 51G show specific examples of electronic devices equipped with a storage device or a semiconductor device according to one aspect of the present invention.

[0485] <Electronic device / system> A memory device or semiconductor device according to an aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include, for example, information terminals, computers, smartphones, e-book terminals, television devices, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, recording and playback devices, navigation systems, audio playback devices, and the like. Here, the computer includes large computers such as server systems in addition to tablet-type computers, notebook-type computers, and desktop-type computers.

[0486] An electronic device according to an aspect of the present invention may have an antenna. By receiving a signal with the antenna, it is possible to display video, information, etc. on the display unit. Further, when the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

[0487] An electronic device according to an aspect of the present invention may have a sensor (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays).

[0488] An electronic device according to an aspect of the present invention can have various functions. For example, functions such as displaying various information (still images, moving images, text images, etc.) on the display unit, touch panel function, displaying a calendar, date, or time, executing various software (programs), wireless communication function, and reading programs or data recorded on a recording medium can be provided.

[0489] [Information Terminal] Using the memory device or semiconductor device according to one aspect of the present invention, a memory device for holding a program of a microcontroller can be formed. Therefore, according to one aspect of the present invention, the microcontroller chip can be miniaturized.

[0490] FIG. 51A shows a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As an input interface, a touch panel is provided in the display unit 5102, and buttons are provided in the housing 5101. By using the miniaturized microcontroller according to one aspect of the present invention, the limited space inside the mobile phone can be effectively utilized. Also, a memory device according to one aspect of the present invention may be used for the storage of the mobile phone. Thereby, the storage capacity per unit area of the storage can be increased.

[0491] FIG. 51B shows a notebook information terminal 5200. The notebook information terminal 5200 has a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203. By using the miniaturized microcontroller according to one aspect of the present invention, the limited space inside the notebook information terminal can be effectively utilized. Also, a memory device according to one aspect of the present invention may be used for the storage of the notebook information terminal. Thereby, the storage capacity per unit area of the storage can be increased.

[0492] In the above description, a smartphone and a notebook information terminal are illustrated in FIGS. 51A and 51B as examples of electronic devices, respectively. However, information terminals other than smartphones and notebook information terminals can be applied. Examples of information terminals other than smartphones and notebook information terminals include, for example, PDAs (Personal Digital Assistants), desktop information terminals, workstations, and the like.

[0493] [Game console] FIG. 51C shows a portable game machine 5300 which is an example of a game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, etc. The housing 5302 and the housing 5303 can be removed from the housing 5301. By attaching the connection unit 5305 provided in the housing 5301 to another housing (not shown), the video output to the display unit 5304 can be output to another video device (not shown). At this time, the housing 5302 and the housing 5303 can each function as an operation unit. Thereby, a plurality of players can play games simultaneously. A storage device or a semiconductor device according to an aspect of the present invention can be incorporated into chips etc. provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.

[0494] Also, FIG. 51D shows a stationary game machine 5400 which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.

[0495] By using a miniaturized microcontroller according to an aspect of the present invention in game machines such as the portable game machine 5300 and the stationary game machine 5400, the limited space inside the game machine can be effectively utilized. Also, a storage device or a semiconductor device according to an aspect of the present invention may be used for the storage of the portable game machine. Thereby, the storage capacity per unit area of the storage can be increased.

[0496] In FIGS. 51C and 51D, a portable game machine and a stationary game machine are illustrated as examples of game machines, but the game machines to which the microcontroller according to an aspect of the present invention is applied are not limited thereto. Examples of game machines to which the microcontroller according to an aspect of the present invention is applied include, for example, arcade game machines installed in entertainment facilities (such as game centers and amusement parks), and pitching machines for batting practice installed in sports facilities.

[0497] [Large computer] A memory device or semiconductor device according to an aspect of the present invention can be applied to a large computer.

[0498] FIG. 51E is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 51F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0499] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. Further, a plurality of substrates 5504 are provided on the computer 5502, and a microcontroller according to an aspect of the present invention can be mounted on the substrate. By using a miniaturized microcontroller according to an aspect of the present invention, the limited space of a large computer can be effectively utilized. Also, a memory device or semiconductor device according to an aspect of the present invention may be used for the storage of a large computer. Thereby, the storage capacity per unit area of the storage can be increased.

[0500] In FIGS. 51E and 51F, a supercomputer is illustrated as an example of a large computer, but the large computer to which a microcontroller according to an aspect of the present invention is applied is not limited thereto. Examples of the large computer to which a microcontroller according to an aspect of the present invention is applied include, for example, a computer (server) that provides services, a large general-purpose computer (mainframe), and the like.

[0501] [Household Appliance] FIG. 51G shows an electric refrigerator-freezer 5800, which is an example of a household appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0502] A memory device, a semiconductor device, or the like according to one aspect of the present invention can also be applied to an electric refrigerator 5800. For example, by applying a miniaturized microcontroller according to one aspect of the present invention to the electric refrigerator 5800, the limited space of the electric refrigerator can be effectively utilized.

[0503] Although an electric refrigerator has been described as an example of an electrical appliance, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, air conditioners and other heating and cooling appliances, washing machines, dryers, audio-visual equipment, and the like.

[0504] The electronic devices, the functions of the electronic devices, the effects, etc. described in the present embodiment can be appropriately combined with the descriptions of other electronic devices.

[0505] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

Description of Reference Numerals

[0506] 100: Memory device, 105: Region, 110: Memory cell array, 120: Memory string, 121: Substrate, 122: Conductor, 123: Insulator, 124: Insulator, 125: Semiconductor, 126: Insulator, 127: Semiconductor, 128: Conductor, 129: Insulator, 130: Conductor, 131: Insulator, 132: Insulator, 133: Insulator, 135: Insulator, 136: Conductor, 137: Insulator, 138: Insulator, 139: Insulator, 140: Mask, 141: Opening, 150: Insulator, 156: Insulator, 161: Conductor, 162: Conductor, 163: Conductor, 164: Conductor, 165: Conductor, 166: Conductor, 171: Conductor, 172: Conductor, 173: Conductor, 174: Conductor, 175: Conductor, 176: Conductor, 181: Insulator, 182: Conductor, 183: Conductor

Claims

Claim 1 A method of manufacturing a memory device having a first transistor, a second transistor, and a capacitor on a substrate, wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor and the capacitor, the first transistor having an insulator that functions as a gate insulating film, the insulator being formed by performing a first step of supplying a silicon-containing gas and an oxidizing gas to a chamber in which the substrate is disposed, performing a second step of stopping the supply of the silicon-containing gas to the chamber, performing a third step of generating plasma containing the oxidizing gas in the chamber, and repeating a cycle including these steps a plurality of times. A method of manufacturing a memory device.

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