Wiring board

Abstract

To provide a wiring board having improved adhesion between a wiring layer and an isolation layer.SOLUTION: A wiring board comprises: an isolation layer that coats a first wiring layer and contains a filler; an opening that is formed in the isolation layer and exposes an upper surface of the first wiring layer; and a second wiring layer that fills the opening and is electrically connected to the first wiring layer, the second wiring layer extending to an upper surface of the isolation layer from an inside of the opening. The second wiring layer includes: a via wiring that fills the opening and is electrically connected to the first wiring layer; and a wiring pattern and / or a pad that are / is formed on the via wiring. A concave part resulting from removing the filler is formed on an inner wall surface of the opening.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a wiring board.

Background Art

[0002] A wiring board is known that has an insulating layer covering a first wiring layer, an opening exposing the upper surface of the first wiring layer formed in the insulating layer, and a second wiring layer filling the opening and extending on the upper surface of the insulating layer.

[0003] The second wiring layer is formed, for example, as follows. First, an opening exposing the upper surface of the first wiring layer is formed in the insulating layer. Then, after performing a pretreatment for plating on the entire surface of the insulating layer including the inside of the opening, a seed layer is formed. Next, selective electrolytic plating is performed using the seed layer as a base to form an electrolytic plating layer. Thereafter, an unnecessary seed layer is removed by etching using the electrolytic plating layer as a mask, and a second wiring layer composed of the seed layer and the electrolytic plating layer is formed (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, the insulating layer may contain a filler. In this case, there is a risk that the filler exposed on the inner wall surface of the opening during the pretreatment for plating may fall off. When the filler falls off, since the pretreatment for plating is not performed in the recess formed at the portion where the filler has fallen off, the inside of the recess becomes a non-deposited portion of the seed layer. Since the growth of electrolytic plating is inhibited at the non-deposited portion of the seed layer, the adhesion between the second wiring layer and the insulating layer decreases.

[0006] The present invention has been made in view of the above points, and an object thereof is to provide a wiring board with improved adhesion between a wiring layer and an insulating layer.

Means for Solving the Problems

[0007] This wiring board has an insulating layer containing a filler that covers a first wiring layer, an opening formed in the insulating layer that exposes the upper surface of the first wiring layer, and a second wiring layer that fills the opening and is electrically connected to the first wiring layer and extends from the inside of the opening to the upper surface of the insulating layer. The second wiring layer includes a via wiring that fills the opening and is electrically connected to the first wiring layer, and a wiring pattern and / or pad formed on the via wiring. A recess, which is a mark where the filler has been removed, is formed on the inner wall surface of the opening. The second wiring layer has a structure in which an electrolytic plating layer is laminated on a seed layer. A catalyst is adsorbed on at least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed within the opening. The seed layer is continuously formed on the catalyst along at least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed within the opening. The electrolytic plating layer is continuously formed on the seed layer along at least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed within the opening, and fills the inside of the opening including the inside of the recess.

Effects of the Invention

[0008] According to the disclosed technology, a wiring board with improved adhesion between a wiring layer and an insulating layer can be provided.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Mode for Carrying Out the Invention

[0010] Hereinafter, modes for carrying out the invention will be described with reference to the drawings. In each drawing, the same reference numerals are given to the same components, and duplicate explanations may be omitted.

[0011] 〈First Embodiment〉 [Structure of Wiring Board According to First Embodiment] FIG. 1 is a cross-sectional view illustrating the wiring board according to the first embodiment. FIG. 1(a) is an overall view, and FIG. 1(b) is a partially enlarged view of part A in FIG. 1(a).

[0012] Referring to FIG. 1, the wiring board 1 is a wiring board in which a wiring layer and an insulating layer are laminated on both sides of a core layer 10.

[0013] Specifically, in the wiring board 1, on one surface 10a of the core layer 10, a wiring layer 12, an insulating layer 13, a wiring layer 14, an insulating layer 15, a wiring layer 16, a solder resist layer 17, and a wiring layer 18 are sequentially laminated. On the other surface 10b of the core layer 10, a wiring layer 22, an insulating layer 23, a wiring layer 24, an insulating layer 25, a wiring layer 26, and a solder resist layer 27 are sequentially laminated.

[0014] In the first embodiment, for convenience, the side of the solder resist layer 17 of the wiring board 1 is defined as the upper side or one side, and the side of the solder resist layer 27 is defined as the lower side or the other side. Also, the surface on the side of the solder resist layer 17 of each part is defined as one surface or the upper surface, and the surface on the side of the solder resist layer 27 is defined as the other surface or the lower surface. However, the wiring board 1 can be used in an upside-down state or arranged at an arbitrary angle. The plan view refers to viewing the object from the normal direction of one surface 10a of the core layer 10, and the planar shape refers to the shape of the object viewed from the normal direction of one surface 10a of the core layer 10.

[0015] As the core layer 10, for example, a so-called glass epoxy substrate obtained by impregnating a glass cloth with an insulating resin such as an epoxy resin can be used. As the core layer 10, a substrate obtained by impregnating a woven fabric or non-woven fabric of glass fiber, carbon fiber, aramid fiber, etc. with an epoxy resin or the like may also be used. The thickness of the core layer 10 is, for example, about 60 to 1000 μm. The core layer 10 is provided with a through hole 10x penetrating in the thickness direction. The planar shape of the through hole 10x is, for example, circular.

[0016] The wiring layer 12 is formed on one surface 10a of the core layer 10. Also, the wiring layer 22 is formed on the other surface 10b of the core layer 10. The wiring layer 12 and the wiring layer 22 are electrically connected by a through wiring 11 formed in the through hole 10x. The wiring layers 12 and 22 are each patterned into a predetermined planar shape. As the material of the wiring layers 12 and 22 and the through wiring 11, for example, copper (Cu) or the like can be used. The thickness of the wiring layers 12 and 22 is, for example, about 10 to 40 μm. Note that the wiring layer 12, the wiring layer 22, and the through wiring 11 may be integrally formed.

[0017] The insulating layer 13 is an interlayer insulating layer formed so as to cover the wiring layer 12 on one surface 10a of the core layer 10. As the material of the insulating layer 13, for example, a non-photosensitive thermosetting resin mainly composed of an epoxy resin or the like can be used. The thickness of the insulating layer 13 is, for example, about 25 to 40 μm. The insulating layer 13 contains a filler such as silicon dioxide (SiO2), for example. The particle size of the filler is, for example, about 0.1 to 10 μm. The content of the filler is, for example, about 30 to 80% by weight.

[0018] The insulating layer 13 has a via hole 13x which is an opening. The via hole 13x penetrates the insulating layer 13 and exposes the upper surface of the wiring layer 12. The wiring layer 14 fills the via hole 13x and is electrically connected to the wiring layer 12, and extends from inside the via hole 13x to the upper surface of the insulating layer 13. Specifically, the wiring layer 14 includes a via wiring filled in the via hole 13x and a wiring pattern formed on the upper surface of the insulating layer 13. The wiring pattern of the wiring layer 14 is electrically connected to the wiring layer 12 via the via wiring. The via hole 13x is, for example, an inverted frustum-shaped recess in which the diameter of the opening on the insulating layer 15 side is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 12. The material of the wiring layer 14 and the thickness of the wiring pattern are, for example, the same as those of the wiring layer 12.

[0019] The insulating layer 15 is an interlayer insulating layer formed to cover the wiring layer 14 on the upper surface of the insulating layer 13. The material and thickness of the insulating layer 15 are, for example, the same as those of the insulating layer 13. The insulating layer 15 contains, for example, the same filler as the insulating layer 13.

[0020] The insulating layer 15 has via holes 15x which are openings. The via holes 15x penetrate the insulating layer 15 and expose the upper surface of the wiring layer 14. The wiring layer 16 fills the via holes 15x and is electrically connected to the wiring layer 14, and extends from inside the via holes 15x to the upper surface of the insulating layer 15. Specifically, the wiring layer 16 includes via wirings filled in the via holes 15x and wiring patterns formed on the upper surface of the insulating layer 15. The wiring patterns of the wiring layer 16 are electrically connected to the wiring layer 14 via the via wirings. The via holes 15x are, for example, inverted frustum-shaped recesses in which the diameter of the opening on the side of the solder resist layer 17 is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 14. The material of the wiring layer 16 and the thickness of the wiring patterns are, for example, the same as those of the wiring layer 12.

[0021] The solder resist layer 17 is a protective insulating layer located outermost on one side of the wiring substrate 1, and is formed on the upper surface of the insulating layer 15 to cover the wiring layer 16. The solder resist layer 17 can be formed, for example, from a photosensitive resin mainly composed of an epoxy resin or the like. The thickness of the solder resist layer 17 is, for example, about 15 to 35 μm.

[0022] The solder resist layer 17 contains, for example, fillers 171 such as silicon dioxide (SiO2) and barium sulfate (BaSO4). The particle size of the fillers 171 is, for example, about 0.3 to 4 μm. The content of the fillers 171 is, for example, about 30 to 60% by weight.

[0023] The solder resist layer 17 has openings 17x. The openings 17x penetrate the solder resist layer 17 and expose the upper surface of the wiring layer 16. The wiring layer 18 fills the openings 17x and is electrically connected to the wiring layer 16, and extends from within the openings 17x to the upper surface of the solder resist layer 17. Specifically, the wiring layer 18 includes via wirings filled in the openings 17x and pads formed on the upper surface of the solder resist layer 17. The pads constituting the wiring layer 18 are electrically connected to the wiring layer 16 via the via wirings. The openings 17x are, for example, inverted frustum-shaped recesses in which the diameter of the openings opened on the surface side of the solder resist layer 17 is larger than the diameter of the bottom surface of the openings formed by the upper surface of the wiring layer 16.

[0024] The planar shape of the pads constituting the wiring layer 18 is, for example, circular with a diameter of about 35 to 85 μm. The pitch of the pads constituting the wiring layer 18 is, for example, about 40 to 100 μm. The thickness of the pads constituting the wiring layer 18 is, for example, about 10 to 30 μm. Note that the pads constituting the wiring layer 18 function as pads for mounting electronic components for electrically connecting to electronic components such as semiconductor chips.

[0025] The wiring layer 18 has a seed layer 181 and an electrolytic plating layer 182, and has a structure in which the electrolytic plating layer 182 is laminated on the seed layer 181. The seed layer 181 is continuously formed on the region located around the openings 17x on the upper surface of the solder resist layer 17, the inner wall surface of the openings 17x, and the upper surface of the wiring layer 16 exposed within the openings 17x. The material of the seed layer 181 is, for example, copper. The thickness of the seed layer 181 is, for example, about 0.3 to 1 μm. The material of the electrolytic plating layer 182 is, for example, copper. The material of the electrolytic plating layer 182 may be nickel or tin in addition to copper.

[0026] As shown in FIG. 1(b), the filler 171 contained in the solder resist layer 17 may partially protrude from the inner wall of the opening 17x, or a recess 17y, which is a trace of the filler 171 contained in the solder resist layer 17 falling off, may be formed on the inner wall surface of the opening 17x. In such a case, the seed layer 181 is also formed on the surface of the filler 171 exposed from the inner wall surface of the opening 17x and on the inner wall surface of the recess 17y.

[0027] That is, the seed layer 181 is formed with a substantially uniform thickness on the region located around the opening 17x on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, the surface of the filler 171 exposed from the inner wall surface of the opening 17x, the inner wall surface of the recess 17y, and the upper surface of the wiring layer 16 exposed in the opening 17x. The reason for this will be described in the section on the manufacturing method of the wiring board 1.

[0028] The electrolytic plating layer 182 is formed on the seed layer 181. The electrolytic plating layer 182 is formed so as to fill the opening 17x and further extend above the upper surface of the seed layer 181 located around the opening 17x. Here, the portion filled in the opening 17x of the wiring layer 18 is referred to as a via wiring, and the portion protruding from the upper surface of the solder resist layer 17 is referred to as a pad.

[0029] Note that a metal layer may be formed on the surface of the pad constituting the wiring layer 18, or an antioxidant treatment such as OSP (Organic Solderability Preservative) treatment may be performed to form an organic film. Examples of the metal layer include an Au layer, a Ni / Au layer (a metal layer formed by laminating a Ni layer and an Au layer in this order), a Ni / Pd / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and an Au layer in this order), a Sn layer, and the like.

[0030] The insulating layer 23 is an interlayer insulating layer formed so as to cover the wiring layer 22 on the other surface 10b of the core layer 10. The material and thickness of the insulating layer 23 are, for example, the same as those of the insulating layer 13. The insulating layer 23 contains, for example, the same filler as the insulating layer 13.

[0031] The insulating layer 23 has via holes 23x which are openings. The via holes 23x penetrate the insulating layer 23 and expose the lower surface of the wiring layer 22. The wiring layer 24 fills the via holes 23x and is electrically connected to the wiring layer 22, and extends from inside the via holes 23x to the lower surface of the insulating layer 23. Specifically, the wiring layer 24 includes via wirings filled in the via holes 23x and wiring patterns formed on the lower surface of the insulating layer 23. The wiring patterns of the wiring layer 24 are electrically connected to the wiring layer 22 via the via wirings. The via holes 23x are, for example, frustum-shaped recesses in which the diameter of the opening on the insulating layer 25 side is larger than the diameter of the bottom surface of the opening formed by the lower surface of the wiring layer 22. The material of the wiring layer 24 and the thickness of the wiring patterns are, for example, the same as those of the wiring layer 12.

[0032] The insulating layer 25 is an interlayer insulating layer formed to cover the wiring layer 24 on the lower surface of the insulating layer 23. The material and thickness of the insulating layer 25 are, for example, the same as those of the insulating layer 13. The insulating layer 25 contains, for example, the same filler as the insulating layer 13.

[0033] The insulating layer 25 has via holes 25x which are openings. The via holes 25x penetrate the insulating layer 25 and expose the lower surface of the wiring layer 24. The wiring layer 26 fills the via holes 25x and is electrically connected to the wiring layer 24, and extends from inside the via holes 25x to the lower surface of the insulating layer 25. Specifically, the wiring layer 26 includes via wirings filled in the via holes 25x and wiring patterns formed on the lower surface of the insulating layer 25. The wiring patterns of the wiring layer 26 are electrically connected to the wiring layer 24 via the via wirings. The via holes 25x are, for example, frustum-shaped recesses in which the diameter of the opening on the solder resist layer 27 side is larger than the diameter of the bottom surface of the opening formed by the lower surface of the wiring layer 24. The material of the wiring layer 26 and the thickness of the wiring patterns are, for example, the same as those of the wiring layer 12.

[0034] The solder resist layer 27 is a protective insulating layer located outermost on the other side of the wiring board 1, and is formed on the lower surface of the insulating layer 25 so as to cover the wiring layer 26. The material and thickness of the solder resist layer 27 are, for example, the same as those of the solder resist layer 17. The solder resist layer 27 contains, for example, the same filler as the solder resist layer 17.

[0035] The solder resist layer 27 has an opening 27x, and a part of the lower surface of the wiring layer 26 is exposed in the opening 27x. The planar shape of the opening 27x is, for example, circular. The wiring layer 26 exposed in the opening 27x can be used as a pad for electrically connecting to a mounting board (not shown) such as a motherboard. If necessary, a metal layer may be formed on the lower surface of the wiring layer 26 exposed in the opening 27x, or an antioxidant treatment such as OSP treatment may be performed to form an organic film.

[0036] [Manufacturing Method of Wiring Board According to First Embodiment] FIGS. 2 to 5 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment. FIGS. 2, 4(a), 4(c), and 5 are cross-sectional views corresponding to FIG. 1(a), and FIGS. 3 and 4(b) are cross-sectional views corresponding to FIG. 1(b). Here, an example of the process of manufacturing one wiring board is shown, but it may also be a process of manufacturing a plurality of parts that will become the wiring board and then separating them into individual wiring boards.

[0037] First, in the process shown in FIG. 2(a), the through-wiring 11, the wiring layers 12 and 22 are formed on the core layer 10. Specifically, for example, a laminate in which a planar copper foil that has not been patterned is formed on one surface 10a and the other surface 10b of the core layer 10, which is a so-called glass epoxy substrate or the like, is prepared. Then, in the prepared laminate, after thinning the copper foil on each surface as necessary, a through-hole 10x that penetrates the core layer 10 and the copper foil on each surface is formed by a laser processing method using a CO2 laser or the like.

[0038] Next, if necessary, perform desmear treatment to remove the resin residue contained in the core layer 10 adhering to the inner wall surface of the through hole 10x. Then, for example, by electroless plating method, sputtering method, etc., form a seed layer (such as copper) that coats the copper foil on each surface and the inner wall surface of the through hole 10x, and form an electrolytic plating layer (such as copper) on the seed layer by an electrolytic plating method using the seed layer as the power supply layer. As a result, the through hole 10x is filled with the electrolytic plating layer formed on the seed layer, and wiring layers 12 and 22 in which a copper foil, a seed layer, and an electrolytic plating layer are laminated are formed on one surface 10a and the other surface 10b of the core layer 10. Next, pattern the wiring layers 12 and 22 into a predetermined planar shape by a subtractive method or the like.

[0039] Next, in the process shown in FIG. 2(b), a non-photosensitive thermosetting resin mainly composed of a semi-cured film-like epoxy resin or the like is laminated so as to cover the wiring layer 12 on one surface 10a of the core layer 10 and cured to form an insulating layer 13. Also, a non-photosensitive thermosetting resin mainly composed of a semi-cured film-like epoxy resin or the like is laminated so as to cover the wiring layer 22 on the other surface 10b of the core layer 10 and cured to form an insulating layer 23. Alternatively, instead of laminating a film-like epoxy resin or the like, a liquid or paste-like epoxy resin or the like may be applied and then cured to form the insulating layers 13 and 23. The thickness of each of the insulating layers 13 and 23 is, for example, about 25 to 40 μm.

[0040] Each of the insulating layers 13 and 23 contains, for example, a filler such as silicon dioxide (SiO2). The particle size of the filler is, for example, about 0.1 to 10 μm. The content of the filler is, for example, about 30 to 80% by weight.

[0041] Next, vias 13x, which are openings that penetrate the insulation layer 13 and expose the upper surface of the wiring layer 12, are formed in the insulation layer 13. Also, vias 23x, which are openings that penetrate the insulation layer 23 and expose the lower surface of the wiring layer 22, are formed in the insulation layer 23. The vias 13x and 23x can be formed, for example, by a laser processing method using a CO2 laser or the like. After forming the vias 13x and 23x, it is preferable to perform a desmear treatment to remove the resin residues attached to the surfaces of the wiring layers 12 and 22 exposed at the bottoms of the vias 13x and 23x, respectively.

[0042] Next, the via 13x is filled to electrically connect to the wiring layer 12, and a wiring layer 14 that extends from within the via 13x to the upper surface of the insulation layer 13 is formed. The wiring layer 14 includes via wirings filled in the via 13x and wiring patterns formed on the upper surface of the insulation layer 13. The material of the wiring layer 14 and the thickness of the wiring pattern are, for example, the same as those of the wiring layer 12. The wiring pattern of the wiring layer 14 is electrically connected to the wiring layer 12 exposed at the bottom of the via 13x.

[0043] Also, the via 23x is filled to electrically connect to the wiring layer 22, and a wiring layer 24 that extends from within the via 23x to the lower surface of the insulation layer 23 is formed. The wiring layer 24 includes via wirings filled in the via 23x and wiring patterns formed on the lower surface of the insulation layer 23. The material of the wiring layer 24 and the thickness of the wiring pattern are, for example, the same as those of the wiring layer 12. The wiring layer 24 is electrically connected to the wiring layer 22 exposed at the bottom of the via 23x. The wiring layers 14 and 24 can be formed using various wiring formation methods such as the semi-additive method and the subtractive method.

[0044] Next, in the same formation method as that of the insulating layer 13, an insulating layer 15 is formed so as to cover the wiring layer 14 on the upper surface of the insulating layer 13. The material and thickness of the insulating layer 15 are the same as those of the insulating layer 13, for example. Then, via holes 15x are formed by the same formation method as that of the via holes 13x. Also, in the same formation method as that of the insulating layer 13, an insulating layer 25 is formed so as to cover the wiring layer 24 on the lower surface of the insulating layer 23. The material and thickness of the insulating layer 25 are the same as those of the insulating layer 13, for example. Then, via holes 25x are formed by the same formation method as that of the via holes 13x. Each of the insulating layers 15 and 25 contains a filler similar to that of the insulating layer 13, for example.

[0045] After forming the via holes 15x and 25x, it is preferable to perform a desmear treatment to remove the resin residues attached to the surfaces of the wiring layers 14 and 24 respectively exposed at the bottoms of the via holes 15x and 25x.

[0046] Next, the via holes 15x are filled to be electrically connected to the wiring layer 14, and a wiring layer 16 extending from inside the via holes 15x to the upper surface of the insulating layer 15 is formed. The wiring layer 16 includes via wirings filled in the via holes 15x and wiring patterns formed on the upper surface of the insulating layer 15. The material of the wiring layer 16 and the thickness of the wiring patterns are the same as those of the wiring layer 12, for example. The wiring patterns of the wiring layer 16 are electrically connected to the wiring layer 14 exposed at the bottom of the via holes 15x.

[0047] Also, the via holes 25x are filled to be electrically connected to the wiring layer 24, and a wiring layer 26 extending from inside the via holes 25x to the lower surface of the insulating layer 25 is formed. The wiring layer 26 includes via wirings filled in the via holes 25x and wiring patterns formed on the lower surface of the insulating layer 25. The material of the wiring layer 26 and the thickness of the wiring patterns are the same as those of the wiring layer 12, for example. The wiring layer 26 is electrically connected to the wiring layer 24 exposed at the bottom of the via holes 25x. The wiring layers 16 and 26 can be formed using various wiring formation methods such as semi-additive method and subtractive method.

[0048] Next, in the process shown in FIG. 2(c), a solder resist layer 17 is formed on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. Also, a solder resist layer 27 is formed on the lower surface of the insulating layer 25 so as to cover the wiring layer 26. The solder resist layer 17 can be formed, for example, by applying a liquid or paste-like photosensitive epoxy-based insulating resin onto the upper surface of the insulating layer 15 so as to cover the wiring layer 16 by screen printing, roll coating, spin coating, or the like. Alternatively, for example, it may be formed by laminating a film-like photosensitive epoxy-based insulating resin onto the upper surface of the insulating layer 15 so as to cover the wiring layer 16. The method of forming the solder resist layer 27 is the same as that of the solder resist layer 17.

[0049] Note that the solder resist layers 17 and 27 contain, for example, fillers 171 such as silicon dioxide (SiO2) and barium sulfate (BaSO4). The particle size of the filler 171 is, for example, about 0.3 to 4 μm. The content of the filler 171 is, for example, about 30 to 60% by weight.

[0050] Next, in the process shown in FIG. 2(d), by exposing and developing the solder resist layers 17 and 27, openings 17x are formed in the solder resist layer 17 to expose a part of the upper surface of the wiring layer 16 (photolithography method). Also, openings 27x are formed in the solder resist layer 27 to expose a part of the lower surface of the wiring layer 26 (photolithography method). The planar shape of each of the openings 17x and 27x is, for example, circular. The diameter of each of the openings 17x and 27x can be arbitrarily designed according to the connection target (such as a semiconductor chip).

[0051] FIG. 3(a) is an enlarged view of part B in FIG. 2(d). As shown in FIG. 3(a), when the opening 17x is formed in the solder resist layer 17, for example, the filler 171 is exposed on the inner wall surface of the opening 17x. Also, although not shown, when the opening 27x is formed in the solder resist layer 27, for example, the filler is exposed on the inner wall surface of the opening 27x.

[0052] Next, in the process shown in FIG. 3(b), a first alkali treatment is performed as a pretreatment for electroless plating. Specifically, for example, on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, the surface of the filler 171 exposed from the inner wall surface of the opening 17x, and the upper surface of the wiring layer 16 exposed in the opening 17x, a treatment liquid obtained by adding an appropriate amount of surfactant to 1.5 - 2% sodium hydroxide is used, and the treatment is performed for about 4 - 5 minutes in a temperature environment of about 50 - 60°C. Examples of the surfactant include octylphenol ethoxylate (ether compound).

[0053] By the first alkali treatment, cleaning and conditioning are performed on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, the surface of the filler 171 exposed from the inner wall surface of the opening 17x, and the upper surface of the wiring layer 16 exposed in the opening 17x. In FIG. 3(b), the surfaces subjected to cleaning and conditioning are shown by broken lines for convenience.

[0054] Here, cleaning is a cleaning process of the surface of the solder resist layer 17 for forming a seed layer (electroless plating layer) on the surface of the solder resist layer 17. Conditioning is a process for adjusting the surface state of the solder resist layer 17.

[0055] In this embodiment, a seed layer is formed on the surface of the solder resist layer 17 by electroless plating. By cleaning and conditioning, a catalyst (such as palladium) for depositing electroless plating is likely to be adsorbed on the surface of the solder resist layer 17. Due to the presence of the catalyst, an electroless plating layer can be formed well on the surface of the solder resist layer 17. That is, a seed layer for forming an electrolytic plating layer can be formed well on the surface of the solder resist layer 17.

[0056] Also, due to the first alkali treatment, the resin constituting the solder resist layer 17 becomes wet and swollen. By this treatment, the force with which the solder resist layer 17 fixes the filler 171 at the opening 17x is reduced, and the filler 171 is likely to fall off from the solder resist layer 17.

[0057] Next, in the process shown in FIG. 3(c), ultrasonic cleaning treatment is performed. The ultrasonic cleaning treatment is, for example, ultrasonic water washing in which ultrasonic vibration with a frequency of 35 to 50 kHz is applied, and the treatment time is about 3 to 10 minutes. By the ultrasonic cleaning treatment, the filler 171 that was likely to fall off in the process shown in FIG. 3(b) is removed. After the removal, a concave portion 17y, which is a mark where the filler 171 has been removed, is formed on the inner wall surface of the opening 17x. The removed filler 171 is removed from the inside of the opening 17x by the ultrasonic cleaning treatment. Even if there is filler 171 that has fallen off before the ultrasonic cleaning treatment, the fallen filler 171 is removed from the inside of the opening 17x by the ultrasonic cleaning treatment. The concave portion 17y is in a state where cleaning and conditioning have not been performed. In FIG. 3(c), the surface that has been cleaned and conditioned is shown by a broken line for convenience.

[0058] Next, in the process shown in FIG. 3(d), a second alkali treatment is performed. The second alkali treatment is performed under conditions where the filler 171 is less likely to fall off from the solder resist layer 17 than in the first alkali treatment.

[0059] The second alkali treatment can be performed, for example, using the same type of treatment liquid as in the first alkali treatment. In this case, the second alkali treatment can be performed under the following conditions. That is, it can be performed so as to satisfy any one or more of the conditions: (1) the treatment temperature of the first alkali treatment > the treatment temperature of the second alkali treatment, (2) the treatment time of the first alkali treatment > the treatment time of the second alkali treatment, (3) the treatment liquid concentration of the first alkali treatment > the treatment liquid concentration of the second alkali treatment.

[0060] That is, when the second alkali treatment is performed using a treatment liquid of the same type as the first alkali treatment, the second alkali treatment is performed so as to satisfy any one of the conditions (1), (2), and (3), so as to satisfy the conditions (1) and (2), so as to satisfy the conditions (1) and (3), so as to satisfy the conditions (2) and (3), or so as to satisfy all of the conditions (1), (2), and (3).

[0061] Specifically, for example, on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, the surface of the filler 171 exposed from the inner wall surface of the opening 17x, the inner wall surface of the recess 17y, and the upper surface of the wiring layer 16 exposed in the opening 17x, a solution obtained by adding an appropriate amount of surfactant to 1 to 1.5% sodium hydroxide is used, and the treatment is performed for about 3 to 4 minutes in a temperature environment of about 40 to 50°C. This is an example of performing the second alkali treatment so as to satisfy all of the conditions (1), (2), and (3).

[0062] By the second alkali treatment, cleaning and conditioning are performed on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, the surface of the filler 171 exposed from the inner wall surface of the opening 17x, the inner wall surface of the recess 17y, and the upper surface of the wiring layer 16 exposed in the opening 17x. In FIG. 3(d), the surfaces subjected to cleaning and conditioning are shown by broken lines for convenience.

[0063] The second alkali treatment is performed under conditions such that the filler 171 is less likely to fall off from the solder resist layer 17 than in the first alkali treatment, so the resin constituting the solder resist layer 17 is less likely to get wet. Therefore, in the second alkali treatment, there is no newly falling-off filler 171. In other words, the conditions of the second alkali treatment may be determined so that there is no newly falling-off filler 171 in the second alkali treatment.

[0064] Next, in the process shown in FIG. 4(a), a seed layer 181 is continuously formed on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, and the upper surface of the wiring layer 16 exposed in the opening 17x. Also, a seed layer 281 is continuously formed on the lower surface of the solder resist layer 27, the inner wall surface of the opening 27x, and the lower surface of the wiring layer 26 exposed in the opening 27x. The materials of the seed layers 181 and 281 are, for example, copper. The thicknesses of the seed layers 181 and 281 are, for example, about 0.3 to 1 μm. The seed layers 181 and 281 can be formed, for example, by electroless plating.

[0065] FIG. 4(b) is an enlarged view of part B in FIG. 4(a). As shown in FIG. 4(b), the seed layer 181 is also formed on the surface of the filler 171 exposed from the inner wall surface of the opening 17x and the inner wall surface of the recess 17y. That is, the seed layer 181 is formed with a substantially uniform thickness on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, the surface of the filler 171 exposed from the inner wall surface of the opening 17x, the inner wall surface of the recess 17y, and the upper surface of the wiring layer 16 exposed in the opening 17x. The same applies to the seed layer 281.

[0066] Next, in the process shown in FIG. 4(c), a resist layer 310 is formed on the upper surface of the seed layer 181. Also, a resist layer 320 is formed on the lower surface of the seed layer 281. The resist layers 310 and 320 can be formed, for example, by laminating a photosensitive dry film resist.

[0067] Next, in the process shown in FIG. 5(a), by exposing and developing the resist layer 310, an opening 310x that exposes a part of the seed layer 181 is formed in the resist layer 310. The opening 310x is opened in accordance with the shape of the electrolytic plating layer formed on the seed layer 181.

[0068] Next, in the process shown in FIG. 5(b), by the electrolytic plating method of supplying power from the seed layer 181, copper or the like is deposited on the seed layer 181 exposed in the opening 310x, and the electrolytic plating layer 182 is selectively formed. The electrolytic plating layer 182 fills the opening 17x and is further formed so as to extend above the upper surface of the seed layer 181 around the opening 17x.

[0069] Next, in the process shown in FIG. 5(c), the resist layers 310 and 320 are removed. The resist layers 310 and 320 can be removed using, for example, a stripping solution. After removing the resist layers 310 and 320, etching is performed using the electrolytic plating layer 182 as a mask to remove the seed layer 181 exposed from the electrolytic plating layer 182, and the wiring layer 18 is formed.

[0070] When the seed layer 181 and the electrolytic plating layer 182 are made of copper, for example, an aqueous hydrogen peroxide / sulfuric acid solution, an aqueous sodium persulfate solution, an aqueous ammonium persulfate solution, etc. can be used as the etching solution. At the same time as removing the seed layer 181, the seed layer 281 is also removed. Thus, the wiring board 1 is obtained.

[0071] FIGS. 6 and 7 are diagrams illustrating a method for manufacturing a wiring board according to a comparative example. In the method for manufacturing a wiring board according to the comparative example, in the process shown in FIG. 6(a), an opening 17x is formed in the solder resist layer 17 in the same manner as in the process shown in FIG. 3(a). Also, in the process shown in FIG. 6(b), an alkali treatment is performed as a pretreatment for electroless plating in the same manner as in the process shown in FIG. 3(a). However, in the method for manufacturing a wiring board according to the comparative example, the alkali treatment is performed only once, which corresponds to the first alkali treatment in the method for manufacturing a wiring board according to the first embodiment, and there is no step of the second alkali treatment. Also, there is no step of ultrasonic cleaning treatment.

[0072] When the alkali treatment is performed in the process of FIG. 6(b), the resin constituting the solder resist layer 17 becomes wet and swollen. Therefore, as shown in FIG. 6(c), the force with which the solder resist layer 17 fixes the filler 171 in the opening 17x is reduced, and the filler 171 falls off from the solder resist layer 17.

[0073] In the method for manufacturing a wiring board according to the comparative example, since ultrasonic cleaning treatment is not performed, the filler 171 that has fallen off from the solder resist layer 17 is not removed from within the opening 17x. Also, in the method for manufacturing a wiring board according to the comparative example, since the second alkali treatment is not performed, a part of the inner wall surface of the recess 17y and the surface of the filler 171 that has fallen into the opening 17x is in a state where cleaning and conditioning have not been performed. In FIG. 6(c), the surface that has been cleaned and conditioned is shown by a broken line for convenience.

[0074] Next, as shown in FIG. 6(d), a seed layer 181a is formed on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, and the upper surface of the wiring layer 16 exposed within the opening 17x by electroless plating or the like. The catalyst does not adsorb to the inner wall surface of the recess 17y where cleaning and conditioning have not been performed, and electroless plating does not deposit. Similarly, the catalyst does not adsorb to a part of the surface of the fallen filler 171 where cleaning and conditioning have not been performed, and electroless plating does not deposit. As a result, the seed layer 181a is not formed continuously and has discontinuous portions.

[0075] Next, the same steps as those in FIGS. 4(c) to 5(c) in the method for manufacturing a wiring board according to the first embodiment are executed. As a result, as shown in FIG. 7(a), a wiring layer 18a having an electrolytic plating layer 182a formed on the seed layer 181a is formed, and the wiring board 1X according to the comparative example is completed. In the wiring board 1X, since the electrolytic plating layer 182a does not deposit in the vicinity of the portion where the seed layer 181a is not formed, for example, voids B1 to B4 are formed within the opening 17x.

[0076] Next, as shown in FIG. 7(b), consider the case where the wiring layer 18a of the wiring substrate 1X is electrically connected to the electrode pad 120 of the semiconductor chip 110 via the bump 130 such as a solder bump. As shown in FIG. 7(a), since the voids B1 to B4 are formed in the opening 17x, the portions where the voids B1 to B4 exist are likely to be the starting points of the cracks C1 and C2 when an electrical or thermal load is applied. When the cracks C1 and C2 occur, there is a risk of causing a conduction failure between the wiring layer 18a and the electrode pad 120, and the connection reliability between the wiring substrate 1X and the semiconductor chip 110 is reduced.

[0077] On the other hand, as described above, the method for manufacturing a wiring substrate according to the first embodiment includes a step of sequentially performing a first alkali treatment, an ultrasonic cleaning treatment, and a second alkali treatment on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, and the upper surface of the wiring layer 16 exposed in the opening 17x between the step of forming the opening 17x and the step of forming the wiring layer 18.

[0078] Therefore, since there is no portion where cleaning and conditioning are not performed, the seed layer 181a is continuously formed without an unfilled portion. As a result, there is no portion where the electrolytic plating layer 182 is not deposited, no voids are formed in the opening 17x, and no cracks starting from the voids occur.

[0079] As a result, the adhesion between the solder resist layer 17 and the wiring layer 18 is improved, and a good adhesive force is obtained between the two. Thereby, problems such as swelling of the wiring layer 18 due to poor adhesion between the solder resist layer 17 and the wiring layer 18 are avoided.

[0080] Also, in the wiring substrate 1, since the ultrasonic cleaning treatment is performed, there is no residue of the filler 171 at the bottom of the opening 17x. Thereby, the connection strength at the connection portion between the wiring layer 16 and the wiring layer 18 in the opening 17x is ensured, and the connection reliability between the wiring layer 16 and the wiring layer 18 is improved.

[0081] Moreover, when the wiring layer 18 of the wiring substrate 1 is electrically connected to the electrode pad 120 of the semiconductor chip 110 via the bump 130, there is no possibility of causing a conduction failure between the wiring layer 18 and the electrode pad 120. Therefore, the connection reliability between the wiring substrate 1 and the semiconductor chip 110 can be improved.

[0082] <Second Embodiment> In the second embodiment, an example in which the manufacturing method of the wiring substrate according to the present invention is applied to the internal wiring of the wiring substrate is shown. In the second embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0083] [Structure of Wiring Substrate According to Second Embodiment] First, the structure of the wiring substrate according to the second embodiment will be described. FIG. 8 is a cross-sectional view illustrating the wiring substrate according to the second embodiment, and FIG. 8(a) is an overall view, and FIG. 8(b) is a partially enlarged view of part C in FIG. 8(a).

[0084] Referring to FIG. 8, in the wiring substrate 1A, the wiring layer 14 has the same structure as the wiring layer 18 of the first embodiment. That is, the wiring layer 14 has a seed layer 141 and an electrolytic plating layer 142, and has a structure in which the electrolytic plating layer 142 is laminated on the seed layer 141. The wiring layers 16, 24, and 26 may have the same structure as the wiring layer 14.

[0085] The seed layer 141 is continuously formed on the region located around the via hole 13x on the upper surface of the insulating layer 13, the inner wall surface of the via hole 13x, and the upper surface of the wiring layer 12 exposed in the via hole 13x. The material of the seed layer 141 is, for example, copper. The thickness of the seed layer 141 is, for example, about 0.3 to 1 μm.

[0086] As shown in FIG. 8(b), there may be a case where the filler 173 contained in the insulating layer 13 partially protrudes from the inner wall of the via hole 13x, or a recess 13y which is a mark where the filler 173 contained in the insulating layer 13 has fallen off is formed on the inner wall surface of the via hole 13x. In such a case, the seed layer 141 is also formed on the surface of the filler 173 exposed from the inner wall surface of the via hole 13x and on the inner wall surface of the recess 13y.

[0087] That is, the seed layer 141 is formed with a substantially uniform thickness on the region located around the via hole 13x on the upper surface of the insulating layer 13, the inner wall surface of the via hole 13x, the surface of the filler 173 exposed from the inner wall surface of the via hole 13x, the inner wall surface of the recess 13y, and the upper surface of the wiring layer 12 exposed in the via hole 13x. The reason for this will be described in the section on the manufacturing method of the wiring board 1A.

[0088] The electrolytic plating layer 142 is formed on the seed layer 141. The electrolytic plating layer 142 is formed so as to fill the via hole 13x and further extend above the upper surface of the seed layer 141 located around the via hole 13x. Here, the portion filled in the via hole 13x of the wiring layer 14 is referred to as a via wiring, and the portion protruding from the upper surface of the insulating layer 13 is referred to as a wiring pattern.

[0089] Note that the wiring pattern constituting the wiring layer 14 may be routed to an arbitrary position on the upper surface of the insulating layer 13 from above the via hole 13x. That is, the seed layer 141 may be routed to an arbitrary position on the upper surface of the insulating layer 13 from above the via hole 13x, and in that case as well, the electrolytic plating layer 142 is laminated on the seed layer 141.

[0090] [Manufacturing Method of Wiring Board According to Second Embodiment] Next, the manufacturing method of the wiring board according to the second embodiment will be described. FIGS. 9 and 10 are diagrams illustrating the manufacturing process of the wiring board according to the second embodiment. FIGS. 9 and 10 are cross-sectional views corresponding to FIG. 8(b). Here, an example of the process of manufacturing one wiring board is shown, but it may also be a process of manufacturing a plurality of portions that will become the wiring board and then separating them into individual wiring boards.

[0091] First, after performing the same steps as in FIG. 2(a) of the first embodiment, a non-photosensitive thermosetting resin mainly composed of a film-like epoxy resin or the like in a semi-cured state is laminated so as to cover the wiring layer 12 on one surface 10a of the core layer 10 and cured to form the insulating layer 13. Also, a non-photosensitive thermosetting resin mainly composed of a film-like epoxy resin or the like in a semi-cured state is laminated so as to cover the wiring layer 22 on the other surface 10b of the core layer 10 and cured to form the insulating layer 23. Alternatively, instead of laminating a film-like epoxy resin or the like, a liquid or paste-like epoxy resin or the like may be applied and then cured to form the insulating layers 13 and 23. The thickness of each of the insulating layers 13 and 23 is, for example, about 25 to 40 μm.

[0092] Each of the insulating layers 13 and 23 contains, for example, a filler 173 such as silicon dioxide (SiO2). The particle size of the filler 173 is, for example, about 0.1 to 10 μm. The content of the filler 173 is, for example, about 30 to 80% by weight.

[0093] Hereinafter, only the side of one surface 10a of the core layer 10 will be illustrated and described, but the same steps will be performed on the side of the other surface 10b of the core layer 10.

[0094] Next, in the step shown in FIG. 9(a), via holes 13x, which are openings that penetrate the insulating layer 13 and expose the upper surface of the wiring layer 12, are formed in the insulating layer 13. Also, via holes 23x, which are openings that penetrate the insulating layer 23 and expose the lower surface of the wiring layer 22, are formed in the insulating layer 23. The filler 173 is exposed on the inner wall surfaces of the via holes 13x and 23x. The via holes 13x and 23x can be formed, for example, by a laser processing method using a CO2 laser or the like. After forming the via holes 13x and 23x, it is preferable to perform a desmear treatment to remove the resin residues adhering to the surfaces of the wiring layers 12 and 22 exposed at the bottoms of the via holes 13x and 23x, respectively.

[0095] Next, in the process shown in FIG. 9(b), a first alkali treatment is performed as a pretreatment for electroless plating. The details of the first alkali treatment are as described in the process of FIG. 3(b).

[0096] By the first alkali treatment, cleaning and conditioning are performed on the upper surface of the insulating layer 13, the inner wall surface of the via hole 13x, the surface of the filler 173 exposed from the inner wall surface of the via hole 13x, and the upper surface of the wiring layer 12 exposed in the via hole 13x. In FIG. 9(b), the surfaces subjected to cleaning and conditioning are shown by broken lines for convenience.

[0097] Here, cleaning is a cleaning process of the surface of the insulating layer 13 for forming a seed layer (electroless plating layer) on the surface of the insulating layer 13. Also, conditioning is a process for adjusting the surface state of the insulating layer 13.

[0098] In this embodiment, a seed layer is formed on the surface of the insulating layer 13 by electroless plating. By cleaning and conditioning, a catalyst (such as palladium) for depositing electroless plating is likely to be adsorbed on the surface of the insulating layer 13. Due to the presence of the catalyst, an electroless plating layer can be favorably formed on the surface of the insulating layer 13. That is, a seed layer for forming an electroplating layer can be favorably formed on the surface of the insulating layer 13.

[0099] Also, by the first alkali treatment, cleaning and conditioning are performed on the lower surface of the insulating layer 23, the inner wall surface of the via hole 23x, the surface of the filler 173 exposed from the inner wall surface of the via hole 23x, and the lower surface of the wiring layer 22 exposed in the via hole 23x.

[0100] Also, due to the first alkali treatment, the resin constituting the insulating layer 13 becomes wet and swollen. By this treatment, the force by which the insulating layer 13 fixes the filler 173 within the via hole 13x is reduced, and the filler 173 easily falls off from the insulating layer 13. Also, due to the first alkali treatment, the resin constituting the insulating layer 23 becomes wet and swollen. By this treatment, the force by which the insulating layer 23 fixes the filler 173 within the via hole 23x is reduced, and the filler 173 easily falls off from the insulating layer 23.

[0101] Next, in the process shown in FIG. 9(c), an ultrasonic cleaning process is performed. Details of the ultrasonic cleaning process are as described in the process of FIG. 3(c).

[0102] By the ultrasonic cleaning process, the filler 173 that was in a state of being likely to fall off in the process shown in FIG. 9(b) is removed. After the removal, a recess 13y, which is a mark where the filler 173 has been removed, is formed on the inner wall surface of the via hole 13x. The removed filler 173 is removed from within the via hole 13x by the ultrasonic cleaning process. Even if there is filler 173 that has fallen off before the ultrasonic cleaning process, the fallen filler 173 is removed from within the via hole 13x by the ultrasonic cleaning process. The recess 13y formed on the inner wall surface of the via hole 13x is in a state where no cleaning and conditioning have been performed. In FIG. 9(c), the surface on which cleaning and conditioning have been performed is shown by a broken line for convenience.

[0103] Next, in the process shown in FIG. 9(d), a second alkali treatment is performed. Details of the second alkali treatment are as described in the process of FIG. 3(d).

[0104] By the second alkali treatment, cleaning and conditioning are performed on the upper surface of the insulating layer 13, the inner wall surface of the via hole 13x, the surface of the filler 173 exposed from the inner wall surface of the via hole 13x, the inner wall surface of the recess 13y, and the upper surface of the wiring layer 12 exposed within the via hole 13x. In FIG. 9(d), the surface on which cleaning and conditioning have been performed is shown by a broken line for convenience.

[0105] Also, by the second alkali treatment, cleaning and conditioning are performed on the lower surface of the insulating layer 23, the inner wall surface of the via hole 23x, the surface of the filler 173 exposed from the inner wall surface of the via hole 23x, the inner wall surface of the recess formed on the inner wall surface of the via hole 23x, and the lower surface of the wiring layer 22 exposed in the via hole 23x.

[0106] Next, in the process shown in Fig. 10(a), a seed layer 141 is continuously formed on the upper surface of the insulating layer 13, the inner wall surface of the via hole 13x, and the upper surface of the wiring layer 12 exposed in the via hole 13x. Also, a seed layer is continuously formed on the lower surface of the insulating layer 23, the inner wall surface of the via hole 23x, and the lower surface of the wiring layer 22 exposed in the via hole 23x. The material of the seed layer 141 is, for example, copper. The thickness of the seed layer 141 is, for example, about 0.3 to 1 μm. The seed layer 141 can be formed, for example, by electroless plating. The material, thickness, and manufacturing method of the seed layer formed on the lower surface of the wiring layer 22 are the same as those of the seed layer 141.

[0107] The seed layer 141 is also formed on the surface of the filler 173 exposed from the inner wall surface of the via hole 13x and the inner wall surface of the recess 13y. That is, the seed layer 141 is formed with a substantially uniform thickness on the upper surface of the insulating layer 13, the inner wall surface of the via hole 13x, the surface of the filler 173 exposed from the inner wall surface of the via hole 13x, the inner wall surface of the recess 13y, and the upper surface of the wiring layer 12 exposed in the via hole 13x. The same applies to the seed layer formed on the lower surface of the wiring layer 22.

[0108] Next, in the process shown in FIG. 10(b), wiring layers 14 and 24 are formed. Specifically, for example, a resist layer having an opening conforming to the shape of the wiring layer 14 is formed on the seed layer 141. Then, by the electrolytic plating method of supplying power from the seed layer 141, copper or the like is deposited on the seed layer 141 exposed in the opening of the resist layer, and the electrolytic plating layer 142 is selectively formed. Next, after removing the resist layer, etching is performed using the electrolytic plating layer 142 as a mask, and the seed layer 141 exposed from the electrolytic plating layer 142 is removed, thereby forming the wiring layer 14 in which the electrolytic plating layer 142 is laminated on the seed layer 141. The wiring layer 24 can also be formed by the same method.

[0109] After the process shown in FIG. 10(b), an insulating layer 15 is formed so as to cover the wiring layer 14 on the upper surface of the insulating layer 13 by the same formation method as that of the insulating layer 13. The material and thickness of the insulating layer 15 are, for example, the same as those of the insulating layer 13. Also, an insulating layer 25 is formed so as to cover the wiring layer 24 on the lower surface of the insulating layer 23 by the same formation method as that of the insulating layer 13. The material and thickness of the insulating layer 25 are, for example, the same as those of the insulating layer 13. Then, the same processes as those in FIGS. 9(a) to 10(b) are executed to form a wiring layer 16 in which an electrolytic plating layer is formed on a seed layer on one side of the insulating layer 15. Also, a wiring layer 26 in which an electrolytic plating layer is formed on a seed layer is formed on the other side of the insulating layer 25.

[0110] Next, by executing the same processes as those in FIGS. 2(c) to 5(c) of the first embodiment, the wiring substrate 1A is completed.

[0111] Thus, the manufacturing method of the wiring substrate according to the present invention may be applied to the internal wirings (wiring layers 14, 16, 24, and 26) of the wiring substrate 1A. Thereby, the same effects as those of the first embodiment are achieved.

[0112] 〈Application Example of the First Embodiment〉 In the application example of the first embodiment, an example of a semiconductor package in which a semiconductor chip is mounted on the wiring substrate according to the first embodiment is shown. Note that, in the application example of the first embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0113] FIG. 11 is a cross-sectional view illustrating a semiconductor package according to an application example of the first embodiment. Referring to FIG. 11, the semiconductor package 100 includes a wiring substrate 1 shown in FIG. 1, a semiconductor chip 110, electrode pads 120, bumps 130, underfill resin 140, and bumps 150.

[0114] The semiconductor chip 110 is, for example, formed by forming a semiconductor integrated circuit (not shown) or the like on a thinned semiconductor substrate (not shown) made of silicon or the like. An electrode pad 120 electrically connected to the semiconductor integrated circuit (not shown) is formed on the semiconductor substrate (not shown).

[0115] The bump 130 is formed on the electrode pad 120 of the semiconductor chip 110 and is electrically connected to the wiring layer 18 of the wiring substrate 1. The underfill resin 140 is filled between the semiconductor chip 110 and the upper surface of the wiring substrate 1. The bump 150 is formed on the lower surface of the wiring layer 26 exposed at the bottom of the opening 27x of the solder resist layer 27. The bump 150 is connected to, for example, a motherboard or the like. The bumps 130 and 150 are, for example, solder bumps. As the material of the solder bumps, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu, or the like can be used.

[0116] In this way, a semiconductor package 100 in which the semiconductor chip 110 is mounted on the wiring substrate 1 according to the first embodiment can be realized. As described above, in the wiring substrate 1, no void is formed in the opening 17x, and no crack starting from the void occurs. Therefore, there is no possibility of causing a conduction failure between the wiring layer 18 and the electrode pad 120, and the connection reliability between the wiring substrate 1 and the semiconductor chip 110 can be improved.

[0117] Note that in the semiconductor package 100, a wiring substrate 1A may be used instead of the wiring substrate 1.

[0118] Although the preferred embodiments have been described in detail above, the invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope described in the claims.

[0119] For example, in the above embodiment, an example in which the present invention is applied to a wiring board including a core layer manufactured by a build-up method has been shown. However, the present invention may also be applied to a coreless wiring board manufactured by a build-up method. Further, the present invention is not limited thereto and can be applied to various wiring boards.

Explanation of Reference Numerals

[0120] 1, 1A Wiring board 10 Core layer 10a One surface 10b The other surface 10x Through hole 11 Through wiring 12, 14, 16, 18, 22, 24, 26 Wiring layer 13, 15, 23, 25 Insulating layer 13x, 15x, 23x, 25x Via hole 13y, 17y Recess 17, 27 Solder resist layer 17x, 27x Opening 100 Semiconductor package 110 Semiconductor chip 120 Electrode pad 130, 150 Bump 140 Underfill resin 141, 181 Seed layer 142, 182 Electrolytic plating layer 171, 173 Filler

Claims

1. An insulating layer containing a filler that covers the first wiring layer, An opening formed in the insulating layer that exposes the upper surface of the first wiring layer, A second wiring layer that fills the opening and is electrically connected to the first wiring layer, and extends from within the opening to the upper surface of the insulating layer, The second wiring layer includes a via wiring that fills the opening and is electrically connected to the first wiring layer, and a wiring pattern and / or pad formed on the via wiring, A recess, which is a mark where the filler has been removed, is formed on the inner wall surface of the opening, The second wiring layer has a structure in which an electrolytic plating layer is laminated on a seed layer, A catalyst is adsorbed on at least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed within the opening, The seed layer is continuously formed on the catalyst along at least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed within the opening, The electrolytic plating layer is continuously formed on the seed layer along at least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed within the opening, and fills the opening including the inside of the recess. A wiring substrate.

2. The wiring substrate according to claim 1, wherein the seed layer is formed on the catalyst with a substantially uniform thickness along at least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed within the opening.

3. The wiring substrate according to claim 1 or 2, wherein the content of the filler is 30 to 80% by weight.

4. The insulating layer is the outermost insulating layer, The wiring substrate according to any one of claims 1 to 3, wherein the second wiring layer includes a pad formed on the via wiring.

5. The wiring substrate according to claim 4, wherein the pad is a pad for mounting an electronic component for electrically connecting to an electronic component.

6. The insulating layer is an interlayer insulating layer, The wiring substrate according to any one of claims 1 to 3, wherein the second wiring layer includes a wiring pattern formed on the via wiring.

7. The insulating layer is made of a photosensitive resin containing the filler, The wiring board according to claim 4 or 5, wherein the filler is silicon dioxide or barium sulfate.

8. The insulating layer is made of a non-photosensitive resin containing the filler, The wiring board according to claim 6, wherein the filler is silicon dioxide.

Images