Semiconductor device

Abstract

To reduce the size of a semiconductor device.SOLUTION: A semiconductor device 1 includes die pads 5 and 6, semiconductor chips 2 and 3, and an insulator part 28 for sealing these. The semiconductor chip 2 includes a source electrode 2S formed on a front surface side, and a drain electrode 2D formed on a back surface side. The drain electrode 2D is mounted on the die pad 5 so as to face the die pad 5. The semiconductor chip 3 includes a source electrode 3S formed on a front surface side and a drain electrode 3D formed on a back surface side. The source electrode 3S is mounted on the die pad 6 so as to face the die pad 6. In the insulator part 28, a wire 26DS for electrically connecting the source electrode 2S of the semiconductor chip 2 and the drain electrode 3D of the semiconductor chip 3 is formed.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and can be suitably used, for example, in a semiconductor device in which a semiconductor chip including a field effect transistor for a high-side switch and a semiconductor chip including a field effect transistor for a low-side switch are encapsulated together.

Background Art

[0002] As a power supply circuit, for example, a DC-DC converter has a configuration in which a power MOSFET for a high-side switch and a power MOSFET for a low-side switch are connected in series. For this reason, a semiconductor device in which a semiconductor chip on which a power MOSFET for a high-side switch is formed and a semiconductor chip on which a power MOSFET for a low-side switch is formed are packaged together is used.

[0003] Japanese Unexamined Patent Application Publication No. 2010-50286 (Patent Document 1) describes a technique related to a semiconductor device in which a three-terminal semiconductor chip on which a vertical MOS transistor is formed is resin-sealed.

[0004] Japanese Unexamined Patent Application Publication No. 2013-219324 (Patent Document 2) describes a technique related to a semiconductor package including a semiconductor chip in which a source electrode and a gate electrode are formed on the front surface side and a drain electrode is formed on the back surface side.

[0005] Japanese Unexamined Patent Application Publication No. 2019-102765 (Patent Document 3) describes a technique related to a semiconductor package in which a first semiconductor chip including a high-side switching element and a second semiconductor chip including a low-side switching element are mold-sealed.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

[0007] In a semiconductor device in which a semiconductor chip on which a power MOSFET for a high-side switch is formed and a semiconductor chip on which a power MOSFET for a low-side switch is formed are packaged together, the power MOSFET for the high-side switch and the power MOSFET for the low-side switch may be connected in series inside the semiconductor device. Even in such a semiconductor device, it is desirable to achieve miniaturization as much as possible. [Means for Solving the Problems]

[0008] According to one embodiment, a semiconductor device includes a first chip mounting portion, a second chip mounting portion, a first semiconductor chip mounted on the first chip mounting portion, a second semiconductor chip mounted on the second chip mounting portion, and an insulator portion that seals these. The first semiconductor chip has a source electrode formed on the main surface side and a drain electrode formed on the back surface side opposite to the main surface, and the drain electrode is mounted on the first chip mounting portion in a direction facing the first chip mounting portion. The second semiconductor chip has a source electrode formed on the main surface side and a drain electrode formed on the back surface side opposite to the main surface side, and the source electrode is mounted on the second chip mounting portion in a direction facing the second chip mounting portion. And a first wiring for electrically connecting the source electrode of the first semiconductor chip and the drain electrode of the second semiconductor chip is formed in the insulator portion. [Advantages of the Invention]

[0009] According to one embodiment, miniaturization of the semiconductor device can be achieved. [Brief Description of the Drawings]

[0010]

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Mode for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. Further, in the following embodiments, explanations of the same or similar parts are not repeated as a rule unless particularly necessary.

[0012] Also, in the present application, although the field effect transistor is described as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a non-oxide film is not excluded as the gate insulating film.

[0013] (Embodiment 1) <Regarding the circuit configuration> FIG. 1 is a circuit diagram showing the circuit configuration of a semiconductor device (semiconductor package) 1 according to an embodiment of the present invention. The semiconductor device 1 can be used, for example, in a non-insulated type DC-DC converter or an inverter. In FIG. 1, the portion surrounded by the dashed-dotted line with reference numeral 1 indicates the circuit formed in the semiconductor device 1. Among them, the portion surrounded by the dotted line with reference numeral 2 is the portion formed in the semiconductor chip 2, the portion surrounded by the dotted line with reference numeral 3 is the portion formed in the semiconductor chip 3, and the portion surrounded by the dotted line with reference numeral 4 is the portion formed in the semiconductor chip 4.

[0014] As shown in FIG. 1, the semiconductor device 1 has semiconductor chips 2, 3, and 4, and these three semiconductor chips 2, 3, and 4 are sealed in one package to form the semiconductor device 1. A power MOSFET 12 is formed in the semiconductor chip 2, a power MOSFET 13 is formed in the semiconductor chip 3, and a control circuit 14 is formed in the semiconductor chip 4. As the power MOSFET, for example, a trench gate type MOSFET or the like can be used.

[0015] The semiconductor chip 2 has a source electrode 2S electrically connected to the source (S) of the power MOSFET 12 formed in the semiconductor chip 2, a drain electrode 2D electrically connected to the drain (D) of the power MOSFET 12 formed in the semiconductor chip 2, and a gate electrode 2G electrically connected to the gate (G) of the power MOSFET 12 formed in the semiconductor chip 2. Further, the semiconductor chip 3 has a source electrode 3S electrically connected to the source (S) of the power MOSFET 13 formed in the semiconductor chip 3, a drain electrode 3D electrically connected to the drain (D) of the power MOSFET 13 formed in the semiconductor chip 3, and a gate electrode 3G electrically connected to the gate (G) of the power MOSFET 13 formed in the semiconductor chip 3. Further, the semiconductor chip 4 has a plurality of electrodes 4C electrically connected to the control circuit 14 formed in the semiconductor chip 4.

[0016] The power MOSFET 12 is a field effect transistor for a high-side switch (high potential side switch), and the power MOSFET 13 is a field effect transistor for a low-side switch (low potential side switch).

[0017] The power MOSFET 12 and the power MOSFET 13 are connected in series between the terminal T1 and the terminal T2. The drain (D) of the power MOSFET 12 is connected to the terminal T1, the source (S) of the power MOSFET 12 is connected to the drain (D) of the power MOSFET 13, and the source (S) of the power MOSFET 13 is connected to the terminal T2. Specifically, the drain electrode 2D of the semiconductor chip 2 is electrically connected to the terminal T1, the source electrode 2S of the semiconductor chip 2 is electrically connected to the drain electrode 3D of the semiconductor chip 3, and the source electrode 3S of the semiconductor chip 3 is electrically connected to the terminal T2. The terminal T3 is electrically connected to both the source electrode 2S of the semiconductor chip 2 and the drain electrode 3D of the semiconductor chip 3.

[0018] Terminals T1, T2, and T3 are external terminals (terminals for external connection) of the semiconductor device 1. A power supply potential (VIN) is supplied to terminal T1 from an external power supply or the like outside the semiconductor device 1. A reference potential lower than the power supply potential, for example, a ground potential (GND), is supplied to terminal T2. Terminal T3 is an output terminal. Terminal T3 is connected to a load provided outside the semiconductor device 1, for example.

[0019] The gate electrode 2G of the semiconductor chip 2 is electrically connected to the electrode 4C of the semiconductor chip 4, and the gate electrode 3G of the semiconductor chip 3 is electrically connected to another electrode 4C of the semiconductor chip 4. The control circuit 14 formed in the semiconductor chip 4 includes a circuit (drive circuit) that controls the operations of the power MOSFETs 12 and 13. The control circuit 14 can control the operations of the power MOSFETs 12 and 13 by controlling the gate voltage supplied from the electrode 4C of the semiconductor chip 4 to the gate electrodes 2G and 3G of the semiconductor chips 2 and 3. Still another electrode 4C of the semiconductor chip 4 is electrically connected to the terminal T4. Terminal T4 is also an external terminal of the semiconductor device 1, and the control circuit 14 can be connected to a circuit outside the semiconductor device 1 through terminal T4.

[0020] <Regarding the structure of the semiconductor device> FIG. 2 is a top view of the semiconductor device 1 of the present embodiment, and FIG. 3 is a bottom view (rear view) of the semiconductor device 1 of the present embodiment. FIGS. 4 to 7 are perspective plan views of the semiconductor device 1 of the present embodiment, and FIGS. 8 to 10 are cross-sectional views of the semiconductor device 1 of the present embodiment. FIG. 11 is a top view of the semiconductor chips 2 and 3 used in the semiconductor device 1 of the present embodiment, and FIG. 12 is a bottom view (rear view) of the semiconductor chips 2 and 3 used in the semiconductor device 1 of the present embodiment.

[0021] In FIG. 2, a state where the electronic component 31 is mounted on the semiconductor device 1 is shown. Further, FIG. 4 shows a plan perspective view of the semiconductor device 1 when the components made of an insulator (insulating layer 27 and sealing portion 9) are seen through. Further, FIG. 5 shows a plan perspective view of the semiconductor device 1 when the wirings 30 (wirings 30DS, 30C) are further seen through in FIG. 4. Further, FIG. 6 shows a plan perspective view of the semiconductor device 1 when the wirings 26 (wirings 26DS, 26GH, 26GL, 26C1, 26C2, 26C3) are further seen through in FIG. 5. In FIG. 6, what is actually visible is the drain electrode 3D of the semiconductor chip 3, but for ease of understanding, the planar positions of the gate electrode 3G and the source electrode 3S in the semiconductor chip 3 are indicated by dotted lines. Further, FIG. 7 shows a plan perspective view of the semiconductor device 1 when the semiconductor chips 2, 3, 4 and the plug portion 22 are further seen through in FIG. 6. Further, FIG. 8 is a cross-sectional view of the semiconductor device 1 at the position of the line A1 - A1 shown in FIG. 4, FIG. 9 is a cross-sectional view of the semiconductor device 1 at the position of the line A2 - A2 shown in FIG. 4, and FIG. 10 is a cross-sectional view of the semiconductor device 1 at the position of the line A3 - A3 shown in FIG. 4.

[0022] In the present embodiment, as described above, the semiconductor chip 2 on which the power MOSFET 12 for the high-side switch is formed, the semiconductor chip 3 on which the power MOSFET 13 for the low-side switch is formed, and the semiconductor chip 4 on which the control circuit 14 is formed are packaged together as one semiconductor device 1. Here, as the semiconductor device 1, for example, a case where a surface mount type semiconductor package of the QFN (Quad Flat Non-leaded package) type is applied will be described as an example. Hereinafter, with reference to FIGS. 2 to 12, the specific configuration of the semiconductor device 1 of the present embodiment will be described.

[0023] The semiconductor device 1 of the present embodiment has die pads (chip mounting portions) 5, 6, 7, semiconductor chips 2, 3, 4 mounted on the respective die pads 5, 6, 7, a plurality of leads 8, and a sealing portion (sealing resin portion) 9 for sealing these.

[0024] The sealing portion 9 is made of an insulating resin material such as a thermosetting resin. The sealing portion 9 has an upper surface 9a which is one of the main surfaces, a lower surface 9b which is the main surface on the opposite side of the upper surface 9a, and four side surfaces connecting the upper surface 9a and the lower surface 9b.

[0025] The plurality of leads 8 of the semiconductor device 1 are arranged side by side on the outer periphery of the semiconductor device 1, and the lower surfaces of the respective leads 8 are exposed on the lower surface 9b of the sealing portion 9. Also, on the lower surface 9b of the sealing portion 9, the lower surfaces of the die pads 5, 6, and 7 are also exposed. The die pads 5, 6, and 7 are spaced apart from each other, and the sealing portion 9 is filled between the die pads 5, 6, and 7.

[0026] Each of the semiconductor chips 2, 3, and 4 has a front surface which is one of the main surfaces and a back surface which is the main surface on the opposite side. In FIG. 11, the front surface sides of the semiconductor chips 2 and 3 are shown, and in FIG. 12, the back surface sides of the semiconductor chips 2 and 3 are shown.

[0027] In the semiconductor chip 2, the source electrode 2S and the gate electrode 2G are formed on the front surface side of the semiconductor chip 2, and the drain electrode 2D is formed on the back surface side of the semiconductor chip 2. That is, in the semiconductor chip 2, the source electrode 2S and the gate electrode 2G and the drain electrode 2D are formed on surfaces on opposite sides of each other. Similarly, in the semiconductor chip 3, the source electrode 3S and the gate electrode 3G are formed on the front surface side of the semiconductor chip 3, and the drain electrode 3D is formed on the back surface side of the semiconductor chip 3. That is, in the semiconductor chip 3, the source electrode 3S and the gate electrode 3G and the drain electrode 3D are formed on surfaces on opposite sides of each other.

[0028] In the semiconductor chip 4, a plurality of electrodes 4C are formed on the front surface side of the semiconductor chip 4. The electrode 4C is a connecting electrode formed on the pad electrode of the semiconductor chip 4 and is, for example, a columnar electrode.

[0029] In the semiconductor device 1 of this embodiment, the semiconductor chip 2 and the semiconductor chip 3 are mounted with their top and bottom (front and back) reversed. The semiconductor chip 2 has its front side facing upward and its back side facing downward (toward the die pad 5). On the other hand, the semiconductor chip 3 has its back side facing upward and its front side facing downward (toward the die pad 6).

[0030] That is, in the semiconductor chip 2, the source electrode 2S and the gate electrode 2G face upward, and the drain electrode 2D faces the upper surface of the die pad 5. The semiconductor chip 2 is joined to the upper surface of the die pad 5 by a conductive bonding material 10D. As a result, the drain electrode 2D of the semiconductor chip 2 and the die pad 5 are electrically connected via the conductive bonding material 10D. On the other hand, in the semiconductor chip 3, the drain electrode 3D faces upward, and the source electrode 3S faces the upper surface of the die pad 6. The semiconductor chip 3 is joined to the upper surface of the die pad 6 via a conductive bonding material 10S. As a result, the source electrode 3S of the semiconductor chip 3 and the die pad 6 are electrically connected via the conductive bonding material 10S. The gate electrode 3G of the semiconductor chip 3 is electrically connected to the gate connection conductor portion 6G. The gate electrode 3G of the semiconductor chip 3 is electrically connected to the gate connection conductor portion 6G via a conductive bonding material 10G. It is preferable that the gate connection conductor portion 6G is not exposed on the lower surface 9b of the sealing portion 9. For example, by half-etching the lower surface side of the gate connection conductor portion 6G or the like to make the gate connection conductor portion 6G thinner than the die pads 5, 6, 7 and the leads 8, the lower surfaces of the die pads 5, 6, 7 and the leads 8 are exposed on the lower surface 9b of the sealing portion 9, but the gate connection conductor portion 6G can be made not to be exposed.

[0031] In the semiconductor chip 4, the electrode 4C faces upward, and the back surface of the semiconductor chip 4 faces the upper surface of the die pad 7. The semiconductor chip 4 is joined to the upper surface of the die pad 7 by an insulating or conductive bonding material 10C.

[0032] The die pads 5, 6, 7, the gate connection conductor portion 6G, and the plurality of leads 8 are made of a conductor, preferably a metal material such as copper (Cu) or a copper alloy (for example, a copper alloy containing nickel), and a plating film (for example, a nickel plating film) can be formed on the surface thereof as necessary. Further, if the die pads 5, 6, 7, the gate connection conductor portion 6G, and the plurality of leads 8 are composed of a single lead frame, it is not necessary to combine a plurality of members, and it becomes easy to manufacture the semiconductor device 1 using the lead frame.

[0033] The source electrode 2S and the gate electrode 2G of the semiconductor chip 2 and the plurality of electrodes 4C of the semiconductor chip 4 are exposed on the upper surface of the sealing portion 9. For example, on the source electrode 2S of the semiconductor chip 2, an opening is provided in the sealing portion 9 so as to expose the source electrode 2S. Further, on the gate electrode 2G of the semiconductor chip 2, an opening is provided in the sealing portion 9 so as to expose the gate electrode 2G.

[0034] On the upper surface of the sealing portion 9, a wiring (wiring layer, patterned conductor layer) 26 is formed. The wiring 26 includes a wiring 26DS, a wiring 26GH, a wiring 26GL, a wiring 26C1, a wiring 26C2, and a wiring 26C3. Each of the wirings 26DS, 26GH, 26GL, 26C1, 26C2, 26C3 included in the wiring 26 is formed in the same layer. Further, a conductive plug portion 22 is formed on each of the die pads 5, 6, the gate connection conductor portion 6G, and the lead 8. The plug portion 22 is made of a metal material such as copper (Cu) and is formed in a hole provided in the sealing portion 9. The plug portion 22 is provided to electrically connect the wiring 26 on the plug portion 22 and the conductor (die pad 5, die pad 6, gate connection conductor portion 6G, or lead 8) under the plug portion 22.

[0035] The wiring 26DS is a wiring for electrically connecting the source electrode 2S of the semiconductor chip 2 and the drain electrode 3D of the semiconductor chip 3. The wiring 26DS integrally has a portion located on the source electrode 2S of the semiconductor chip 2 and electrically connected to the source electrode 2S, a portion located on the drain electrode 3D of the semiconductor chip 3 and electrically connected to the drain electrode 3D, and a portion connecting them.

[0036] The wiring 26GL is a wiring for electrically connecting the gate electrode 3G of the semiconductor chip 3 and the electrode 4C of the semiconductor chip 4. One end of the wiring 26GL is located on the plug portion 22 provided on the gate connection conductor portion 6G and electrically connected to the plug portion 22, and the other end of the wiring 26GL is located on the electrode 4C of the semiconductor chip 4 and electrically connected to the electrode 4C. Thus, the gate electrode 3G of the semiconductor chip 3 and the electrode 4C of the semiconductor chip 4 are electrically connected through the conductive bonding material 10G, the gate connection conductor portion 6G, the plug portion 22 (the plug portion 22 formed on the gate connection conductor portion 6G), and the wiring 26GL.

[0037] The wiring 26GH is a wiring for electrically connecting the gate electrode 2G of the semiconductor chip 2 and the electrode 4C of the semiconductor chip 4. One end of the wiring 26GH is located on the gate electrode 2G of the semiconductor chip 2 and electrically connected to the gate electrode 2G, and the other end of the wiring 26GH is located on the electrode 4C of the semiconductor chip 4 and electrically connected to the electrode 4C.

[0038] The wiring 26C1 is a wiring for electrically connecting the lead 8 and the electrode 4C of the semiconductor chip 4. One end of the wiring 26C1 is located on the plug portion 22 provided on the lead 8 and electrically connected to the plug portion 22, and the other end of the wiring 26C1 is located on the electrode 4C of the semiconductor chip 4 and electrically connected to the electrode 4C.

[0039] The wiring 26C2 is a wiring for electrically connecting the drain electrode 2D of the semiconductor chip 2 and the electrode 4C of the semiconductor chip 4. One end of the wiring 26C2 is located on the plug portion 22 provided on the die pad 5 and is electrically connected to the plug portion 22, and the other end of the wiring 26C2 is located on the electrode 4C of the semiconductor chip 4 and is electrically connected to the electrode 4C. Thereby, the drain electrode 2D of the semiconductor chip 2 and the electrode 4C of the semiconductor chip 4 are electrically connected through the conductive bonding material 10D, the die pad 5, the plug portion 22 (the plug portion 22 formed on the die pad 5), and the wiring 26C2.

[0040] The wiring 26C3 is a wiring for electrically connecting the source electrode 3S of the semiconductor chip 3 and the electrode 4C of the semiconductor chip 4. One end of the wiring 26C3 is located on the plug portion 22 provided on the die pad 6 and is electrically connected to the plug portion 22, and the other end of the wiring 26C3 is located on the electrode 4C of the semiconductor chip 4 and is electrically connected to the electrode 4C. Thereby, the source electrode 3S of the semiconductor chip 3 and the electrode 4C of the semiconductor chip 4 are electrically connected through the conductive bonding material 10S, the die pad 6, the plug portion 22 (the plug portion 22 formed on the die pad 6), and the wiring 26C3.

[0041] An insulating layer 27 is formed on the upper surface of the sealing portion 9 so as to cover the wiring 26. The sealing portion 9 and the insulating layer 27 constitute an insulating body portion (sealing insulating body portion) 28 that seals the semiconductor chips 2, 3, 4, the die pads 5, 6, 7, the gate connection conductor portion 6G, and the plurality of leads 8. The die pads 5, 6, 7, the gate connection conductor portion 6G, and the plurality of leads 8 only need to be at least partially sealed by the insulating body portion 28, but it is preferable that the semiconductor chips 2, 3, 4 are not exposed from the insulating body portion 28.

[0042] Also, the number of layers of the wiring layer and the insulating layer formed on the sealing portion 9 can be increased. In that case, the increased insulating layer also constitutes a part of the sealing insulating body portion 28.

[0043] On the insulating layer 27, a wiring (wiring layer, patterned conductor layer) 30 is formed. The wiring 30 is electrically connected to the wiring 26 through an opening (hole) 29 provided in the insulating layer 27.

[0044] The wiring 30 includes a wiring 30DS electrically connected to the wiring 26DS and a wiring 30C electrically connected to the wiring 26C1. It is preferable to provide a plurality of openings 29 for connecting the wiring 26DS and the wiring 30DS. The wiring 30DS is electrically connected to both the source electrode 2S of the semiconductor chip 2 and the drain electrode 3D of the semiconductor chip 3 through the wiring 26DS. The wiring 30DS corresponds to the terminal T3 in FIG. 1 above and can function as an output terminal. The wiring 30C is electrically connected to the lead 8 through the wiring 26C1 and the plug portion 22 (the plug portion 22 formed on the lead 8). For example, a ground potential is supplied to the wiring 30C through the lead 8, the plug portion 22, and the wiring 26C1.

[0045] The wirings 26, 30 and the plug portion 22 constitute the wiring structure of the semiconductor device 1. Each of the gate electrode 2G of the semiconductor chip 2, the gate electrode 3G of the semiconductor chip 3, and the plurality of leads 8 is electrically connected to the electrode 4C of the semiconductor chip 4 through the wiring structure of the semiconductor device 1. Also, the source electrode 2S of the semiconductor chip 2 and the drain electrode 3D of the semiconductor chip 3 are electrically connected through the wiring structure of the semiconductor device 1.

[0046] When mounting the semiconductor device 1 on a substrate, an electronic component 31 (see FIG. 2) can be mounted on the semiconductor device 1. For example, when mounting a coil as the electronic component 31, one electrode of the electronic component 31 is electrically connected to the wiring 30DS, and the other electrode is electrically connected to the wiring 30C.

[0047] Also, when the electronic component 31 is not mounted on the semiconductor device 1, the formation of the wiring 30C can be omitted. Also, the formation of the wiring 30 itself can be omitted, and in that case, the wiring 26DS of the portion exposed from the opening of the insulating layer 27 can be used as the output terminal (terminal T3) of the semiconductor device 1.

[0048] <Regarding the manufacturing process of the semiconductor device> Next, the manufacturing process of the semiconductor device 1 of the present embodiment will be described. FIGS. 13 to 29 are cross-sectional views showing the manufacturing process of the semiconductor device 1 of the present embodiment. Among FIGS. 13 to 29, FIGS. 13, 15, 18, 20, 22, 24, 26, and 28 are cross-sectional views of the semiconductor device 1 corresponding to the line A1-A1 in FIG. 4 in each manufacturing process, and FIGS. 14, 16, 17, 19, 21, 23, 25, 27, and 29 are cross-sectional views of the semiconductor device 1 corresponding to the line A2-A2 in FIG. 4 in each manufacturing process. Note that only one package is shown in the drawing, but a plurality of packages can be manufactured simultaneously in a state where a plurality of packages are connected in the plane direction. This is the same in other embodiments.

[0049] First, as shown in FIGS. 13 and 14, a lead frame is prepared. The lead frame has a frame body (not shown), die pads 5, 6, 7, a gate connection conductor part 6G, and a plurality of leads 8 connected to the frame body. The lead frame is used in a state of being adhered to a back tape (not shown) such as a polyimide film.

[0050] Next, as shown in FIGS. 15 and 16, a die bonding process is performed to mount semiconductor chips 2, 3, and 4 on die pads 5, 6, and 7. In the die bonding process, the semiconductor chip 2 and the semiconductor chip 3 have opposite vertical (front and back) orientations when mounted on the die pad. That is, for the semiconductor chip 2, the source electrode 2S and the gate electrode 2G face upward, and the drain electrode 2D faces the upper surface of the die pad 5. The semiconductor chip 2 is mounted on the upper surface of the die pad 5 via a conductive bonding material 10D. For the semiconductor chip 3, the drain electrode 3D faces upward, the source electrode 3S faces the upper surface of the die pad 6, and the gate electrode 3G of the semiconductor chip 3 faces the upper surface of the gate connection conductor portion 6G. The semiconductor chip 3 is mounted on the upper surface of the die pad 6 via a conductive bonding material 10S and on the upper surface of the gate connection conductor portion 6G via a conductive bonding material 10G. The semiconductor chip 4 is mounted on the upper surface of the die pad 7 with the back surface of the semiconductor chip 4 facing the upper surface of the die pad 7 via an insulating or conductive bonding material 10C. Thereafter, the bonding materials 10D, 10S, 10G, and 10C are cured. As a result, the semiconductor chip 2 is fixed to the die pad 5, and the drain electrode 2D of the semiconductor chip 2 and the die pad 5 are electrically connected via the conductive bonding material 10D. Also, the semiconductor chip 3 is fixed to the die pad 6, the source electrode 3S of the semiconductor chip 3 and the die pad 6 are electrically connected via the conductive bonding material 10S, and the gate electrode 3G of the semiconductor chip 3 and the gate connection conductor portion 6G are electrically connected via the conductive bonding material 10G. Also, the semiconductor chip 4 is fixed to the die pad 7. As the conductive bonding material, a conductive paste-type bonding material (for example, silver paste) or a solder material can be used. When bonding using a solder material, an electrode on the semiconductor chip side to be soldered can also have a laminated structure including a nickel layer.

[0051] Next, as shown in FIGS. 15 and 16, a sealing portion (sealing resin portion) 9 is formed to seal the semiconductor chips 2, 3, 4, the die pads 5, 6, 7, the gate connection conductor portion 6G, and the plurality of leads 8. At this stage, the semiconductor chips 2, 3, 4 and their respective electrodes 2S, 2G, 3D, 4C are covered by the sealing portion 9 and do not protrude from the sealing portion 9. Also, since the lower surface side of the lead frame is fixed to the back tape, the lower surfaces of the die pads 5, 6, 7 and the leads 8 are flush with the lower surface 9b of the sealing portion 9. Further, the gate connection conductor portion 6G has a reduced thickness compared to the leads 8 by means of half-etching or the like from the lower surface side. For this reason, since the sealing portion 9 is also formed on the lower surface of the gate connection conductor portion 6G, the gate connection conductor portion 6G is not exposed on the lower surface 9b of the sealing portion 9.

[0052] Next, as shown in FIG. 17, for example, by laser processing or the like, a hole portion 21 is formed in the sealing portion 9. The hole portion 21 is formed downward from the upper surface side of the sealing portion 9. The hole portions 21 are formed on the leads 8, on the gate connection conductor portion 6G, on the die pad 5 at a position that does not overlap the semiconductor chip 2 in plan view, and on the die pad 6 at a position that does not overlap the semiconductor chip 3 in plan view, respectively. At the bottom of the hole portion 21, the lead 8, the gate connection conductor portion 6G, the die pad 5, and the die pad 6 are exposed.

[0053] Then, a conductive plug portion 22 is formed in the hole portion 21 of the sealing portion 9 using an electrolytic plating method or the like. The plug portion 22 is made of a metal material such as copper (Cu) and is formed so as to fill the hole portion 21. The plug portion 22 formed on the lead 8 is electrically connected to the lead 8. Also, the plug portion 22 formed on the gate connection conductor portion 6G is electrically connected to the gate connection conductor portion 6G. Further, the plug portion 22 formed on the die pad 5 is electrically connected to the die pad 5. Also, the plug portion 22 formed on the die pad 6 is electrically connected to the die pad 6.

[0054] Next, as shown in FIGS. 18 and 19, the upper surface 9a of the sealing portion 9 is polished to reduce the thickness of the sealing portion 9. At least by polishing to such an extent that the upper surfaces of the electrode 4C and the plug portion 22 are reached, the upper surfaces of the electrode 4C, the upper surface of the plug portion 22 are exposed from the upper surface 9a of the sealing portion 9.

[0055] Next, as shown in FIGS. 20 and 21, openings 23 are formed on the source electrode 2S, the gate electrode 2G of the semiconductor chip 2, and the drain electrode 3D of the semiconductor chip 3 of the sealing portion 9 using laser processing or the like. At the bottom of the opening 23, the source electrode 2S of the semiconductor chip 2, the gate electrode 2G of the semiconductor chip 2, and the drain electrode 3D of the semiconductor chip 3 are exposed. When the opening 23 is formed by laser processing, in order to prevent damage to the electrodes 2S, 2G, 3D by the laser, a copper film having a thickness of about 4 to 10 μm may be formed in advance on the electrodes 2S, 2G, 3D. At this stage, the back tape is peeled off, whereby the lower surface 9b of the sealing portion 9 and the lower surfaces of the die pads 5, 6, 7 and the leads 8 are exposed.

[0056] Next, as shown in FIGS. 22 and 23, a metal film 24a is formed using electroless plating. The metal film 24a is continuously formed on the upper surface 9a of the sealing portion 9, on the source electrode 2S, the gate electrode 2G, the drain electrode 3D exposed from the opening 23, on the upper surface of the electrode 4C exposed from the upper surface 9a of the sealing portion 9, and on the upper surface of the plug portion 22 exposed from the upper surface 9a of the sealing portion 9.

[0057] Next, as shown in FIGS. 24 and 25, a resist pattern 25 is formed on the metal film 24a. Then, a metal film 24b is formed on the exposed portion of the metal film 24a that is not covered by the resist pattern 25 using an electrolytic plating method. After that, as shown in FIGS. 26 and 27, after removing the resist pattern 25, the exposed portion of the metal film 24a that is not covered by the metal film 24b is removed by etching or the like. Thereby, a wiring 26 composed of the metal film 24a and the metal film 24b on the metal film 24a is formed. As described above, the wiring 26 includes a wiring 26DS, a wiring 26GH, a wiring 26GL, a wiring 26C1, a wiring 26C2, and a wiring 26C3.

[0058] Next, as shown in FIGS. 28 and 29, an insulating layer 27 is formed on the upper surface 9a of the sealing portion 9 so as to cover the wiring 26. The insulating layer 27 is made of an insulating resin material such as a thermosetting resin. In FIGS. 28 and 29, for simplicity, the metal film 24a and the metal film 24b constituting the wiring 26 are shown integrally without being separated (the same applies to FIGS. 8 and 9 above).

[0059] Next, an opening 29 is formed in the insulating layer 27. At the bottom of the opening 29, a part of the wiring 26 is exposed.

[0060] Next, a wiring 30 is formed on the insulating layer 27. Since the method of forming the wiring 30 is basically the same as that of forming the wiring 26, the repeated description is omitted here. The wiring 30 is electrically connected to the wiring 26 exposed from the opening 29. As described above, the wiring 30 includes a wiring 30DS and a wiring 30C. After that, when an electroless plating film is also formed on the lower surface 9b of the sealing portion 9 when the metal film 24a is formed by the electroless plating method, the electroless plating film on the lower surface 9b of the sealing portion 9 is removed by etching or the like.

[0061] Thereafter, the semiconductor device 1 can be obtained by cutting between adjacent packages with a dicing blade.

[0062] <Regarding the main features and effects> In power circuits such as DC-DC converters and inverters, a field-effect transistor for a high-side switch and a field-effect transistor for a low-side switch are connected in series. If a semiconductor device is configured with a high-side semiconductor chip on which a field-effect transistor for a high-side switch is formed and a low-side semiconductor chip on which a field-effect transistor for a low-side switch is formed as one package, the number of semiconductor devices required to configure a desired circuit can be reduced compared to the case where those semiconductor chips are packaged as separate semiconductor devices. However, in order to electrically connect the source electrode of the high-side semiconductor chip and the drain electrode of the low-side semiconductor chip within the semiconductor device, it is necessary to arrange the members required for wiring between the electrodes within the semiconductor device, so there is a concern about an increase in the size of the semiconductor device.

[0063] The semiconductor device 1 of the present embodiment includes die pads 5 and 6, a semiconductor chip 2 mounted on the die pad 5, a semiconductor chip 3 mounted on the die pad 6, and an insulator portion 28 that seals them. The semiconductor chip 2 has a source electrode 2S formed on the front surface side and a drain electrode 2D formed on the back surface side, and the semiconductor chip 3 has a source electrode 3S formed on the front surface side and a drain electrode 3D formed on the back surface side.

[0064] One of the main features of the present embodiment is that the semiconductor chip 2 and the semiconductor chip 3 are mounted on the die pads with their top and bottom (front and back) reversed. That is, the semiconductor chip 2 is mounted on the die pad 5 with the drain electrode 2D facing the die pad 5, and the semiconductor chip 3 is mounted on the die pad 6 with the source electrode 3S facing the die pad 6. And a wiring 26DS for electrically connecting the source electrode 2S of the semiconductor chip 2 and the drain electrode 3D of the semiconductor chip 3 is formed within the insulator portion 28.

[0065] Unlike the present embodiment, assume a case where a high-side semiconductor chip (corresponding to semiconductor chip 2) and a low-side semiconductor chip (corresponding to semiconductor chip 3) are mounted on a die pad with the top and bottom (front and back) facing the same direction, and this will be referred to as a study example hereinafter. In the case of this study example, both the high-side semiconductor chip and the low-side semiconductor chip are mounted on the die pad with the drain electrode facing the die pad. In this case, the high-side die pad on which the high-side semiconductor chip is mounted is electrically connected to the drain electrode of the high-side semiconductor chip, and the low-side die pad on which the low-side semiconductor chip is mounted is electrically connected to the drain electrode of the low-side semiconductor chip.

[0066] However, in the case of this study example, in order to electrically connect the source electrode of the high-side semiconductor chip and the drain electrode of the low-side semiconductor chip within the semiconductor device, it is conceivable to electrically connect the source electrode of the high-side semiconductor chip and the low-side die pad using a metal plate. However, this requires an area (space) required to connect the low-side die pad and the metal plate, resulting in an increase in the size of the semiconductor device. For example, since the distance between the high-side semiconductor chip and the low-side semiconductor chip is increased and the source electrode of the high-side semiconductor chip and the low-side die pad are connected by a metal plate, an increase in the size of the semiconductor device is caused by the increase in the distance between the semiconductor chips.

[0067] In contrast, in the present embodiment, the semiconductor chip 2 is mounted on the die pad 5 with the drain electrode 2D facing the die pad 5, and the semiconductor chip 3 is mounted on the die pad 6 with the source electrode 3S facing the die pad 6. As a result, both the source electrode 2S of the semiconductor chip 2 and the drain electrode 3D of the semiconductor chip 3 face upward (the side opposite to the die pad), and the height positions of the source electrode 2S of the semiconductor chip 2 and the drain electrode 3D of the semiconductor chip 3 are approximately the same height position. For this reason, the source electrode 2S of the semiconductor chip 2 and the drain electrode 3D of the semiconductor chip 3 can be easily and accurately electrically connected using the wiring 26DS formed in the insulator portion 28.

[0068] Therefore, in the present embodiment, since it is not necessary to electrically connect the die pad 6 on which the semiconductor chip 3 is mounted and the source electrode 2S of the semiconductor chip 2 with a metal plate or the like, there is no need to secure a space required for arranging a metal plate in the semiconductor device, and there is also no need to secure a space for connecting a metal plate to the die pad 6 on which the semiconductor chip 3 is mounted. In the present embodiment, even if the interval between the semiconductor chips 2 and 3 is reduced, the source electrode 2S of the semiconductor chip 2 and the drain electrode 3D of the semiconductor chip 3 can be easily and accurately electrically connected by the wiring 26DS. Therefore, the interval between the semiconductor chips 2 and 3 can be reduced to reduce the size (smaller area) of the semiconductor device.

[0069] Further, in the present embodiment, the source electrode 2S of the semiconductor chip 2 and the drain electrode 3D of the semiconductor chip 3 are electrically connected by the wiring 26DS instead of a metal plate. The wiring 26DS has a high degree of freedom in wiring width, and the source electrode 2S of the semiconductor chip 2 and the drain electrode 3D of the semiconductor chip 3 can be connected by the wiring 26DS along the shortest path. For this reason, it becomes easy to realize low impedance and low on-resistance of the semiconductor device. Therefore, the performance of the semiconductor device can be improved.

[0070] Also, it is desirable to increase the wiring width of the wiring 26DS to a certain extent and connect the source electrode 2S of the semiconductor chip 2 and the drain electrode 3D of the semiconductor chip 3 with low resistance by the wiring 26DS. From this perspective, the width W1 (see FIG. 5) of the wiring 26DS is preferably larger than the width W2 of the other wirings 26GH, 26GL, 26C1, 26C2, 26C3. Here, the wiring width corresponds to the width (dimension) in a direction substantially perpendicular to the thickness direction of the wiring and substantially perpendicular to the current direction flowing through the wiring.

[0071] Also, not only the semiconductor chips 2 and 3 but also the semiconductor chip 4 that controls them (and thus is electrically connected to the gate electrodes 2G and 3G of the semiconductor chips 2 and 3) are packaged together as one semiconductor device, so that the number of semiconductor devices required to configure a desired circuit can be reduced as compared with the case where the semiconductor chip 4 is packaged separately.

[0072] Also, the gate electrode 2G of the semiconductor chip 2 can be electrically connected to the electrode 4C of the semiconductor chip 4 using the wiring 26GH formed in the insulator portion 28. Also, the gate electrode 3G of the semiconductor chip 3 can be electrically connected to the electrode 4C of the semiconductor chip 4 using the wiring 26GL formed in the insulator portion 28. Also, the lead 8 can be electrically connected to the electrode 4C of the semiconductor chip 4 using the wiring 26C1 formed in the insulator portion 28. In this way, in the semiconductor device, members to be electrically connected to each other can be electrically connected using the wiring formed in the insulator portion 28. Since wiring is used instead of a metal plate or wire, the space required for electrical connection can be reduced, and the semiconductor device can be miniaturized (reduced in area). Also, the layout design of each component of the semiconductor device becomes easier. Also, the manufacturing cost of the semiconductor device can be suppressed.

[0073] (Embodiment 2) FIG. 30 is a circuit diagram showing the circuit configuration of the semiconductor device 1a according to Embodiment 2. FIGS. 31 to 33 are perspective plan views of the semiconductor device 1a according to Embodiment 2, FIG. 34 is a bottom view (rear view) of the semiconductor device 1a according to Embodiment 2, and FIGS. 35 to 39 are cross-sectional views of the semiconductor device 1a according to Embodiment 2. Note that FIG. 31 shows a perspective plan view of the semiconductor device 1a when the components made of an insulator (sealing portions 58 and 59 and insulating layer 64) are seen through. Further, FIG. 32 shows a perspective plan view of the semiconductor device 1a when the wirings 62 (wirings 62DS1, 62DS2, 62DS3, 62GH1, 62GH2, 62GH3, 62GL1, 62GL2, 62GL3, 62C1, 62C2) are seen through in FIG. 31. Note that in FIG. 32, what are actually visible are the drain electrodes 44D, 45D, and 46D of the semiconductor chips 44, 45, and 46, but for easy understanding, the planar positions of the gate electrodes 44G, 45G, and 46G and the source electrodes 44S, 45S, and 46S in the semiconductor chips 44, 45, and 46 are indicated by dotted lines. Further, FIG. 33 shows a perspective plan view of the semiconductor device 1a when the semiconductor chips 41, 42, 43, 44, 45, 46, 47, 48 and the plug portions 63 are seen through in FIG. 32. FIG. 35 is a cross-sectional view of the semiconductor device 1a at the position of the line B1 - B1 shown in FIG. 31, FIG. 36 is a cross-sectional view of the semiconductor device 1a at the position of the line B2 - B2 shown in FIG. 31, and FIG. 37 is a cross-sectional view of the semiconductor device 1a at the position of the line B3 - B3 shown in FIG. 31. FIG. 38 is a cross-sectional view of the semiconductor device 1a at the position along the wiring 62GL1 and the wiring 62C2, and FIG. 39 is a cross-sectional view of the semiconductor device 1a at the position along the wiring 62GH1 and the wiring 62C1.

[0074] Note that the cross-sectional views of the semiconductor device 1a at the position along the wiring 62GL2 and the cross-sectional view of the semiconductor device 1a at the position along the wiring 62GL3, although having different reference numerals from FIG. 38, have the same structure, so the figures are omitted. Further, the cross-sectional views of the semiconductor device 1a at the position along the wiring 62GH2 and the cross-sectional view of the semiconductor device 1a at the position along the wiring 62GH3, although having different reference numerals from FIG. 39, have the same structure, so the figures are omitted.

[0075] As shown in the circuit diagram of FIG. 30, pairs of power MOSFETs 41a and 44a, 42a and 45a, 43a and 46a connected in series are connected in parallel between terminal T49 and terminal T50. A power supply potential (VIN) is supplied to terminal T49, and a reference potential lower than the power supply potential, for example, a ground potential (GND), is supplied to terminal T50. The gates of the power MOSFETs 41a, 42a, 43a for the high-side switches are connected to the control circuit 47a, and the gates of the power MOSFETs 44a, 45a, 46a for the low-side switches are connected to the control circuit 48a. Terminal T51 is connected to the source of power MOSFET 41a and the drain of power MOSFET 44a, terminal T52 is connected to the source of power MOSFET 42a and the drain of power MOSFET 45a, and terminal T53 is connected to the source of power MOSFET 43a and the drain of power MOSFET 46a. Terminals T51, T52, and T53 are output terminals and are connected to a load provided outside the semiconductor device 1a, for example.

[0076] In the second embodiment, the semiconductor chips 41, 42, 43 for the high-side switches, the semiconductor chips 44, 45, 46 for the low-side switches, and the control semiconductor chips 47, 48 are integrated as one package to form the semiconductor device 1a. The structure of the semiconductor device 1a of the second embodiment will be described below with reference to FIGS. 30 to 39.

[0077] The semiconductor device 1a of the second embodiment includes semiconductor chips 41, 42, 43, 44, 45, 46, 47, 48, die pads (chip mounting parts) 49, 50, output conductor parts 51, 52, 53, gate connection conductor parts 54, 55, 56, a plurality of leads 57, and sealing parts 58, 59 and an insulating layer 64 that seal these.

[0078] Inside the semiconductor chip 41, a power MOSFET 41a is formed. Similarly, power MOSFETs 42a to 46a are formed in semiconductor chips 42 to 46 respectively. Inside the semiconductor chip 47, a control circuit 47a for controlling the semiconductor chips 41, 42, and 43 for the high-side switch is formed, and inside the semiconductor chip 48, a control circuit 48a for controlling the semiconductor chips 44, 45, and 46 for the low-side switch is formed.

[0079] The configuration of each of the semiconductor chips 41, 42, 43, 44, 45, and 46 is the same as that of the semiconductor chips 2 and 3 described above. Therefore, the semiconductor chip 41 has a source electrode 41S and a gate electrode 41G on the surface side, and a drain electrode 41D on the opposite back side. Similarly, the corresponding semiconductor chips 42 to 46 have source electrodes 42S to 46S and gate electrodes 42G to 46G on the surface side, and drain electrodes 42D to 46D on the opposite back side. Further, the semiconductor chip 47 has a plurality of electrodes 47C on the surface side that are electrically connected to the control circuit 47a inside the semiconductor chip 47. Also, the semiconductor chip 48 has a plurality of electrodes 48C on the surface side that are electrically connected to the control circuit 48a inside the semiconductor chip 48.

[0080] The semiconductor chips 41, 42, and 43 are mounted on a common die pad 49 with the drain electrodes 41D, 42D, and 43D facing the die pad 49. The drain electrodes 41D, 42D, and 43D are electrically connected to the common die pad 49 via a conductive bonding material 61D.

[0081] The semiconductor chips 44, 45, and 46 are mounted on a common die pad 50 with the source electrodes 44S, 45S, and 46S facing the die pad 50. The source electrodes 44S, 45S, and 46S are electrically connected to the common die pad 50 via a conductive bonding material 61S.

[0082] Therefore, in the semiconductor device 1a of the second embodiment, the semiconductor chips 41, 42, and 43 are oriented in the same up-and-down (front-back) direction, and the semiconductor chips 44, 45, and 46 are also oriented in the same up-and-down (front-back) direction. However, the semiconductor chips 41, 42, 43 and the semiconductor chips 44, 45, 46 are oriented in opposite up-and-down (front-back) directions.

[0083] The gate electrode 44G of the semiconductor chip 44 faces the gate connection conductor portion 54 and is electrically connected to the gate connection conductor portion 54 via the conductive bonding material 61G. The gate electrode 45G of the semiconductor chip 45 faces the gate connection conductor portion 55 and is electrically connected to the gate connection conductor portion 55 via the conductive bonding material 61G. The gate electrode 46G of the semiconductor chip 46 faces the gate connection conductor portion 56 and is electrically connected to the gate connection conductor portion 56 via the conductive bonding material 61G.

[0084] The die pads 49, 50, the output conductor portions 51, 52, 53, the gate connection conductor portions 54, 55, 56, and the plurality of leads 57 are made of a conductor, but are formed of the same material as the die pads 5, 6, 7, etc., and are spaced apart from each other via the sealing portion 58. The height position of the upper surface of the sealing portion 58 is substantially the same as the height position of the upper surface of each of the die pads 49, 50, the output conductor portions 51, 52, 53, the gate connection conductor portions 54, 55, 56, and the plurality of leads 57. The sealing portion 58 is formed so as to fill the space between the die pads 49, 50, the output conductor portions 51, 52, 53, the gate connection conductor portions 54, 55, 56, and the plurality of leads 57.

[0085] Each of the semiconductor chips 47 and 48 is mounted on the sealing portion 58 with the back surfaces of the semiconductor chips 47 and 48 facing the sealing portion 58, via an insulating or conductive bonding material 61C. The sealing portion 58 is made of an insulator and is formed of, for example, the same material as the above-described sealing portion 9. On the lower surface of the sealing portion 58, the lower surfaces of the die pads 49, 50, the output conductor portions 51, 52, 53, and the plurality of leads 57 are exposed, but preferably the gate connection conductor portions 54, 55, 56 are not exposed. This can be achieved, for example, by making the gate connection conductor portions 54, 55, 56 thinner than the die pads 49, 50, etc. by performing half etching on the lower surface side of the gate connection conductor portions 54, 55, 56 and covering the lower surfaces of the gate connection conductor portions 54, 55, 56 with the sealing portion 58.

[0086] A sealing portion 59 is formed so as to cover the semiconductor chips 41, 42, 43, 44, 45, 46, 47, 48 on the sealing portion 58, the die pads 49, 50, the output conductor portions 51, 52, 53, the gate connection conductor portions 54, 55, 56, and the plurality of leads 57. The sealing portion 59 is made of an insulator and is formed of, for example, the same material as the sealing portion 58.

[0087] Openings are provided in the sealing portion 59 so as to expose the source electrodes 41S, 41S, 41S and gate electrodes 41G, 41G, 41G of the semiconductor chips 41, 42, 43, the drain electrodes 44D, 45D, 46D of the semiconductor chips 44, 45, 46, and the electrodes 47C, 48C of the semiconductor chips 47, 48.

[0088] A wiring 62 is formed on the upper surface of the sealing portion 59. The wiring 62 includes wiring 62DS1 to 62DS3, wiring 62GH1 to 62GH3, wiring 62GL1 to 62GL3, and wiring 62C1 and 62C2, and they are formed on the same layer. Further, conductive plug portions (via portions, via wirings) 63 are formed in each of the output conductor portions 51, 52, 53, the gate connection conductor portions 54, 55, 56, and the lead 8. The plug portion 63 is made of a metal material such as copper (Cu) and is formed in a hole provided in the sealing portion 59. The plug portion 63 is provided to electrically connect the wiring 62 on the plug portion 63 and each conductor (output conductor portions 51, 52, 53, gate connection conductor portions 54, 55, 56, and lead 8) below the plug portion 63.

[0089] The wiring 62DS1 is a wiring for electrically connecting the source electrode 41S of the semiconductor chip 41 and the drain electrode 44D of the semiconductor chip 44. The wiring 62DS1 integrally has a portion located on the source electrode 41S of the semiconductor chip 41 and electrically connected to the source electrode 41S, a portion located on the drain electrode 44D of the semiconductor chip 44 and electrically connected to the drain electrode 44D, and a portion connecting them. Thereby, the source electrode 41S of the semiconductor chip 41 and the drain electrode 44D of the semiconductor chip 44 are electrically connected through the wiring 62DS1. Further, the plug portion 63 formed on the output conductor portion 51 is interposed between the wiring 62DS1 and the output conductor portion 51. Thereby, the wiring 62DS1 and the output conductor portion 51 are electrically connected through the plug portion 63 on the output conductor portion 51.

[0090] With the same configuration as the wiring 62DS1, the wiring 62DS2 electrically connects the source electrode 42S of the semiconductor chip 42 and the drain electrode 45D of the semiconductor chip 45, and electrically connects the wiring 62DS2 and the output conductor portion 52 through the plug portion 63 on the output conductor portion 52.

[0091] Similar to the wiring 62DS1, the wiring 62DS3 electrically connects the source electrode 43S of the semiconductor chip 43 and the drain electrode 46D of the semiconductor chip 46, and electrically connects the wiring 62DS3 and the output conductor part 53 through the plug part 63 on the output conductor part 53.

[0092] The wiring 62GL1 is a wiring for electrically connecting the gate electrode 44G of the semiconductor chip 44 and the electrode 48C of the semiconductor chip 48. One end of the wiring 62GL1 is located on the plug part 63 provided on the gate connection conductor part 54 and is electrically connected to the plug part 63, and the other end of the wiring 62GL1 is located on the electrode 48C of the semiconductor chip 48 and is electrically connected to the electrode 48C. The plug part 63 arranged between the gate connection conductor part 54 and the wiring 62GL1 electrically connects the gate connection conductor part 54 and the wiring 62GL1. Thereby, the gate electrode 44G of the semiconductor chip 44 and the electrode 48C of the semiconductor chip 48 are electrically connected through the conductive bonding material 61G, the gate connection conductor part 54, the plug part 63, and the wiring 62GL1.

[0093] Similar to the wiring 62GL1, the wiring 62GL2 electrically connects the gate electrode 45G of the semiconductor chip 45 and the electrode 48C of the semiconductor chip 48 through the conductive bonding material 61G, the gate connection conductor part 55, the plug part 63, and the wiring 62GL2.

[0094] Similar to the wiring 62GL1, the wiring 62GL3 electrically connects the gate electrode 46G of the semiconductor chip 46 and the electrode 48C of the semiconductor chip 48 through the conductive bonding material 61G, the gate connection conductor part 56, the plug part 63, and the wiring 62GL2.

[0095] The wiring 62GH1 is a wiring for electrically connecting the gate electrode 41G of the semiconductor chip 41 and the electrode 47C of the semiconductor chip 47. One end of the wiring 62GH1 is located on the gate electrode 41G of the semiconductor chip 41 and is electrically connected to the gate electrode 41G, and the other end of the wiring 62GH1 is located on the electrode 47C of the semiconductor chip 47 and is electrically connected to the electrode 47C. Thereby, the gate electrode 41G of the semiconductor chip 41 and the electrode 47C of the semiconductor chip 47 are electrically connected through the wiring 62GH1.

[0096] With the same configuration as the wiring 62GH1, the wiring 62GH2 electrically connects the gate electrode 42G of the semiconductor chip 42 and the electrode 47C of the semiconductor chip 47 through the wiring 62GH2.

[0097] With the same configuration as the wiring 62GH1, the wiring 62GH3 electrically connects the gate electrode 43G of the semiconductor chip 43 and the electrode 47C of the semiconductor chip 47 through the wiring 62GH3.

[0098] The wiring 62C1 is a wiring for electrically connecting the lead 57 and the electrode 47C of the semiconductor chip 47. One end of the wiring 62C1 is located on the plug portion 63 provided on the lead 57 and is electrically connected to the plug portion 63, and the other end of the wiring 62C1 is located on the electrode 47C of the semiconductor chip 47 and is electrically connected to the electrode 47C. The plug portion 63 disposed between the lead 57 and the wiring 62C1 electrically connects the lead 57 and the wiring 62C1. Thereby, the lead 57 and the electrode 47C of the semiconductor chip 47 are electrically connected through the plug portion 63 and the wiring 62C1.

[0099] With the same configuration as the wiring 62C1, the wiring 62C2 electrically connects the lead 57 and the electrode 48C of the semiconductor chip 48 through the plug portion 63 and the wiring 62C2.

[0100] An insulating layer 64 is formed on the upper surface of the sealing portion 59 so as to cover the wiring 62. The sealing portions 58 and 59 and the insulating layer 64 constitute an insulating body portion 65 that seals the semiconductor chips 41, 42, 43, 44, 45, 46, 47, 48, the die pads 49, 50, the output conductor portions 51, 52, 53, the gate connection conductor portions 54, 55, 56, and the plurality of leads 57. The die pads 49, 50, the output conductor portions 51, 52, 53, the gate connection conductor portions 54, 55, 56, and the plurality of leads 57 only need to be at least partially sealed by the insulating body portion 65, but it is preferable that the semiconductor chips 41, 42, 43, 44, 45, 46, 47, 48 are not exposed from the insulating body portion 65.

[0101] Also, the number of layers of the wiring layer and the insulating layer formed on the sealing portion 59 can be increased. In that case, the increased insulating layer also constitutes a part of the insulating body portion 65 for sealing.

[0102] In the semiconductor device 1a, the output conductor portions 51, 52, 53 respectively correspond to the terminals T51, T52, T53 in the circuit diagram of FIG. 30 and function as output terminals. The die pad 49 corresponds to the terminal T49 in the circuit diagram of FIG. 30, and the die pad 50 corresponds to the terminal T50 in the circuit diagram of FIG. 30.

[0103] Next, the manufacturing process of the semiconductor device 1a according to the second embodiment will be described with reference to FIGS. 31 to 39 and FIGS. 40 to 53. FIGS. 40 to 53 are cross-sectional views showing the manufacturing process of the semiconductor device 1a according to the second embodiment. Among FIGS. 40 to 53, FIGS. 40, 42, 44, 46, 48, 50, and 52 are cross-sectional views of the semiconductor device 1a corresponding to the B1 - B1 line in FIG. 29 in each manufacturing process. Also, FIGS. 41, 43, 45, 47, 49, 51, and 53 are cross-sectional views of the semiconductor device 1a corresponding to the same cutting line as in FIG. 36 in each manufacturing process.

[0104] First, as shown in FIGS. 40 and 41, prepare a lead frame. The lead frame has a frame (not shown here), die pads 49, 50 connected to the frame, output conductor parts 51, 52, 53, gate connection conductor parts 54, 55, 56, and a plurality of leads 57. The lead frame is used in a state of being adhered to a back tape (not shown) such as a polyimide film.

[0105] Next, as shown in FIGS. 41 and 42, form a sealing part 58. At the stage when the sealing part 58 is formed, as shown in FIGS. 41 and 42, the thickness of the sealing part 58 is thicker than that of the die pads 49, 50, etc., and the die pads 49, 50, output conductor parts 51, 52, 53, gate connection conductor parts 54, 55, 56, and the plurality of leads 57 are covered not only on the side surfaces but also on the upper surfaces by the sealing part 58. Since the lower surface side of the sealing part 58 is fixed to the back tape, the lower surfaces of the die pads 49, 50, output conductor parts 51, 52, 53, gate connection conductor parts 54, 55, 56, and the plurality of leads 57 are flush with the lower surface of the sealing part 58.

[0106] Next, as shown in FIGS. 44 and 45, by polishing the upper surface of the sealing part 58, the thickness of the sealing part 58 is reduced. As a result, the upper surfaces of the die pads 49, 50, output conductor parts 51, 52, 53, gate connection conductor parts 54, 55, 56, and the plurality of leads 57 are exposed from the sealing part 58.

[0107] Next, as shown in FIGS. 46 and 47, perform a die bonding process. In the die bonding process, semiconductor chips 41, 42, 43 are mounted on the die pad 49, semiconductor chips 44, 45, 46 are mounted on the die pad 50, and semiconductor chips 47, 48 are mounted on the sealing part 58.

[0108] In the die bonding process, the semiconductor chips 41, 42, 43 and the semiconductor chips 44, 45, 46 are in opposite vertical (front and back) orientations when mounted on the die pads. That is, for the semiconductor chips 41, 42, 43, the source electrodes 41S, 42S, 43S and the gate electrodes 41G, 42G, 43G face upward, and the drain electrodes 41D, 42D, 43D face the upper surface of the die pad 49. They are mounted on the upper surface of the die pad 49 via the conductive bonding material 61D. For the semiconductor chips 44, 45, 46, the drain electrodes 44D, 45D, 46D face upward, the source electrodes 44S, 45S, 46S face the upper surface of the die pad 50, and the gate electrodes 44G, 45G, 46G face the upper surfaces of the gate connection conductor parts 54, 55, 56. They are mounted on the upper surface of the die pad 50 via the conductive bonding material 61S and on the upper surfaces of the gate connection conductor parts 54, 55, 56 via the conductive bonding material 61G. For the semiconductor chips 47, 48, the back surfaces of the semiconductor chips 47, 48 face the upper surface of the sealing part 58, and they are mounted on the upper surface of the sealing part 58 via the insulating or conductive bonding material 61C. As the bonding materials 61D, 61S, 61G, a conductive paste-type bonding material (e.g., silver paste) or a soldering material can be used. As the bonding material 61C, for example, DAF (Die Attach Film) can be used.

[0109] Next, as shown in FIGS. 48 and 49, a sealing part 59 for sealing the semiconductor chips 41, 42, 43, 44, 45, 46, 47, 48 is formed. At this stage, the semiconductor chips 41 to 48 and their respective electrodes 41S to 46S, 41G to 46G, 41D to 46D, 47C, 48C are covered by the sealing part 59 and do not protrude from the sealing part 59.

[0110] Next, as shown in FIGS. 48 and 49, after forming holes in the sealing part 59 by, for example, laser processing, conductive plug parts 63 are formed in the holes by electrolytic plating or the like. The plug parts 63 are formed on the lead 57, on the output conductor parts 51, 52, 53, and on the gate connection conductor parts 54, 55, 56, respectively.

[0111] Next, as shown in FIGS. 50 and 51, the upper surface of the sealing portion 59 is polished to reduce the thickness of the sealing portion 59. Along with this, the upper surfaces of the electrodes 47C and 48C and the upper surface of the plug portion 63 are exposed from the upper surface of the sealing portion 59.

[0112] Next, as shown in FIGS. 50 and 51, an opening is formed in the sealing portion 59 using laser processing or the like. The openings in the sealing portion 59 are formed on the respective electrodes 41S to 43S, 41G to 43G, 44D to 46D of the semiconductor chips 41 to 46 so that the respective electrodes are exposed. At this stage, the back tape is peeled off, whereby the lower surface of the sealing portion 59 and the lower surfaces of the die pads 49, 50, the output conductor portions 51, 52, 53, and the leads 57 are exposed.

[0113] Next, as shown in FIGS. 52 and 53, a wiring 62 is formed. Since the method of forming the wiring 62 is the same as the method of forming the wiring 26 in the first embodiment described above, the description thereof is omitted. As described above, the wiring 62 includes wirings 62DS1 to 62DS3, 62GH1 to 62GH3, 62GL1 to 62GL3, 62C1, and 62C2.

[0114] Next, as shown in FIGS. 35 to 39 above, an insulating layer 64 is formed on the upper surface of the sealing portion 59 so as to cover the wiring 62. The insulating layer 64 is made of an insulator, for example, a resin material or the like.

[0115] Thereafter, the semiconductor device 1a can be obtained by cutting between adjacent packages with a dicing blade.

[0116] In the semiconductor device 1a of the second embodiment, the semiconductor chips 41, 42, 43 and the semiconductor chips 44, 45, 46 are mounted on the die pads with their tops and bottoms (front and back) facing in opposite directions. That is, the semiconductor chips 41, 42, 43 are mounted on the die pad 49 with their drain electrodes 41D, 42D, 43D facing the die pad 49, and the semiconductor chips 44, 45, 46 are mounted on the die pad 50 with their source electrodes 44S, 45S, 46S facing the die pad 50. Then, inside the insulator portion 65, a wiring 62DS1 that electrically connects the source electrode 41S of the semiconductor chip 41 and the drain electrode 44D of the semiconductor chip 44, a wiring 62DS2 that electrically connects the source electrode 42S of the semiconductor chip 42 and the drain electrode 45D of the semiconductor chip 45, and a wiring 62DS3 that electrically connects the source electrode 43S of the semiconductor chip 43 and the drain electrode 46D of the semiconductor chip 46 are formed. As a result, the effects as described in the first embodiment can be obtained.

[0117] That is, the source electrodes 41S, 42S, 43S of the semiconductor chips 41, 42, 43 and the drain electrodes 44D, 45D, 46D of the semiconductor chips 44, 45, 46 face upward (opposite to the die pad), and their height positions are generally the same. Therefore, using the wirings 62DS1, 62DS2, 62DS3 formed inside the insulator portion 65, the source electrodes 41S, 42S, 43S of the semiconductor chips 41, 42, 43 and the drain electrodes 44D, 45D, 46D of the semiconductor chips 44, 45, 46 can be electrically connected easily and accurately, respectively. By not using a metal plate for the connection, there is no need to secure the space required for arranging the metal plate inside the semiconductor device, and the semiconductor device can be miniaturized (reduced in area).

[0118] Also, in the second embodiment, as an example of a configuration in which a plurality of sets of two semiconductor chips having source electrodes and drain electrodes on opposite surfaces and connected in series are mounted, a configuration in which three sets are mounted is illustrated. However, the number of sets of semiconductor chips may be two, or four or more.

[0119] (Embodiment 3) Figures 54 to 58 are cross-sectional views of the semiconductor device 1b according to Embodiment 3. Figure 54 corresponds to FIG. 35 above, Figure 55 corresponds to FIG. 36 above, Figure 56 corresponds to FIG. 37 above, Figure 57 corresponds to FIG. 38 above, and Figure 58 corresponds to FIG. 39 above.

[0120] Figure 57 corresponds to a cross-sectional view of the semiconductor device 1b at a position along the wiring 62GL1 and the wiring 62C2. Cross-sectional views of the semiconductor device 1b at positions along the wiring 62GL2 and the wiring 62C2, and cross-sectional views of the semiconductor device 1b at positions along the wiring 62GL3 and the wiring 62C2 are omitted in the figure because, although they have different reference numerals from Figure 57, their structures are the same.

[0121] Figure 58 corresponds to a cross-sectional view of the semiconductor device 1b at a position along the wiring 62GH1. Cross-sectional views of the semiconductor device 1a at positions along the wiring 62GH2 and cross-sectional views of the semiconductor device 1a at positions along the wiring 62GH3 are omitted in the figure because, although they have different reference numerals from Figure 58, their structures are the same.

[0122] The differences between the semiconductor device 1b of Embodiment 3 and the semiconductor device 1a of Embodiment 2 described above will be explained below.

[0123] What corresponds to the sealing portion 58a in the semiconductor device 1b of Embodiment 3 is the combined sealing portion 58 and sealing portion 59 in the semiconductor device 1a of Embodiment 2 described above. In Embodiment 3, the semiconductor chips 47 and 48 are mounted on the upper surface of the sealing portion 58a. Also, in Embodiment 3, the insulating layer 64 is formed on the upper surface of the sealing portion 58a so as to cover the wiring 62 and the semiconductor chips 47 and 48. Reflecting the fact that the semiconductor chips 47 and 48 are mounted on the sealing portion 58a, the thickness of the insulating layer 64 in Embodiment 3 is greater than the thickness of the insulating layer 64 in Embodiment 2 described above. The insulator portion 65 in Embodiment 3 is composed of the sealing portion 58a and the insulating layer 64.

[0124] Also, in the case of the third embodiment, for the semiconductor chip 47, each of the plurality of electrodes 47C is located on and electrically connected to any one of the wirings 62GH1, 62GH2, 62GH3, 62C1. Also, for the semiconductor chip 48, each of the plurality of electrodes 48C is located on and electrically connected to any one of the wirings 62GL1, 62GL2, 62GL3, 62C2. Thus, similar to the second embodiment, also in the third embodiment, the gate electrodes 41G, 42G, 43G of the semiconductor chips 41, 42, 43 can be electrically connected to the electrode 47C of the semiconductor chip 47 through the wirings 62GH1, 62GH2, 62GH3, and the lead 57 can be electrically connected to the electrode 47C of the semiconductor chip 47 through the wiring 62C1. Also, the gate electrodes 44G, 45G, 46G of the semiconductor chips 44, 45, 46 can be electrically connected to the electrode 48C of the semiconductor chip 48 through the wirings 62GL1, 62GL2, 62GL3, and the lead 57 can be electrically connected to the electrode 48C of the semiconductor chip 48 through the wiring 62C2.

[0125] Since other configurations of the semiconductor device 1b of the third embodiment are the same as those of the semiconductor device 1a of the second embodiment, repeated description is omitted.

[0126] Next, the manufacturing process of the semiconductor device 1b of the third embodiment will be described. FIGS. 59 to 66 are cross-sectional views showing the manufacturing process of the semiconductor device 1b of the third embodiment. Among FIGS. 59 to 66, FIGS. 59, 61, 63, and 65 are cross-sectional views in each manufacturing process having the same cutting line as FIG. 50, and FIGS. 60, 62, 64, and 66 are cross-sectional views in each manufacturing process having the same cutting line as FIG. 53.

[0127] First, as shown in FIGS. 59 and 60, a lead frame similar to that of the second embodiment is prepared. The lead frame has a frame body, die pads 49, 50 connected to the frame body, output conductor portions 51, 52, 53, gate connection conductor portions 54, 55, 56, and a plurality of leads 57. The lead frame is used in a state of being adhered to a back tape (not shown) such as a polyimide film.

[0128] Next, as shown in FIGS. 59 and 60, a die bonding process is performed to mount semiconductor chips 41, 42, and 43 on die pad 49 and mount semiconductor chips 44, 45, and 46 on die pad 50. The die bonding of semiconductor chips 41, 42, 43 and semiconductor chips 44, 45, 46 is the same as that in the second embodiment in the third embodiment, so the repeated description is omitted here. However, in the case of the third embodiment, at this stage, the die bonding of semiconductor chips 47 and 48 is not performed.

[0129] Next, as shown in FIGS. 61 and 62, a sealing portion 58a is formed to seal semiconductor chips 41, 42, 43, 44, 45, 46, die pads 49, 50, output conductor portions 51, 52, 53, gate connection conductor portions 54, 55, 56, and a plurality of leads 57. At this stage, semiconductor chips 41, 42, 43, 44, 45, 46 and their respective electrodes are covered with the sealing portion 58a and are not exposed from the sealing portion 58a. Since the lower surface side of the sealing portion 58a is covered with a back tape, the lower surfaces of the die pads 49, 50, the output conductor portions 51, 52, 53, and the plurality of leads 57 are flush with the lower surface of the sealing portion 58a.

[0130] Next, as shown in FIGS. 61 and 62, holes are formed in the sealing portion 58a so as to reach the output conductor portions 51, 52, 53, the gate connection conductor portions 54, 55, 56, and the plurality of leads 57 by, for example, laser processing or the like, and then conductive plug portions 63 are formed in the holes by an electrolytic plating method or the like.

[0131] Next, as shown in FIGS. 63 and 64, the upper surface of the sealing portion 58a is polished to reduce the thickness of the sealing portion 59. When the polishing process of the sealing portion 58a is completed, the upper surface of the plug portion 63 is exposed from the upper surface of the sealing portion 58a.

[0132] Next, as shown in FIGS. 63 and 64, an opening is formed in the sealing portion 58a using laser processing or the like. The opening of the sealing portion 58a is formed on each of the electrodes 41S to 43S, 41G to 43G, 44D to 46D of the semiconductor chips 41 to 46 so that each electrode is exposed from the sealing portion 58a. At this stage, the back tape is peeled off, whereby the lower surface of the sealing portion 58a and the lower surfaces of the die pads 49, 50, the output conductor portions 51, 52, 53, and the leads 57 are exposed.

[0133] Next, as shown in FIGS. 65 and 66, wiring 62 is formed. The method of forming the wiring 62 is basically the same as the method of forming the wiring 26 in the above-described Embodiment 1 and the method of forming the wiring 62 in the above-described Embodiment 2, and thus the description thereof is omitted here. Similar to Embodiment 2, in this embodiment as well, the wiring 62 includes wiring 62DS1, 62DS2, 62DS3, 62GH1, 62GH2, 62GH3, 62GL1, 62GL2, 62GL3, 62C1, and 62C2.

[0134] Next, as shown in FIGS. 65 and 66, a die bonding process is performed to mount semiconductor chips 47 (not shown) and 48 on the sealing portion 58a. The semiconductor chips 47 and 48 are mounted on the sealing portion 58a with the electrodes 47C and 48C of the semiconductor chips 47 and 48 facing the sealing portion 58a. A plurality of electrodes 47C of the semiconductor chip 47 and the wirings 62GH1, 62GH2, 62GH3, and 62C1 are electrically connected to each other, and a plurality of electrodes 48C of the semiconductor chip 48 and the wirings 62GL1, 62GL2, 62GL3, and 62C2 are electrically connected to each other.

[0135] Next, as shown in FIGS. 54 to 58, an insulating layer 64 is formed on the upper surface of the sealing portion 58a so as to cover the wiring 62 and the semiconductor chips 47 and 48.

[0136] Thereafter, the semiconductor device 1b can be obtained by cutting between adjacent packages with a dicing blade.

[0137] In Embodiment 3, both of the control semiconductor chips 47 and 48 are flip-chip connected with face down. Therefore, when flip-chip connection to the semiconductor chips 47 and 48 is desired, it is preferable to apply Embodiment 3. On the other hand, in Embodiment 2 described above, both of the control semiconductor chips 47 and 48 are face-up connected and the semiconductor chips 47 and 48 are not mounted on the sealing portion 59, so the thickness of the insulating layer 64 can be made relatively thin. For this reason, the thickness of the entire semiconductor device can be reduced.

[0138] (Embodiment 4) Figs. 67 to 71 are cross-sectional views of the semiconductor device 1c according to Embodiment 4. Figs. 72 and 73 are plan perspective views of the semiconductor device 1c according to Embodiment 4. Wiring 62 is shown in Fig. 72, and the positions of the semiconductor chips 41, 42, 43, 44, 45, 46, 47, and 48 are indicated by dotted lines. Further, in Fig. 73, die pads 49, 50, output conductor portions 51, 52, 53, leads 57, wirings 62GL1, 62GL2, 62GL3, 62C2, plug portions 63, and conductor patterns 66 are shown, and the positions of the semiconductor chips 41, 42, 43, 44, 45, 46, 47, and 48 are indicated by dotted lines.

[0139] Note that Fig. 70 corresponds to a cross-sectional view of the semiconductor device 1c at a position along the wiring 62GL1 and the wiring 62C2. Cross-sectional views of the semiconductor device 1c at positions along the wiring 62GL2 and the wiring 62C2 are omitted from the drawing because, although they have different reference numerals from Fig. 70, their structures are similar. Similarly, cross-sectional views of the semiconductor device 1c at positions along the wiring 62GL3 and the wiring 62C2 are also omitted from the drawing. Further, Fig. 71 corresponds to a cross-sectional view of the semiconductor device 1c at a position along the wiring 62GH1 and the wiring 62C1. Cross-sectional views of the semiconductor device 1c at positions along the wiring 62GH2 and the wiring 62C1 are omitted from the drawing because, although they have different reference numerals from Fig. 71, their structures are similar. Similarly, cross-sectional views of the semiconductor device 1c at positions along the wiring 62GH3 and the wiring 62C1 are also omitted from the drawing.

[0140] The differences between the semiconductor device 1c of the fourth embodiment and the semiconductor device 1a of the second embodiment will be described below.

[0141] In the case of the second embodiment, both of the control semiconductor chips 47 and 48 were mounted on the sealing portion 58. On the other hand, in the fourth embodiment, for one of the control semiconductor chips 47 and 48, one semiconductor chip 47 is mounted on the sealing portion 58, and the other semiconductor chip 48 is mounted on the conductor pattern 66. Along with this, the wirings 62GL1, 62GL2, 62GL3 for electrically connecting the gate electrodes 44G, 45G, 46G of the semiconductor chips 44, 45, 46 to the electrode 48C of the semiconductor chip 48, and the wiring 62C2 for electrically connecting the electrode 48C of the semiconductor chip 48 to the lead 57 are formed not on the sealing portion 59 but on the sealing portion 58 (that is, between the sealing portion 58 and the sealing portion 59).

[0142] In the fourth embodiment, the wirings 62GL1, 62GL2, 62GL3, 62C2 and the conductor pattern 66 for chip mounting are formed on the upper surface of the sealing portion 58. The semiconductor chip 47 is mounted and fixed on the conductor pattern 66 with the electrode 47C of the semiconductor chip 47 facing upward and the back surface of the semiconductor chip 47 facing the conductor pattern 66 (sealing portion 58) via a bonding material 61C such as solder. The semiconductor chip 48 is mounted on the sealing portion 58 with the electrode 48C of the semiconductor chip 48 facing the sealing portion 58, and each of the plurality of electrodes 48C is located on one of the wirings 62GL1, 62GL2, 62GL3, 62C2 and is electrically connected via a conductive bonding material 61a.

[0143] In the case of the fourth embodiment, the gate connection conductor portion is not formed. The gate electrodes 44G to 46G of the semiconductor chips 44 to 46 are electrically connected to the electrode 48C of the semiconductor chip 48 through the wirings 62GL1 to 62GL3 without passing through the plug portion. The lead 57 and the electrode 48C of the semiconductor chip 48 are electrically connected through the wiring 62C2 without passing through the plug portion.

[0144] Since the other configuration of the semiconductor device 1c according to the fourth embodiment is substantially the same as that of the semiconductor device 1a according to the second embodiment described above, the repeated description thereof will be omitted here.

[0145] Next, the manufacturing process of the semiconductor device 1c according to the fourth embodiment will be described. FIGS. 74 to 82 are cross-sectional views showing the manufacturing process of the semiconductor device 1c according to the fourth embodiment. Among FIGS. 74 to 82, FIGS. 74, 77, and 80 show cross-sections corresponding to FIG. 67 above, FIGS. 75, 78, and 81 show cross-sections corresponding to FIG. 70 above, and FIGS. 76, 79, and 82 show cross-sections corresponding to FIG. 71 above.

[0146] First, a lead frame is prepared. In the case of the fourth embodiment, the lead frame has a frame (not shown here), die pads 49, 50, output conductor portions 51, 52, 53, and a plurality of leads 57 connected to the frame, but does not have a gate connection conductor portion. Then, after forming the sealing portion 58 as shown in FIGS. 42 and 43 of the second embodiment, the upper surface of the sealing portion 58 is polished to reduce the thickness of the sealing portion 58. As a result, as shown in FIGS. 74 to 76, the upper surfaces of the die pads 49, 50, the output conductor portions 51, 52, 53, and the plurality of leads 57 are exposed from the sealing portion 58.

[0147] Next, as shown in FIGS. 77 to 79, a metal layer 70 is formed. The metal layer 70 formed on the sealing portion 58 forms wirings 62GL1, 62GL2, 62GL3, 62C2 and a conductor pattern 66. The metal layer 70 is also formed on the die pads 49, 50, the output conductor portions 51, 52, 53, and the leads 57. This process can be performed in substantially the same manner as the wiring 26 forming process described in the first embodiment above, so the description thereof will be omitted here. In FIGS. 80 to 82 below, for simplicity, the metal layer 70 formed on each of the die pads 49, 50, the output conductor portions 51, 52, 53, and the leads 57 is not shown separately and is included in the die pads 49, 50, the output conductor portions 51, 52, 53, and the leads 57 (the same applies to FIGS. 67 to 71 above).

[0148] Next, as shown in FIGS. 80 to 82, a die bonding process is performed. In the die bonding process, semiconductor chips 41, 42, and 43 are mounted on die pad 49, semiconductor chips 44, 45, and 46 are mounted on die pad 50, and semiconductor chips 47 and 48 are mounted on sealing portion 58. The semiconductor chips 41, 42, and 43 are mounted in such a direction that the drain electrodes 41D, 42D, and 43D face the upper surface of the die pad 49, and the drain electrodes 41D, 42D, and 43D are electrically connected to the die pad 49 via a conductive bonding material 61D. The semiconductor chips 44, 45, and 46 are mounted in such a direction that the source electrodes 44S, 45S, and 46S face the upper surface of the die pad 50, and the source electrodes 44S, 45S, and 46S are electrically connected to the die pad 50 via a conductive bonding material 61S. The gate electrodes 44G, 45G, and 46G of the semiconductor chips 44, 45, and 46 are electrically connected to the wirings 62GL1, 62GL2, and 62GL3 via a conductive bonding material 61G such as solder. The semiconductor chip 47 is mounted on the upper surface of the conductor pattern 66 (sealing portion 58) in such a direction that the back surface of the semiconductor chip 47 faces the upper surface of the conductor pattern 66 via a bonding material 61C such as solder. The semiconductor chip 48 is mounted on the upper surface of the sealing portion 58 in such a direction that the surface of the semiconductor chip 48 (the main surface on the side where the electrode 48C is formed) faces the upper surface of the sealing portion 58. Each of the plurality of electrodes 48C of the semiconductor chip 48 is electrically connected to any one of the wirings 62GL1, 62GL2, 62GL3, and 62C2.

[0149] The subsequent steps are generally the same as those in the second embodiment. That is, as can also be seen from FIGS. 67 to 71, first, a sealing portion 59 is formed so as to cover the semiconductor chips 41, 42, 43, 44, 45, 46, 47, 48. Then, a hole portion is formed in the sealing portion 59, and a plug portion 63 is formed in the hole portion. Then, the upper surface of the sealing portion 59 is polished to reduce the thickness of the sealing portion 59, thereby exposing the electrode 47C of the semiconductor chip 47 and the upper surface of the plug portion 63 from the upper surface of the sealing portion 59. Further, openings are provided in the sealing portion 59 above the source electrodes 41S, 42S, 43S and the gate electrodes 41G, 42G, 43G of the semiconductor chips 41, 42, 43, and the drain electrodes 44D, 45D, 46D of the semiconductor chips 44, 45, 46 to expose the respective electrodes. Then, wirings 62DS1, 62DS2, 62DS3, 62GH1, 62GH2, 62GH3, 62C2 are formed. Then, an insulating layer 64 is formed on the upper surface of the sealing portion 59 so as to cover the wiring 62. Then, the semiconductor device 1c can be obtained by cutting between adjacent packages with a dicing blade.

[0150] In the fourth embodiment, the plug portion 63 is not necessary to electrically connect the gate electrodes 41G, 42G, 43G of the semiconductor chips 41, 42, 43 and the electrode 47C of the semiconductor chip 47, and the plug portion 63 is also not necessary to electrically connect the gate electrodes 44G, 45G, 46G of the semiconductor chips 44, 45, 46 and the electrode 48C of the semiconductor chip 48. Therefore, the structure necessary for the electrical connection between the semiconductor chips can be simplified. Therefore, it is also advantageous for miniaturization of the semiconductor device.

[0151] (Embodiment 5) The fifth embodiment is a modified example in which an upper-layer wiring is further added to the semiconductor device 1c of the fourth embodiment so that electronic components can be mounted on the semiconductor device. FIGS. 83 and 84 are cross-sectional views of the semiconductor device 1d of the fifth embodiment, FIG. 83 corresponds to FIG. 67 above, and FIG. 84 corresponds to FIG. 71 above.

[0152] For the structure below the insulating layer 64, since the semiconductor device 1d of the fifth embodiment is the same as the semiconductor device 1c of the fourth embodiment, the repeated description thereof will be omitted here.

[0153] As also shown in FIGS. 83 and 84, in the semiconductor device 1d of the fifth embodiment, one or more wiring layers are further formed on the insulating layer 64. In the cases of FIGS. 83 and 84, a wiring 72 is formed on the insulating layer 64, an insulating layer 73 is formed on the insulating layer 64 so as to cover the wiring 72, and a wiring 75 is formed on the insulating layer 73. The wiring 72 is electrically connected to the wiring 62 through an opening 71 provided in the insulating layer 64 (the opening 71 that exposes the wiring 62). The wiring 75 is electrically connected to the wiring 72 through an opening 74 provided in the insulating layer 73 (the opening 74 that exposes the wiring 72). An electronic component 77 is mounted on the semiconductor device 1d, that is, on the wiring 75 of the semiconductor device 1d. In the cases of FIGS. 83 and 84, the electronic components 77a and 77b are mounted, but the number of the mounted electronic components is arbitrary. The electrodes of the electronic component 77 are electrically connected to the wiring 75 through a conductive bonding material 76 such as solder. Thereby, the electronic component 77 can be electrically connected to any one of the semiconductor chips 41, 42, 43, 44, 45, 46, 47, 48 incorporated in the semiconductor device 1d via the wiring 62. As the electronic component 77, for example, a coil or a capacitor can be used.

[0154] In the fifth embodiment, since other electronic components can be mounted on the semiconductor device, in a mounting substrate or the like on which the semiconductor device is mounted, the space required for mounting the electronic components becomes unnecessary.

[0155] The semiconductor device 1d shown in FIGS. 83 and 84 is based on the semiconductor device 1c of the fourth embodiment, but it can also be based on the semiconductor devices of embodiments other than the fourth embodiment.

[0156] (Sixth Embodiment) So far, embodiments using a lead frame have been described. In Embodiment 6, a case of manufacturing a semiconductor device without using a lead frame will be described. FIGS. 85 to 99 are cross-sectional views showing the manufacturing process of the semiconductor device of Embodiment 6. Among FIGS. 85 to 99, FIGS. 85, 88, 91, 94, and 97 show cross-sections corresponding to FIG. 67 above, FIGS. 86, 89, 92, 95, and 98 show cross-sections corresponding to FIG. 70 above, and FIGS. 87, 90, 93, 96, and 99 show cross-sections corresponding to FIG. 71 above.

[0157] First, as shown in FIGS. 85 to 87, a metal plate 81 is prepared. The metal plate 81 is composed of a base metal layer (metal substrate) 81a and a metal layer 81b formed on the upper surface of the metal layer 81a. The metal layer 81b is thinner than the metal layer 81a. Also, the metal layer 81a and the metal layer 81b are made of different metal materials. The metal layer 81b functions as an etching stopper layer when etching the metal layer 81a later.

[0158] Next, a metal pattern 82 is formed on the upper surface of the metal plate 81, that is, on the metal layer 81b constituting the metal plate 81. The process of forming the metal pattern 82 can be performed in substantially the same manner as the wiring 26 forming process described in Embodiment 1 above, so the description thereof is omitted here.

[0159] The metal pattern 82 is preferably made of the same metal material as the metal layer 81a. For example, both the metal layer 81a and the metal pattern 82 are made of copper or a copper alloy. The metal layer 81b can be, for example, a titanium layer. It is preferable that the metal layer 81a is thicker than the metal pattern 82.

[0160] The metal pattern 82 includes portions that will become the die pads 49, 50, portions that will become the output conductor portions 51 to 53, portions that will become the leads 57, and portions that will become the wirings 62, respectively.

[0161] Next, as shown in FIGS. 88 to 90, a die bonding process is performed.

[0162] In the die bonding process, the semiconductor chips 41, 42, 43 connect the drain electrodes 41D, 42D, 43D to the portion of the metal pattern 82 that becomes the die pad 49 via a conductive bonding material 61D such as solder. Also, the semiconductor chips 44, 45, 46 connect the source electrodes 44S, 45S, 46S to the portion of the metal pattern 82 that becomes the die pad 50 via a conductive bonding material 61S such as solder. Further, the gate electrodes 44G, 45G, 46G of the semiconductor chips 44, 45, 46 are connected to the portions of the metal pattern 82 that become the wirings 62GL1, 62GL2, 62GL3 via a conductive bonding material 61G such as solder.

[0163] Also, the semiconductor chips 47, 48 are electrically connected with the electrode 47C to the portions of the metal pattern 82 that become the wirings 62GH1, 62GH2, 62GH3, 62C1 and the electrode 48C to the portions of the metal pattern 82 that become the wirings 62GL1, 62GL2, 62GL3, 62C2 via a conductive bonding material 61a such as solder with the surfaces (main surfaces on the side where the electrodes 47C, 48C are formed) of the semiconductor chips 47, 48 facing the metal plate 81.

[0164] After the die bonding process and up to the insulating layer 64 formation process, Embodiment 6 is also generally the same as Embodiment 4. That is, as can also be seen from FIGS. 91 to 93, first, a sealing portion 59 is formed so as to cover the semiconductor chips 41, 42, 43, 44, 45, 46, 47, 48. Then, a hole is formed in the sealing portion 59, and a plug portion 63 is formed in the hole. Then, the upper surface of the sealing portion 59 is polished to reduce the thickness of the sealing portion 59, and then openings are formed in the sealing portion 59 on each electrode, so that the source electrodes 41S, 42S, 43S and gate electrodes 41G, 42G, 43G of the semiconductor chips 41, 42, 43 and the drain electrodes 44D, 45D, 46D of the semiconductor chips 44, 45, 46 are exposed from the openings. Then, a wiring 62 is formed. The wiring 62 includes wirings 62DS1, 62DS2, 62DS3, 62GH1, 62GH2, 62GH3. The method of forming the wiring 62 is the same as that in Embodiment 4 and the like. Then, an insulating layer 64 is formed on the upper surface of the sealing portion 59 so as to cover the wiring 62. This stage corresponds to FIGS. 91 to 93.

[0165] Next, a resist pattern (not shown) is formed on the lower surface of the metal plate 81, and then, from the lower surface side of the metal plate 81, the metal plate 81 in the portion not covered by the resist pattern is etched and removed. The stage after removing the resist pattern is shown in FIGS. 94 to 96. During the etching, first, the metal layer 81a is etched using the metal layer 81b as an etching stopper, and then, the exposed metal layer 81b is etched. As a result, the metal plate 81 is partially removed, and the remaining metal plate 81 and the metal pattern 82 thereon constitute the die pad 49, the die pad 50, the output conductor portions 51, 52, 53, and the lead 57. The metal plate 81 does not remain under the portions where the lead 57 is not formed among the wirings 62GH1 to 62GH3, the wirings 62GL1 to 62GL1, and the wirings 62C1, 62C2.

[0166] Next, as shown in FIGS. 97 to 99, a sealing portion 58 made of an insulator is formed. The sealing portion 58 is formed so as to cover the respective side surfaces of the die pads 49, 50, the output conductor portions 51, 52, 53, and the leads 57, the respective lower surfaces of the wirings 62GL1, 62GL2, 62GL3, 62GH1, 62GH2, 62GH3, 62C1, 62C2, and the exposed lower surface of the sealing portion 59. On the lower surface of the sealing portion 58, the respective lower surfaces of the die pads 49, 50, the output conductor portions 51, 52, 53, and the leads 57 are exposed. Alternatively, after forming the sealing portion 58 so as to cover each lower surface, it may be exposed by polishing.

[0167] In Embodiment 6, both of the semiconductor chips 47 and 48 are connected face down. The wirings 62GH1, 62GH2, 62GH3 that electrically connect the gate electrodes 41G, 42G, 43G of the semiconductor chips 41, 42, 43 to the electrode 47C of the semiconductor chip 47 are composed of the wiring 62 and the metal pattern 82, and the two are electrically connected via the plug portion 63. For example, one end of the wiring 62GH1 formed by the wiring 62 is connected to the gate electrode 41G of the semiconductor chip 41 and the other end is connected to the plug portion 63, and one end of the wiring 62GH1 formed by the metal pattern 82 is connected to the electrode 47C of the semiconductor chip 47, and the other end is connected to the plug portion 63. The same applies to the wiring 62GH2 and the wiring 62GH3.

[0168] Also, as a modification of Embodiment 6, one or both of the semiconductor chips 47 and 48 may be face-up bonded.

[0169] (Embodiment 7) In Embodiment 7 as well, a semiconductor device that does not use a lead frame will be described. FIGS. 100 to 114 are cross-sectional views showing the manufacturing process of the semiconductor device of Embodiment 7. Among FIGS. 100 to 114, FIGS. 100, 103, 106, 109, and 112 show cross-sections corresponding to FIG. 67 above, FIGS. 101, 104, 107, 110, and 113 show cross-sections corresponding to FIG. 70 above, and FIGS. 102, 105, 108, 111, and 114 show cross-sections corresponding to FIG. 71 above.

[0170] First, as shown in FIGS. 100 to 102, an insulating substrate 91 is prepared. As the insulating substrate 91, for example, a glass substrate can be used. A metal layer for a seed layer may be formed on the entire upper surface of the insulating substrate 91 as necessary.

[0171] Next, as shown in FIGS. 100 to 102, a metal pattern 92 is formed on the insulating substrate 91. For example, after forming a resist pattern (not shown) on the insulating substrate 91, a metal layer is formed by electrolytic plating in a region of the upper surface of the insulating substrate 91 that is not covered by the resist pattern, thereby forming the metal pattern 92. The metal pattern 92 is made of, for example, copper or a copper alloy. Then, the resist pattern is removed. The metal pattern 92 includes portions that will become the die pads 49, 50, portions that will become the output conductor portions 51 to 53, and portions that will become the leads 57.

[0172] Next, a sealing portion 58 is formed so as to cover the metal pattern 92, and then the upper surface of the sealing portion 58 is polished so that the upper surface of the metal pattern 92 is exposed from the sealing portion 58, as shown in FIGS. 103 to 105.

[0173] Next, as shown in FIGS. 106 to 108, a metal layer 93 is formed. This step can be performed in the same manner as the metal layer 70 forming step of the fourth embodiment described above. The metal layer 93 formed on the sealing portion 58 forms the wirings 62GL1, 62GL2, 62GL3, 62C2 and the conductor pattern 66. Further, the metal layer 93 is also formed on the metal pattern 92. The metal pattern 92 and the metal layer 93 thereon form the die pads 49, 50, the output conductor portions 51, 52, 53 and the leads 57. In FIGS. 109 to 114 below, for the sake of simplicity, the die pads 49, 50, the output conductor portions 51, 52, 53 and the leads 57 are shown integrally without separately showing the metal pattern 92 and the metal layer 93.

[0174] Next, in the same manner as in the fourth embodiment, by performing the steps from the die bonding step to the step of forming the insulating layer 64, the structures of FIGS. 109 to 111 can be obtained. Since the steps during this period are substantially the same in the seventh embodiment as in the fourth embodiment, the repeated description thereof is omitted here.

[0175] Next, as shown in FIGS. 112 to 114, the insulating substrate 91 and the structure thereon are separated. When the metal layer for the seed layer described above has been formed, it can be removed by etching after this separation step. In this way, a semiconductor device can be manufactured.

[0176] The manufacturing process of the sixth embodiment can be applied not only to the fourth embodiment but also to other embodiments.

[0177] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, needless to say, the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Description of Reference Numerals

[0178] 1, 1a, 1b, 1c, 1d Semiconductor device 2, 3, 4 Semiconductor chip 2D, 3D Drain Electrodes 2G, 3G Gate Electrodes 2S, 3S Source Electrodes 4C Electrodes 5, 6, 7 Die Pads 6G Conductor Portion for Gate Connection 8 Leads 9 Sealing Portion 10C, 10D, 10G, 10S Bonding Materials 12, 13 Power MOSFETs 14 Control Circuit 21 Hole Portion 22 Plug Portion 23 Opening 24a, 24b Metal Films 25 Resist Pattern 26, 26DS, 26GL, 26GH, 26C1, 26C2, 26C3 Wiring 27 Insulating Layer 28 Insulator Portion 29 Opening 30, 30C, 30DS Wiring 31 Electronic Component 41, 42, 43, 44, 45, 46, 47, 48 Semiconductor Chips 41a, 42a, 43a, 44a, 45a, 46a Power MOSFETs 47a, 48a Control Circuits 41D, 42D, 43D, 44D, 45D, 46D Drain Electrodes 41G, 42G, 43G, 44G, 45G, 46G Gate Electrodes 41S, 42S, 43S, 44S, 45S, 46S Source Electrodes 47C, 48C Electrodes 49, 50 Die Pads 51, 52, 53 Conductor Portions for Output 54, 55, 56 Conductor Portions for Gate Connection 57 Leads 58, 59 Sealing Portions 61a, 61C, 61D, 61G, 61S Bonding Materials Wiring of 62, 62C1, 62C2, 62DS1, 62DS2, 6sDS3, 62GH1, 62GH2, 62GH3, 62GL1, 62GL2, 62GL3 63 Plug portion 64 Insulation layer 65 Insulator portion 71 Opening 72 Wiring 73 Insulation layer 74 Opening 75 Wiring 76 Bonding material 77 Electronic component 81 Metal plate 81a, 81b Metal layer 82 Metal pattern 91 Insulating substrate 92 Metal pattern 93 Metal layer

Claims

1. a first chip mounting portion, a second chip mounting portion, a first semiconductor chip having a main surface and a back surface opposite to the main surface, and mounted on the first chip mounting portion, a second semiconductor chip having a main surface and a back surface opposite to the main surface, and mounted on the second chip mounting portion, a first insulator portion that seals at least a part of the first chip mounting portion, at least a part of the second chip mounting portion, the first semiconductor chip, and the second semiconductor chip, a first wiring formed of a plating film on the first insulator portion, a second insulator portion formed on the first insulator portion and sealing the first wiring, and comprising the first semiconductor chip has a source electrode formed on the main surface side of the first semiconductor chip and a drain electrode formed on the back surface side of the first semiconductor chip, and the drain electrode is mounted on the first chip mounting portion in a direction facing the first chip mounting portion, the second semiconductor chip has a source electrode formed on the main surface side of the second semiconductor chip and a drain electrode formed on the back surface side of the second semiconductor chip, and the source electrode is mounted on the second chip mounting portion in a direction facing the second chip mounting portion, the source electrode of the first semiconductor chip has an exposed portion exposed from a first opening of the first insulator portion, the exposed portion of the source electrode of the first semiconductor chip is exposed at a position lower than the upper surface of the first insulator portion, the first opening of the first insulator portion is located inside the outer periphery of the main surface of the first semiconductor chip, the drain electrode of the second semiconductor chip has an exposed portion exposed from a second opening of the first insulator portion, the exposed portion of the drain electrode of the second semiconductor chip is exposed at a position lower than the upper surface of the first insulator portion, the second opening of the first insulator portion is located inside the outer periphery of the back surface of the second semiconductor chip, the first wiring is formed so as to contact the exposed portion of the source electrode of the first semiconductor chip, the exposed portion of the drain electrode of the second semiconductor chip, and the first insulator portion, a semiconductor device in which the source electrode of the first semiconductor chip and the drain electrode of the second semiconductor chip are electrically connected by the first wiring.

2. In the semiconductor device according to claim 1, the first wiring is The exposed portion of the source electrode of the first semiconductor chip, the exposed portion of the drain electrode of the second semiconductor chip, and a first plating film in contact with the first insulator portion; A second plating film formed on the first plating film; A semiconductor device having the above.

3. In the semiconductor device according to claim 1, A third semiconductor chip sealed by the first insulator portion and having a plurality of electrodes; A second wiring formed on the first insulator portion and made of a plating film; Further comprising: The first semiconductor chip further has a gate electrode formed on the main surface side of the first semiconductor chip, The second wiring is sealed by the second insulator portion, A semiconductor device in which a first electrode among the plurality of electrodes of the third semiconductor chip and the gate electrode of the first semiconductor chip are electrically connected by the second wiring.

4. In the semiconductor device according to claim 3, A semiconductor device further comprising a third chip mounting portion on which at least a part is sealed by the first insulator portion and on which the third semiconductor chip is mounted.

5. In the semiconductor device according to claim 1, A semiconductor device in which the back surface on the side opposite to the surface on which the first semiconductor chip of the first chip mounting portion is placed, the back surface on the side opposite to the surface on which the second semiconductor chip of the second chip mounting portion is placed, and the back surface of the first insulator portion are on the same plane.

6. In the semiconductor device according to claim 1, A semiconductor device in which the first chip mounting portion and the second chip mounting portion are exposed on the back surface of the first insulator portion.

7. In the semiconductor device according to claim 3, The second semiconductor chip further has a gate electrode formed on the main surface side of the second semiconductor chip, Further comprising a conductor portion that is sealed by the first insulator portion, faces the gate electrode of the second semiconductor chip, and is electrically connected, A semiconductor device in which the first chip mounting portion and the second chip mounting portion are exposed on the back surface of the first insulator portion, and the conductor portion is not exposed.

8. In the semiconductor device according to claim 7, Further comprising a third wiring formed on the first insulator portion and made of a plating film, The third wiring is sealed by the second insulator portion, A semiconductor device in which a second electrode among the plurality of electrodes of the third semiconductor chip and the conductor portion are electrically connected including the third wiring in a conduction path.

9. In the semiconductor device according to claim 8, further comprising a conductive plug portion that is sealed by the first insulator portion, disposed between the conductor portion and the third wiring, and electrically connects the conductor portion and the third wiring, wherein the gate electrode of the second semiconductor chip is electrically connected to the second electrode of the third semiconductor chip via the conductor portion, the plug portion, and the third wiring. A semiconductor device.

10. In the semiconductor device according to claim 3, a semiconductor device, wherein a control circuit for controlling the first semiconductor chip is formed in the third semiconductor chip.

11. In the semiconductor device according to claim 10, a field effect transistor for a high side switch is formed in the first semiconductor chip, and a field effect transistor for a low side switch is formed in the second semiconductor chip. A semiconductor device.

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