Semiconductor device

Abstract

To provide a semiconductor device which makes it difficult to replicate the semiconductor device through reverse engineering.SOLUTION: A semiconductor device includes a plurality of first signal output circuits and a plurality of second signal output circuits. Each signal output circuit has: a first P-channel type transistor and a first N-channel type transistor connected in series; and a second P-channel type transistor and a second N-channel type transistor connected in series. The first and second signal output circuits have the same layout. In the first signal output circuit, a threshold voltage of at least one of the first P-channel type transistor and the second N-channel type transistor is higher than threshold voltages of the second P-channel type transistor and the first N-channel type transistor. In the second signal output circuit, a threshold voltage of at least one of the second P-channel type transistor and the first N-channel type transistor is higher than threshold voltages of the first P-channel type transistor and the second N-channel type transistor.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a protection technique for a semiconductor device from reverse engineering.

Background Art

[0002] In recent years, improper reverse engineering of semiconductor devices has been increasing. As reverse engineering techniques, not only optical analysis from the chip surface on which a semiconductor device is mounted, but also a technique of peeling off wiring layers one by one, photographing them, superimposing the obtained images, and extracting wiring information with software tools to reproduce a circuit diagram is also used.

[0003] Various methods for preventing reverse engineering have been proposed (see, for example, Patent Documents 1 to 9). In order to prevent reverse engineering, for example, by devising the wiring layer or using a diffusion layer or bulk layer below the wiring layer, the characteristics and connection information of transistors are changed so that the function cannot be reproduced only by reading the wiring layer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

[0005] In general, a special process is required to make it difficult to reproduce a semiconductor device by reverse engineering, which causes problems such as an increase in the process development period and cost. An object of the present invention is to provide a semiconductor device that makes it difficult to reproduce a semiconductor device by reverse engineering. [Means for Solving the Problems]

[0006] The semiconductor device according to the present invention includes a plurality of first signal output circuits and a plurality of second signal output circuits. Each of the first signal output circuit and the second signal output circuit includes a first P-channel transistor and a first N-channel transistor connected in series between a signal line for supplying a power supply voltage and a signal line for supplying a reference voltage, and a second P-channel transistor and a second N-channel transistor connected in series between the signal line for supplying the power supply voltage and the signal line for supplying the reference voltage. The first signal output circuit and the second signal output circuit have the same layout. In the first signal output circuit, the threshold voltage of at least one of the first P-channel transistor and the second N-channel transistor is higher than the threshold voltage of the second P-channel transistor and the first N-channel transistor. In the second signal output circuit, the threshold voltage of at least one of the second P-channel transistor and the first N-channel transistor is higher than the threshold voltage of the first P-channel transistor and the second N-channel transistor. [Advantages of the Invention]

[0007] According to the present invention, it is possible to provide a semiconductor device that makes it difficult to reproduce a semiconductor device by reverse engineering.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0010] (First Embodiment) The first embodiment of the present invention will be described. The semiconductor device in the first embodiment has a plurality of signal output circuits as shown in FIGS. 1, 2, 4, and 5. FIGS. 1, 2, 4, and 5 are diagrams showing examples of the signal output circuits included in the semiconductor device in the first embodiment.

[0011] The signal output circuit shown in FIG. 1 will be described. FIG. 1(A) is a schematic cross-sectional view schematically showing the configuration of the signal output circuit 102A as a first example. In FIG. 1(A), the logic circuit A101 receives the signal IN1 and outputs the signal OUT1. The logic circuit B103 receives the signal IN2 and outputs the signal OUT2. The signal output circuit 102A is connected between the logic circuit A101 and the logic circuit B103, receives the signal OUT1 output from the logic circuit A101, and outputs the signal IN2 input to the logic circuit B103.

[0012] The signal output circuit 102A has an N-well 112 having an N-type conductivity type formed on a substrate (P-type semiconductor substrate) 111. On the surface of the N-well 112, P+ regions 113, 114A having a P-type conductivity type and an N+ region 115 having an N-type conductivity type are formed. The P+ region 113 and the P+ region 114A are not separated and are formed in contact (as one region). The N+ region 115 is formed separately from the P+ regions 113, 114A. Also, a P+ region 116 having a P-type conductivity type is formed on the surface of the substrate (P-type semiconductor substrate) 111. The P+ region 113 is connected to the signal line of the signal OUT1, and the P+ region 114A is connected to the signal line of the signal IN2. The N+ region 115 is connected to the signal line supplying the power supply voltage VDD, and the P+ region 116 is connected to the signal line supplying the reference voltage VSS.

[0013] In the example shown in FIG. 1(A), the signal line of the signal OUT1 output from the logic circuit A101 and the signal line of the signal IN2 input to the logic circuit B103 are connected via the non-separated (contacting) P+ regions 113 and 114A that the signal output circuit 102A has. That is, as shown in FIG. 1(B), the logic circuit A101 and the logic circuit B103 are connected via the parasitic resistance R11 formed by the P+ region 113 and the P+ region 114A. Therefore, the signal output from the logic circuit A101 is input to the logic circuit B103 with the same logical value (logical level) via the signal output circuit 102A. That is, the signal output circuit 102A transmits and outputs the signal OUT1 output from the logic circuit A101 with the same logical value (logical level).

[0014] Next, the signal output circuit shown in FIG. 2 will be described. FIG. 2(A) is a schematic cross-sectional view schematically showing the configuration of the signal output circuit 102B as a second example. In FIG. 2(A), the same components as those shown in FIG. 1(A) are denoted by the same reference numerals, and redundant descriptions are omitted. The signal output circuit 102B as a second example is different from the signal output circuit 102A as a first example in that an N+ region 114B is formed on the surface of the N well 112 instead of the P+ region 114A.

[0015] In the signal output circuit 102B, a P+ region 113 having a P-type conductivity type, an N+ region 114B having an N-type conductivity type, and an N+ region 115 having an N-type conductivity type are formed on the surface of the N well 112. The P+ region 113 and the N+ region 114B are formed in contact (so as to form a PN junction). The N+ region 115 is formed separately from the P+ region 113 and the N+ region 114B. The N+ region 114B is connected to the signal line of the signal IN2.

[0016] In the example shown in FIG. 2(A), the signal line of the signal OUT1 output from the logic circuit A101 and the signal line of the signal IN2 input to the logic circuit B103 are connected via the P+ region 113 and the N+ region 114B of the signal output circuit 102B. Further, the N+ region 114B of the signal output circuit 102B is connected to the N+ region 115 connected to the signal line supplying the power supply voltage VDD via the N well 112. That is, as shown in FIG. 2(B), the logic circuit A101 and the logic circuit B103 are connected via the parasitic diode D11 formed by the PN junction of the P+ region 113 and the N+ region 114B. Also, the signal line of the signal line IN2 is connected to the signal line supplying the power supply voltage VDD via the parasitic resistance R12 formed by the N well 112. Therefore, regardless of the logical value (logical level) of the signal output from the logic circuit A101, the signal of the power supply voltage VDD (high level) is input to the logic circuit B103 as the signal IN2. That is, the signal output circuit 102B outputs a signal of the power supply voltage VDD (high level) regardless of the signal OUT1 output from the logic circuit A101.

[0017] Here, as described above, the signal output circuit 102A as the first example and the signal output circuit 102B as the second example are different only in the conductivity type of the diffusion region formed on the surface of the N well 112 and have the same shape including the wiring and contacts to be connected, as shown in FIGS. 3(A) and 3(B). That is, the layouts of the signal output circuit 102A and the signal output circuit 102B are the same. FIG. 3(A) is a schematic plan view schematically showing the configuration of the signal output circuit 102A as the first example described above, and FIG. 3(B) is a schematic plan view schematically showing the configuration of the signal output circuit 102B as the second example described above. FIGS. 3(A) and 3(B) show a part of the signal output circuits 102A and 102B.

[0018] As shown in FIG. 3(A), in the signal output circuit 102A, a P+ region 113 and a P+ region 114A are formed in contact with the surface of the N well 112. The P+ region 113 is connected to the signal line of the signal OUT1 via a contact 121, and the P+ region 114A is connected to the signal line of the signal IN2 via a contact 122. Also, as shown in FIG. 3(B), in the signal output circuit 102B, a P+ region 113 and an N+ region 114B are formed in contact with the surface of the N well 112 in the same layout as the P+ region 113 and the P+ region 114A that the signal output circuit 102A has. The P+ region 113 is connected to the signal line of the signal OUT1 via a contact 123, and the N+ region 114B is connected to the signal line of the signal IN2 via a contact 124.

[0019] In this way, the signal output circuit 102A and the signal output circuit 102B have the same layout and wiring shape. By switching the conductivity type of the diffusion region formed on the surface of the N well 112, parasitic resistance and parasitic diodes can be realized with the same layout. The switching of the conductivity type of the diffusion region can be performed, for example, at the time of creation, by changing the mask pattern or the like when performing impurity implantation. Thereby, it is possible to make it indistinguishable in appearance, and switch between a signal output circuit that outputs the input signal as it is and a signal output circuit that outputs a fixed potential (power supply voltage VDD), so that it is possible to disguise the logical function of a series of circuits including the signal output circuit, and make it difficult to reproduce the semiconductor device by reverse engineering.

[0020] Next, the signal output circuit shown in FIG. 4 will be described. FIG. 4(A) is a schematic cross-sectional view schematically showing the configuration of the signal output circuit 202A as a third example. In FIG. 4(A), the logic circuit A201 receives the signal IN1 and outputs the signal OUT1. The logic circuit B203 receives the signal IN2 and outputs the signal OUT2. The signal output circuit 202A is connected between the logic circuit A201 and the logic circuit B203, receives the signal OUT1 output from the logic circuit A201, and outputs the signal IN2 input to the logic circuit B203.

[0021] The signal output circuit 202A has an N+ region 212, 213A having an N-type conductivity type and a P+ region 214 having a P-type conductivity type formed on the surface of a substrate (P-type semiconductor substrate) 211. The N+ region 212 and the N+ region 213A are not separated and are formed in contact (as one region). The P+ region 214 is formed separately from the N+ regions 212, 213A. The N+ region 212 is connected to the signal line of the signal OUT1, and the N+ region 213A is connected to the signal line of the signal IN2. The P+ region 214 is connected to the signal line that supplies the reference voltage VSS.

[0022] In the example shown in FIG. 4(A), the signal line of the signal OUT1 output from the logic circuit A201 and the signal line of the signal IN2 input to the logic circuit B203 are connected via the non-separated (in contact) N+ region 212 and N+ region 213A that the signal output circuit 202A has. That is, as shown in FIG. 4(B), the logic circuit A201 and the logic circuit B203 are connected via the parasitic resistance R21 formed by the N+ region 212 and the N+ region 213A. Therefore, the signal output from the logic circuit A201 is input to the logic circuit B203 with the same logic value (logic level) as it is via the signal output circuit 202A. That is, the signal output circuit 202A transmits and outputs the signal OUT1 output from the logic circuit A201 with the same logic value (logic level) as it is.

[0023] Next, the signal output circuit shown in FIG. 5 will be described. FIG. 5(A) is a schematic cross-sectional view schematically showing the configuration of the signal output circuit 202B as a fourth example. In FIG. 5(A), the same components as those shown in FIG. 4(A) are denoted by the same reference numerals, and redundant descriptions are omitted. The signal output circuit 202B as a fourth example is different from the signal output circuit 202A as a third example in that a P+ region 213B is formed on the surface of the substrate (P-type semiconductor substrate) 211 instead of the N+ region 213A.

[0024] The signal output circuit 202B has an N+ region 212 having an N-type conductivity type, a P+ region 213B having a P-type conductivity type, and a P+ region 214 having a P-type conductivity type formed on the surface of a substrate (P-type semiconductor substrate) 211. The N+ region 212 and the P+ region 213B are formed in contact (so as to form a PN junction). The P+ region 214 is formed separately from the N+ region 212 and the P+ region 213B. The P+ region 213B is connected to the signal line of the signal IN2.

[0025] In the example shown in FIG. 5(A), the signal line of the signal OUT1 output from the logic circuit A201 and the signal line of the signal IN2 input to the logic circuit B203 are connected via the N+ region 212 and the P+ region 213B included in the signal output circuit 202B. Further, the P+ region 213B of the signal output circuit 202B is connected to the P+ region 214 connected to the signal line supplying the reference voltage VSS via the substrate (P-type semiconductor substrate) 211. That is, as shown in FIG. 5(B), the logic circuit A201 and the logic circuit B203 are connected via the parasitic diode D21 formed by the PN junction of the N+ region 212 and the P+ region 213B. Also, the signal line of the signal line IN2 is connected to the signal line supplying the reference voltage VSS via the parasitic resistance R22 formed by the P-type semiconductor substrate 211. Therefore, regardless of the logic value (logic level) of the signal output from the logic circuit A201, a signal of the reference voltage VSS (low level) is input to the logic circuit B203 as the signal IN2. That is, the signal output circuit 202B outputs a signal of the reference voltage VSS (low level) regardless of the signal OUT1 output from the logic circuit A201.

[0026] Here, as the third example of the signal output circuit 202A and the fourth example of the signal output circuit 202B described above, as shown in FIGS. 6(A) and 6(B), only the conductivity type of the diffusion regions formed on the surface of the substrate (P-type semiconductor substrate) 211 is different, and they have the same shape including the connecting wirings, contacts, etc. That is, the layouts of the signal output circuit 202A and the signal output circuit 202B are the same. FIG. 6(A) is a schematic plan view schematically showing the configuration of the signal output circuit 202A as the third example described above, and FIG. 6(B) is a schematic plan view schematically showing the configuration of the signal output circuit 202B as the fourth example described above. FIGS. 6(A) and 6(B) show a part of the signal output circuits 202A and 202B.

[0027] As shown in FIG. 6(A), in the signal output circuit 202A, an N+ region 212 and an N+ region 213A are formed in contact with the surface of the substrate (P-type semiconductor substrate) 211. The N+ region 212 is connected to the signal line of signal OUT1 via a contact 221, and the N+ region 213A is connected to the signal line of signal IN2 via a contact 222. Further, as shown in FIG. 6(B), in the signal output circuit 202B, with the same layout as the N+ region 212 and the N+ region 213A of the signal output circuit 202A, an N+ region 212 and a P+ region 213B are formed in contact with the surface of the substrate (P-type semiconductor substrate) 211. The N+ region 212 is connected to the signal line of signal OUT1 via a contact 223, and the P+ region 213B is connected to the signal line of signal IN2 via a contact 224.

[0028] In this way, the signal output circuits 202A and 202B have the same layout and wiring shape. By switching the conductivity type of the diffusion region formed on the surface of the substrate (P-type semiconductor substrate) 211, parasitic resistance and parasitic diodes can be realized with the same layout. The switching of the conductivity type of the diffusion region can be performed, for example, at the time of creation, by changing the mask pattern or the like when performing impurity implantation. As a result, it is possible to switch between a signal output circuit that outputs the input signal as it is without being distinguishable in appearance and a signal output circuit that outputs a fixed potential (reference voltage VSS), thereby disguising the logical function of a series of circuits including the signal output circuit and making it difficult to reproduce the semiconductor device by reverse engineering.

[0029] Further, for the signal output circuits 102A, 102B, 202A, and 202B, the layout and wiring shape may be made the same, and by switching the conductivity type of the diffusion region, it may be made indistinguishable in appearance, and it may be switched between a signal output circuit that outputs the input signal as it is, a signal output circuit that outputs a fixed potential of the power supply voltage VDD, or a signal output circuit that outputs a fixed potential of the reference voltage VSS.

[0030] FIG. 7 is a diagram showing an application example of the semiconductor device in the present embodiment. In FIG. 7, 301, 303, 311, 313, 321, and 323 are logic circuits that realize a predetermined logical function, and 302, 312, and 322 are the signal output circuits in the present embodiment described above. The signal output circuits 302, 312, and 322 have the same layout, wiring, etc. as described above, but can realize different functions by switching the conductivity type of the diffusion region. As shown in FIG. 7, by connecting the signal output circuit in the present embodiment between the logic circuits and appropriately controlling the conductivity type of the diffusion region in the signal output circuit, it becomes possible to disguise the logical function of a series of circuits including the signal output circuit.

[0031] Referring to FIGS. 8 to 11, a specific application example of the semiconductor device in the first embodiment will be described. Hereinafter, an example having a signal output circuit and four inverters as logic circuits in this embodiment will be described, but this is just an example, and the present invention is not limited to this example.

[0032] FIG. 8 is a schematic plan view schematically showing a first application example. Each of the four inverters (INV) 401, 402, 403, and 404 has a P+ region 413 serving as a source and a P+ region 414 serving as a drain formed on the surface of an N well 411 having an N-type conductivity type formed on a substrate. The P+ region 413 and the P+ region 414 are separated from each other. Also, each of the inverters (INV) 401, 402, 403, and 404 has an N+ region 415 serving as a source and an N+ region 416 serving as a drain formed on the surface of a P well 412 having a P-type conductivity type formed on the substrate. The N+ region 415 and the N+ region 416 are separated from each other. Further, a gate electrode 417 is formed via a gate insulating film (not shown) on the region between the P+ region 413 and the P+ region 414 and on the region between the N+ region 415 and the N+ region 416. The gate electrode 417 is made of, for example, polysilicon.

[0033] The P+ region 413 serving as a source is connected to a metal wiring 418 for supplying a power supply voltage VDD via a contact 420, and the N+ region 415 serving as a source is connected to a metal wiring 419 for supplying a reference voltage VSS via a contact 421. The gate electrode 417 is connected to a metal wiring 422 as an input wiring via a contact 423. The P+ region 414 and the N+ region 416 serving as drains are connected to a metal wiring 424 as an output wiring via contacts 425 and 426.

[0034] The signal output circuit 405A is formed such that the P+ region 431 and the P+ region 432 are in contact (as one region) with the surface of the N well 411 formed on the substrate. Also, the signal output circuit 405A is formed such that the N+ region 433 and the N+ region 434 are in contact (as one region) with the surface of the P well 412 formed on the substrate.

[0035] The output wiring 424 of the first inverter (INV#1) 401 is connected to the N+ region 433 of the signal output circuit 405A via the via 441, the metal wiring 442, the via 443, the metal wiring 444, and the contact 445. The output wiring 424 of the second inverter (INV#2) 402 is connected to the P+ region 431 of the signal output circuit 405A via the contact 437. The input wiring 422 of the third inverter (INV#3) 403 is connected to the P+ region 432 of the signal output circuit 405A via the contact 438. The input wiring 422 of the fourth inverter (INV#4) 404 is connected to the N+ region 434 of the signal output circuit 405A via the contact 466, the metal wiring 447, the via 448, the metal wiring 449, and the via 450.

[0036] That is, in the example shown in FIG. 8, the output wiring 424 of the first inverter (INV#1) 401 and the input wiring 422 of the fourth inverter (INV#4) 404 are connected via the N+ regions 433 and 434 of the signal output circuit 405A. Also, the output wiring 424 of the second inverter (INV#2) 402 and the input wiring 422 of the third inverter (INV#3) 403 are connected via the P+ regions 431 and 432 of the signal output circuit 405A. That is, as shown in the circuit configuration, the first inverter (INV#1) 401 and the fourth inverter (INV#4) 404 are connected via the parasitic resistance R41 formed by the N+ regions 433 and 434. The second inverter (INV#2) 402 and the third inverter (INV#3) 403 are connected via the parasitic resistance R42 formed by the P+ regions 431 and 432. Therefore, in the example shown in FIG. 8, the fourth inverter (INV#4) 404 outputs a signal with the same logical value (logic level) as the signal input to the first inverter (INV#1) 401, and the third inverter (INV#3) 403 outputs a signal with the same logical value (logic level) as the signal input to the second inverter (INV#2) 402.

[0037] FIG. 9 is a schematic plan view schematically showing a second application example. In FIG. 9, the same components as those shown in FIG. 8 are denoted by the same reference numerals, and redundant descriptions are omitted. The semiconductor device shown in FIG. 9 has the same layout as the semiconductor device shown in FIG. 8 including the shape of the wiring. The example shown in FIG. 9 is different from the example shown in FIG. 8 in that an N+ region 435 is formed on the surface of the N well 411 instead of the P+ region 432, and a P+ region 436 is formed on the surface of the P well 412 instead of the N+ region 434.

[0038] That is, in the signal output circuit 405B shown in FIG. 9, a P+ region 431 and an N+ region 435 are formed in contact with (so as to form a PN junction) the surface of an N well 411 formed on a substrate. Also, in the signal output circuit 405B, an N+ region 433 and a P+ region 436 are formed in contact with (so as to form a PN junction) the surface of a P well 412 formed on the substrate. The input wiring 422 of the third inverter (INV#3) 403 is connected to the N+ region 435 of the signal output circuit 405B via a contact 438, and the input wiring 422 of the fourth inverter (INV#4) 404 is connected to the P+ region 436 of the signal output circuit 405B via a contact 466, a metal wiring 447, a via 448, a metal wiring 449, and a via 450.

[0039] In the example shown in FIG. 9, the output wiring 424 of the first inverter (INV#1) 401 and the input wiring 422 of the fourth inverter (INV#4) 404 are connected via the N+ region 433 and the P+ region 436 of the signal output circuit 405B. Also, the output wiring 424 of the second inverter (INV#2) 402 and the input wiring 422 of the third inverter (INV#3) 403 are connected via the P+ region 431 and the N+ region 435 of the signal output circuit 405B. That is, as shown in the circuit configuration, the first inverter (INV#1) 401 and the fourth inverter (INV#4) 404 are connected via a parasitic diode D41 formed by the PN junction of the N+ region 433 and the P+ region 436. The second inverter (INV#2) 402 and the third inverter (INV#3) 403 are connected via a parasitic diode D42 formed by the PN junction of the P+ region 431 and the N+ region 435. Therefore, in the example shown in FIG. 9, the fourth inverter (INV#4) 404 outputs a high-level (power supply voltage VDD) signal regardless of the signal input to the first inverter (INV#1) 401, and the third inverter (INV#3) 403 outputs a low-level (reference voltage VSS) signal regardless of the signal input to the second inverter (INV#2) 402.

[0040] FIG. 10 is a schematic plan view schematically showing a third application example. In FIG. 10, the same components as those shown in FIG. 8 are denoted by the same reference numerals, and redundant descriptions are omitted. The semiconductor device shown in FIG. 10 has the same layout including the wiring shape as the semiconductor devices shown in FIGS. 8 and 9. The example shown in FIG. 10 is different from the example shown in FIG. 8 in that an N+ region 435 is formed on the surface of the N well 411 instead of the P+ region 432. That is, in the signal output circuit 405C shown in FIG. 10, a P+ region 431 and an N+ region 435 are formed in contact with (so as to form a PN junction) the surface of the N well 411 formed on the substrate. The input wiring 422 of the third inverter (INV#3) 403 is connected to the N+ region 435 of the signal output circuit 405C via a contact 438.

[0041] In the example shown in FIG. 10, the output wiring 424 of the first inverter (INV#1) 401 and the input wiring 422 of the fourth inverter (INV#4) 404 are connected via the N+ regions 433 and 434 of the signal output circuit 405C. Also, the output wiring 424 of the second inverter (INV#2) 402 and the input wiring 422 of the third inverter (INV#3) 403 are connected via the P+ region 431 and the N+ region 435 of the signal output circuit 405C. That is, as shown in the circuit configuration, the first inverter (INV#1) 401 and the fourth inverter (INV#4) 404 are connected via a parasitic resistance R41 formed by the N+ regions 433 and 434. The second inverter (INV#2) 402 and the third inverter (INV#3) 403 are connected via a parasitic diode D42 formed by the PN junction between the P+ region 431 and the N+ region 435. Therefore, in the example shown in FIG. 10, the fourth inverter (INV#4) 404 outputs a signal having the same logical value (logical level) as the signal input to the first inverter (INV#1) 401, and the third inverter (INV#3) 403 outputs a low-level (reference voltage VSS) signal regardless of the signal input to the second inverter (INV#2) 402.

[0042] FIG. 11 is a schematic plan view schematically showing a fourth application example. In FIG. 11, the same components as those shown in FIG. 8 are denoted by the same reference numerals, and redundant descriptions are omitted. The semiconductor device shown in FIG. 11 has the same layout including the wiring shape as the semiconductor devices shown in FIGS. 8, 9, and 10. The example shown in FIG. 11 is different from the example shown in FIG. 8 in that a P+ region 436 is formed on the surface of a P well 412 instead of the N+ region 434. That is, in the signal output circuit 405D shown in FIG. 11, an N+ region 433 and a P+ region 436 are formed in contact with (so as to form a PN junction) on the surface of a P well 412 formed in the substrate. The input wiring 422 of the fourth inverter (INV#4) 404 is connected to the P+ region 436 of the signal output circuit 405D via a contact 466, a metal wiring 447, a via 448, a metal wiring 449, and a via 450.

[0043] In the example shown in FIG. 11, the output wiring 424 of the first inverter (INV#1) 401 and the input wiring 422 of the fourth inverter (INV#4) 404 are connected via the N+ region 433 and the P+ region 436 of the signal output circuit 405D. Also, the output wiring 424 of the second inverter (INV#2) 402 and the input wiring 422 of the third inverter (INV#3) 403 are connected via the P+ region 431 and the P+ region 432 of the signal output circuit 405D. That is, as shown in the circuit configuration, the first inverter (INV#1) 401 and the fourth inverter (INV#4) 404 are connected via a parasitic diode D41 formed by the PN junction of the N+ region 433 and the P+ region 436. The second inverter (INV#2) 402 and the third inverter (INV#3) 403 are connected via a parasitic resistance R42 formed by the P+ region 431 and the P+ region 432. Therefore, in the example shown in FIG. 11, the fourth inverter (INV#4) 404 outputs a signal of a high level (power supply voltage VDD) regardless of the signal input to the first inverter (INV#1) 401, and the third inverter (INV#3) 403 outputs a signal having the same logical value (logical level) as the signal input to the second inverter (INV#2) 402.

[0044] As shown in an example of FIGS. 8 to 11, by switching the conductivity type of the diffusion region of the signal output circuit provided between logic circuits with the same layout and wiring, it becomes possible to disguise the logic function of the circuit, and it is possible to make it difficult to reproduce the semiconductor device by reverse engineering.

[0045] (Second Embodiment) Next, a second embodiment of the present invention will be described. The semiconductor device in the second embodiment has a plurality of signal output circuits as shown in FIGS. 12(A) and 12(B). FIGS. 12(A) and 12(B) are diagrams showing examples of the signal output circuits included in the semiconductor device in the second embodiment.

[0046] The first signal output circuit 500A shown in FIG. 12(A) includes P-channel field effect transistors (hereinafter also referred to as "P-channel transistors") MP1 and MP2 and N-channel field effect transistors (hereinafter also referred to as "N-channel transistors") MN1 and MN2. Between the signal line for supplying the power supply voltage VDD and the signal line for supplying the reference voltage VSS, the P-channel transistor MP1 and the N-channel transistor MN1 are connected in series in this order from the signal line side for supplying the power supply voltage VDD. Also, between the signal line for supplying the power supply voltage VDD and the signal line for supplying the reference voltage VSS, the P-channel transistor MP2 and the N-channel transistor MN2 are connected in series in this order from the signal line side for supplying the power supply voltage VDD.

[0047] The gates of the P-channel transistor MP1 and the N-channel transistor MN1 are connected to the connection point ND2 between the P-channel transistor MP2 and the N-channel transistor MN2, and the gates of the P-channel transistor MP2 and the N-channel transistor MN2 are connected to the connection point ND1 between the P-channel transistor MP1 and the N-channel transistor MN1. Also, the voltage at the connection point ND2 between the P-channel transistor MP2 and the N-channel transistor MN2 is output as the output signal SOUT.

[0048] That is, for the P-channel transistor MP1, the source is connected to the signal line supplying the power supply voltage VDD, the gate is connected to the connection point between the drain of the P-channel transistor MP2 and the drain of the N-channel transistor MN2, and the drain is connected to the drain of the N-channel transistor MN1. Also, for the N-channel transistor MN1, the source is connected to the signal line supplying the reference voltage VSS, and the gate is connected to the connection point between the drain of the P-channel transistor MP2 and the drain of the N-channel transistor MN2. For the P-channel transistor MP2, the source is connected to the signal line supplying the power supply voltage VDD, the gate is connected to the connection point between the drain of the P-channel transistor MP1 and the drain of the N-channel transistor MN1, and the drain is connected to the drain of the N-channel transistor MN2. Also, for the N-channel transistor MN2, the source is connected to the signal line supplying the reference voltage VSS, and the gate is connected to the connection point between the drain of the P-channel transistor MP1 and the drain of the N-channel transistor MN1. The voltage at the connection point between the drain of the P-channel transistor MP1 and the drain of the N-channel transistor MN1 is output as the signal SOUT.

[0049] Here, the threshold voltages of the P-channel transistors MP1 and MP2 and the N-channel transistor MN1 are general (standard) threshold voltages, and the threshold voltage of the N-channel transistor MN2 is a value higher than the general (standard) threshold voltage. Control of the threshold voltage of the transistor can be achieved by channel implant doping control or the like that changes the doping amount for the channel. By using a transistor with a high threshold voltage as the N-channel transistor MN2 in this way, after power-on, the voltage at the connection point ND1 between the P-channel transistor MP1 and the N-channel transistor MN1 is fixed at a low level (L), and the voltage at the connection point ND2 between the P-channel transistor MP2 and the N-channel transistor MN2 is fixed at a high level (H). The first signal output circuit 500A fixedly outputs a high-level (H) signal as the output signal SOUT.

[0050] The second signal output circuit 500B shown in FIG. 12(B) has P-channel transistors MP1, MP2 and N-channel transistors MN1, MN2 connected in the same manner as the first signal output circuit 500A shown in FIG. 12(A). In the second signal output circuit, the threshold voltages of the P-channel transistors MP1, MP2 and the N-channel transistor MN2 are general (standard) threshold voltages, and the threshold voltage of the N-channel transistor MN1 is higher than the general (standard) threshold voltage. By using a transistor with a high threshold voltage as the N-channel transistor MN1 in this way, after the power is turned on, the voltage at the connection point ND1 between the P-channel transistor MP1 and the N-channel transistor MN1 is fixed at a high level (H), and the voltage at the connection point ND2 between the P-channel transistor MP2 and the N-channel transistor MN2 is fixed at a low level (L). The second signal output circuit 500B fixedly outputs a signal of a low level (L) as the output signal SOUT.

[0051] FIG. 13(A) is a schematic plan view schematically showing the configuration of the first signal output circuit 500A. The first signal output circuit 500A has a P+ region 503 serving as the sources of the P-channel transistors MP1, MP2 formed on the surface of an N-well 501 having an N-type conductivity type formed on a substrate. On the surface of the N-well 501, a P+ region 504 serving as the drain of the P-channel transistor MP1 and a P+ region 505 serving as the drain of the P-channel transistor MP2 are formed. The P+ region 503, the P+ region 504, and the P+ region 505 are separated from each other.

[0052] Also, an N+ region 506 serving as the sources of the N-channel transistors MN1, MN2 is formed on the surface of a P-well 502 having a P-type conductivity type formed on the substrate. On the surface of the P-well 502, an N+ region 507 serving as the drain of the N-channel transistor MN1 and an N+ region 508 serving as the drain of the N-channel transistor MN2 are formed. The N+ region 506, the N+ region 507, and the N+ region 508 are separated from each other.

[0053] Over the region between the P+ region 503 and the P+ region 504, and over the region between the N+ region 506 and the N+ region 507, gate electrodes 509 of a P-channel transistor MP1 and an N-channel transistor MN1 are formed via a gate insulating film (not shown). Also, over the region between the P+ region 503 and the P+ region 505, and over the region between the N+ region 506 and the N+ region 508, gate electrodes 510 of a P-channel transistor MP2 and an N-channel transistor MN2 are formed via a gate insulating film (not shown). The gate electrodes 509, 510 are made of, for example, polysilicon.

[0054] The P+ region 503 serving as the source of the P-channel transistors MP1, MP2 is connected via a contact 512 to a metal wiring 511 that supplies a power supply voltage VDD. The N+ region 506 serving as the source of the N-channel transistors MN1, MN2 is connected via a contact 514 to a metal wiring 513 that supplies a reference voltage VSS. A metal wiring 515 is connected via contacts 516, 517 to the P+ region 504 serving as the drain of the P-channel transistor MP1 and the N+ region 507 serving as the drain of the N-channel transistor MN1, respectively, and is connected via a contact 518 to the gate electrodes 510 of the P-channel transistor MP2 and the N-channel transistor MN2. Also, a metal wiring 519 is connected via contacts 520, 521 to the P+ region 505 serving as the drain of the P-channel transistor MP2 and the N+ region 508 serving as the drain of the N-channel transistor MN2, respectively, and is connected via a contact 522 to the gate electrodes 509 of the P-channel transistor MP1 and the N-channel transistor MN1. The metal wiring 519 is also a signal line that outputs an output signal OUT.

[0055] Here, in the first signal output circuit 500A, the channel 531A between the N+ region 506 and the N+ region 508 of the N-channel transistor MN2 has its doping amount with respect to the channel controlled during the fabrication of the transistor so as to increase the threshold voltage of the N-channel transistor MN2.

[0056] FIG. 13(B) is a schematic plan view schematically showing the configuration of the second signal output circuit 500B. In FIG. 13(B), the same components as those shown in FIG. 13(A) are denoted by the same reference numerals, and redundant descriptions are omitted. The second signal output circuit 500B has the same shape as the first signal output circuit 500A shown in FIG. 13(A), including the layout of each transistor MP1, MP2, MN1, MN2 and the wiring related thereto. However, in the second signal output circuit 500B, the channel 531B between the N+ regions 506 and 507 of the N-channel transistor MN1 in the second signal output circuit 500B has its doping amount with respect to the channel controlled during the manufacture of the transistor so as to increase the threshold voltage of the N-channel transistor MN1.

[0057] In this way, the signal output circuits 500A and 500B are configured to be the same including the layout of each transistor MP1, MP2, MN1, MN2 and the wiring related thereto, and by controlling the threshold voltages of the N-channel transistors MN1 and MN2, it is possible to switch between fixedly outputting a high-level (H) signal or a low-level (L) signal as the output signal SOUT. Thereby, it becomes possible to appropriately set whether to output a high-level (H) signal or a low-level (L) signal so as not to be distinguishable externally, and it is possible to make it difficult to reproduce the semiconductor device by reverse engineering.

[0058] Note that in the above description, the threshold voltages of the N-channel transistors MN1 and MN2 are controlled, but it is not limited to this example. For example, as shown in FIG. 14, even if the threshold voltages of each transistor MP1, MP2, MN1, MN2 are controlled, it is possible to appropriately set whether to output a high-level (H) signal or a low-level (L) signal so as not to be distinguishable externally, and it is possible to make it difficult to reproduce the semiconductor device by reverse engineering.

[0059] For example, as in the signal output circuit 500C shown in FIG. 14(A) and the signal output circuit 500D shown in FIG. 14(B), the threshold voltages of the P-channel transistors MP1 and MP2 may be controlled. In the case of the signal output circuit 500C shown in FIG. 14(A), when the threshold voltages of the P-channel transistor MP2 and the N-channel transistors MN1 and MN2 are set to general (standard) threshold voltages, and the threshold voltage of the P-channel transistor MP1 is set to a value higher than the general (standard) threshold voltage, a high-level (H) signal is fixedly output as the output signal SOUT. Also, in the case of the signal output circuit 500D shown in FIG. 14(B), when the threshold voltages of the P-channel transistor MP1 and the N-channel transistors MN1 and MN2 are set to general (standard) threshold voltages, and the threshold voltage of the P-channel transistor MP2 is set to a value higher than the general (standard) threshold voltage, a low-level (L) signal is fixedly output as the output signal SOUT.

[0060] Further, for example, as in the signal output circuit 500E shown in FIG. 14(C) and the signal output circuit 500F shown in FIG. 14(D), the threshold voltages of the P-channel transistors MP1 and MP2 and the N-channel transistors MN1 and MN2 may be controlled. In the case of the signal output circuit 500E shown in FIG. 14(C), when the threshold voltages of the P-channel transistor MP2 and the N-channel transistor MN1 are set to general (standard) threshold voltages, and the threshold voltages of the P-channel transistor MP1 and the N-channel transistor MN2 are set to values higher than the general (standard) threshold voltages, a high-level (H) signal is fixedly output as the output signal SOUT. Also, in the case of the signal output circuit 500F shown in FIG. 14(D), when the threshold voltages of the P-channel transistor MP1 and the N-channel transistor MN2 are set to general (standard) threshold voltages, and the threshold voltages of the P-channel transistor MP2 and the N-channel transistor MN1 are set to values higher than the general (standard) threshold voltages, a low-level (L) signal is fixedly output as the output signal SOUT.

[0061] Note that each of the above embodiments merely shows an example of the implementation of the present invention, and the technical scope of the present invention should not be construed in a limited manner by these. That is, the present invention can be implemented in various forms without departing from its technical idea or its main features.

Explanation of Reference Numerals

[0062] 101, 103, 201, 203 Logic circuits 102A, 102B, 202A, 202B Signal output circuits 111, 211 Substrates 112 N-well 113, 114A, 116, 213B, 214 P+ regions 115, 212, 213A N+ regions

Claims

1. including a plurality of first signal output circuits and a plurality of second signal output circuits, each of the first signal output circuit and the second signal output circuit has a first P-channel transistor and a first N-channel transistor connected in series between a signal line for supplying a power supply voltage and a signal line for supplying a reference voltage, and has a second P-channel transistor and a second N-channel transistor connected in series between the signal line for supplying the power supply voltage and the signal line for supplying the reference voltage, the first signal output circuit and the second signal output circuit have the same layout, in the first signal output circuit, the threshold voltage of at least one transistor among the first P-channel transistor and the second N-channel transistor is higher than the threshold voltages of the second P-channel transistor and the first N-channel transistor, in the second signal output circuit, the threshold voltage of at least one transistor among the second P-channel transistor and the first N-channel transistor is higher than the threshold voltages of the first P-channel transistor and the second N-channel transistor, and a semiconductor device characterized by this.

2. in the first signal output circuit, the threshold voltage of the first P-channel transistor is higher than the threshold voltage of the second P-channel transistor, in the second signal output circuit, the threshold voltage of the second P-channel transistor is higher than the threshold voltage of the first P-channel transistor, and the semiconductor device according to Claim 1, characterized by this.

3. in the first signal output circuit, the threshold voltage of the second N-channel transistor is higher than the threshold voltage of the first N-channel transistor, in the second signal output circuit, the threshold voltage of the first N-channel transistor is higher than the threshold voltage of the second N-channel transistor, and the semiconductor device according to Claim 1, characterized by this.

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