Semiconductor element

Abstract

To provide a semiconductor element with reliability improved.SOLUTION: A semiconductor element in an embodiment of the present invention includes: a gate structure having a side surface along a first direction and extending in a second direction intersecting with the first direction; a source / drain region disposed on the side surface of the gate structure; a plurality of channel layers separated from each other in a third direction intersecting with the first direction and the second direction and surrounded by the gate structure; and a plurality of internal spacers disposed between the gate structure and the source / drain region. The plurality of internal spacers are taller in the third direction as they are positioned further to a lower level and are thinner in the first direction as they are positioned further to the lower level.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] As the requirements for high performance, high speed, and / or multifunctionality of semiconductor devices increase, the integration density of semiconductor devices has been increasing. In manufacturing semiconductor devices with fine patterns corresponding to the trend of high integration of semiconductor devices, it is required to realize patterns having a fine width or a fine separation distance. In addition, in order to overcome the limitations of operating characteristics due to the reduction in the size of planar MOSFETs (metal oxide semiconductor FETs), efforts have been made to develop semiconductor devices including FinFETs having a three-dimensional channel.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the technical problems to be solved by the present invention is to provide a semiconductor device with improved integration density and reliability.

Means for Solving the Problems

[0004] A semiconductor device according to an exemplary embodiment has a side surface along a first direction, a gate structure extending in a second direction intersecting the first direction, a source / drain region disposed on the side surface of the gate structure, a plurality of channel layers spaced apart from each other along a third direction intersecting the first direction and the second direction and surrounded by the gate structure, and a plurality of internal spacers disposed between the gate structure and the source / drain region, wherein the plurality of internal spacers can have a greater height in the third direction as they are located at a lower level and a smaller thickness in the first direction as they are located at a lower level.

[0005] A semiconductor device according to an exemplary embodiment includes a plurality of channel layers spaced apart from each other along a third direction, a gate structure extending in a second direction intersecting the third direction and surrounding the plurality of channel layers, a source / drain region disposed on a side surface of the gate structure in a first direction intersecting the second direction and the third direction, and a plurality of internal spacers disposed between the gate structure and the source / drain region. Among the plurality of internal spacers, a first internal spacer located at the highest level may have a smaller height in the third direction and a larger thickness in the first direction than a second internal spacer located at another level.

[0006] A semiconductor device according to an exemplary embodiment has a side surface along a first direction, a gate structure extending in a second direction intersecting the first direction, a source / drain region disposed on the side surface of the gate structure, and first to third channel layers spaced apart from each other along a third direction intersecting the first direction and the second direction and arranged in order from top to bottom. The semiconductor device includes a plurality of channel layers surrounded by the gate structure and a plurality of internal spacers including first to third internal spacers that separate the gate structure and the source / drain region and are arranged in order from top to bottom. The gate structure includes a first gate portion on the first internal spacer, a second gate portion on the second internal spacer, and a third gate portion on the third internal spacer. One of the first to third gate portions may have different heights in the third direction and widths in the first direction from the remaining gate portions.

Advantages of the Invention

[0007] A semiconductor device with improved reliability can be provided by optimizing the structure and material of the internal spacer according to the source / drain conductivity type.

[0008] The diverse and meaningful advantages and effects of the present invention are not limited to the above-described content and can be more easily understood in the process of describing specific embodiments of the present invention.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described as follows with reference to the accompanying drawings. In the following, terms such as "upper", "upper part", "upper surface", "lower", "lower part", "lower surface", "side surface", etc. are denoted by reference numerals, and it can be understood that they are referred to based on the drawings unless otherwise specified.

[0011] FIG. 1 is a top view showing a semiconductor device according to an exemplary embodiment. For the sake of convenience of explanation, only some components of the semiconductor device are shown in FIG. 1.

[0012] FIG. 2 is a schematic cross-sectional view showing a semiconductor element according to an exemplary embodiment. FIG. 2 schematically shows a cross-section of the semiconductor element of FIG. 1 cut along cutting lines I-I' and II-II'.

[0013] FIG. 3a is a partially enlarged view showing a semiconductor element according to an exemplary embodiment. FIG. 3a shows an enlarged view of the "A" region of the semiconductor element of FIG. 2.

[0014] Referring to FIGS. 1 to 3a, the semiconductor element 100A includes a substrate 101 including an active region 105, a channel structure 140 including first to third channel layers 141, 142, 143 disposed apart from each other in a direction perpendicular to each other on the active region 105, a gate structure 160 extending across the active region 105 and including gate electrodes 165 respectively, a source / drain region 130 in contact with the channel structure 140 and including a first epitaxial layer 131 and a second epitaxial layer 133, a plurality of internal spacers 150 disposed between the gate structure 160 and the source / drain region 130 under each of the channel layers 141, 142, 143, and a contact structure 180 connected to the source / drain region 130. The semiconductor element 100A can further include an element isolation layer 110 and an interlayer insulating layer 170.

[0015] In the semiconductor element 100A, the active region 105 has a fin structure, and the gate electrode 165 can be disposed between the active region 105 and the channel structure 140, between the first to third channel layers 141, 142, 143 of the channel structure 140, and on the channel structure 140. Thereby, the semiconductor element 100A is a MBCFET (Multi Bridge Channel FET) structure transistor that is a Gate-All-Around type field effect transistor. TM (Multi Bridge Channel FET) structure can be included.

[0016] The substrate 101 can have an upper surface extending in the X direction and the Y direction. The substrate 101 can include a semiconductor material, for example, a Group IV semiconductor, a III-V compound semiconductor, or a II-VI compound semiconductor. For example, the Group IV semiconductor can include silicon, germanium, or silicon-germanium. The substrate 101 can also be provided as a bulk wafer, an epitaxial layer, an SOI (Silicon On Insulator) layer, or a SeOI (Semiconductor On Insulator) layer, etc.

[0017] The substrate 101 can include an active region 105 disposed on the upper part. The active region 105 can be defined by an element isolation layer 110 within the substrate 101 and can be arranged to extend in a first direction, for example, the X direction. However, depending on the description method, it is also possible to describe the active region 105 in a configuration separate from the substrate 101. The active region 105 partially protrudes above the element isolation layer 110, and the upper surface of the active region 105 can be located at a higher level than the upper surface of the element isolation layer 110. The active region 105 can also be composed of a part of the substrate 101 or can include an epitaxial layer grown from the substrate 101. However, on both sides of the gate structure 160, the active region 105 is partially recessed to form a recessed region, and the source / drain region 130 can be disposed in the above-mentioned recessed region.

[0018] In an exemplary embodiment, the active region 105 may or may not include a well region containing impurities. For example, in the case of a p-type transistor (pFET), the well region can include n-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb), and in the case of an n-type transistor (nFET), the well region can include p-type impurities such as boron (B), gallium (Ga), or indium (In). The well region can be located, for example, at a predetermined depth from the upper surface of the active region 105.

[0019] The element isolation layer 110 can define the active region 105 within the substrate 101. The element isolation layer 110 can be formed, for example, by a shallow trench isolation (STI) process. The element isolation layer 110 can expose the upper surface of the active region 105 and can also partially expose the upper portion. In some embodiments, the element isolation layer 110 can have an upper surface that is bent so as to have a higher level the closer it is to the active region 105. The element isolation layer 110 can be made of an insulating material. The element isolation layer 110 can be, for example, an oxide, a nitride, or a combination thereof.

[0020] The gate structure 160 can be arranged to extend in a second direction, for example, the Y direction, intersecting the active region 105 and the channel structure 140 on the active region 105 and the channel structure 140. In the active region 105 and / or the channel structure 140 that intersects the gate electrode 165 of the gate structure 160, a functional channel region of the transistor can be formed. Each of the gate structures 160 can include a gate electrode 165, a gate dielectric layer 162 between the gate electrode 165 and the first to third channel layers 141, 142, 143, and a gate spacer layer 164 on the side surface of the gate electrode 165. The gate structure 160 can include a first gate portion 160_1 located at the same level as the first internal spacer 151 under the first channel layer 141, a second gate portion 160_2 located at the same level as the second internal spacer 152 under the second channel layer 142, and a third gate portion 160_3 located at the same level as the third internal spacer 153 under the third channel layer 143. The surface of the first gate portion 160_1 along the third direction (for example, the Z direction) can contact the first channel layer 141 and the second channel layer 142, and the side surface along the first direction (for example, the X direction) can contact the first internal spacer 151. The surface of the second gate portion 160_2 along the third direction (for example, the Z direction) can contact the second channel layer 142 and the third channel layer 143, and the side surface along the first direction (for example, the X direction) can contact the second internal spacer 152. The surface of the third gate portion 160_3 along the third direction (for example, the Z direction) can contact the third channel layer 143 and the active region 105, and the side surface along the first direction (for example, the X direction) can contact the third internal spacer 153. In the first direction (for example, the X direction), the distance by which the second gate portion 160_2 is separated from the source / drain region 130 can be smaller than the distance by which the first gate portion 160_1 is separated from the source / drain region 130, and the distance by which the third gate portion 160_3 is separated from the source / drain region 130 can be smaller than the distance by which the second gate portion 160_2 is separated from the source / drain region 130.The height H2 of the second gate portion 160_2 may be greater than the height H1 of the first gate portion 160_1, and the height H3 of the third gate portion 160_3 may be greater than the height H2 of the second gate portion 160_2. In one embodiment, the height H3 of the third gate portion 160_3 may be greater than the height of each of the plurality of channel layers 141, 142, 143.

[0021] The gate dielectric layer 162 can be disposed between the active region 105 and the gate electrode 165, and between the channel structure 140 and the gate electrode 165, and can be disposed to cover at least a part of the surface of the gate electrode 165. For example, the gate dielectric layer 162 can be disposed to surround all surfaces of the gate electrode 165 except the uppermost surface. The gate dielectric layer 162 can contact the plurality of internal spacers 150 under the plurality of channel layers 141, 142, 143. The gate dielectric layer 162 may extend between the gate electrode 165 and the gate spacer layer 164, but is not limited thereto. The gate dielectric layer 162 can include an oxide, a nitride, or a high-k (high-dielectric constant) material. The high-k material can mean a dielectric material having a higher dielectric constant than a silicon oxide film (SiO2). The high-k material is, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y) and can be any one of praseodymium oxide (Pr2O3). According to an embodiment, the gate dielectric layer 162 can be composed of a multilayer film.

[0022] The gate electrode 165 can fill the space between the first to third channel layers 141, 142, 143 over the active region 105 and extend and be disposed on the channel structure 140. The gate electrode 165 can be separated from the first to third channel layers 141, 142, 143 by the gate dielectric layer 162. The gate electrode 165 can include a conductive material, for example, a metal nitride such as a titanium nitride film (TiN), a tantalum nitride film (TaN), or a tungsten nitride film (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. According to an embodiment, the gate electrode 165 may be composed of two or more multilayers.

[0023] The gate spacer layer 164 can be disposed on both side surfaces of the gate electrode 165 over the channel structure 140. The gate spacer layer 164 can insulate the source / drain region 130 from the gate electrode 165. According to an embodiment, the gate spacer layer 164 can also be composed of a multilayer structure. The gate spacer layer 164 can be composed of at least one of an oxide, a nitride, and a oxynitride, for example, it can be composed of a low dielectric constant film.

[0024] The channel structure 140 can be disposed on the active region 105 in a region where the active region 105 intersects with the gate structure 160. Each of the channel structures 140 can include first to third channel layers 141, 142, 143 which are a plurality of channel layers spaced apart from each other in the Z direction. The first to third channel layers 141, 142, 143 may be arranged in order from top to bottom, and the first channel layer 141 may be the uppermost channel layer. The channel structure 140 can be connected to the source / drain region 130. The channel structure 140 can have the same or a similar width as the gate structure 160 in the X direction, and can have the same or a smaller width as the active region 105 in the Y direction. In a cross-section along the Y direction, the channel layer disposed at the lower part among the first to third channel layers 141, 142, 143 can have the same or a larger width than the channel layer disposed at the upper part. The number and shape of the channel layers forming one channel structure 140 can be variously changed in embodiments. For example, one channel structure 140 can also include four channel layers, or can include two channel layers, or can include five or more channel layers.

[0025] The channel structure 140 can be made of a semiconductor material, and can include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). The channel structure 140 can be made of, for example, the same material as the active region 105. In some embodiments, the channel structure 140 may also include an impurity region located in a region adjacent to the source / drain region 130.

[0026] The source / drain regions 130 can be respectively arranged to contact the channel structure 140 on both sides or one side of the gate structure 160. The source / drain regions 130 can be arranged to cover the side surfaces along the X direction of the first to third channel layers 141, 142, 143 of the channel structure 140. The source / drain regions 130 can be connected to the contact structure 180 through the upper surface or the upper end. The upper region of the source / drain regions 130 can have a shape recessed by the contact structure 180. The source / drain regions 130 can be electrically connected to the contact structure 180. The upper surface of the source / drain regions 130 can be located at the same or higher level as the lower surface of the gate electrode 165 on the channel structure 140, and the above level can be variously changed in the embodiments.

[0027] The source / drain regions 130 can be epitaxially grown regions and can include a plurality of epitaxial layers. For example, the source / drain regions 130 can include first to second epitaxial layers 131, 133 arranged in order from bottom. The first epitaxial layer 131 can cover the side surfaces along the X direction of the first to third channel layers 141, 142, 143 respectively, and can cover the side surfaces along the X direction of the plurality of internal spacers 151, 152, 153 under the channel structure 140. The first epitaxial layer 131 can cover the inner surface of the recessed region where the source / drain regions 130 are arranged.

[0028] The second epitaxial layer 133 covers the first epitaxial layer 131 and can fill the recessed region on the first epitaxial layer 131. The width of the second epitaxial layer 133 may decrease as the level decreases, and the distance between the gate structure 160 and the first direction (e.g., the X direction) may increase as the level decreases. For example, the distance between the second epitaxial layer 133 and the third gate portion 160_3 in the first direction (e.g., the X direction) may be greater than the distance between the second epitaxial layer 133 and the first and second gate portions 160_1, 160_2 in the first direction. The distance between the second epitaxial layer 133 and the plurality of internal spacers 151, 152, 153 in the first direction (e.g., the X direction) may increase as the level decreases. For example, the distance D3 between the third internal spacer 153 and the second epitaxial layer 133 in the first direction (e.g., the X direction) may be greater than the distances D1 and D2 between the first and second internal spacers 151, 152 and the second epitaxial layer 133 in the first direction (e.g., the X direction). A part of the surface in the upper region of the second epitaxial layer 133 can contact the contact structure 180 and can have a curved surface shape along the shape of the contact structure 180.

[0029] The source / drain region 130 can include at least one of semiconductor materials, such as silicon (Si) and germanium (Ge), and can further include impurities. The first and second epitaxial layers 131 and 133 can have different compositions. For example, the first epitaxial layer 131 can include a non-silicon element concentration of a first concentration, and the second epitaxial layer 133 can have a non-silicon element concentration of a second concentration higher than the first concentration. The non-silicon element can be, for example, germanium (Ge) and / or a doping element.

[0030] The doping concentration of the doping element, i.e., the impurity, in the second epitaxial layer 133 can be made higher than that in the first epitaxial layer 131. As a result, the resistivity of the second epitaxial layer 133 can be made smaller than the resistivity of the first epitaxial layer 131. When the semiconductor device 100 is a pFET, the impurity can be at least one of boron (B), gallium (Ga), and indium (In), and when it is an nFET, the impurity can be at least one of phosphorus (P), arsenic (As), and antimony (Sb).

[0031] The interlayer insulating layer 170 can be disposed on the element isolation layer 110 so as to cover the upper surface of the element isolation layer 110 and the source / drain regions 130. The interlayer insulating layer 170 can include at least one of an oxide, a nitride, and a oxynitride, and can include, for example, a low dielectric constant material. Depending on the embodiment, the interlayer insulating layer 170 can include a plurality of insulating layers.

[0032] A plurality of internal spacers 150 can be disposed between the gate structure 160 and the source / drain regions 130 under each of the plurality of channel layers 141, 142, 143 over the active region 105. The plurality of internal spacers 150 can be arranged side by side with the gate electrode 165 under each of the first to third channel layers 141, 142, 143. The plurality of internal spacers 150 can cover the side surface of the gate structure 160 along the X direction under the channel structure 140. The side surface of the plurality of internal spacers 150 in contact with the gate structure 160 may be concave toward the gate structure 160. The upper and lower ends of the side surface of the plurality of internal spacers 150 facing the gate structure 160 can have a form protruding toward the gate structure 160. That is, each of the first to third gate portions 160_1, 160_2, 160_3 can have a convex shape toward the first to third internal spacers 151, 152, 153. The respective central thicknesses T1, T2, T3 of the internal spacers 150 can be the minimum thickness, and the respective upper end thickness or lower end thickness can be the maximum thickness. Here, the central thickness can be understood to mean the thickness at the center in the third direction (for example, the Z direction). Depending on the form of the source / drain regions 130, the process method and order of the internal spacers 150, etc., the form of the internal spacers 150 can be variously deformed. The internal spacers 150 can include an insulating material and can include at least one of an oxide, a nitride, and an oxynitride. For example, the internal spacers 150 can include at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). The gate electrode 165 can be stably separated and electrically isolated from the source / drain regions 130 by the plurality of internal spacers 150.

[0033] The first to third internal spacers 151, 152, and 153 may be arranged in order from above, and the first internal spacer 151 may be the uppermost internal spacer. The first internal spacer 151 can be disposed under the first channel layer 141, the second internal spacer 152 can be disposed under the second channel layer 142, and the third internal spacer 153 can be disposed under the third channel layer 143. The height H2 of the second internal spacer 152 may be greater than the height H1 of the first internal spacer 151, and the height H3 of the third internal spacer 153 may be greater than the height H3 of the second internal spacer 152. Conversely, the central thickness T2 of the second internal spacer 152 may be smaller than the central thickness T1 of the first internal spacer 151, and the central thickness T3 of the third internal spacer 153 may be smaller than the central thickness T2 of the second internal spacer. That is, among the first to third internal spacers 151, 152, and 153 in order from above, the height in the third direction (e.g., the Z direction) may be greater and the central thickness in the first direction may be smaller as the level is lower. The contact area between the first channel layer 141 and the first internal spacer 151 may be larger than the contact area between the second channel layer 142 and the second internal spacer 152, and the contact area between the second channel layer 142 and the second internal spacer 152 may be larger than the contact area between the third channel layer 143 and the third internal spacer 153.

[0034] Among the plurality of internal spacers 150, by having a structure in which the thickness of the internal spacer 150 located at a higher level is greater than the thickness of the internal spacer 150 located at a lower level, the second epitaxial layer 133 having a high non-silicon concentration and the gate structure 160 can be stably separated. Thereby, a semiconductor device with improved reliability can be provided.

[0035] The contact structure 180 can be disposed on the source / drain region 130. The contact structure 180 is connected to the source / drain region 130 and can apply an electrical signal to the source / drain region 130. The contact structure 180 can recess the source / drain region 130 and extend into the source / drain region 130. The contact structure 180 can have a side surface inclined such that the width decreases toward the substrate 101 depending on the aspect ratio, but is not limited thereto. The contact structure 180 can extend below the lower surface of the first channel layer 141 which is the first channel layer from above the channel structure 140 as in the present embodiment, and can extend below the lower surface of the second channel layer 142 or the third channel layer 143 depending on the embodiment. The contact structure 180 can include a metallic material such as tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), ruthenium (Ru), aluminum (Al), etc.

[0036] In the following description of the embodiments, descriptions overlapping with those described above with reference to FIGS. 1 to 3a are omitted.

[0037] FIGS. 3b to 3e are partial enlarged views illustrating a semiconductor device according to an exemplary embodiment. FIGS. 3b to 3e show corresponding enlarged regions of the region obtained by enlarging the "A" region of the semiconductor device of FIG. 2, and show a modification of FIG. 3a. The specific form of the plurality of internal spacers 150 is not limited to the exemplary embodiments of FIGS. 3a to 3e.

[0038] Referring to FIG. 3b together with FIG. 2, the side surface of the internal spacer 150 facing the gate structure 160 can have a concave-round shape toward the gate structure 160. Accordingly, each of the first to third gate portions 160_1, 160_2, 160_3 can have a convex-round shape toward each of the first to third internal spacers 151, 152, 153. Each of the first to third gate portions 160_1, 160_2, 160_3 can have the most protruding end portions P1, P2, P3 protruding toward the source / drain region 130. The first protruding end portion P1 of the first gate portion 160_1 can contact the portion where the first internal spacer 151 has the minimum thickness T1, and the first protruding end portion P1 can be separated from the first and second channel layers 141, 142. The second protruding end portion P2 of the second gate portion 160_2 can contact the portion where the second internal spacer 152 has the minimum thickness T2, and the second protruding end portion P2 can be separated from the second and third channel layers 142, 143. The third protruding end portion P3 of the third gate portion 160_3 can contact the portion where the third internal spacer 153 has the minimum thickness T3, and the third protruding end portion P3 can be separated from the third channel layer 143 and the active region 105. Similar to the embodiment of FIG. 3a, the central thickness T2 of the second internal spacer 152 can be smaller than the central thickness T1 of the first internal spacer 151, and the central thickness T3 of the third internal spacer 153 can be smaller than the central thickness T2 of the second internal spacer.

[0039] However, unlike the embodiment of FIG. 3a, the magnitude relationship of the upper end thicknesses U1, U2, and U3 of the first to third internal spacers 151, 152, and 153 may be different from the magnitude relationship of the central thicknesses T1, T2, and T3. For example, the upper end thicknesses U1, U2, and U3 of the first to third internal spacers 151, 152, and 153 can have substantially the same magnitude. Or, the upper end thickness U1 of the first internal spacer 151 may be smaller than the upper end thickness U2 of the second internal spacer 152, or the upper end thickness U2 of the second internal spacer 152 may be smaller than the upper end thickness U3 of the third internal spacer 153. These magnitude relationships can be changed in various ways. The description regarding the upper end thicknesses U1, U2, and U3 of the plurality of internal spacers 151, 152, and 153 can be similarly applied to the lower thicknesses of the plurality of internal spacers 151, 152, and 153.

[0040] Referring to FIG. 3c together with FIG. 2, the first epitaxial layer 131 can have an outer surface that protrudes convexly toward the gate structure 160 under the channel structure 140, and thus, the outer surface can have a bend. The side surface portion of the source / drain region 130 that contacts the plurality of internal spacers 151, 152, and 153 can protrude toward the gate structure 160 more than the side surface portion that contacts the plurality of channel layers 141, 142, and 143. By having a form in which the side surface of the source / drain region 130 protrudes in the direction of the gate electrode 165 between the plurality of channel layers 141, 142, and 143, the side surface of each of the plurality of internal spacers 150 that contacts the source / drain region 130 can be concave toward the source / drain region 130. Also in this case, similar to the embodiment of FIG. 3a, the central thickness T2 of the second internal spacer 152 can be smaller than the central thickness T1 of the first internal spacer 151, and the central thickness T3 of the third internal spacer 153 can be smaller than the central thickness T2 of the second internal spacer.

[0041] Referring to FIG. 3d together with FIG. 2, the degree to which the side surfaces of the source / drain region 130 protrude in the direction of the gate electrode 165 between the plurality of channel layers 141, 142, 143 can vary depending on the level. Different from the embodiment of FIG. 3c, the distance by which the side surface portions of the source / drain region 130 that contact the first to third internal spacers 151, 152, 153 protrude toward the gate structure 160 can vary depending on the heights H1, H2, H3 of the first to third internal spacers 151, 152, 153. For example, the protrusion distance E2 of the side surface portion of the source / drain region 130 that contacts the second internal spacer 152 may be greater than the protrusion distance E1 of the side surface portion that contacts the first internal spacer 151, and the protrusion distance E3 of the side surface portion that contacts the third internal spacer 153 may be greater than the protrusion distance E2 of the side surface portion that contacts the second internal spacer 152. Also in this case, similar to the embodiment of FIG. 3a, the center thickness T2 of the second internal spacer 152 can be smaller than the center thickness T1 of the first internal spacer 151, and the center thickness T3 of the third internal spacer 153 can be smaller than the center thickness T2 of the second internal spacer. That is, the protrusion distance by which the source / drain region 130 protrudes toward the gate structure 160 increases as the height of the contacting internal spacer increases. In some embodiments, conversely, the protrusion distance by which the source / drain region 130 protrudes toward the gate structure 160 can decrease as the height of the contacting internal spacer increases.

[0042] Referring to FIG. 3e together with FIG. 2, some of the plurality of internal spacers 150 can have substantially the same height and thickness. For example, the height H1 of the first internal spacer 151 and the height H2 of the second internal spacer 152 can be substantially the same, and the central thickness T1 of the first internal spacer 151 and the central thickness T2 of the second internal spacer 152 can be substantially the same. The height H3 of the third internal spacer 153 may be greater than the height H1 of the first internal spacer 151 and the height H2 of the second internal spacer 152, and the central thickness T3 of the third internal spacer 153 can be smaller than the central thickness T1 of the first internal spacer 151 and the central thickness T2 of the second internal spacer 152. Thereby, the height H1 of the first gate portion 160_1 and the height of the second gate portion 160_2 can be substantially the same, and the height of the third gate portion 160_3 may be greater than the height H1 of the first gate portion 160_1 and the height H2 of the second gate portion 160_2. That is, some of the plurality of internal spacers 151, 152, 153 can have substantially the same height and the same thickness even when located at different levels, and such features can be similarly applied to the embodiments of FIGS. 3a to 3d, and there can be various modifications.

[0043] The embodiments of FIGS. 3a to 3e described above are exemplary, and the specific configurations, arrangement relationships, contact relationships, thicknesses, and presence or absence of each component of the gate structure 160 including the gate electrode 165, the source / drain region 130, and the internal spacer 150 are not limited thereto and can be variously modified.

[0044] FIG. 4 is a schematic cross-sectional view showing a semiconductor device according to an exemplary embodiment. FIG. 4 schematically shows a cross-sectional view corresponding to the cross-section obtained by cutting the semiconductor device of FIG. 1 along the cutting lines I-I' and II-II'.

[0045] FIG. 5a is a partially enlarged view showing a semiconductor device according to an exemplary embodiment. FIG. 5a shows an enlargement of the "B" region of the semiconductor device of FIG. 4.

[0046] Referring to FIGS. 4 to 5a, in the semiconductor element 100B, the first to third gate portions 160_1, 160_2, and 160_3 extend in the third direction (for example, the Z direction) and can extend into the first to third channel layers 141, 142, 143 and the active region 105. Accordingly, the height W1 of the first gate portion 160_1 may be greater than the height H1' of the first inner spacer 151, the height W2 of the second gate portion 160_2 may be greater than the height H2' of the second inner spacer 152, and the height W3 of the third gate portion 160_3 may be greater than the height H3' of the third inner spacer 153. The height of the central portion of each of the first to third channel layers 141, 142, 143 may be smaller than the height of the side surface portion along the first direction (for example, the X direction) of each of the first to third channel layers 141, 142, 143. Here, it can be understood that the height of the central portion means the height at the center in the first direction (for example, the X direction). For example, the height C1 of the central portion of the second channel layer 142 may be smaller than the height C2 of the side surface in contact with the source / drain region 130. Among the lower surfaces of the first channel layer 141, the lower surface portion in contact with the first gate portion 160_1 may be the same as or located at a higher level than the lower surface portion in contact with the first inner spacer 151. Among the lower surfaces of the second channel layer 142, the lower surface portion in contact with the second gate portion 160_2 can be the same as or located at a higher level than the lower surface portion in contact with the second inner spacer 152, and among the upper surfaces of the second channel layer 142, the upper surface portion in contact with the first gate portion 160_1 can be the same as or located at a lower level than the upper surface portion in contact with the first inner spacer 151. Among the lower surfaces of the third channel layer 143, the lower surface portion in contact with the third gate portion 160_3 may be the same as or located at a higher level than the lower surface portion in contact with the third inner spacer 153. Among the upper surfaces of the third channel layer 143, the upper surface portion in contact with the second gate portion 160_2 can be the same as or located at a lower level than the upper surface portion in contact with the second inner spacer 152. Among the upper surfaces of the active region 105, the upper surface portion in contact with the third gate portion 160_3 can be the same as or located at a lower level than the upper surface portion in contact with the third inner spacer 153.The lengths V1, V2, and V3 by which the first to third gate portions 160_1, 160_2, and 160_3 extend into the first to third channel layers 141, 142, and 143, respectively, may be substantially the same.

[0047] As each of the gate portions 160_1, 160_2, and 160_3 extends in the third direction (e.g., the Z direction), the plurality of channel layers 141, 142, and 143 can have a dog bone shape in which the central height is smaller than the side height. In the present embodiment, since the side heights of the plurality of channel layers 141, 142, and 143 are maintained, the electrical characteristics of the plurality of channel layers 141, 142, and 143 do not deteriorate and can be maintained or improved.

[0048] Figures 5b to 5d are partial enlarged views showing a semiconductor device according to an exemplary embodiment. Figures 5b to 5d show corresponding enlarged regions of the region obtained by enlarging the "B" region of the semiconductor device of Figure 4, and show a modified example of Figure 5a. The specific form of the plurality of internal spacers 150 is not limited to the exemplary embodiments of Figures 5a to 5d.

[0049] Referring to FIG. 5b together with FIG. 4, the first to third gate portions 160_1, 160_2, 160_3 can each have a side surface that is convexly rounded toward the first to third internal spacers 151, 152, 153. The first protruding end portion P1 where the first gate portion 160_1 protrudes most toward the source / drain region 130 can contact the portion where the first internal spacer 151 has the minimum thickness T1', and can be separated from the first and second channel layers 141, 142. The distance U1' between the upper end of the first gate portion 160_1 and the source / drain region 130 may be greater than the central thickness T1' of the first internal spacer 151. The distance between the lower end of the first gate portion 160_1 and the source / drain region 130 may also be greater than the central thickness T1' of the first internal spacer 151. Similarly, the protruding end portion P2 where the second gate portion 160_2 protrudes most toward the source / drain region 130 can contact the portion where the second internal spacer 152 has the minimum thickness T2', and can be separated from the second and third channel layers 142, 143. The distance U2' between the upper end of the second gate portion 160_2 and the source / drain region 130 may be greater than the central thickness T2' of the second internal spacer 152. The distance between the lower end of the second gate portion 160_2 and the source / drain region 130 may also be greater than the central thickness T1' of the second internal spacer 152. Similarly, the protruding end portion P3 where the third gate portion 160_3 protrudes most toward the source / drain region 130 can contact the portion where the third internal spacer 153 has the minimum thickness T3', and can be separated from the third channel layer 143 and the active region 105. The distance U3' between the upper end of the third gate portion 160_3 and the source / drain region 130 may be greater than the central thickness T3' of the third internal spacer 152. The distance between the lower end of the third gate portion 160_3 and the source / drain region 130 may also be greater than the central thickness T3' of the third internal spacer 153.

[0050] Referring to FIG. 5c together with FIG. 4, the distances V1, V2, V3 that each of the plurality of gate portions 160_1, 160_2, 160_3 extend into each of the plurality of channel layers 141, 142, 143 may be different from each other. For example, the distance V2 that the second gate portion 160_2 extends into the second channel layer 142 may be greater than the distance V1 that the first gate portion 160_1 extends into the first channel layer 141, and the distance V3 that the third gate portion 160_3 extends into the third channel layer 143 may be greater than the distance V2 that the second gate portion 160_2 extends into the second channel layer 142. That is, the greater the width of the plurality of gate portions 160_1, 160_2, 160_3 in the first direction (e.g., the X direction), the greater the distance that each of the plurality of channel layers 141, 142, 143 extends into may be. In some embodiments, on the contrary, the greater the width of the plurality of gate portions 160_1, 160_2, 160_3 in the first direction (e.g., the X direction), the smaller the distance that each of the plurality of channel layers 141, 142, 143 extends into may be.

[0051] Referring to FIG. 5d together with FIG. 4, similar to the embodiment of FIG. 3e, some of the plurality of internal spacers 150 can have substantially the same height and thickness. For example, the height H1' of the first internal spacer 151 and the height H2' of the second internal spacer 152 can be substantially the same, and the central thickness T1' of the first internal spacer 151 and the central thickness T2' of the second internal spacer 152 can be substantially the same. The height H3' of the third internal spacer 153 may be greater than the height H1' of the first internal spacer 151 and the height H2' of the second internal spacer 152, and the central thickness T3' of the third internal spacer 153 may be smaller than the central thickness T1' of the first internal spacer 151 and the central thickness T2' of the second internal spacer 152. Thereby, the central height W1 of the first gate portion 160_1 and the central height W2 of the second gate portion 160_2 can be substantially the same. The central height W3 of the third gate portion 160_3 may be greater than the central height W1 of the first gate portion 160_1 and the central height W2 of the second gate portion 160_2. That is, some of the first to third gate portions 160_1, 160_2, 160_3 can have substantially the same height and the same thickness even when located at different levels, and such features can be similarly applied in the embodiments of FIGS. 5a to 5c, and there can be various modifications.

[0052] The compatible features of the embodiments of FIGS. 3a to 3e and the embodiments of FIGS. 5a to 5d can be applied to one semiconductor element simultaneously. For example, in one embodiment, some of the gate portions 160_1, 160_2, 160_3 can have a form extended in the third direction (for example, the Z direction) similar to the embodiment of FIG. 5a, while the remaining part can have the same height as the internal spacers at the same level as in FIG. 3a.

[0053] FIGS. 6a to 6f and FIGS. 8a to 8b are cross-sectional views shown in accordance with the process steps for explaining a method of manufacturing a semiconductor element according to an exemplary embodiment. FIGS. 6a to 6f and FIGS. 8a to 8b show cross-sections corresponding to FIG. 2.

[0054] Figs. 7a to 7b are partial enlarged views shown according to a process procedure for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment. Figs. 7a to 7b show enlarged views corresponding to Fig. 3a.

[0055] Referring to Fig. 6a, a plurality of sacrificial layers 120 and a plurality of channel layers 141, 142, 143 can be alternately stacked on a substrate 101.

[0056] The substrate 101 can include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The substrate 101 can include a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, or a semiconductor on insulator (SeOI) layer.

[0057] The plurality of channel layers 141, 142, 143 can include the first to third channel layers 141, 142, 143. The sacrificial layer 120 can be a layer that is replaced with the gate dielectric layer 162 and the gate electrode 165 under the first channel layer 141 as shown in FIG. 2 through subsequent processes. The thicknesses H1, H2, H3 of the sacrificial layers 120 laminated alternately can be formed to be different from each other. For example, the thickness H3 of the sacrificial layer 120 located at the lowest level may be larger than the thickness H1 of the sacrificial layer 120 located at the highest level. In order to form the thickness of the internal spacer 150 in FIG. 2 variably by subsequent processes, the thicknesses of the sacrificial layers 120 can be laminated differently at this stage. The sacrificial layer 120 can be made of a material having etching selectivity with respect to the first to third channel layers 141, 142, 143. The first to third channel layers 141, 142, 143 can include a material different from that of the sacrificial layer 120. The sacrificial layer 120 and the first to third channel layers 141, 142, 143 include a semiconductor material including at least one of, for example, silicon (Si), silicon germanium (SiGe), and germanium (Ge), but can include different materials from each other and may or may not include impurities. For example, the sacrificial layer 120 can include silicon germanium (SiGe), and the first to third channel layers 141, 142, 143 can include silicon (Si).

[0058] The sacrificial layer 120 and the first to third channel layers 141, 142, 143 can be formed by performing an epitaxial growth process on the above laminated structure. The number of channel layers laminated alternately with the sacrificial layer 120 can be variably changed in the embodiment.

[0059] Referring to FIG. 6b, a part of the sacrificial layer 120, the first to third channel layers 141, 142, 143, and the substrate 101 can be removed to form an active structure including an active region 105, and an element isolation layer 110 can be formed.

[0060] The above active structure can include an active region 105, a sacrificial layer 120, and first to third channel layers 141, 142, 143. The above active structure can be formed in a line shape extending in one direction, for example, the X direction, and can be formed separately from the active structures adjacent in the Y direction. The side surfaces of the above active structure along the Y direction can be coplanar with each other and located in a straight line.

[0061] In a region where a part of each of the active region 105, the sacrificial layer 120, and the first to third channel layers 141, 142, 143 is removed, after embedding an insulating material, the element isolation layer 110 can be formed by partially removing the insulating material so that the active region 105 protrudes. The upper surface of the element isolation layer 110 can be formed lower than the upper surface of the active region 105.

[0062] Referring to FIG. 6c, a sacrificial gate structure 200 and a gate spacer layer 164 can be formed on the active structure.

[0063] Each of the sacrificial gate structures 200 can be a sacrificial structure formed in a region where a gate dielectric layer 162 and a gate electrode 165 are disposed on the channel structure 140 as shown in FIG. 2 through subsequent processes. The sacrificial gate structure 200 can have a line shape intersecting the above active structure and extending in one direction. The sacrificial gate structure 200 can extend in the y direction, for example. Each of the sacrificial gate structures 200 can include first and second sacrificial gate layers 202, 205 and a mask pattern layer 206 that are sequentially stacked. The first and second sacrificial gate layers 202, 205 can be patterned using the mask pattern layer 206.

[0064] The first and second sacrificial gate layers 202 and 205 may be an insulating layer and a conductive layer respectively, but are not limited thereto, and the first and second sacrificial gate layers 202 and 205 may also be composed of one layer. For example, the first sacrificial gate layer 202 may contain silicon oxide, and the second sacrificial gate layer 205 may contain polysilicon. The mask pattern layer 206 may contain silicon oxide and / or silicon nitride.

[0065] The gate spacer layer 164 can be formed on both sidewalls of the sacrificial gate structure 200. The gate spacer layer 164 can be made of a low-k dielectric material, and for example, can contain at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0066] Referring to FIG. 6d, an etching process using the sacrificial gate structure 200 as an etching mask can proceed to form a recessed region RC that penetrates the active structure and exposes the active region 105.

[0067] A recessed region RC can be formed by partially removing the sacrificial layer 120 and the first to third channel layers 141, 142, and 143 exposed from the sacrificial gate structure 200, and the sacrificial layer 120 can be partially removed. Thereby, the first to third channel layers 141, 142, and 143 can form a channel structure 140 having a length limited along the X direction.

[0068] In this stage, the sacrificial layer 120 may be selectively etched with respect to the channel structure 140, for example, and removed at a predetermined depth from the side surface along the X direction. The sacrificial layer 120 can have a concave side surface on the inside by the side etching as described above. In this case, by subsequent processes, a source / drain region 130 having a bent side surface as shown in FIGS. 3c to 3d can be formed.

[0069] Referring to FIG. 6e, a source / drain region 130 can be formed in the recessed region RC.

[0070] The source / drain region 130 is formed within the recess region and can be grown, for example, by a selective epitaxial process from the side surfaces of the active region 105 and the channel structure 140. The source / drain region 130 can include a plurality of epitaxial layers, and these epitaxial layers can have different non-silicon concentrations from each other. For example, after first forming a first epitaxial layer 131 that covers the side surfaces of the plurality of channel layers 141, 142, 143, the side surface of the sacrificial layer 120, and the upper surface of the active region 105 exposed by the recess region, a second epitaxial layer 133 that fills the remaining portion of the recess region can be formed on the first epitaxial layer 131. The first epitaxial layer 131 can have a first non-silicon concentration, and the second epitaxial layer 133 can have a second non-silicon concentration higher than the first concentration. The source / drain region 130 can contain impurities by in-situ doping and can also include a plurality of layers having different doping elements and / or doping concentrations from each other.

[0071] Referring to FIG. 6f, a part of the interlayer insulating layer 170 can be formed, and the sacrificial gate structure and the sacrificial layer can be removed.

[0072] The interlayer insulating layer 170 can be formed by forming an insulating film that covers the sacrificial gate structure 200 and the source / drain region 130 and performing a planarization process.

[0073] The sacrificial gate structure 200 and the sacrificial layer 120 can be selectively removed with respect to the gate spacer layer 164 and the channel structure 140. First, the sacrificial gate structure 200 can be removed to form an upper gap region UR, and then the sacrificial layer 120 exposed through the upper gap region UR can be removed to form a lower gap region LR. For example, when the sacrificial layer 120 contains silicon germanium (SiGe) and the channel structure 140 contains silicon (Si), the sacrificial layer 120 can be selectively removed with respect to the channel structure 140 by performing a wet etching process.

[0074] Referring to FIG. 7a together with FIG. 6f, a plurality of internal spacers 151, 152, 153 can be formed under each of the plurality of channel layers 141, 142, 143.

[0075] The plurality of internal spacers 151, 152, 153 can be formed along the surface of the source / drain region 130 and the surfaces of the plurality of channel layers 141, 142, 143 within the lower gap region LR above the active region 105. Depending on the height of each lower gap region LR, the thickness at which the plurality of internal spacers 151, 152, 153 are formed may be different. For example, the height H3 of the portion of the lower gap region LR where the third internal spacer 153 is formed may be greater than the height H1 of the portion of the lower gap region LR where the first internal spacer 151 is formed, and the thickness of the third internal spacer 153 on the side covering the source / drain region 130 may be smaller than the thickness of the first internal spacer 151 on the side covering the source / drain region 130. That is, the greater the height of each portion of the lower gap region LR, the smaller the thickness can be formed for each of the plurality of internal spacers 151, 152, 153 on the side covering the source / drain region 130.

[0076] Referring to FIG. 7b together with FIG. 6f, a part of the plurality of internal spacers 151, 152, 153 can be etched to expose the plurality of channel layers 141, 142, 143 above the lower gap region LR.

[0077] Depending on the height of each lower gap region LR, the central thicknesses T1, T2, T3 of each of the plurality of internal spacers 151, 152, 153 can be formed in various ways. For example, the central thickness T3 of the third internal spacer 153 having a height H3 greater than the height H1 of the first internal spacer 151 can be formed smaller than the central thickness T1 of the first internal spacer 151. Thereby, a plurality of internal spacers 151, 152, 153 having various thicknesses can be formed without increasing the process difficulty.

[0078] Depending on differences such as the form, thickness, and degree of etching in which a plurality of internal spacers 151, 152, 153 are formed, various modified embodiments as shown in FIGS. 3a to 3e can be manufactured. The side surfaces of the plurality of internal spacers 151, 152, 153 that contact the source / drain regions 130 can be determined according to the surface form of the side surfaces of the source / drain regions 130. The side surfaces of the plurality of internal spacers 151, 152, 153 that contact the gate structure 160 can be variously deformed not only by the respective heights of the plurality of internal spacers 151, 152, 153, but also by the type of insulating material each contains, the amount of insulating material, the forming method, the etching method, the etching time, and the like.

[0079] Referring to FIG. 8a, a gate dielectric layer 162 and a gate electrode 165 can be formed to form a gate structure 160.

[0080] The gate structure 160 can be formed to fill the upper gap region UR and the lower gap region LR. The gate dielectric layer 162 can be formed to conformally cover the inner surfaces of the upper gap region UR and the lower gap region LR. After the gate electrode 165 is formed to completely fill the upper gap region UR and the lower gap region LR, it can be removed from the upper part at a predetermined depth in the upper gap region UR together with the gate dielectric layer 162 and the gate spacer layer 164. Thereby, a gate structure 160 including the gate dielectric layer 162, the gate electrode 165, and the gate spacer layer 164 can be formed.

[0081] The gate dielectric layer 162, the gate electrode 165, and the gate spacer layer 164 can be formed to continuously extend in the Y direction and then removed in some regions by an etching process. Thereby, gate structures 160 separated from each other in the Y direction can be formed.

[0082] Referring to FIG. 8b, an interlayer insulating layer 170 can be further formed on the gate structure 160, and a contact hole CTH that penetrates the interlayer insulating layer 170 and extends into the source / drain region 130 can be formed.

[0083] The contact hole CTH can be formed by etching a part of the source / drain region 130 from the upper surface through the interlayer insulating layer 170 on the source / drain region 130. After that, referring to FIG. 2 together, a conductive material can be deposited to fill the contact hole CTH to form a contact structure 180. According to an embodiment, after forming the contact structure 180, the contact structure 180 and the interlayer insulating layer 170 can be partially etched from the upper surface by a planarization process.

[0084] Hereinafter, descriptions overlapping with the description of the manufacturing method described above with reference to FIGS. 6a to 8b are omitted.

[0085] FIG. 9 is a cross-sectional view shown according to a process sequence to explain a method of manufacturing a semiconductor device according to an exemplary embodiment. FIG. 9 shows a region corresponding to FIG. 4.

[0086] FIGS. 10a to 10b are partial enlarged views shown according to a process sequence to explain a method of manufacturing a semiconductor device according to an exemplary embodiment. FIGS. 10a to 10b show enlarged views corresponding to FIG. 5a.

[0087] Referring to FIGS. 9 and 10a to 10b, after forming a plurality of internal spacers 151, 152, 153, a plurality of channel layers 141, 142, 143 and a part of the active region 105 exposed by the lower gap region LR can be etched.

[0088] This stage can be understood as the stage that proceeds after the manufacturing process described with reference to FIGS. 7a to 7b. The lower gap region LR can extend in a third direction (e.g., the Z direction) and extend into the plurality of channel layers 141, 142, 143 and the active region 105. Depending on the etching selectivity, the plurality of internal spacers 151, 152, 153 are not etched, and a part of the plurality of channel layers 141, 142, 143 and the active region 105 exposed by the lower gap region LR can be partially etched. Depending on the respective forms, thicknesses, heights, etc. of the plurality of internal spacers 151, 152, 153, the respective extension distances V1, V2, V3 of the lower gap region LR can be variously deformed.

[0089] The present invention is not limited by the above-described embodiments and the attached drawings, but is limited by the attached claims. Therefore, various forms of substitution, modification, and change are possible by those having ordinary knowledge in the art without departing from the technical idea of the present invention described in the claims, and combinations of embodiments are possible, and this can also be said to belong to the scope of the present invention.

Description of Reference Numerals

[0090] 101 Substrate 105 Active region 110 Element isolation layer 120 Sacrificial layer 140 Channel structure 130 Source / drain region 131 First epitaxial layer 133 Second epitaxial layer 150 Plurality of internal spacers 151 First internal spacer 152 Second internal spacer 153 Third internal spacer 160 Gate structure 170 Interlayer insulating layer 180 Contact structure

Claims

1. A gate structure having a side surface along a first direction and extending in a second direction intersecting the first direction, A source / drain region disposed on the side surface of the gate structure, A plurality of channel layers spaced apart from each other along a third direction intersecting the first direction and the second direction and surrounded by the gate structure, Including a plurality of internal spacers disposed between the gate structure and the source / drain region, The plurality of internal spacers, The lower the level, the greater the height in the third direction, A semiconductor device in which the thickness in the first direction becomes smaller as the level becomes lower.

2. The plurality of channel layers include first to third channel layers arranged in order from top to bottom, The plurality of internal spacers include first to third internal spacers arranged in order from top to bottom, The source / drain region includes a first epitaxial layer in contact with the plurality of channel layers and a second epitaxial layer on the first epitaxial layer, In the first direction, the distance at which the third internal spacer is separated from the second epitaxial layer is greater than each of the distance at which the first internal spacer is separated from the second epitaxial layer and the distance at which the second internal spacer is separated from the second epitaxial layer. The semiconductor device according to claim 1.

3. The plurality of channel layers include first to third channel layers arranged in order from top to bottom, The plurality of internal spacers include first to third internal spacers arranged in order from top to bottom, The contact area between the first channel layer and the first internal spacer is larger than the contact area between the third channel layer and the third internal spacer. The semiconductor device according to claim 1.

4. The plurality of internal spacers include first to third internal spacers arranged in order from top to bottom, In the first direction, the distance at which the portion of the gate structure in contact with the first internal spacer is separated from the source / drain region is greater than the distance at which the portion of the gate structure in contact with the third internal spacer is separated from the source / drain region. The semiconductor device according to claim 1.

5. The plurality of channel layers include first to third channel layers arranged in order from top to bottom, The plurality of internal spacers include first to third internal spacers arranged in order from top to bottom, In the third direction, the height of the third internal spacer is greater than the height of the third channel layer. The semiconductor device according to claim 1.

6. The side surface portion of the source / drain region that contacts the plurality of internal spacers protrudes toward the gate structure more than the side surface portion that contacts the plurality of channel layers. The semiconductor device according to claim 1.

7. The plurality of internal spacers include first to third internal spacers arranged in order from the top. The side surface portion of the source / drain region that contacts the third internal spacer protrudes further toward the gate structure than the side surface portion that contacts the first internal spacer and the side surface portion that contacts the second internal spacer. The semiconductor device according to claim 1.

8. The plurality of channel layers include first to third channel layers arranged in order from the top. The plurality of internal spacers include first to third internal spacers arranged in order from the top. Of the lower surface of the second channel layer, the lower surface portion that contacts the gate structure is located at the same or higher level as the lower surface portion that contacts the second internal spacer. Of the upper surface of the second channel layer, the upper surface portion that contacts the gate structure is located at the same or lower level as the upper surface portion that contacts the first internal spacer. The semiconductor device according to claim 1.

9. The height of the central portion of each of the plurality of channel layers in the third direction is smaller than the height of the side surface portion along the first direction of each of the plurality of channel layers in the third direction. The semiconductor device according to claim 1.

10. At least one of the plurality of internal spacers has a side surface that contacts the gate structure and is concave toward the gate structure. The semiconductor device according to claim 1.

11. At least one of the plurality of internal spacers has a side surface that contacts the source / drain region and is concave toward the source / drain region. The semiconductor device according to claim 1.

12. The central thickness of each of the plurality of internal spacers in the first direction is smaller than the upper end thickness of each of the plurality of internal spacers in the first direction. The semiconductor device according to claim 1.

13. The central thickness of each of the plurality of internal spacers in the first direction is smaller than the lower end thickness of each of the plurality of internal spacers in the first direction. The semiconductor device according to claim 1.

14. The source / drain region includes a first epitaxial layer in contact with the plurality of channel layers and a second epitaxial layer on the first epitaxial layer. The first epitaxial layer contains a non-silicon element with a first concentration. The second epitaxial layer contains a non-silicon element with a second concentration greater than the first concentration. The semiconductor device according to claim 1, wherein in the first direction, the distance by which the second epitaxial layer is separated from the gate structure increases as the level decreases.

15. Among the plurality of internal spacers, at least two have the same height in the third direction and the same thickness in the first direction, and have a different height and a different thickness from another one of the internal spacers. The semiconductor device according to claim 1.

16. A plurality of channel layers spaced apart from each other along a third direction, A gate structure extending in a second direction intersecting the third direction and surrounding the plurality of channel layers, A source / drain region disposed on side surfaces of the gate structure in a first direction intersecting the second direction and the third direction, Including a plurality of internal spacers disposed between the gate structure and the source / drain region, The first internal spacer located at the highest level among the plurality of internal spacers has a smaller height in the third direction and a larger thickness in the first direction than a second internal spacer located at another level. A semiconductor device.

17. In the first direction, each of the plurality of internal spacers has a concave shape toward the gate structure. The semiconductor device according to claim 16.

18. A gate structure having a side surface along a first direction and extending in a second direction intersecting the first direction, A source / drain region disposed on the side surface of the gate structure, Including a plurality of channel layers including first to third channel layers spaced apart from each other along a third direction intersecting the first direction and the second direction and arranged in order from top to bottom, and surrounded by the gate structure. Including a plurality of internal spacers including first to third internal spacers that separate the gate structure and the source / drain region and are arranged in order from top to bottom, The gate structure includes a first gate portion on the first internal spacer, a second gate portion on the second internal spacer, and a third gate portion on the third internal spacer. One of the first to third gate portions is a semiconductor element having a height in the third direction and a width in the first direction different from those of the remaining gate portions.

19. The semiconductor element according to claim 18, wherein side surfaces of each of the first to third gate portions in contact with the first to third internal spacers are convex toward the respective first to third internal spacers.

20. The semiconductor element according to claim 18, wherein in the third direction, a height of the third gate portion is greater than heights of the first gate portion and the second gate portion.

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