Crystal oscillator circuit

Abstract

To provide a crystal oscillation circuit capable of stably continuing oscillation output without being affected by leakage current.SOLUTION: A crystal oscillator circuit includes a first current path formed between an inverter circuit and a first voltage node to which a first voltage is supplied, a second current path formed between the inverter circuit and a second voltage node to which a second voltage different from the first voltage is supplied, a first Schmitt buffer that receives an output signal of the inverter circuit and outputs a first buffer signal, a second Schmitt buffer that receives the output signal of the inverter circuit and outputs a second buffer signal, the second Schmitt buffer having a larger hysteresis width than the first Schmitt buffer, an amplitude detection circuit for detecting a decrease in the amplitude of the output signal of the inverter circuit based on the first buffer signal and the second buffer signal, and a current control unit for controlling current flowing through the first current path and the second current path based on a detection result of the amplitude detection circuit so as to increase the current.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a crystal oscillation circuit.

Background Art

[0002] As a circuit capable of generating a high-precision clock signal, a crystal oscillation circuit is known. The crystal oscillation circuit is composed of a crystal oscillator and an oscillation circuit, and is an oscillation circuit that can obtain an oscillation output of the natural frequency of the crystal oscillator. Since a high-precision oscillation output can be obtained, the crystal oscillation circuit is used as a frequency signal source or a time reference signal source in, for example, communication devices and in-vehicle devices.

[0003] The crystal oscillation circuit has a drawback of being vulnerable to leakage current, and it may rarely occur that the oscillation of the crystal oscillation circuit stops due to the influence of the leakage current. There is a need for a crystal oscillation circuit that can suppress the influence of the leakage current and obtain a stable oscillation output.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the present invention is to provide a crystal oscillation circuit that can stably continue to output an oscillation without being affected by leakage current.

Means for Solving the Problems

[0006] To solve the above problems, a crystal oscillation circuit according to the present invention includes an inverter circuit in which both terminals of a crystal oscillator are connected to an input terminal and an output terminal, a first current path formed between the inverter circuit and a first voltage node to which a first voltage is applied, a second current path formed between the inverter circuit and a second voltage node to which a second voltage different from the first voltage is applied, a first Schmitt buffer that receives an output signal of the inverter circuit and outputs a first buffer signal and has a first hysteresis width, a second Schmitt buffer that receives the output signal of the inverter circuit and outputs a second buffer signal and has a second hysteresis width larger than the first hysteresis width, an amplitude detection circuit that detects a decrease in the amplitude of the output signal of the inverter circuit based on the first buffer signal and the second buffer signal, and a current control unit that controls to increase the currents flowing through the first current path and the second current path based on a detection result of the amplitude detection circuit.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Embodiments for Carrying Out the Invention

[0008] Hereinafter, this embodiment will be described with reference to the accompanying drawings. In the accompanying drawings, elements having the same function may sometimes be denoted by the same reference numerals. Note that the accompanying drawings show embodiments and implementation examples in accordance with the principles of the present disclosure, but these are for the purpose of understanding the present disclosure and are not used to limit the interpretation of the present disclosure in any way. The description in this specification is merely a typical example and does not limit the scope of the claims or application examples of the present disclosure in any sense.

[0009] In this embodiment, the description is given in sufficient detail for those skilled in the art to practice the present disclosure. However, other implementations and forms are possible, and it is necessary to understand that changes in configuration and structure and replacement of various elements can be made without departing from the scope and spirit of the technical idea of the present disclosure. Therefore, the following description should not be construed as being limited thereto.

[0010] [First Embodiment] Referring to FIG. 1, the crystal oscillator circuit according to the first embodiment will be described. This crystal oscillator circuit is connected to a crystal oscillator (not shown), an input terminal XTO, and an output terminal XT1, and is configured to output a clock signal CLK. Specifically, this crystal oscillator circuit includes a CMOS inverter circuit 11, a feedback resistor 12, an input-side load capacitance element 13, an output-side load capacitance element 14, and limiting resistors 15 and 16 as basic components. In addition to this, the crystal oscillator circuit according to the first embodiment includes a first Schmitt buffer 21, a second Schmitt buffer 22, a clock detection circuit (amplitude detection circuit) 23, and an inverter IN1, transistors M3, and M4 as a current control unit.

[0011] The CMOS inverter circuit 11 is configured by connecting a P-type MOS transistor M1 and an N-type MOS transistor M2 in series, connecting an input terminal XTO to the gates of both transistors M1 and M2, and setting an output terminal XT1 as the connection node of both transistors.

[0012] The source of the P-type MOS transistor M1 is connected to a first voltage node VL1 to which a power supply voltage VDD is supplied via a limiting resistor 15, and the source of the N-type MOS transistor M2 is connected to a second voltage node VL2 to which a ground voltage VSS is supplied via a limiting resistor 16. The limiting resistor 15 constitutes a first current circuit CP1 between the first voltage node VL1 and the CMOS inverter circuit 11, and the limiting resistor 16 constitutes a second current circuit CP2 between the CMOS inverter circuit 11 and the second voltage node VL2. The limiting resistors 15 and 16 are for suppressing the current supplied to the CMOS inverter circuit 11 to reduce power consumption.

[0013] A P-type MOS transistor M3 is connected in parallel with the limiting resistor 15, and an N-type MOS transistor M4 is connected in parallel with the limiting resistor 16. When these transistors M3 and M4 are in a conductive state, they constitute a part of the first current paths CP1 and CP2, and function as a current control unit that short-circuits the limiting resistors 15 and 16 to increase the current of the CMOS inverter circuit 11. A turbo-on signal TURBO_ON as a command signal for instructing an increase in current is input to the gates of the transistors M3 and M4 via an inverter IN1 or directly.

[0014] The output terminal of the CMOS inverter circuit 11 is connected to a first Schmitt buffer 21 and a second Schmitt buffer 21. The first Schmitt buffer 21 receives the output signal of the CMOS inverter circuit 11 and outputs a first buffer signal SBUF01. This first Schmitt buffer has a hysteresis characteristic, and the hysteresis width is HYS1. On the other hand, similar to the first Schmitt buffer 21, the second Schmitt buffer 22 receives the output signal of the CMOS inverter circuit 11 and outputs a second buffer signal SBUF02. However, the hysteresis width HYS2 of the hysteresis characteristic of the second Schmitt buffer 22 is made larger than the hysteresis width HYS1.

[0015] An input-side load capacitance element 13 is connected between the input terminal XTO and the second voltage node VL2, and an output-side capacitance element 14 is connected between the output terminal XT1 and the second voltage node VL2. The output signal of the first Schmitt buffer 21 is a clock signal CLK that is the output signal of the crystal oscillator circuit. Since the first Schmitt buffer 21 has a hysteresis characteristic, noise (hairs) in the output signal of the CMOS inverter circuit 11 is removed.

[0016] The clock detection circuit 23 receives the first buffer signal SBUF01 and the second buffer signal SBUF02, and has a function of detecting a decrease in the amplitude of the output signal of the crystal oscillator (CMOS inverter circuit 11) according to the relationship between the two and switching the turbo-on signal TURBO_ON. The detailed circuit configuration example and operation will be described later.

[0017] FIG. 2 is a circuit diagram of a crystal oscillation circuit according to a comparative example of the first embodiment. For the same components as in FIG. 1, the same reference numerals are given in FIG. 2, and thus redundant explanations are omitted below. The crystal oscillation circuit of this comparative example includes a limiting resistor 15 and a limiting resistor 16, which form a first current path CP1 and a second current path CP2. However, transistors M3 and M4 parallel to the limiting resistors 15 and 16 are not provided, nor is there a clock detection circuit 23 for controlling their conduction. A single Schmitt buffer 21C is connected to the output terminal of the CMOS inverter circuit 11, and its output signal is used as the clock signal CLK.

[0018] A crystal oscillation circuit such as the comparative example in FIG. 2 has a problem of being vulnerable to leakage current flowing through the terminals. That is, generally, since a crystal oscillator (not shown) is connected to the input terminal XT0 and the output terminal XT1 of the crystal oscillation circuit, leakage current may occur due to condensation on the circuit board or the like. Due to the influence of this leakage current, the gain of the CMOS inverter circuit 11 may decrease and oscillation may stop. When the crystal oscillation circuit stops, the clock source disappears, and the microcontroller or the like of the device using the crystal oscillator also stops, and furthermore, there is a risk that the entire system equipped with the microcontroller may stop.

[0019] To address such a problem, in the crystal oscillation circuit shown in FIG. 1, a first Schmitt buffer 21 and a second Schmitt buffer 22 having different hysteresis characteristics are connected to the output terminal XT1 of the CMOS inverter circuit 11.

[0020] Referring to FIG. 3, the operations of the first Schmitt buffer 21 and the second Schmitt buffer 22 will be described. FIG. 3 shows an example of waveforms of an input signal input to the input terminal XTO and first buffer signal SBUF01 and second buffer signal SBUF02. As described above, the hysteresis width HYS1 of the first Schmitt buffer 21 is made smaller than the hysteresis width of the second Schmitt buffer 22. For this reason, during normal times (when the amplitude of the output signal of the CMOS inverter circuit 11 is sufficiently large), the output signal SBUF01 of the first Schmitt buffer 21 and the output signal SBUF02 of the second Schmitt buffer 22 are clock signals of the same frequency, but the latter is slightly delayed by the amount of the hysteresis characteristic. This delay is about several μs for a 32.768 kHz crystal oscillation.

[0021] Referring to FIG. 4, a specific configuration example of the clock detection circuit 23 will be described. As an example, the clock detection circuit 23 includes D flip-flops 41 to 43, 46, an exclusive NOR circuit (EXNOR circuit) 44, and an inverter 45.

[0022] The D flip-flop 41 is a frequency division circuit that divides the second buffer signal SBUF02 by two and outputs a divided signal DIV2. The D flip-flops 42 and 43 function as shift registers that delay the divided signal DIV2 by the first buffer signal SBUF01 and output delayed signals DIV2' and DIV2''.

[0023] The EXNOR circuit 44 calculates the exclusive NOR (EXNOR) of the delayed signals DIV2' and DIV2'' and outputs an output signal EXNOROUT. The D flip-flop circuit 46 operates to remove noise (hairs) from the output signal EXNOROUT and output a turbo on signal TURBO_ON by delaying the output signal EXNOROUT with the inverted signal SBUF01N of the first buffer signal SBUF01 by means of the inverter 45. Specifically described, the delayed signal DIV2'' is a signal obtained by inverting the phase of the DIV2' D flip-flop 43, and a delay corresponding thereto occurs. For this reason, if the delayed signals DIV2' and DIV2'' are directly input to the EXNOR circuit 44, noise (hairs) corresponding to the delay may occur. The D flip-flop 46 functions as a filter for removing this noise. Since the noise occurs at the rising edge of the first buffer signal SBUFO1, this noise can be effectively removed by the clock SBUFO1N with the opposite phase. A reset signal RST is input to each of the D flip-flops 41 to 43 and 45.

[0024] Next, with reference to FIGS. 5 and 6, the operation of the crystal oscillator circuit according to the first embodiment will be described while comparing it with the operation of the crystal oscillator circuit of the comparative example. As shown in FIG. 5, in the crystal oscillator circuit of the comparative example, when a leakage current occurs, for example, at time t1 while oscillating at the natural frequency of the crystal oscillator (not shown), the amplitude of the output signal (output terminal XT1) of the CMOS inverter circuit 11 gradually decreases, and eventually, when the amplitude falls below the hysteresis width HYSc of the Schmitt buffer 21C at time t2, the oscillation stops.

[0025] In the crystal oscillation circuit of the first embodiment, oscillation stop as described above is prevented by two Schmitt buffers 21 and 22 having different hysteresis widths. As shown in FIG. 6, for example, when a leakage current occurs at time t1 and the amplitude of the output signal of the CMOS inverter circuit 11 decreases, first, the amplitude of the second buffer signal SBUF02 output from the second Schmitt buffer 22 having a large hysteresis width HYS2 stops. However, the first buffer signal SBUF01 output from the first Schmitt buffer 21 having a small hysteresis width HYS continues to have an amplitude.

[0026] When the clock detection circuit 23 detects this, the turbo on signal TURBO_ON becomes "Hi" at time t2, and the transistors M3 and M4 switch to the conducting state, shorting (short-circuiting) the current limiting resistors 15 and 16. When the current limiting resistors 15 and 16 are shorted, the current supplied to the CMOS inverter circuit 11 increases and the gain of the CMOS inverter circuit 11 increases, and oscillation can be maintained even in a state where a leakage current is occurring. The supply of the clock signal CLK to the outside is continued by the first Schmitt buffer 21 having a narrow hysteresis width.

[0027] With reference to the waveform diagrams of FIGS. 7 and 8, the operation of the clock detection circuit 23 will be described. First, during normal operation (when the leakage current is small and the amplitude of the output signal of the CMOS inverter circuit 11 is sufficiently large), the second buffer signal SBUF02 output from the second Schmitt buffer 22 and the first buffer signal SBUF01 output from the first Schmitt buffer 21 are clock signals of the same frequency. Due to the difference in hysteresis width, the second buffer signal SBUF2 of the second Schmitt buffer 22 is slightly delayed compared to the first buffer signal SBUF01 of the first Schmitt buffer 21.

[0028] The second buffer signal SBUF02 is divided by the D flip-flop 41 to become a divided signal DIV2. The divided signal DIV2 is delayed by the subsequent D flip-flops 42 and 43 (shift registers) according to the rising timing of the first buffer signal SBUFO1 to become a delayed signal DIV2´, and further the delayed signal DIV2´ is delayed by one clock of the first buffer signal SBUFO1 to become a delayed signal DIV2´´. When the amplitudes of the delayed signals DIV2´ and DIV2´´ are sufficiently large (during normal oscillation), they alternately repeat "Hi" and "Low", so the output signal EXNOROUT of the subsequent EXNOR circuit 44 also becomes "Low". The output signal EXNOROUT is delayed at the falling timing of the first buffer signal SBUFO1 in the D flip-flop 46 to become a turbo-on signal TURBO_ON from which noise (hairs) has been removed from the output signal EXNOROUT.

[0029] Thus, during normal operation, the turbo-on TURBO_ON, which is the output signal of the clock detection circuit 23, is maintained at "Low". However, when the amplitude of the output signal of the CMOS inverter 11 decreases, only the second buffer signal SBUFO2 output by the second Schmitt buffer 22 switches to "Low". The divided signal DIV2 and the delayed signals DIV2´ and DIV2´´ also become "Low", the output signal EXNOR and the turbo-on signal TURBO_ON also switch to "Hi", and the transistors M3 and M4 become conductive. As shown in FIG. 8, the second buffer signal SBUFO2 may stop at "Hi" when the clock stops depending on the timing of crossing the hysteresis threshold of the second Schmitt buffer 22. However, since the EXNOR circuit 44 performs a negative exclusive OR, as shown in FIG. 8, the turbo-on signal TURBO_ON similarly switches from "Low" to "Hi".

[0030] As described above, according to the first embodiment, even when the output signal to the CMOS inverter circuit 11 decreases, by detecting this and increasing the current flowing through the CMOS inverter circuit 11, a stable oscillation output can be continued without stopping the oscillation output of the crystal oscillator circuit.

[0031] [Second Embodiment] Referring to FIG. 9, the configuration of the crystal oscillator circuit according to the second embodiment will be described. In FIG. 9, for the components identical to those in the first embodiment (FIG. 1), the same reference numerals as those in FIG. 1 are given, and redundant descriptions will be omitted below.

[0032] The crystal oscillator circuit according to the second embodiment has the same basic configuration as that of the first embodiment, and the configurations (21, 22, 23) for clock oscillation stop are the same as those in the first embodiment. However, this second embodiment is different from the first embodiment in the configuration of the first current path CP1, the second current path CP2, and the current control unit.

[0033] In the crystal oscillator circuit according to this second embodiment, the limiting resistors 15 and 16 of the first current path CP1 and the second current path CP2 are omitted. Instead, P-type MOS transistors M7 and M8 are connected to the first current circuit CP1. Also, the transistor constituting the current control unit is only the P-type MOS transistor M3, and the N-type MOS transistor M4 is omitted. However, similar to the first embodiment, it is also possible to connect the same limiting resistors 15 and 16 and the N-type PMOS transistor M4 as in the first embodiment.

[0034] Both of these P-type MOS transistors M7 and M8 are connected in parallel between the first voltage node and the CMOS inverter circuit 11 (the source of the P-type MOS transistor M1) to form the first current path CP1. The P-type MOS transistors M7 and M8, together with the P-type MOS transistor M6 connected to the bias current source CS, constitute a current mirror circuit and have the function of mirroring the current of the bias current source CS.

[0035] The P-type MOS transistor M3 that constitutes the current control unit is connected in series with at least one of the transistors that constitute the current mirror circuit, for example, the PMOS-type MOS transistor M7, and is controlled to conduct by the turbo-on signal TURBO_ON to control the current in the first current path CP1. That is, in the crystal oscillation circuit of the second embodiment, when the P-type MOS transistor switches to the conductive state, the current in the first current path CP1 is increased by increasing the number of transistors through which the current flows. In this regard, it is different from the first embodiment in which the current is increased by shorting the limiting resistor to reduce the resistance. A similar current mirror circuit may also be provided in the second current path CP2.

[0036] During normal operation (when the amplitude of the output signal of the CMOS inverter circuit 11 is sufficiently large), similar to the first embodiment, the turbo-on signal TURBO_ON output by the clock detection circuit 23 is "Low". Therefore, the PMOS transistor that constitutes the current control unit is in the non-conductive state (OFF), and the current supplied from the bias current source CS through the current mirror circuit (transistors M6 to M8) flows only through the P-type MOS transistor M8. Therefore, the current flowing through the CMOS inverter circuit 11 is limited.

[0037] When the amplitude of the output signal of the CMOS inverter circuit 11 becomes small and becomes less than or equal to the hysteresis width HYS2 of the second Schmitt buffer 22, the turbo-on signal TURBO_ON becomes "Hi", the P-type MOS transistor M3 switches to the conductive state, and current also flows through the P-type MOS transistor M7. As a result, the current supplied to the CMOS inverter circuit 11 increases, the gain of the CMOS inverter circuit 11 can be increased, and the amplitude of the output signal can be maintained.

[0038] [Others] The present invention is not limited to the above-described embodiments, and includes various modifications. For example, the above-described embodiments have been described in detail for the purpose of clearly explaining the present invention, and are not necessarily limited to those having all the configurations described. Also, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can also be added to the configuration of one embodiment. Further, for a part of the configuration of each embodiment, addition, deletion, or replacement with other configurations is possible.

Explanation of Reference Numerals

[0039] 11 ··· CMOS inverter circuit 12 ··· Feedback resistor 13 ··· Input-side load capacitance element 14 ··· Output-side load capacitance element 15, 16 ··· Limiting resistors VL1 ··· First voltage node VL2 ··· Second voltage node 21 ··· First Schmitt buffer 22 ··· Second Schmitt buffer 23 ··· Clock detection circuit (amplitude detection circuit) IN1 ··· Inverter M1, M2, M3, M4, M6, M7, M8 ··· Transistors

Claims

1. An inverter circuit in which both terminals of a crystal oscillator are connected to an input terminal and an output terminal; A first current path formed between the inverter circuit and a first voltage node to which a first voltage is applied; A second current path formed between the inverter circuit and a second voltage node to which a second voltage different from the first voltage is applied; A first Schmitt buffer that receives the output signal of the inverter circuit and outputs a first buffer signal and has a first hysteresis width; A second Schmitt buffer that receives the output signal of the inverter circuit and outputs a second buffer signal and has a second hysteresis width larger than the first hysteresis width; An amplitude detection circuit that detects a decrease in the amplitude of the output signal of the inverter circuit based on the first buffer signal and the second buffer signal; A current control unit that controls to increase the current flowing through the first current path and the second current path based on the detection result of the amplitude detection circuit A crystal oscillator circuit characterized by comprising.

2. The crystal oscillator circuit according to claim 1, wherein the amplitude detection circuit detects a decrease in the amplitude of the output signal of the inverter circuit by detecting a stop in the amplitude of the second buffer signal.

3. The amplitude detection circuit A frequency division circuit that divides the second buffer signal and outputs a frequency division signal; A shift register that delays the frequency division signal with the first buffer signal to generate a first delay signal, and further delays the first delay signal with the first buffer signal to generate a second delay signal Comprising The crystal oscillator circuit according to claim 2, which outputs a command signal for increasing the current flowing through the first current path and the second current path according to the exclusive OR signal of the first delay signal and the second delay signal.

4. The crystal oscillator circuit according to claim 1, wherein the current control unit further includes a semiconductor element that conducts according to the detection result of the amplitude detection circuit and increases the current flowing through the first current path or the second current path.

5. The first current path or the second current path includes a limiting resistor connected between the first voltage node or the second voltage node and the inverter circuit, The crystal oscillator circuit according to claim 4, wherein the semiconductor element is connected in parallel with the limiting resistor and shorts the limiting resistor when brought into a conducting state.

6. The first current path or the second current path includes a plurality of transistors constituting a current mirror circuit, The crystal oscillation circuit according to claim 4, wherein the semiconductor element is connected in series with at least one of the plurality of transistors.

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