Semiconductor device

Abstract

To provide a semiconductor device with a seal conductor capable of improving pressure resistance.SOLUTION: In a semiconductor module, a semiconductor device includes: a semiconductor chip 41 having a principal surface 42; an insulating layer 51 formed on the principal surface; functional devices 45, 60 formed on at least one of the semiconductor chip and the insulating layer; at least one terminal 11, 12 formed on the insulating layer and electrically connected to the functional device; and a seal conductor 61 which partitions, in a plan view, a region including the functional device and at least one terminal from other regions and includes a plurality of seal plug conductors 64, and a plurality of seal via conductors 65 positioned between the semiconductor chip and the seal plug conductors, arranged adjacent to each other in the plan view and each having a width in the plan view smaller than that of the seal plug conductors.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to a semiconductor device including a seal conductor.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, active elements, a plurality of interlayer insulating layers, a plurality of metal electrodes, and a moisture-resistant ring (seal conductor). The active elements are formed on the semiconductor substrate. The plurality of interlayer insulating layers are stacked on the semiconductor substrate. The plurality of metal electrodes are formed on the uppermost interlayer insulating layer. The moisture-resistant ring is embedded in the plurality of interlayer insulating layers so as to surround the active elements and the plurality of metal electrodes in a plan view. The moisture-resistant ring is grounded to the semiconductor substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] In the semiconductor device according to Patent Document 1, due to the structure in which the seal conductor is grounded to the semiconductor substrate, when a voltage is applied to the plurality of metal electrodes, undesired conduction may occur between the plurality of metal electrodes and the seal conductor. The breakdown voltage of the semiconductor device decreases due to this type of conduction. Examples of the mode of undesired conduction include leakage and discharge.

[0005] One embodiment of the present invention provides a semiconductor device capable of improving the breakdown voltage in a structure including a seal conductor.

[0006] One embodiment of the present invention provides a semiconductor device including: a semiconductor chip having a main surface; an insulating layer formed on the main surface; a functional device formed on at least one of the semiconductor chip and the insulating layer; a low-potential terminal formed on the insulating layer and electrically connected to the functional device; a high-potential terminal formed on the insulating layer at a distance from the low-potential terminal and electrically connected to the functional device; and a seal conductor embedded in the insulating layer in a wall shape so as to partition a region including the functional device, the low-potential terminal, and the high-potential terminal from other regions, the seal conductor being electrically isolated from the semiconductor chip, the functional device, the low-potential terminal, and the high-potential terminal.

[0007] According to this semiconductor device, when voltages are applied to the low-potential terminal and the high-potential terminal, undesired conduction between the high-potential terminal and the seal conductor can be suppressed. Also, undesired conduction between the low-potential terminal and the seal conductor can be suppressed. Further, undesired conduction between the functional device and the seal conductor can be suppressed. Thus, the breakdown voltage can be improved.

[0008] One embodiment of the present invention provides a semiconductor device including: a semiconductor chip having a main surface; an insulating layer formed on the main surface; a low-potential pattern formed in the insulating layer; a high-potential pattern formed in the insulating layer so as to face the low-potential pattern in the normal direction of the main surface; a dummy pattern formed around the high-potential pattern in the insulating layer and including a conductor for shielding an electric field between the low-potential pattern and the high-potential pattern; a low-potential terminal formed on the insulating layer and electrically connected to the low-potential pattern; a high-potential terminal formed on the insulating layer at a distance from the low-potential terminal and electrically connected to the high-potential pattern; and a seal conductor embedded in the insulating layer in a wall shape so as to partition a region including the low-potential pattern, the high-potential pattern, the dummy pattern, the low-potential terminal, and the high-potential terminal from other regions, the seal conductor being electrically isolated from the semiconductor chip, the low-potential pattern, the high-potential pattern, the dummy pattern, the low-potential terminal, and the high-potential terminal.

[0009] According to this semiconductor device, when voltages are applied to the low-potential terminal and the high-potential terminal, the electric field concentration on the high-potential pattern can be suppressed by the dummy pattern. Further, according to this semiconductor device, when voltages are applied to the low-potential terminal and the high-potential terminal, the undesired conduction between the high-potential pattern (high-potential terminal) and the seal conductor can be suppressed. Also, the undesired conduction between the low-potential pattern (low-potential terminal) and the seal conductor can be suppressed. Also, the undesired conduction between the dummy pattern and the seal conductor can be suppressed. Therefore, the breakdown voltage can be improved.

[0010] One embodiment of the present invention provides a semiconductor device including: a semiconductor chip having a main surface; an insulating layer formed on the main surface; a functional device formed on at least one of the semiconductor chip and the insulating layer; at least one terminal formed on the insulating layer and electrically connected to the functional device; a seal conductor that partitions a region including the functional device and at least one of the terminals from other regions in a plan view, into a first portion; and a plurality of second portions located between the semiconductor chip and the first portion, arranged adjacent to each other in a plan view, and each having a width smaller than that of the first portion in the plan view.

[0011] The above-described, or further other objects, features, and effects of the present invention will be clarified by the description of the embodiments described below with reference to the accompanying drawings.

Brief Description of the Drawings

[0012]

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Embodiments for Carrying Out the Invention

[0013] FIG. 1 is a plan view of a semiconductor module 1 in which a semiconductor device 5 according to the first embodiment of the present invention is incorporated. In FIG. 1, for clarity of the internal structure, it is shown through the central part of the package body 2.

[0014] Referring to FIG. 1, in this embodiment, the semiconductor module 1 is of the SOP (Small Outline Package) type. The semiconductor module 1 is not limited to the SOP, and may be composed of a QFN (Quad For Non-Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package), or SOJ (Small Outline J-leaded Package), or various packages similar thereto.

[0015] In this embodiment, the semiconductor module 1 is a composite module including a plurality of devices. The semiconductor module 1 includes a package body 2, a plurality of die pads 3, a plurality of lead terminals 4, a semiconductor device 5, a controller IC 6, a driver IC 7, and a plurality of conducting wires 17 to 20.

[0016] The semiconductor device 5 is a transformer chip that boosts an input electrical signal and outputs it. The controller IC 6 is an IC chip that drives and controls the semiconductor device 5. The driver IC 7 is an IC chip that generates an electrical signal corresponding to the electrical signal from the semiconductor device 5 and drives and controls a load (such as a switching device or the like). The controller IC 6 is a low-potential device with respect to the semiconductor device 5. The driver IC 7 is a high-potential device with respect to the semiconductor device 5.

[0017] The package body 2 includes a molding resin. The molding resin may include an epoxy resin. The package body 2 is formed in a rectangular parallelepiped shape. The package body 2 has a non-mounting surface 8 on one side, a mounting surface 9 on the other side, and side walls 10A to 10D that connect the non-mounting surface 8 and the mounting surface 9. The non-mounting surface 8 and the mounting surface 9 are formed in a rectangular shape in a plan view seen from the normal direction Z thereof. The mounting surface 9 is a surface that faces the connection target in a state where the semiconductor module 1 is mounted on the connection target. Examples of the connection target include a circuit board such as a PCB (printed circuit board).

[0018] The side walls 10A to 10D include a first side wall 10A, a second side wall 10B, a third side wall 10C, and a fourth side wall 10D. The first side wall 10A and the second side wall 10B extend along the first direction X and face each other in a second direction Y orthogonal to the first direction X. The third side wall 10C and the fourth side wall 10D extend in the second direction Y and face each other in the first direction X.

[0019] The plurality of die pads 3 are arranged in the package body 2. In this form, the plurality of die pads 3 are each formed in a rectangular parallelepiped shape. The plurality of die pads 3 include a first die pad 3A and a second die pad 3B. The first die pad 3A is arranged on the first side wall 10A side. The second die pad 3B is arranged on the second side wall 10B side at an interval from the first die pad 3A.

[0020] The plurality of lead terminals 4 are respectively provided on the first side wall 10A side and the second side wall 10B side of the package body 2. Each lead terminal 4 has one end portion located inside the package body 2 and the other end portion located outside the package body 2. The other end portion of each lead terminal 4 is formed as an external connection portion to be connected to a connection target.

[0021] The semiconductor device 5 is disposed on the first die pad 3A within the package body 2. In this form, the semiconductor device 5 is formed in a rectangular shape in plan view. The semiconductor device 5 is disposed on the first die pad 3A with its long side facing the first side wall 10A (second side wall 10B).

[0022] The semiconductor device 5 includes a plurality of low potential terminals 11 and a plurality of high potential terminals 12. The plurality of low potential terminals 11 are arranged at intervals along the long side on the first side wall 10A side in the semiconductor device 5. The plurality of high potential terminals 12 are arranged at intervals along the long side on the second side wall 10B side in the semiconductor device 5.

[0023] The controller IC 6 is disposed on the first die pad 3A within the package body 2. Specifically, the controller IC 6 is disposed on the first die pad 3A at a distance from the semiconductor device 5 toward the first side wall 10A side. In this form, the controller IC 6 is formed in a rectangular shape in plan view. The controller IC 6 is disposed on the first die pad 3A with its long side facing the first side wall 10A (second side wall 10B).

[0024] The controller IC 6 includes a plurality of first input pads 13 and a plurality of first output pads 14. The plurality of first input pads 13 are arranged at intervals along the long side on the first side wall 10A side in the controller IC 6. The plurality of first output pads 14 are arranged at intervals along the long side on the second side wall 10B side in the controller IC 6.

[0025] The driver IC7 is disposed on the second die pad 3B within the package body 2. In this form, the driver IC7 is formed in a rectangular shape in plan view. The driver IC7 is disposed on the second die pad 3B with its long side facing the first side wall 10A (second side wall 10B).

[0026] The driver IC7 includes a plurality of second input pads 15 and a plurality of second output pads 16. The plurality of second input pads 15 are arranged at intervals along the long side on the first side wall 10A side in the driver IC7. The plurality of second output pads 16 are arranged at intervals along the long side on the second side wall 10B side in the driver IC7.

[0027] The plurality of conductive wires 17 - 20 selectively connect the plurality of lead terminals 4, semiconductor device 5, controller IC6, and driver IC7 within the package body 2. The plurality of conductive wires 17 - 20 are each formed from bonding wires. The plurality of conductive wires 17 - 20 include at least one of copper wire, gold wire, and aluminum wire.

[0028] The plurality of conductive wires 17 - 20 include a first conductive wire 17, a second conductive wire 18, a third conductive wire 19, and a fourth conductive wire 20. The first conductive wire 17 is connected to the lead terminal 4 on the first side wall 10A side and the first input pad 13 of the controller IC6. The second conductive wire 18 is connected to the low - potential terminal 11 of the semiconductor device 5 and the first output pad 14 of the controller IC6. The third conductive wire 19 is connected to the high - potential terminal 12 of the semiconductor device 5 and the second input pad 15 of the driver IC7. The fourth conductive wire 20 is connected to the second output pad 16 of the driver IC7 and the lead terminal 4 on the second side wall 10B side.

[0029] FIG. 2 is a diagram for explaining the operation of the semiconductor module 1 shown in FIG. 1. FIG. 3 is a voltage waveform diagram used for the explanation of FIG. 2.

[0030] Referring to FIG. 2, the semiconductor device 5 includes a transformer 21. The transformer 21 includes a primary low-potential coil 22 (low-potential conductor pattern) and a secondary high-potential coil 23 (high-potential conductor pattern) facing each other in the vertical direction. The high-potential coil 23 is disposed above the low-potential coil 22 and faces the low-potential coil 22.

[0031] The high-potential coil 23 is AC-connected to the low-potential coil 22 by magnetic coupling and is DC-insulated from the low-potential coil 22 at the same time. That is, the driver IC 7 is AC-connected to the controller IC 6 via the semiconductor device 5 and is DC-insulated from the controller IC 6 by the semiconductor device 5 at the same time.

[0032] The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 spirally wound between the first inner end 24 and the first outer end 25. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 spirally wound between the second inner end 27 and the second outer end 28.

[0033] The semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34. The first low-potential wiring 31 connects the first inner end 24 of the low-potential coil 22 to the corresponding low-potential terminal 11. The second low-potential wiring 32 connects the first outer end 25 of the low-potential coil 22 to the corresponding low-potential terminal 11. The first high-potential wiring 33 connects the second inner end 27 of the high-potential coil 23 to the corresponding high-potential terminal 12. The second high-potential wiring 34 connects the second outer end 28 of the high-potential coil 23 to the corresponding high-potential terminal 12.

[0034] The controller IC6 includes a first wiring 35 and a second wiring 36. The first wiring 35 is connected to the corresponding first input pad 13 and first output pad 14. The second wiring 36 is connected to the corresponding first input pad 13 and first output pad 14. The controller IC6 further includes a first switching device Sw1 and a second switching device Sw2. The first switching device Sw1 and the second switching device Sw2 are each formed of a transistor.

[0035] The first switching device Sw1 is interposed in the first wiring 35. The first switching device Sw1 controls the conduction and interruption of the electrical signal transmitted through the first wiring 35. The second switching device Sw2 is interposed in the second wiring 36. The second switching device Sw2 controls the conduction and interruption of the electrical signal transmitted through the second wiring 36.

[0036] The first input pad 13 on the first wiring 35 side is connected to the ground via a first conductor 17. The first output pad 14 on the first wiring 35 side is electrically connected to the low potential terminal 11 on the first inner end 24 side via a second conductor 18. The first input pad 13 on the second wiring 36 side is electrically connected to a power supply 37 via the first conductor 17. The power supply 37 applies a voltage of, for example, 5V to the controller IC6. The first output pad 14 on the second wiring 36 side is electrically connected to the low potential terminal 11 on the first outer end 25 side via a second conductor 18.

[0037] The driver IC7 is electrically connected to the semiconductor device 5 via a plurality of third conductors 19. Specifically, the second input pad 15 of the driver IC7 is electrically connected to the high potential terminal 12 on the second inner end 27 side via the third conductor 19. Also, the second input pad 15 of the driver IC7 is electrically connected to the high potential terminal 12 on the second outer end 28 side via the third conductor 19.

[0038] The driver IC7 is connected to a reference voltage power supply 38, a power supply 39, and a SiC-MISFET (Metal Insulator Semiconductor field Effect Transistor) as an example of a load. The reference voltage power supply 38 applies a reference voltage of, for example, 1200V to the driver IC7. This reference voltage is also applied to the high-potential coil 23 via the driver IC7. The power supply 39 applies a voltage of, for example, 15V to the driver IC7. The driver IC7 drives and controls the SiC-MISFET with 1200V as the reference voltage.

[0039] Referring to FIG. 3, the controller IC6 controls the on / off states of the first switching device Sw1 and the second switching device Sw2 in a predetermined switching pattern to generate a pulse signal PS. The predetermined switching pattern includes, in this example, a first applied state (Sw1 on, Sw2 off) and a second applied state (Sw1 off, Sw2 on). FIG. 3 shows an example in which a 5V pulse signal PS referenced to 0V (ground potential) is generated.

[0040] The pulse signal PS generated by the controller IC6 is input to the semiconductor device 5. The semiconductor device 5 transmits the pulse signal PS from the low-potential coil 22 to the high-potential coil 23. As a result, the pulse signal PS is boosted by an amount corresponding to the winding ratio (turns ratio) of the low-potential coil 22 and the high-potential coil 23. FIG. 3 shows an example in which the pulse signal PS is boosted to 15V.

[0041] The boosted pulse signal PS is input to the driver IC7. The driver IC7 generates an electrical signal corresponding to the boosted pulse signal PS and drives and controls the SiC-MISFET. The numerical values shown in FIGS. 2 and 3 are merely examples. For example, the reference voltage on the secondary side (high-potential side) may be 500V or more and 4000V or less.

[0042] FIG. 4 is a perspective view showing the semiconductor device 5 shown in FIG. 1. FIG. 5 is a plan view of the semiconductor device 5 shown in FIG. 4. FIG. 6 is a plan view showing the layer in which the low potential coil 22 is formed in the semiconductor device 5 shown in FIG. 4. FIG. 7 is a plan view showing the layer in which the high potential coil 23 is formed in the semiconductor device 5 shown in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 7. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 7. FIG. 10 is an enlarged view of region X shown in FIG. 7. FIG. 11 is an enlarged view of region XI shown in FIG. 7. FIG. 12 is an enlarged view of region XII shown in FIG. 7. FIG. 13 is an enlarged view of region XIII shown in FIG. 8, and is a view showing the separation structure 130 according to the first exemplary embodiment.

[0043] Referring to FIGS. 4 to 8, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0044] The wide bandgap semiconductor is composed of a semiconductor having a bandgap exceeding that of silicon (about 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or more. The wide bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0045] In this embodiment, the semiconductor chip 41 includes a semiconductor substrate made of silicon. The semiconductor chip 41 may be an epitaxial substrate having a laminated structure including a semiconductor substrate made of silicon and an epitaxial layer made of silicon. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0046] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a rectangular shape (rectangular in this form) in a plan view (hereinafter simply referred to as "plan view") when viewed from the normal direction Z thereof.

[0047] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face each other in the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face each other in the first direction X. The chip sidewalls 44A to 44D are composed of ground surfaces.

[0048] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating sidewalls 53A to 53D. The insulating main surface 52 is formed in a rectangular shape (rectangular in this form) that coincides with the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0049] The insulating sidewalls 53A to 53D include a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C, and a fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form a ground surface flush with the chip sidewalls 44A to 44D.

[0050] The insulating layer 51 has a multilayer insulating laminated structure including a bottommost insulating layer 55, a topmost insulating layer 56, and a plurality (11 layers in this embodiment) of interlayer insulating layers 57. The bottommost insulating layer 55 is an insulating layer that directly covers the first main surface 42. The topmost insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottommost insulating layer 55 and the topmost insulating layer 56. The bottommost insulating layer 55 has a single-layer structure including silicon oxide in this embodiment. The topmost insulating layer 56 has a single-layer structure including silicon oxide in this embodiment. The thickness of the bottommost insulating layer 55 and the thickness of the topmost insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0051] The plurality of interlayer insulating layers 57 each have a laminated structure including a first insulating layer 58 on the side of the bottommost insulating layer 55 and a second insulating layer 59 on the side of the topmost insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer with respect to the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, about 0.3 μm).

[0052] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, about 2 μm). It is preferable that the thickness of the second insulating layer 59 exceeds the thickness of the first insulating layer 58.

[0053] The total thickness DT of the insulating layer 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layer 51 and the number of laminated layers of the interlayer insulating layers 57 are arbitrary and are adjusted according to the insulation breakdown voltage (insulation breakdown tolerance) to be achieved. Also, the insulating materials of the bottommost insulating layer 55, the topmost insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to specific insulating materials.

[0054] The semiconductor device 5 includes a first functional device 45 formed in an insulating layer 51. The first functional device 45 includes one or more (in this form, a plurality) of transformers 21. That is, the semiconductor device 5 is composed of a multi-channel type device including a plurality of transformers 21. The plurality of transformers 21 are formed in the inner part of the insulating layer 51 at intervals from the insulating sidewalls 53A to 53D. The plurality of transformers 21 are formed at intervals in the first direction X.

[0055] Specifically, the plurality of transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D formed in this order from the insulating sidewall 53C side to the insulating sidewall 53D side in a plan view. The plurality of transformers 21A to 21D each have a similar structure. Hereinafter, the structure of the first transformer 21A will be described as an example. Regarding the description of the structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D, the description of the structure of the first transformer 21A shall apply mutatis mutandis and will be omitted.

[0056] Referring to FIGS. 6 to 9, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in the insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this form, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between the lowermost insulating layer 55 and the uppermost insulating layer 56 (that is, a plurality of interlayer insulating layers 57).

[0057] The low-potential coil 22 is formed on the lowermost insulating layer 55 (semiconductor chip 41) side within the insulating layer 51, and the high-potential coil 23 is formed on the uppermost insulating layer 56 (insulating main surface 52) side with respect to the low-potential coil 22 within the insulating layer 51. That is, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 interposed therebetween. The arrangement positions of the low-potential coil 22 and the high-potential coil 23 are arbitrary. Also, the high-potential coil 23 only needs to face the low-potential coil 22 with one or more interlayer insulating layers 57 interposed therebetween.

[0058] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of stacked interlayer insulation layers 57) is appropriately adjusted according to the breakdown voltage and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this form, the low-potential coil 22 is formed in the third interlayer insulation layer 57 counted from the side of the bottom insulation layer 55. In this form, the high-potential coil 23 is formed in the first interlayer insulation layer 57 counted from the side of the top insulation layer 56.

[0059] The low-potential coil 22 is embedded through the first insulation layer 58 and the second insulation layer 59 in the interlayer insulation layer 57. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 spirally wound between the first inner end 24 and the first outer end 25. The first spiral portion 26 is spirally wound and extends in an elliptical shape (oval shape) in a plan view. The portion forming the innermost periphery of the first spiral portion 26 demarcates an elliptical first inner region 66 in a plan view.

[0060] The number of turns of the first spiral portion 26 may be 5 or more and 30 or less. The width of the first spiral portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the first spiral portion 26 is 1 μm or more and 3 μm or less. The width of the first spiral portion 26 is defined by the width in a direction orthogonal to the spiral direction. The first winding pitch of the first spiral portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the first winding pitch is 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions in a direction orthogonal to the spiral direction in the first spiral portion 26.

[0061] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the form shown in FIG. 6 and the like. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a square shape, or a circular shape in a plan view. The first inner region 66 may be demarcated in a polygonal shape such as a triangular shape or a square shape, or a circular shape in a plan view according to the winding shape of the first spiral portion 26.

[0062] The low-potential coil 22 may contain at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a laminated structure including a barrier layer and a body layer. The barrier layer partitions a recess space within the interlayer insulating layer 57. The body layer is embedded in the recess space partitioned by the barrier layer. The barrier layer may contain at least one of titanium and titanium nitride. The body layer may contain at least one of copper, aluminum, and tungsten.

[0063] The high-potential coil 23 is embedded through the first insulating layer 58 and the second insulating layer 59 in the interlayer insulating layer 57. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 spirally wound between the second inner end 27 and the second outer end 28. The second spiral portion 29 is spirally wound and extends in an elliptical shape (oval shape) in a plan view. The portion forming the innermost peripheral edge of the second spiral portion 29 defines a second inner region 67 having an elliptical shape in a plan view in this form. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0064] The number of turns of the second spiral portion 29 may be 5 or more and 30 or less. The number of turns of the second spiral portion 29 with respect to the number of turns of the first spiral portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second spiral portion 29 preferably exceeds the number of turns of the first spiral portion 26. Of course, the number of turns of the second spiral portion 29 may be less than the number of turns of the first spiral portion 26, or may be equal to the number of turns of the first spiral portion 26.

[0065] The width of the second spiral portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second spiral portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second spiral portion 29 is defined by the width in a direction orthogonal to the spiral direction. The width of the second spiral portion 29 is preferably equal to the width of the first spiral portion 26.

[0066] The second winding pitch of the second spiral portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the second winding pitch is 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions in a direction orthogonal to the spiral direction in the second spiral portion 29. Preferably, the second winding pitch is equal to the first winding pitch of the first spiral portion 26.

[0067] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the forms shown in FIG. 7 and the like. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a plan view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a plan view according to the winding shape of the second spiral portion 29.

[0068] Preferably, the high potential coil 23 is formed of the same conductive material as the low potential coil 22. That is, preferably, the high potential coil 23 includes a barrier layer and a main body layer, similar to the low potential coil 22.

[0069] Referring to FIG. 5, the semiconductor device 5 includes a plurality (12 in this embodiment) of low potential terminals 11 and a plurality (12 in this embodiment) of high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0070] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in a region on the insulating side wall 53B side at an interval in the second direction Y from the plurality of transformers 21A to 21D and are arranged at an interval in the first direction X.

[0071] The plurality of low-potential terminals 11 includes a first low-potential terminal 11A, a second low-potential terminal 11B, a third low-potential terminal 11C, a fourth low-potential terminal 11D, a fifth low-potential terminal 11E, and a sixth low-potential terminal 11F. In this form, the plurality of low-potential terminals 11A to 11F are each formed in pairs. The number of the plurality of low-potential terminals 11A to 11F is arbitrary.

[0072] The first low-potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low-potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low-potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low-potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low-potential terminal 11E is formed in a region between the first low-potential terminal 11A and the second low-potential terminal 11B in a plan view. The sixth low-potential terminal 11F is formed in a region between the third low-potential terminal 11C and the fourth low-potential terminal 11D in a plan view.

[0073] The first low-potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low-potential coil 22). The second low-potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low-potential coil 22). The third low-potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low-potential coil 22). The fourth low-potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low-potential coil 22).

[0074] The fifth low-potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22). The sixth low-potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low-potential coil 22) and the first outer end 25 of the fourth transformer 21D (low-potential coil 22).

[0075] The plurality of high-potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low-potential terminals 11. Specifically, the plurality of high-potential terminals 12 are formed in a region on the insulating sidewall 53A side at intervals in the second direction Y from the plurality of low-potential terminals 11, and are arranged at intervals in the first direction X.

[0076] The plurality of high-potential terminals 12 are respectively formed in regions close to the corresponding transformers 21A to 21D in a plan view. That the high-potential terminal 12 is close to the transformers 21A to 21D means that the distance between the high-potential terminal 12 and the transformers 21 in a plan view is less than the distance between the low-potential terminal 11 and the high-potential terminal 12.

[0077] Specifically, the plurality of high-potential terminals 12 are formed at intervals along the first direction X so as to face the plurality of transformers 21A to 21D along the first direction X in a plan view. More specifically, the plurality of high-potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high-potential coil 23 and the region between adjacent high-potential coils 23 in a plan view. Thereby, the plurality of high-potential terminals 12 are arranged in a line with the plurality of transformers 21A to 21D in the first direction X in a plan view.

[0078] The plurality of high-potential terminals 12 include a first high-potential terminal 12A, a second high-potential terminal 12B, a third high-potential terminal 12C, a fourth high-potential terminal 12D, a fifth high-potential terminal 12E, and a sixth high-potential terminal 12F. In this form, two of the plurality of high-potential terminals 12A to 12F are respectively formed. The number of the plurality of high-potential terminals 12A to 12F is arbitrary.

[0079] The first high-potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high-potential coil 23) in a plan view. The second high-potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high-potential coil 23) in a plan view. The third high-potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high-potential coil 23) in a plan view. The fourth high-potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high-potential coil 23) in a plan view. The fifth high-potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high-potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0080] The first high-potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high-potential coil 23). The second high-potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high-potential coil 23). The third high-potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high-potential coil 23). The fourth high-potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high-potential coil 23).

[0081] The fifth high-potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23). The sixth high-potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high-potential coil 23) and the second outer end 28 of the fourth transformer 21D (high-potential coil 23).

[0082] Referring to FIGS. 6 to 9, the semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34, which are respectively formed in the insulating layer 51. In this embodiment, a plurality of first low-potential wirings 31, a plurality of second low-potential wirings 32, a plurality of first high-potential wirings 33, and a plurality of second high-potential wirings 34 are formed.

[0083] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coils 22 of the first transformer 21A and the low-potential coils 22 of the second transformer 21B at the same potential. Also, the first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coils 22 of the third transformer 21C and the low-potential coils 22 of the fourth transformer 21D at the same potential. In this form, the first low-potential wiring 31 and the second low-potential wiring 32 fix all the low-potential coils 22 of the transformers 21A to 21D at the same potential.

[0084] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coils 23 of the first transformer 21A and the high-potential coils 23 of the second transformer 21B at the same potential. Also, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coils 23 of the third transformer 21C and the high-potential coils 23 of the fourth transformer 21D at the same potential. In this form, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D at the same potential.

[0085] The plurality of first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. The plurality of first low-potential wirings 31 have the same structure. Hereinafter, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. Regarding the description of the structures of the other first low-potential wirings 31, the description of the structure of the first low-potential wiring 31 connected to the first transformer 21A shall apply mutatis mutandis and will be omitted.

[0086] The first low-potential wiring 31 includes a through-wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (a plurality in this form) pad plug electrodes 76, and one or more (a plurality in this form) substrate plug electrodes 77.

[0087] The through-wiring 71, the low-potential connection wiring 72, the lead-out wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed of the same conductive material as the low-potential coil 22 or the like. That is, the through-wiring 71, the low-potential connection wiring 72, the lead-out wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, respectively, in the same manner as the low-potential coil 22 or the like.

[0088] The through-wiring 71 penetrates a plurality of interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this form, the through-wiring 71 is formed in a region between the lowermost insulating layer 55 and the uppermost insulating layer 56 in the insulating layer 51. The through-wiring 71 has an upper end portion on the uppermost insulating layer 56 side and a lower end portion on the lowermost insulating layer 55 side. The upper end portion of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end portion of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0089] The through-wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80 in this form. In the through-wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed of the same conductive material as the low-potential coil 22 or the like. That is, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, respectively, in the same manner as the low-potential coil 22 or the like.

[0090] The first electrode layer 78 forms the upper end portion of the through-wiring 71. The second electrode layer 79 forms the lower end portion of the through-wiring 71. The first electrode layer 78 is formed in an island shape and faces the low-potential terminal 11 (the first low-potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0091] The plurality of wiring plug electrodes 80 are respectively embedded in a plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be electrically connected to each other, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area less than the planar area of the first electrode layer 78 and the planar area of the second electrode layer 79.

[0092] The number of stacked wiring plug electrodes 80 matches the number of stacked interlayer insulating layers 57. In this form, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 penetrating the plurality of interlayer insulating layers 57 may be formed.

[0093] The low-potential connection wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connection wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connection wiring 72 preferably has a planar area exceeding the planar area of the wiring plug electrode 80. The low-potential connection wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0094] The extraction wiring 73 is formed in the region between the semiconductor chip 41 and the through wiring 71 within the interlayer insulating layer 57. In this form, the extraction wiring 73 is formed in the first interlayer insulating layer 57 counted from the bottommost insulating layer 55. The extraction wiring 73 includes a first end portion on one side, a second end portion on the other side, and a wiring portion connecting the first end portion and the second end portion. The first end portion of the extraction wiring 73 is located in the region between the semiconductor chip 41 and the lower end portion of the through wiring 71. The second end portion of the extraction wiring 73 is located in the region between the semiconductor chip 41 and the low potential connection wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end portion and the second end portion.

[0095] The first connection plug electrode 74 is formed in the region between the through wiring 71 and the extraction wiring 73 within the interlayer insulating layer 57 and is electrically connected to the first end portions of the through wiring 71 and the extraction wiring 73. The second connection plug electrode 75 is formed in the region between the low potential connection wiring 72 and the extraction wiring 73 within the interlayer insulating layer 57 and is electrically connected to the second end portions of the low potential connection wiring 72 and the extraction wiring 73.

[0096] The plurality of pad plug electrodes 76 are formed in the region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71 within the uppermost insulating layer 56 and are electrically connected to the upper end portions of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the extraction wiring 73 within the bottommost insulating layer 55. In this form, the substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the first end portion of the extraction wiring 73 and are electrically connected to the semiconductor chip 41 and the first end portion of the extraction wiring 73, respectively.

[0097] Referring to FIG. 9, the plurality of second low potential wirings 32 are electrically connected to the corresponding low potential terminals 11E, 11F and the first outer ends 25 of the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of second low potential wirings 32 each have a similar structure. Hereinafter, the structure of the second low potential wiring 32 connected to the fifth low potential terminal 11E and the first transformer 21A (second transformer 21B) will be described as an example. Regarding the description of the structures of the other second low potential wirings 32, the description of the structure of the second low potential wiring 32 connected to the first transformer 21A (second transformer 21B) shall apply mutatis mutandis and will be omitted.

[0098] Similar to the first low potential wiring 31, the second low potential wiring 32 includes a through wiring 71, a low potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, a pad plug electrode 76, and a substrate plug electrode 77. The second low potential wiring 32 has a structure similar to that of the first low potential wiring 31, except that the low potential connection wiring 72 is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22).

[0099] The low potential connection wiring 72 of the second low potential wiring 32 is formed around the low potential coil 22 within the same interlayer insulating layer 57 as the low potential coil 22. Specifically, the low potential connection wiring 72 is formed in the region between two adjacent low potential coils 22 in a plan view. The pad plug electrode 76 is formed in the region between the low potential terminal 11 (fifth low potential terminal 11E) and the low potential connection wiring 72 within the uppermost insulating layer 56 and is electrically connected to the low potential terminal 11 and the low potential connection wiring 72.

[0100] Referring to FIG. 8, the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A to 12D and the second inner ends 27 of the corresponding transformers 21A to 21D (high-potential coils 23), respectively. The plurality of first high-potential wirings 33 each have a similar structure. Hereinafter, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. Regarding the description of the structures of the other first high-potential wirings 33, the description of the structure of the first high-potential wiring 33 connected to the first transformer 21A shall be applied mutatis mutandis and will be omitted.

[0101] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (a plurality in this embodiment) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrodes 82 are preferably formed of the same conductive material as the low-potential coil 22 or the like. That is, the high-potential connection wiring 81 and the pad plug electrodes 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22 or the like.

[0102] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (the first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connection wiring 81 is formed at an interval from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z. Thereby, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the insulation breakdown voltage of the insulating layer 51 is enhanced.

[0103] The plurality of pad plug electrodes 82 are formed in the region between the high-potential terminal 12 (the first high-potential terminal 12A) and the high-potential connection wiring 81 within the uppermost insulating layer 56 and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively. The plurality of pad plug electrodes 82 each have a planar area less than the planar area of the high-potential connection wiring 81 in a plan view.

[0104] Referring to FIG. 9, a plurality of second high potential wirings 34 are electrically connected to corresponding high potential terminals 12E, 12F and the second outer ends 28 of corresponding transformers 21A to 21D (high potential coils 23), respectively. The plurality of second high potential wirings 34 each have a similar structure. Hereinafter, the structure of the second high potential wiring 34 connected to the fifth high potential terminal 12E and the first transformer 21A (second transformer 21B) will be described as an example. Regarding the description of the structures of the other second high potential wirings 34, the description of the structure of the second high potential wiring 34 connected to the first transformer 21A (second transformer 21B) shall apply mutatis mutandis and will be omitted.

[0105] Similar to the first high potential wiring 33, the second high potential wiring 34 includes a high potential connection wiring 81 and a pad plug electrode 82. The second high potential wiring 34 has a structure similar to that of the first high potential wiring 33, except that the high potential connection wiring 81 is electrically connected to the second outer ends 28 of the first transformer 21A (high potential coil 23) and the second outer ends 28 of the second transformer 21B (high potential coil 23).

[0106] The high potential connection wiring 81 of the second high potential wiring 34 is formed around the high potential coil 23 within the same interlayer insulating layer 57 as the high potential coil 23. The high potential connection wiring 81 is formed in a region between two adjacent high potential coils 23 in a plan view and faces the high potential terminal 12 (the fifth high potential terminal 12E) in the normal direction Z. The high potential connection wiring 81 is formed at an interval from the low potential connection wiring 72 in a plan view and does not face the low potential connection wiring 72 in the normal direction Z.

[0107] A plurality of pad plug electrodes 82 are formed in a region between the high potential terminal 12 (the fifth high potential terminal 12E) and the high potential connection wiring 81 within the topmost insulating layer 56 and are electrically connected to the high potential terminal 12 and the high potential connection wiring 81, respectively.

[0108] Referring to FIGS. 8 and 9, the distance D1 between the low potential terminal 11 and the high potential terminal 12 preferably exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2 < D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the breakdown voltage to be achieved.

[0109] Referring to FIGS. 7 to 12, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view. In FIGS. 10 to 12, the dummy pattern 85 is shown by hatching. The dummy pattern 85 includes a conductor. The dummy pattern 85 is preferably formed of the same conductive material as the low potential coil 22 or the like. That is, the dummy pattern 85 preferably includes a barrier layer and a main body layer, like the low potential coil 22 or the like.

[0110] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high potential coil 23 and the low potential coil 22 and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low potential coil 22 and the high potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high potential coil 23.

[0111] In this form, the dummy pattern 85 is routed in a dense line shape so as to partially cover and partially expose the area around one or more high-potential coils 23 in a plan view. In this form, the dummy pattern 85 is routed with a line density equal to that of the high-potential coil 23 per unit area. That the line density of the dummy pattern 85 is equal to that of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within the range of ±20% of the line density of the high-potential coil 23.

[0112] The dummy pattern 85 is preferably formed in an area close to the high-potential coil 23 with respect to the low-potential terminal 11 in a plan view. That the dummy pattern 85 is close to the high-potential coil 23 in a plan view means that the distance between the dummy pattern 85 and the high-potential coil 23 is less than the distance between the dummy pattern 85 and the low-potential terminal 11.

[0113] The depth position of the dummy pattern 85 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be relaxed. The dummy pattern 85 is preferably formed in an area close to the high-potential coil 23 with respect to the low-potential coil 22 in the normal direction Z. That the dummy pattern 85 is close to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 is less than the distance between the dummy pattern 85 and the low-potential coil 22 in the normal direction Z.

[0114] In this case, the electric field concentration on the high-potential coil 23 can be appropriately suppressed. In the normal direction Z, the smaller the distance between the dummy pattern 85 and the high-potential coil 23, the more the electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, the electric field concentration on the high-potential coil 23 can be more appropriately suppressed.

[0115] The dummy pattern 85 is preferably formed around a plurality of high-potential coils 23 so as to be interposed in a region between adjacent high-potential coils 23 in a plan view. In this case, by using the region between adjacent high-potential coils 23, an undesired electric field concentration on the plurality of high-potential coils 23 can be suppressed.

[0116] The dummy pattern 85 is preferably interposed in a region between the low-potential terminal 11 and the high-potential coil 23 in a plan view. In this case, an undesired conduction between the low-potential terminal 11 and the high-potential coil 23 due to the electric field concentration of the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably interposed in a region between the low-potential terminal 11 and the high-potential terminal 12 in a plan view. In this case, an undesired conduction between the low-potential terminal 11 and the high-potential terminal 12 due to the electric field concentration of the high-potential coil 23 can be suppressed.

[0117] In this form, the dummy pattern 85 is formed along a plurality of high-potential coils 23 in a plan view and is interposed in a region between adjacent high-potential coils 23. Further, the dummy pattern 85 collectively surrounds a region including a plurality of high-potential coils 23 and a plurality of high-potential terminals 12 in a plan view. Further, the dummy pattern 85 is interposed in a region between a plurality of low-potential terminals 11A to 11F and a plurality of high-potential coils 23 in a plan view. Further, the dummy pattern 85 is interposed in a region between a plurality of low-potential terminals 11A to 11F and a plurality of high-potential terminals 12A to 12F in a plan view.

[0118] Referring to FIGS. 7 to 12, the dummy pattern 85 includes a plurality of dummy patterns having different electrical states. The dummy pattern 85 includes a high-potential dummy pattern 86. The high-potential dummy pattern 86 is formed in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view. The high-potential dummy pattern 86 is formed in a pattern (discontinuous pattern) different from that of the high-potential coil 23 and the low-potential coil 22 and is independent of the transformers 21A to 21D. That is, the high-potential dummy pattern 86 does not function as the transformers 21A to 21D.

[0119] In this form, the high-potential dummy pattern 86 is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. In this form, the high-potential dummy pattern 86 is routed with a line density equal to that of the high-potential coil 23 per unit area. That the line density of the high-potential dummy pattern 86 is equal to that of the high-potential coil 23 means that the line density of the high-potential dummy pattern 86 falls within the range of ±20% of the line density of the high-potential coil 23.

[0120] The high-potential dummy pattern 86 shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high-potential coil 23. Specifically, the high-potential dummy pattern 86 shields the electric field between the low-potential coil 22 and the high-potential coil 23, thereby moving the electric field leaking to the upper side of the high-potential coil 23 away from the high-potential coil 23. Thereby, the electric field concentration of the high-potential coil 23 caused by the electric field leaking to the upper side of the high-potential coil 23 is suppressed.

[0121] A voltage higher than the voltage applied to the low-potential coil 22 is applied to the high-potential dummy pattern 86. Thereby, the voltage drop between the high-potential coil 23 and the high-potential dummy pattern 86 can be suppressed, so that the electric field concentration on the high-potential coil 23 can be suppressed. It is preferable that the voltage applied to the high-potential coil 23 is applied to the high-potential dummy pattern 86. That is, it is preferable that the high-potential dummy pattern 86 is fixed at the same potential as the high-potential coil 23. Thereby, the voltage drop between the high-potential coil 23 and the high-potential dummy pattern 86 can be surely suppressed, so that the electric field concentration on the high-potential coil 23 can be appropriately suppressed.

[0122] The depth position of the high-potential dummy pattern 86 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 with respect to the normal direction Z. That the high-potential dummy pattern 86 is closer to the high-potential coil 23 with respect to the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22 with respect to the normal direction Z.

[0123] In this case, the electric field concentration on the high-potential coil 23 can be appropriately suppressed. With respect to the normal direction Z, the smaller the distance between the high-potential dummy pattern 86 and the high-potential coil 23, the more the electric field concentration on the high-potential coil 23 can be suppressed. The high-potential dummy pattern 86 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, the electric field concentration on the high-potential coil 23 can be more appropriately suppressed.

[0124] The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential terminal 11 in a plan view. That the high-potential dummy pattern 86 is closer to the high-potential coil 23 in a plan view means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential terminal 11.

[0125] The high-potential dummy pattern 86 is preferably formed around a plurality of adjacent high-potential coils 23 so as to be interposed in the region between the plurality of adjacent high-potential coils 23. In this case, by using the region between the plurality of adjacent high-potential coils 23, the undesired electric field concentration on the plurality of high-potential coils 23 can be suppressed.

[0126] The high-potential dummy pattern 86 is preferably interposed in the region between the low-potential terminal 11 and the high-potential coil 23 in a plan view. In this case, it is possible to suppress the undesired conduction between the low-potential terminal 11 and the high-potential coil 23 due to the electric field concentration of the high-potential coil 23. The high-potential dummy pattern 86 is preferably interposed in the region between the low-potential terminal 11 and the high-potential terminal 12 in a plan view. In this case, it is possible to suppress the undesired conduction between the low-potential terminal 11 and the high-potential terminal 12 due to the electric field concentration of the high-potential coil 23.

[0127] In this form, the high-potential dummy pattern 86 is formed along a plurality of high-potential coils 23 in a plan view and is interposed in the region between adjacent high-potential coils 23. Further, the high-potential dummy pattern 86 collectively surrounds the region including the plurality of high-potential coils 23 and the plurality of high-potential terminals 12 in a plan view. Further, the high-potential dummy pattern 86 is interposed in the region between the plurality of low-potential terminals 11A to 11F and the plurality of high-potential coils 23 in a plan view. Further, the high-potential dummy pattern 86 is interposed in the region between the plurality of low-potential terminals 11A to 11F and the plurality of high-potential terminals 12A to 12F in a plan view.

[0128] The high-potential dummy pattern 86 is routed around the high-potential terminals 12E and 12F so as to expose the region directly below the high-potential terminals 12E and 12F in the region between adjacent high-potential coils 23 in a plan view. A part of the high-potential dummy pattern 86 may face the high-potential terminals 12A to 12F in the normal direction Z. In this case, the high-potential terminals 12E and 12F, like the high-potential dummy pattern 86, suppress the electric field leaking to the upper side of the high-potential coil 23 by shielding the electric field. That is, the high-potential terminals 12E and 12F are formed as a shield conductor layer that suppresses the electric field concentration on the high-potential coil 23 together with the high-potential dummy pattern 86.

[0129] The high-potential dummy pattern 86 is preferably formed in an open-ended shape. In this case, it is possible to suppress the formation of a current loop circuit (closed circuit) in the high-potential dummy pattern 86. As a result, noise caused by the current flowing through the high-potential dummy pattern 86 is suppressed. Consequently, it is possible to suppress undesired electric field concentration caused by the noise and, at the same time, suppress fluctuations in the electrical characteristics of the transformers 21A to 21D.

[0130] Specifically, the high-potential dummy pattern 86 includes a first high-potential dummy pattern 87 and a second high-potential dummy pattern 88. The first high-potential dummy pattern 87 is formed in a region between a plurality of adjacent transformers 21A to 21D (a plurality of high-potential coils 23) in a plan view. The second high-potential dummy pattern 88 is formed in a region outside the region between a plurality of adjacent transformers 21A to 21D (a plurality of high-potential coils 23) in a plan view.

[0131] Hereinafter, the region between the adjacent first transformer 21A (high-potential coil 23) and the second transformer 21B (high-potential coil 23) is referred to as a first region 89. Also, the region between the second transformer 21B (high-potential coil 23) and the third transformer 21C (high-potential coil 23) is referred to as a second region 90. Also, the region between the third transformer 21C (high-potential coil 23) and the fourth transformer 21D (high-potential coil 23) is referred to as a third region 91.

[0132] In this form, the first high-potential dummy pattern 87 is electrically connected to the high-potential terminal 12 (the fifth high-potential terminal 12E) via the second high-potential wiring 34. Specifically, the first high-potential dummy pattern 87 includes a first connection portion 92 connected to the second high-potential wiring 34. The position of the first connection portion 92 is arbitrary. As a result, the first high-potential dummy pattern 87 is fixed at the same potential as the plurality of high-potential coils 23.

[0133] The first high potential dummy pattern 87 specifically includes a first pattern 93 formed in the first region 89, a second pattern 94 formed in the second region 90, and a third pattern 95 formed in the third region 91. Thereby, the first high potential dummy pattern 87 suppresses the electric field leaking above the high potential coil 23 in the first region 89, the second region 90, and the third region 91, and suppresses the electric field concentration on a plurality of adjacent high potential coils 23.

[0134] In this form, the first pattern 93, the second pattern 94, and the third pattern 95 are integrally formed and fixed at the same potential. The first pattern 93, the second pattern 94, and the third pattern 95 may be separated as long as they are fixed at the same potential.

[0135] Referring to FIGS. 7 and 10, the first pattern 93 is connected to the second high potential wiring 34 via the first connection portion 92. The first pattern 93 is routed in a dense line shape so as to cover a part of the first region 89 in plan view. The first pattern 93 is formed in the first region 89 at a distance from the high potential terminal 12 (the fifth high potential terminal 12E) in plan view and does not face the high potential terminal 12 in the normal direction Z. Further, the first pattern 93 is formed at a distance from the low potential connection wiring 72 in plan view and does not face the low potential connection wiring 72 in the normal direction Z. Thereby, the insulation distance between the first pattern 93 and the low potential connection wiring 72 is increased, and the dielectric breakdown voltage of the insulating layer 51 is increased.

[0136] The first pattern 93 includes a first outer peripheral line 96, a second outer peripheral line 97, and a plurality of first intermediate lines 98. The first outer peripheral line 96 extends in a band shape along the periphery of the high potential coil 23 of the first transformer 21A. In this form, the first outer peripheral line 96 is formed in a ring shape having an open end in the first region 89 in plan view. The width of the open end of the first outer peripheral line 96 is less than the width along the second direction Y of the high potential coil 23.

[0137] The width of the first outer peripheral line 96 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the first outer peripheral line 96 is 1 μm or more and 3 μm or less. The width of the first outer peripheral line 96 is defined by the width in the direction orthogonal to the direction in which the first outer peripheral line 96 extends. Preferably, the width of the first outer peripheral line 96 is equal to the width of the high-potential coil 23. That the width of the first outer peripheral line 96 is equal to the width of the high-potential coil 23 means that the width of the first outer peripheral line 96 falls within the range of ±20% of the width of the high-potential coil 23.

[0138] The first pitch between the first outer peripheral line 96 and the high-potential coil 23 (the first transformer 21A) may be 0.1 μm or more and 5 μm or less. Preferably, the first pitch is 1 μm or more and 3 μm or less. Preferably, the first pitch is equal to the second winding pitch of the high-potential coil 23. That the first pitch is equal to the first winding pitch means that the first pitch falls within the range of ±20% of the first winding pitch.

[0139] The second outer peripheral line 97 extends in a strip shape along the periphery of the high-potential coil 23 of the second transformer 21B. In this form, the second outer peripheral line 97 is formed in a ring shape having an open end in the first region 89 in a plan view. The width of the open end of the second outer peripheral line 97 is less than the width along the second direction Y of the high-potential coil 23. The open end of the second outer peripheral line 97 faces the open end of the first outer peripheral line 96 along the first direction X.

[0140] The width of the second outer peripheral line 97 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the second outer peripheral line 97 is 1 μm or more and 3 μm or less. The width of the second outer peripheral line 97 is defined by the width in the direction orthogonal to the direction in which the second outer peripheral line 97 extends. Preferably, the width of the second outer peripheral line 97 is equal to the width of the high-potential coil 23. That the width of the second outer peripheral line 97 is equal to the width of the high-potential coil 23 means that the width of the second outer peripheral line 97 falls within the range of ±20% of the width of the high-potential coil 23.

[0141] The second pitch between the second outer line 97 and the high-potential coil 23 (second transformer 21B) may be 0.1 μm or more and 5 μm or less. The second pitch is preferably 1 μm or more and 3 μm or less. The second pitch is preferably equal to the second winding pitch of the high-potential coil 23. That the second pitch is equal to the second winding pitch means that the second pitch falls within a range of ±20% of the second winding pitch.

[0142] The plurality of first intermediate lines 98 extend in a strip shape in the region between the first outer line 96 and the second outer line 97 in the first region 89. The plurality of first intermediate lines 98 include at least one (one in this embodiment) first connection line 99 that electrically connects the first outer line 96 and the second outer line 97.

[0143] From the viewpoint of preventing the formation of a current loop circuit, it is preferable that the plurality of first intermediate lines 98 include only one first connection line 99. The position of the first connection line 99 is arbitrary. A slit 100 for blocking the current loop circuit is formed in at least one of the plurality of first intermediate lines 98. The position of the slit 100 is appropriately adjusted according to the design of the plurality of first intermediate lines 98.

[0144] The plurality of first intermediate lines 98 are preferably formed in a strip shape extending along the facing direction of the plurality of high-potential coils 23. In this embodiment, the plurality of first intermediate lines 98 are each formed in a strip shape extending in the first direction X and are formed at intervals in the second direction Y. The plurality of first intermediate lines 98 are formed in a stripe shape extending in the first direction X as a whole in a plan view.

[0145] Specifically, the plurality of first intermediate lines 98 include a plurality of first lead portions 101 and a plurality of second lead portions 102. The plurality of first lead portions 101 are drawn out in a stripe shape from the first outer line 96 toward the second outer line 97. The tip portions of the plurality of first lead portions 101 are formed at intervals from the first outer line 96 toward the second outer line 97 side.

[0146] The plurality of second lead-out portions 102 are drawn out in a stripe shape from the second outer peripheral line 97 toward the first outer peripheral line 96. The tip portions of the plurality of second lead-out portions 102 are formed at intervals from the second outer peripheral line 97 toward the first outer peripheral line 96 side. In this form, the plurality of second lead-out portions 102 are formed at intervals alternately with the plurality of first lead-out portions 101 in the second direction Y in a manner of sandwiching one first lead-out portion 101.

[0147] The plurality of second lead-out portions 102 may sandwich the plurality of first lead-out portions 101. Also, a group including the plurality of second lead-out portions 102 may be formed adjacent to a group including the plurality of first lead-out portions 101. The slit 100, the plurality of first lead-out portions 101, and the plurality of second lead-out portions 102 suppress the formation of a current loop circuit in the first pattern 93.

[0148] The width of the first intermediate line 98 in the second direction Y may be 0.1 μm or more and 5 μm or less. The width of the first intermediate line 98 is preferably 1 μm or more and 3 μm or less. The width of the first intermediate line 98 is preferably equal to the width of the high-potential coil 23. That the width of the first intermediate line 98 is equal to the width of the high-potential coil 23 means that the width of the first intermediate line 98 falls within a range of ±20% of the width of the high-potential coil 23.

[0149] The third pitch between two adjacent first intermediate lines 98 may be 0.1 μm or more and 5 μm or less. The third pitch is preferably 1 μm or more and 3 μm or less. The third pitch is defined by the distance between adjacent first intermediate lines 98 in the second direction Y. The third pitches are preferably equal to each other. That the third pitches are equal to each other means that the third pitch falls within a range of ±20% of the third pitch. The third pitch is preferably equal to the second winding pitch of the high-potential coil 23. That the third pitch is equal to the second winding pitch means that the third pitch falls within a range of ±20% of the second winding pitch.

[0150] Referring to FIGS. 7 and 11, the second pattern 94 is electrically connected to the high potential terminal 12 via the first high potential wiring 33. In this embodiment, the second pattern 94 is electrically connected to the second high potential wiring 34 (the fifth high potential terminal 12E) via the second outer peripheral line 97 of the first pattern 93. The second pattern 94 is routed in a dense line shape so as to cover the second region 90.

[0151] The second pattern 94 includes the aforementioned second outer peripheral line 97, the third outer peripheral line 103, and a plurality of second intermediate lines 104. The third outer peripheral line 103 extends in a band shape along the periphery of the high potential coil 23 of the third transformer 21C. In this embodiment, the third outer peripheral line 103 is formed in a ring shape having an open end in the third region 91 in a plan view. The width of the open end of the third outer peripheral line 103 is less than the width along the second direction Y of the high potential coil 23 of the third transformer 21C.

[0152] The width of the third outer peripheral line 103 may be 0.1 μm or more and 5 μm or less. The width of the third outer peripheral line 103 is preferably 1 μm or more and 3 μm or less. The width of the third outer peripheral line 103 is defined by the width in a direction orthogonal to the direction in which the third outer peripheral line 103 extends. The width of the third outer peripheral line 103 is preferably equal to the width of the high potential coil 23. That the width of the third outer peripheral line 103 is equal to the width of the high potential coil 23 means that the width of the third outer peripheral line 103 falls within the range of ±20% of the width of the high potential coil 23.

[0153] The fourth pitch between the third outer peripheral line 103 and the high potential coil 23 (the third transformer 21C) may be 0.1 μm or more and 5 μm or less. The fourth pitch is preferably 1 μm or more and 3 μm or less. The fourth pitch is preferably equal to the second winding pitch of the high potential coil 23. That the fourth pitch is equal to the second winding pitch means that the fourth pitch falls within the range of ±20% of the second winding pitch.

[0154] A plurality of second intermediate lines 104 extend in a strip shape in the region between the second outer peripheral line 97 and the third outer peripheral line 103 in the second region 90. The plurality of second intermediate lines 104 include at least one (one in this embodiment) second connection line 105 that electrically connects the second outer peripheral line 97 and the third outer peripheral line 103.

[0155] From the perspective of preventing the formation of a current loop circuit, it is preferable that the plurality of second intermediate lines 104 include only one second connection line 105. The second connection line 105 may have a width exceeding the width of the other second intermediate lines 104. The position of the second connection line 105 is arbitrary. At least one of the plurality of second intermediate lines 104 is formed with a slit 106 that cuts off the current loop circuit. The position of the slit 106 is appropriately adjusted according to the design of the plurality of second intermediate lines 104.

[0156] The plurality of second intermediate lines 104 are preferably formed in a strip shape extending along the opposing direction of the plurality of high potential coils 23. In this embodiment, the plurality of second intermediate lines 104 are each formed in a strip shape extending in the first direction X and are spaced apart in the second direction Y. The plurality of second intermediate lines 104 are formed in a stripe shape extending in the first direction X as a whole in a plan view.

[0157] Specifically, the plurality of second intermediate lines 104 include a plurality of third lead-out portions 107 and a plurality of fourth lead-out portions 108. The plurality of third lead-out portions 107 are drawn out in a stripe shape from the second outer peripheral line 97 toward the third outer peripheral line 103. The tip portions of the plurality of third lead-out portions 107 are formed at intervals from the third outer peripheral line 103 toward the second outer peripheral line 97 side.

[0158] The plurality of fourth lead-out portions 108 are drawn out in a stripe shape from the third outer peripheral line 103 toward the second outer peripheral line 97. The tip ends of the plurality of fourth lead-out portions 108 are formed at intervals from the second outer peripheral line 97 toward the third outer peripheral line 103 side. In this form, the plurality of fourth lead-out portions 108 are formed with intervals alternately with the plurality of third lead-out portions 107 in the second direction Y in a manner of sandwiching one third lead-out portion 107.

[0159] The plurality of fourth lead-out portions 108 may sandwich the plurality of third lead-out portions 107. Also, a group including the plurality of fourth lead-out portions 108 may be formed so as to be adjacent to a group including the plurality of third lead-out portions 107. The slit 106, the plurality of third lead-out portions 107, and the plurality of fourth lead-out portions 108 suppress the formation of a current loop circuit in the second pattern 94.

[0160] The width of the second intermediate line 104 in the second direction Y may be 0.1 μm or more and 5 μm or less. The width of the second intermediate line 104 is preferably 1 μm or more and 3 μm or less. The width of the second intermediate line 104 is preferably equal to the width of the high-potential coil 23. That the width of the second intermediate line 104 is equal to the width of the high-potential coil 23 means that the width of the second intermediate line 104 falls within a range of ±20% of the width of the high-potential coil 23.

[0161] The fifth pitch between two adjacent second intermediate lines 104 may be 0.1 μm or more and 5 μm or less. The fifth pitch is preferably 1 μm or more and 3 μm or less. The fifth pitch is defined by the distance between adjacent second intermediate lines 104 in the second direction Y. The fifth pitches are preferably equal to each other. That the fifth pitches are equal to each other means that the fifth pitch falls within a range of ±20% of the fifth pitch. The fifth pitch is preferably equal to the second winding pitch of the high-potential coil 23. That the fifth pitch is equal to the second winding pitch means that the fifth pitch falls within a range of ±20% of the second winding pitch.

[0162] Referring to FIGS. 7 and 12, the third pattern 95 is electrically connected to the second high-potential wiring 34. In this form, the third pattern 95 is electrically connected to the second high-potential wiring 34 via the second pattern 94 and the first pattern 93. The third pattern 95 is routed in a dense line shape so as to cover a part of the third region 91. The third pattern 95 is formed in the third region 91 at a distance from the high-potential terminal 12 (the sixth high-potential terminal 12F) in a plan view and does not face the high-potential terminal 12 in the normal direction Z.

[0163] The third pattern 95 is formed at a distance from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z. As a result, the insulation distance between the third pattern 95 and the low-potential connection wiring 72 is increased in the normal direction Z, and the breakdown voltage of the insulating layer 51 is enhanced.

[0164] The third pattern 95 includes the aforementioned third outer peripheral line 103, fourth outer peripheral line 109, and a plurality of third intermediate lines 110. The fourth outer peripheral line 109 extends in a strip shape along the periphery of the high-potential coil 23 of the fourth transformer 21D. In this form, the fourth outer peripheral line 109 is formed in a ring shape having an open end in the third region 91 in a plan view. The width of the open end of the fourth outer peripheral line 109 is less than the width along the second direction Y of the high-potential coil 23 of the fourth transformer 21D. The open end of the fourth outer peripheral line 109 faces the open end of the third outer peripheral line 103 along the first direction X.

[0165] The width of the fourth outer peripheral line 109 may be 0.1 μm or more and 5 μm or less. The width of the fourth outer peripheral line 109 is preferably 1 μm or more and 3 μm or less. The width of the fourth outer peripheral line 109 is defined by the width in a direction orthogonal to the direction in which the fourth outer peripheral line 109 extends. The width of the fourth outer peripheral line 109 is preferably equal to the width of the high-potential coil 23. That the width of the fourth outer peripheral line 109 is equal to the width of the high-potential coil 23 means that the width of the fourth outer peripheral line 109 falls within the range of ±20% of the width of the high-potential coil 23.

[0166] The sixth pitch between the fourth outer line 109 and the high-potential coil 23 (the fourth transformer 21D) may be 0.1 μm or more and 5 μm or less. The sixth pitch is preferably 1 μm or more and 3 μm or less. The sixth pitch is preferably equal to the second winding pitch of the high-potential coil 23. That the sixth pitch is equal to the second winding pitch means that the sixth pitch falls within a range of ±20% of the second winding pitch.

[0167] The plurality of third intermediate lines 110 extend in a band shape in a region between the third outer line 103 and the fourth outer line 109 in the third region 91. The plurality of third intermediate lines 110 include at least one (one in this embodiment) third connection line 111 that electrically connects the third outer line 103 and the fourth outer line 109.

[0168] From the viewpoint of preventing the formation of a loop circuit of current, it is preferable that the plurality of third intermediate lines 110 include only one third connection line 111. The position of the third connection line 111 is arbitrary. At least one of the plurality of third intermediate lines 110 is formed with a slit 112 that interrupts the loop circuit of current. The position of the slit 112 is appropriately adjusted according to the design of the plurality of third intermediate lines 110.

[0169] The plurality of third intermediate lines 110 are preferably formed in a band shape extending along the facing direction of the plurality of high-potential coils 23. In this embodiment, the plurality of third intermediate lines 110 are each formed in a band shape extending in the first direction X and are spaced apart in the second direction Y. The plurality of third intermediate lines 110 are formed in a stripe shape as a whole in a plan view.

[0170] In this embodiment, the plurality of third intermediate lines 110 include a plurality of fifth lead portions 113 and a plurality of sixth lead portions 114. The plurality of fifth lead portions 113 are drawn out in a stripe shape from the third outer line 103 toward the fourth outer line 109. The tip portions of the plurality of fifth lead portions 113 are formed at intervals from the fourth outer line 109 toward the third outer line 103 side.

[0171] The plurality of sixth lead-out portions 114 are drawn out in a stripe shape from the fourth outer peripheral line 109 toward the third outer peripheral line 103. The tip portions of the plurality of sixth lead-out portions 114 are formed at intervals from the third outer peripheral line 103 toward the fourth outer peripheral line 109 side. In this form, the plurality of sixth lead-out portions 114 are formed alternately at intervals with the plurality of fifth lead-out portions 113 in the second direction Y in a manner of sandwiching one fifth lead-out portion 113.

[0172] The plurality of sixth lead-out portions 114 may sandwich the plurality of fifth lead-out portions 113. Also, a group including the plurality of sixth lead-out portions 114 may be formed adjacent to a group including the plurality of fifth lead-out portions 113. The slit 112, the plurality of fifth lead-out portions 113, and the plurality of sixth lead-out portions 114 suppress the formation of a current loop circuit in the third pattern 95.

[0173] The width of the third intermediate line 110 in the second direction Y may be 0.1 μm or more and 5 μm or less. The width of the third intermediate line 110 is preferably 1 μm or more and 3 μm or less. The width of the third intermediate line 110 is preferably equal to the width of the high-potential coil 23. That the width of the third intermediate line 110 is equal to the width of the high-potential coil 23 means that the width of the third intermediate line 110 falls within a range of ±20% of the width of the high-potential coil 23.

[0174] The seventh pitch between two adjacent third intermediate lines 110 may be 0.1 μm or more and 5 μm or less. The seventh pitch is preferably 1 μm or more and 3 μm or less. The seventh pitch is defined by the distance between adjacent third intermediate lines 110 in the second direction Y. The seventh pitches are preferably equal to each other. That the seventh pitches are equal to each other means that the seventh pitch falls within a range of ±20% of the seventh pitch. The seventh pitch is preferably equal to the second winding pitch of the high-potential coil 23. That the seventh pitch is equal to the second winding pitch means that the seventh pitch falls within a range of ±20% of the second winding pitch.

[0175] Referring to FIGS. 7 to 12, in this embodiment, the second high-potential dummy pattern 88 is electrically connected to the high-potential terminal 12 via the first high-potential dummy pattern 87. Specifically, the second high-potential dummy pattern 88 includes a second connection portion 115 connected to the first high-potential dummy pattern 87. The position of the second connection portion 115 is arbitrary. Thereby, the second high-potential dummy pattern 88 is fixed at the same potential as the plurality of high-potential coils 23.

[0176] The second high-potential dummy pattern 88 suppresses the electric field leaking above the high-potential coils 23 and suppresses the electric field concentration on the plurality of high-potential coils 23 in a region outside the first region 89, the second region 90, and the third region 91. In this embodiment, the second high-potential dummy pattern 88 collectively surrounds the region including the plurality of high-potential coils 23 and the plurality of high-potential terminals 12A to 12F in a plan view. In this embodiment, the second high-potential dummy pattern 88 is formed in an oval ring shape (elliptical ring shape) in a plan view.

[0177] Thereby, the second high-potential dummy pattern 88 is interposed in the region between the plurality of low-potential terminals 11A to 11F and the plurality of high-potential coils 23 in a plan view. Also, the second high-potential dummy pattern 88 is interposed in the region between the plurality of low-potential terminals 11A to 11F and the plurality of high-potential terminals 12A to 12F in a plan view.

[0178] The second high-potential dummy pattern 88 includes a plurality (six in this embodiment) of high-potential lines 116A, 116B, 116C, 116D, 116E, 116F. The number of high-potential lines is adjusted according to the electric field to be relaxed. The plurality of high-potential lines 116A to 116F are formed at intervals in this order in a direction away from the plurality of high-potential coils 23.

[0179] The plurality of high potential lines 116A to 116F collectively surround the plurality of high potential coils 23 in a plan view. Specifically, the plurality of high potential lines 116A to 116F collectively surround the region including the plurality of high potential coils 23 and the plurality of high potential terminals 12A to 12F in a plan view. In this form, the plurality of high potential lines 116A to 116F are formed in an oval ring shape (elliptical ring shape) in a plan view.

[0180] The plurality of high potential lines 116A to 116F each include a slit 117 that cuts off the current loop circuit. The position of the slit 117 is appropriately adjusted according to the design of the plurality of high potential lines 116A to 116F.

[0181] The width of the high potential lines 116A to 116F may be 0.1 μm or more and 5 μm or less. The width of the high potential lines 116A to 116F is preferably 1 μm or more and 3 μm or less. The width of the high potential lines 116A to 116F is defined by the width in the direction orthogonal to the direction in which the high potential lines 116A to 116F extend. The width of the high potential lines 116A to 116F is preferably equal to the width of the high potential coil 23. That the width of the high potential lines 116A to 116F is equal to the width of the high potential coil 23 means that the width of the high potential lines 116A to 116F falls within the range of ±20% of the width of the high potential coil 23.

[0182] The eighth pitch between two adjacent high potential lines 116A to 116F may be 0.1 μm or more and 5 μm or less. The eighth pitch is preferably 1 μm or more and 3 μm or less. The eighth pitches are preferably equal to each other. That the eighth pitches are equal to each other means that the eighth pitch falls within the range of ±20% of the said eighth pitch.

[0183] The ninth pitch between the adjacent first high-potential dummy patterns 87 and second high-potential dummy patterns 88 may be 0.1 μm or more and 5 μm or less. The ninth pitch is preferably 1 μm or more and 3 μm or less. The ninth pitch is preferably equal to the second winding pitch of the high-potential coil 23. That the ninth pitch is equal to the second winding pitch means that the ninth pitch falls within the range of ±20% of the second winding pitch. The number, width, pitch, etc. of the plurality of high-potential lines 116A to 116F are arbitrary and are adjusted according to the electric field to be relaxed.

[0184] Referring to FIGS. 7 to 12, the dummy pattern 85 includes a floating dummy pattern 121 formed in a floating state electrically in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view. The floating dummy pattern 121 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22 and is independent of the transformers 21A to 21D. That is, the floating dummy pattern 121 does not function as the transformers 21A to 21D.

[0185] In this form, the floating dummy pattern 121 is routed in a dense line shape so as to partially cover and partially expose the region around the high-potential coil 23 in a plan view. The floating dummy pattern 121 may be formed in an end shape or an endless shape.

[0186] The floating dummy pattern 121 is routed with a line density equal to the line density of the high-potential coil 23 per unit area. That the line density of the floating dummy pattern 121 is equal to the line density of the high-potential coil 23 means that the line density of the floating dummy pattern 121 falls within the range of ±20% of the line density of the high-potential coil 23.

[0187] Further, the floating dummy pattern 121 is routed with a line density equal to that of the high-potential dummy pattern 86 per unit area. That the line density of the floating dummy pattern 121 is equal to that of the high-potential dummy pattern 86 means that the line density of the floating dummy pattern 121 falls within the range of ±20% of the line density of the high-potential dummy pattern 86.

[0188] The floating dummy pattern 121 shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high-potential coil 23. Specifically, the floating dummy pattern 121 disperses the electric field leaking to the upper side of the high-potential coil 23 in a direction away from the high-potential coil 23. Thereby, the electric field concentration on the high-potential coil 23 can be suppressed.

[0189] Also, the floating dummy pattern 121 disperses the electric field leaking to the upper side of the high-potential dummy pattern 86 around the high-potential dummy pattern 86 in a direction away from the high-potential coil 23 and the high-potential dummy pattern 86. Thereby, the electric field concentration on the high-potential dummy pattern 86 can be suppressed, and at the same time, the electric field concentration on the high-potential coil 23 can be appropriately suppressed.

[0190] The depth position of the floating dummy pattern 121 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be relaxed. The floating dummy pattern 121 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 with respect to the normal direction Z. That the floating dummy pattern 121 is closer to the high-potential coil 23 with respect to the normal direction Z means that the distance between the floating dummy pattern 121 and the high-potential coil 23 is less than the distance between the floating dummy pattern 121 and the low-potential coil 22 with respect to the normal direction Z.

[0191] In this case, the electric field concentration on the high-potential coil 23 can be appropriately suppressed. Regarding the normal direction Z, the smaller the distance between the floating dummy pattern 121 and the high-potential coil 23, the more effectively the electric field concentration on the high-potential coil 23 can be suppressed. The floating dummy pattern 121 is preferably formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, the electric field concentration on the high-potential coil 23 can be more appropriately suppressed.

[0192] The floating dummy pattern 121 preferably intervenes in the region between the low-potential terminal 11 and the high-potential coil 23 in a plan view. In this case, the undesired conduction between the low-potential terminal 11 and the high-potential coil 23 due to the electric field concentration of the high-potential coil 23 can be suppressed. The floating dummy pattern 121 preferably intervenes in the region between the low-potential terminal 11 and the high-potential terminal 12 in a plan view. In this case, the undesired conduction between the low-potential terminal 11 and the high-potential terminal 12 due to the electric field concentration of the high-potential coil 23 can be suppressed.

[0193] In this form, the floating dummy pattern 121 is formed along a plurality of high-potential coils 23 in a plan view. Specifically, the floating dummy pattern 121 collectively surrounds the region including a plurality of high-potential coils 23 and a plurality of high-potential terminals 12 in a plan view. In this form, the floating dummy pattern 121 collectively surrounds the region including a plurality of high-potential coils 23 and a plurality of high-potential terminals 12 with the high-potential dummy pattern 86 (second high-potential dummy pattern 88) sandwiched therebetween in a plan view.

[0194] As a result, the floating dummy pattern 121 intervenes in the region between a plurality of low-potential terminals 11A to 11F and a plurality of high-potential coils 23 in a plan view. Also, the floating dummy pattern 121 intervenes in the region between a plurality of low-potential terminals 11A to 11F and a plurality of high-potential terminals 12A to 12F in a plan view.

[0195] The number of floating lines is arbitrary and is adjusted according to the electric field to be relaxed. The floating dummy pattern 121 includes, in this form, a plurality (six in this form) of floating lines 122A, 122B, 122C, 122D, 122E, and 122F. The plurality of floating lines 122A to 122F are formed at intervals in this order in a direction away from the plurality of high-potential coils 23.

[0196] The plurality of floating lines 122A to 122F collectively surround the plurality of high-potential coils 23 in a plan view. Specifically, the plurality of floating lines 122A to 122F collectively surround a region including the plurality of high-potential coils 23 and the plurality of high-potential terminals 12A to 12F with the high-potential dummy pattern 86 interposed therebetween in a plan view. The plurality of floating lines 122A to 122F are formed in an oval ring shape (elliptical ring shape) in a plan view in this form.

[0197] The width of the floating lines 122A to 122F may be 0.1 μm or more and 5 μm or less. The width of the floating lines 122A to 122F is preferably 1 μm or more and 3 μm or less. The width of the floating lines 122A to 122F is defined by the width in a direction orthogonal to the direction in which the floating lines 122A to 122F extend.

[0198] The tenth pitch between two adjacent floating lines 122A to 122F may be 0.1 μm or more and 5 μm or less. The tenth pitch is preferably 1 μm or more and 3 μm or less. The width of the floating lines 122A to 122F is preferably equal to the width of the high-potential coil 23. That the width of the floating lines 122A to 122F is equal to the width of the high-potential coil 23 means that the width of the floating lines 122A to 122F falls within a range of ±20% of the width of the high-potential coil 23.

[0199] The 11th pitch between the floating dummy pattern 121 and the high-potential dummy pattern 86 (the second high-potential dummy pattern 88) may be 0.1 μm or more and 5 μm or less. The 11th pitch is preferably 1 μm or more and 3 μm or less. The 11th pitches are preferably equal to each other. That the 11th pitches are equal to each other means that the 11th pitch falls within a range of ±20% of the 11th pitch.

[0200] The 11th pitch is preferably equal to the second winding pitch of the high-potential coil 23. That the 11th pitch between the floating lines 122A to 122F is equal to the second winding pitch means that the 11th pitch falls within a range of ±20% of the second winding pitch. In FIGS. 10 to 12, for clarity, an example in which the 11th pitch exceeds the second winding pitch is shown.

[0201] The 12th pitch between the floating dummy pattern 121 and the high-potential dummy pattern 86 is preferably equal to the second winding pitch. That the 12th pitch is equal to the second winding pitch means that the 12th pitch falls within a range of ±20% of the second winding pitch. The number, width, pitch, etc. of the plurality of floating lines 122A to 122F are adjusted according to the electric field to be relaxed and are not limited to specific values.

[0202] Referring to FIGS. 8 and 9, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in the device region 62. The second functional device 60 is formed using the surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or the region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (the bottommost insulating layer 55). In FIGS. 8 and 9, the second functional device 60 is schematically shown by a broken line shown in the surface layer portion of the first main surface 42.

[0203] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring and to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has the same structure as the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed in the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed in the insulating layer 51 so as to be connected to the second functional device 60. Specific descriptions of the low-potential wiring and high-potential wiring related to the second functional device 60 are omitted.

[0204] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The passive device may include a circuit network in which any two or more of a passive device, a semiconductor rectifying device, and a semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0205] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0206] Referring to FIGS. 8 and 9, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating sidewalls 53A to 53D in a plan view, and partitions the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 suppresses the entry of moisture and cracks from the outer region 63 into the device region 62.

[0207] The device region 62 is a region including the first functional device 45 (a plurality of transformers 21), the second functional device 60, a plurality of low-potential terminals 11, a plurality of high-potential terminals 12, a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, a second high-potential wiring 34, and a dummy pattern 85. The outer region 63 is a region outside the device region 62.

[0208] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (a plurality of transformers 21), the second functional device 60, a plurality of low-potential terminals 11, a plurality of high-potential terminals 12, a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, a second high-potential wiring 34, and a dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path connecting to the device region 62.

[0209] The seal conductor 61 is formed in a strip shape along the insulating sidewalls 53 to 53D in a plan view. In this form, the seal conductor 61 is formed in a square ring shape (specifically, a rectangular ring shape) in a plan view. Thereby, the seal conductor 61 partitions the device region 62 having a square shape (specifically, a rectangular shape) in a plan view. Also, the seal conductor 61 partitions an outer region 63 having a square ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in a plan view.

[0210] Specifically, the seal conductor 61 has an upper end portion on the insulating main surface 52 side, a lower end portion on the semiconductor chip 41 side, and a wall portion extending in a wall shape between the upper end portion and the lower end portion. In this form, the upper end portion of the seal conductor 61 is formed at a distance from the insulating main surface 52 toward the semiconductor chip 41 side and is located within the insulating layer 51. In this form, the upper end portion of the seal conductor 61 is covered by the top insulating layer 56. The upper end portion of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end portion of the seal conductor 61 may be exposed from the top insulating layer 56. The lower end portion of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end portion side.

[0211] Thus, in this form, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low-potential terminals 11 and the plurality of high-potential terminals 12. Also, the seal conductor 61 faces the first functional device 45 (a plurality of transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating main surface 52 within the insulating layer 51. The seal conductor 61 may face a part of the second functional device 60 in a direction parallel to the insulating main surface 52 within the insulating layer 51.

[0212] The seal conductor 61 includes a plurality of seal plug conductors (first portion) 64 and one or more (a plurality in this form) seal via conductors (second portion) 65. The number of the seal via conductors 65 is arbitrary. The top seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed of the same conductive material as the low-potential coil 22. That is, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22 and the like.

[0213] The plurality of seal plug conductors 64 are respectively embedded in the plurality of interlayer insulating layers 57 and are each formed in a rectangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in a plan view. The plurality of seal plug conductors 64 are laminated from the bottommost insulating layer 55 toward the topmost insulating layer 56 so as to be connected to each other. The number of laminated seal plug conductors 64 matches the number of laminated interlayer insulating layers 57. Of course, one or more seal plug conductors 64 penetrating the plurality of interlayer insulating layers 57 may be formed.

[0214] If one annular seal conductor 61 is formed by the aggregate of the plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end-shaped manner. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of end-shaped strip portions. However, in view of the risk of moisture and crack entry into the device region 62, the plurality of seal plug conductors 64 are preferably formed in an endless (annular) shape.

[0215] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the bottommost insulating layer 55. The plurality of seal via conductors 65 are formed at intervals from the semiconductor chip 41 and are connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area less than the planar area of the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of the seal plug conductor 64.

[0216] The width of the seal conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the seal conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the seal conductor 61 is defined by the width in a direction orthogonal to the direction in which the seal conductor 61 extends.

[0217] Referring to FIGS. 8, 9, and 13, the semiconductor device 5 further includes a separation structure 130 interposed between the semiconductor chip 41 and the seal conductor 61, which electrically isolates the seal conductor 61 from the semiconductor chip 41. The separation structure 130 preferably includes an insulator. In this form, the separation structure 130 is composed of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0218] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 preferably consists of a LOCOS (local oxidation of silicon) film as an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0219] The separation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the seal conductor 61 in plan view. In this form, the separation structure 130 is formed in a square ring shape (specifically, a rectangular ring shape) in plan view. The separation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion in which the lower end portion (seal via conductor 65) of the seal conductor 61 bites into the semiconductor chip 41 side. Of course, the connection portion 132 may be formed flush with the main surface of the separation structure 130.

[0220] The separation structure 130 includes an inner end portion 130A on the device region 62 side, an outer end portion 130B on the outer region 63 side, and a main body portion 130C between the inner end portion 130A and the outer end portion 130B. The inner end portion 130A demarcates the region (that is, the device region 62) where the second functional device 60 is formed in plan view. The inner end portion 130A may be integrally formed with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0221] The outer end portion 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. Specifically, the outer end portion 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end portion 130B forms a flush grinding surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other forms, the outer end portion 130B may be formed within the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0222] The main body portion 130C has a flat surface that extends substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body portion 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body portion 130C that is spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 may take various forms shown in FIGS. 14A to 14D in addition to the field insulating film 131.

[0223] FIG. 14A is an enlarged view of the region XIII shown in FIG. 8 and is a diagram showing the isolation structure 130 according to the second exemplary embodiment. Referring to FIG. 14A, the isolation structure 130 may have a laminated structure including an insulating film 133 formed on the first main surface 42 and a conductor film 134 formed on the insulating film 133. In this case, either one or both of the insulating film 133 and the conductor film 134 may be exposed from the chip sidewalls 44A to 44D.

[0224] The insulating film 133 may contain silicon oxide or silicon nitride. The insulating film 133 may be the field insulating film 131. The thickness of the insulating film 133 may be 0.1 μm or more and 5 μm or less. The conductor film 134 contains polysilicon or metal and is formed in an electrically floating state. The thickness of the conductor film 134 may be 0.1 μm or more and 5 μm or less. The connection portion 132 with the seal conductor 61 is formed in the conductor film 134.

[0225] FIG. 14B is an enlarged view of region XIII shown in FIG. 8, and is a diagram showing the separation structure 130 according to the third exemplary embodiment. Referring to FIG. 14B, the separation structure 130 includes a trench 135 formed on the first main surface 42 and an embedded body 136 embedded in the trench 135. In this case, the trench 135 and the embedded body 136 are exposed from the chip sidewalls 44A to 44D. The embedded body 136 is embedded in the trench 135 so as to be electrically separated from the semiconductor chip 41. Specifically, the embedded body 136 is embedded in the trench 135 so as to be in an electrically floating state.

[0226] In this exemplary embodiment, the embedded body 136 is made of an insulator 137. That is, the separation structure 130 is a trench insulation structure. The trench insulation structure may be STI (shallow trench isolation). The depth of the trench 135 may be 0.1 μm or more and 5 μm or less. The embedded body 136 may contain silicon oxide or silicon nitride. The embedded body 136 may have a main surface protruding above the first main surface 42. The embedded body 136 may have a main surface located on the bottom wall side of the trench 135 rather than the first main surface 42. The embedded body 136 may have a main surface continuous with the first main surface 42. The connection portion 132 with the seal conductor 61 is formed on the embedded body 136.

[0227] FIG. 14C is an enlarged view of region XIII shown in FIG. 8, and is a diagram showing the separation structure 130 according to the fourth exemplary embodiment. Referring to FIG. 14C, the separation structure 130 includes a trench 135 formed on the first main surface 42 and an embedded body 136 embedded in the trench 135. In this case, the trench 135 and the embedded body 136 are exposed from the chip sidewalls 44A to 44D. The embedded body 136 is embedded in the trench 135 so as to be electrically separated from the semiconductor chip 41. Specifically, the embedded body 136 is embedded in the trench 135 so as to be in an electrically floating state.

[0228] In this exemplary form, the embedded body 136 includes an insulating film 138 formed on the wall surface of the trench 135 and a conductor 139 embedded in the trench 135 with the insulating film 138 interposed therebetween. The conductor 139 is electrically insulated from the semiconductor chip 41 by the insulating film 138 and is embedded in an electrically floating state. That is, the isolation structure 130 is composed of a trench insulation structure. The trench insulation structure may be STI.

[0229] The depth of the trench 135 may be 0.1 μm or more and 5 μm or less. The insulating film 138 may contain silicon oxide or silicon nitride. The thickness of the insulating film 138 may be 0.1 μm or more and 2 μm or less. The conductor 139 contains polysilicon or metal and is embedded in an electrically floating state. The conductor 139 may have a main surface protruding above the first main surface 42. The conductor 139 may have a main surface located closer to the bottom wall side of the trench 135 than the first main surface 42. The conductor 139 may have a main surface continuous with the first main surface 42. The connection portion 132 with the seal conductor 61 is formed on the conductor 139.

[0230] FIG. 14D is an enlarged view of the region XIII shown in FIG. 8 and shows the isolation structure 130 according to the fifth exemplary form. Referring to FIG. 14D, the isolation structure 130 is composed of a part of the insulating layer 51. The isolation structure 130 may include the bottommost insulating layer 55 and one or more interlayer insulating layers 57. In this exemplary form, the isolation structure 130 is composed of the bottommost insulating layer 55. In this exemplary form, the seal conductor 61 does not have a seal via conductor 65 and has a lower end portion composed of a seal plug conductor 64. The connection portion 132 of the isolation structure 130 is composed of the connection portion of the insulating layer 51 (bottommost insulating layer 55) and the lower end portion of the seal conductor 61 (seal plug conductor 64).

[0231] Referring to FIGS. 8 and 9, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating main surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating main surface 52.

[0232] In this form, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains undoped silicon glass (USG) which is impurity-free silicon oxide. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the breakdown voltage of insulation on the high-potential coil 23 can be increased.

[0233] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when thickening the inorganic insulating layer 140, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0234] The first inorganic insulating layer 141 may contain at least one of borondoped phosphorsilicate glass (BPSG) and phosphorous silicate glass (PSG) as an example of silicon oxide. However, in this case, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the breakdown voltage of insulation on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure composed of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0235] The inorganic insulating layer 140 covers the entire area of the seal conductor 61 and has a plurality of low-potential pad openings 143 and a plurality of high-potential pad openings 144 formed in regions outside the seal conductor 61. The plurality of low-potential pad openings 143 expose the plurality of low-potential terminals 11 respectively. The plurality of high-potential pad openings 144 expose the plurality of high-potential terminals 12 respectively. The inorganic insulating layer 140 may have an overlap portion that rides on the peripheral edge of the low-potential terminal 11. The inorganic insulating layer 140 may have an overlap portion that rides on the peripheral edge of the high-potential terminal 12.

[0236] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may contain a photosensitive resin. The organic insulating layer 145 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this form, the organic insulating layer 145 contains polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0237] Preferably, the thickness of the organic insulating layer 145 exceeds the total thickness of the inorganic insulating layer 140. Further, preferably, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, preferably, the total thickness of the inorganic insulating layer 140 is 2 μm or more and 10 μm or less. Also, preferably, the thickness of the organic insulating layer 145 is 5 μm or more and 50 μm or less. According to these structures, thickening of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, and at the same time, the dielectric breakdown voltage on the high-potential coil 23 can be appropriately increased by the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145.

[0238] The organic insulating layer 145 includes a first portion 146 that covers the region on the low potential side and a second portion 147 that covers the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 interposed therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in regions outside the seal conductor 61. The first portion 146 may have an overlapping portion that rides on the peripheral edge (overlapping portion) of the low potential pad opening 143.

[0239] The second portion 147 is formed at a distance from the first portion 146 and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high potential terminal openings 149 that expose a plurality of high potential terminals 12 (high potential pad openings 144) respectively. The second portion 147 may have an overlapping portion that rides on the peripheral edge (overlapping portion) of the high potential pad opening 144.

[0240] The second portion 147 covers the transformers 21A to 21D and the dummy pattern 85 together. Specifically, the second portion 147 covers a plurality of high potential coils 23, a plurality of high potential terminals 12, a first high potential dummy pattern 87, a second high potential dummy pattern 88, and a floating dummy pattern 121 together.

[0241] When the organic insulating layer 145 is not formed, damage may occur to the plurality of high potential coils 23, the plurality of high potential terminals 12, the seal conductor 61, the first high potential dummy pattern 87, the second high potential dummy pattern 88, and the floating dummy pattern 121 due to the filler contained in the package body 2 (mold resin). This type of damage is referred to as filler attack.

[0242] The organic insulating layer 145 protects the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the seal conductor 61, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121 from the filler contained in the package body 2 (mold resin). The slit between the first portion 146 and the second portion 147 functions as an anchor portion for the package body 2 (mold resin).

[0243] A part of the package body 2 (mold resin) enters the slit between the first portion 146 and the second portion 147 and is connected to the inorganic insulating layer 140. Thereby, the adhesion of the package body 2 (mold resin) to the semiconductor device 5 is enhanced. Of course, the first portion 146 and the second portion 147 may be integrally formed. Also, the organic insulating layer 145 may include only one of the first portion 146 and the second portion 147. However, in this case, it is necessary to pay attention to filler attack.

[0244] FIG. 15 is a graph showing the average instantaneous breakdown voltage. In FIG. 15, the vertical axis represents the average instantaneous breakdown voltage [KV·rms], and the horizontal axis represents the items. The higher the average instantaneous breakdown voltage, the higher the breakdown voltage of the insulating layer 51. FIG. 15 shows a first bar graph G1, a second bar graph G2, a third bar graph G3, and a fourth bar graph G4.

[0245] The first bar graph G1 shows the average instantaneous breakdown voltage of the semiconductor device 5 according to the first structure. In the semiconductor device 5 according to the first structure, the dummy pattern 85 is not formed. The second bar graph G2 shows the average instantaneous breakdown voltage of the semiconductor device 5 according to the second structure. In the semiconductor device 5 according to the second structure, a dummy pattern 85 including only the second high-potential dummy pattern 88 is formed.

[0246] The third bar graph G3 shows the average instantaneous breakdown voltage of the semiconductor device 5 according to the third structure. In the semiconductor device 5 according to the third structure, a dummy pattern 85 including only the floating dummy pattern 121 and the second high-potential dummy pattern 88 is formed. The fourth bar graph G4 shows the average instantaneous breakdown voltage of the semiconductor device 5 according to the fourth structure. In the semiconductor device 5 according to the fourth structure, a dummy pattern 85 including the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121 is formed.

[0247] Referring to the first bar graph G1 and the second bar graph G2, by forming the second high-potential dummy pattern 88, the average instantaneous breakdown voltage increased by 11.2%. Referring to the second bar graph G2 and the third bar graph G3, by forming the floating dummy pattern 121 in addition to the second high-potential dummy pattern 88, the average instantaneous breakdown voltage increased by 13.2%.

[0248] Referring to the third bar graph G3 and the fourth bar graph G4, by forming the first high-potential dummy pattern 87 in addition to the second high-potential dummy pattern 88 and the floating dummy pattern 121, the average instantaneous breakdown voltage increased by 6.2%. Referring to the first bar graph G1 and the fourth bar graph G4, by forming the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121, the average instantaneous breakdown voltage increased by 13.37%.

[0249] FIG. 16 is a diagram in which the equipotential lines (electric field distribution) in the vicinity of the high-potential coil 23 are examined by simulation. In FIG. 16, the electric field distribution of the semiconductor device 5 according to the first structure described above is shown. Referring to FIG. 16, in the case of the semiconductor device 5 according to the first structure, the equipotential lines wrap around the upper side of the high-potential coil 23 and concentrate on the periphery of the high-potential coil 23. That is, in the case of the semiconductor device 5 according to the first structure, it can be seen that the electric field is concentrated on the periphery of the high-potential coil 23. The average instantaneous breakdown voltage decreases due to this kind of electric field concentration.

[0250] FIG. 17 is a diagram showing equipotential lines (electric field distribution) in the vicinity of the first high-potential dummy pattern 87 examined by simulation. In FIG. 17, the electric field distribution of the semiconductor device 5 according to the aforementioned fourth structure is shown. Referring to FIG. 17, in the case of the semiconductor device 5 according to the fourth structure, the equipotential lines bypass the high-potential coil 23 and the first high-potential dummy pattern 87 and leak out above the first high-potential dummy pattern 87. That is, in the case of the semiconductor device 5 according to the fourth structure, the electric field does not concentrate on the high-potential coil 23. Thereby, the average instantaneous breakdown voltage can be increased.

[0251] Although specific illustration is omitted, the second high-potential dummy pattern 88 also has the same effect as the first high-potential dummy pattern 87. That is, in the vicinity of the second high-potential dummy pattern 88, the equipotential lines bypass the high-potential coil 23 and the second high-potential dummy pattern 88 and leak out above the second high-potential dummy pattern 88. Thereby, the electric field concentration on the high-potential coil 23 can be suppressed, so that the average instantaneous breakdown voltage can be increased.

[0252] FIG. 18 is a diagram showing the electric field distribution in the vicinity of the floating dummy pattern 121 examined by simulation. In FIG. 18, the electric field distribution of the semiconductor device 5 according to the aforementioned fourth structure is shown. Referring to FIG. 18, in the case of the semiconductor device 5 according to the fourth structure, the equipotential lines leak out from the region between adjacent floating dummy patterns 121 to the upper side of the high-potential coil 23. That is, in the case of the semiconductor device 5 according to the fourth structure, the electric field leaking out to the upper side of the high-potential coil 23 is thinned out by the floating dummy pattern 121. Thereby, the electric field concentration on the high-potential coil 23 can be suppressed, so that the average instantaneous breakdown voltage can be increased.

[0253] Specifically, the equipotential lines leak out from the region between adjacent floating dummy patterns 121 to the upper side of the high-potential dummy pattern 86. That is, in the case of the semiconductor device 5 according to the fourth structure, the electric field leaking out to the upper side of the high-potential dummy pattern 86 is thinned out by the floating dummy pattern 121.

[0254] In the dummy pattern 85 including the high-potential dummy pattern 86 and the floating dummy pattern 121, the high-potential dummy pattern 86 moves the electric field leaking above the high-potential coil 23 away from the high-potential coil 23. On the other hand, the floating dummy pattern 121 disperses the electric field leaking above the high-potential dummy pattern 86 in a direction away from the high-potential coil 23 and the high-potential dummy pattern 86 in a region away from the high-potential coil 23. Thereby, the electric field concentration with respect to the high-potential coil 23 can be appropriately suppressed, so that the average instantaneous breakdown voltage can be appropriately increased.

[0255] Thus, it has been found that by forming the dummy pattern 85 including the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121, the electric field concentration with respect to the high-potential coil 23 can be suppressed and the average instantaneous breakdown voltage can be improved. Also, from the results of FIGS. 16, 17, and 18, it has been found that the dummy pattern 85 may include at least one of the first high-potential dummy pattern 87, the floating dummy pattern 121, and the second high-potential dummy pattern 88.

[0256] As described above, the semiconductor device 5 includes a semiconductor chip 41, an insulating layer 51, a first functional device 45, a low-potential terminal 11, a high-potential terminal 12, and a seal conductor 61. The insulating layer 51 is formed on the first main surface 42 of the semiconductor chip 41. The first functional device 45 is formed in the insulating layer 51. The low-potential terminal 11 is formed on the insulating layer 51 and is electrically connected to the first functional device 45.

[0257] The high-potential terminal 12 is formed on the insulating layer 51 at an interval from the low-potential terminal 11 and is electrically connected to the first functional device 45. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape so as to partition the region including the first functional device 45, the low-potential terminal 11, and the high-potential terminal 12 from other regions in a plan view, and is electrically separated from the semiconductor chip 41, the first functional device 45, the low-potential terminal 11, and the high-potential terminal 12.

[0258] According to this structure, when voltages are applied to the low-potential terminal 11 and the high-potential terminal 12, undesired conduction between the high-potential terminal 12 and the seal conductor 61 can be suppressed. Also, undesired conduction between the low-potential terminal 11 and the seal conductor 61 can be suppressed. Further, undesired conduction between the first functional device 45 and the seal conductor 61 can be suppressed. Therefore, the breakdown voltage can be improved.

[0259] In this structure, the seal conductor 61 is preferably fixed in an electrically floating state. According to this structure, it is possible to surely suppress the seal conductor 61 from forming a current path. Therefore, undesired conduction of the seal conductor 61 can be appropriately suppressed.

[0260] The seal conductor 61 is preferably embedded in the insulating layer 51 at a distance in the normal direction Z from the first main surface 42 of the semiconductor chip 41. According to this structure, the seal conductor 61 can be appropriately electrically separated from the semiconductor chip 41. Therefore, conduction between the semiconductor chip 41 and the seal conductor 61 can be appropriately suppressed.

[0261] The semiconductor device 5 preferably further includes a separation structure 130 interposed between the semiconductor chip 41 and the seal conductor 61 and electrically separated from the semiconductor chip 41 and the seal conductor 61. According to this structure, the separation structure 130 can appropriately electrically separate the seal conductor 61 from the semiconductor chip 41.

[0262] The separation structure 130 may include a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41. The separation structure 130 may include a trench 135 formed on the first main surface 42 and an embedded body 136 embedded in the trench 135. The embedded body 136 is embedded in the trench 135 so as to be electrically separated from the semiconductor chip 41. Specifically, the embedded body 136 is embedded in the trench 135 so as to be in an electrically floating state. The separation structure 130 may be formed using a part of the insulating layer 51.

[0263] The separation structure 130 is preferably exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41. According to this structure, even if the seal conductor 61 is formed offset toward the chip sidewalls 44A to 44D, since the separation structure 130 exposed from the chip sidewalls 44A to 44D is formed at the periphery of the first main surface 42, the seal conductor 61 can be appropriately connected to the separation structure 130.

[0264] The insulating sidewalls 53A to 53D of the insulating layer 51 are preferably continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. The insulating layer 51 is preferably further continuous with the outer end portion 130B of the separation structure 130. According to this structure, the seal conductor 61 can be appropriately insulated by the insulating layer 51 and the separation structure 130.

[0265] The seal conductor 61 is preferably formed in an annular shape surrounding the first functional device 45, the low potential terminal 11, and the high potential terminal 12 in a plan view. According to this structure, the first functional device 45, the low potential terminal 11, and the high potential terminal 12 can be appropriately protected by the seal conductor 61.

[0266] The semiconductor device 5 includes an inorganic insulating layer 140 that covers the seal conductor 61 on the insulating layer 51. The inorganic insulating layer 140 has a low potential pad opening 143 and a high potential pad opening 144 formed in a region outside the seal conductor 61. The low potential pad opening 143 exposes the low potential terminal 11, and the high potential pad opening 144 exposes the high potential terminal 12. According to this structure, the seal conductor 61 can be protected by the inorganic insulating layer 140, and at the same time, the insulation of the seal conductor 61 from the outside can be enhanced.

[0267] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140 so as to cover the seal conductor 61 with the inorganic insulating layer 140 interposed therebetween. According to this structure, the seal conductor 61 can be protected by the organic insulating layer 145, and at the same time, the insulation of the seal conductor 61 from the outside can be further enhanced.

[0268] The first functional device 45 may include a transformer 21 (passive device) formed in the insulating layer 51. The transformer 21 includes a low-potential coil 22 (low-potential pattern) formed in the insulating layer 51 and a high-potential coil 23 (high-potential pattern) formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. The high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 interposed therebetween. The low-potential coil 22 is electrically connected to the low-potential terminal 11, and the high-potential coil 23 is electrically connected to the high-potential terminal 12.

[0269] According to this structure, when a voltage is applied to the transformer 21 via the low-potential terminal 11 and the high-potential terminal 12, undesired conduction between the high-potential terminal 12 and the seal conductor 61 can be suppressed. Also, when a voltage is applied to the transformer 21 via the low-potential terminal 11 and the high-potential terminal 12, undesired conduction between the low-potential terminal 11 and the seal conductor 61 can be suppressed. Also, when a voltage is applied to the transformer 21 via the low-potential terminal 11 and the high-potential terminal 12, undesired conduction between the transformer 21 and the seal conductor 61 can be suppressed.

[0270] The semiconductor device 5 further includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 covers the second functional device 60. The low-potential terminal 11 and the high-potential terminal 12 are electrically connected to the second functional device 60. The seal conductor 61 partitions the region including the second functional device 60 from other regions in a plan view and is electrically separated from the second functional device 60.

[0271] According to this structure, when a voltage is applied to the low-potential terminal 11 and the high-potential terminal 12, undesired conduction between the second functional device 60 and the seal conductor 61 can be suppressed. Therefore, according to the semiconductor device 5, the same effect as that achieved between the first functional device 45 and the seal conductor 61 can also be achieved between the second functional device 60 and the seal conductor 61.

[0272] Further, the semiconductor device 5 includes a dummy pattern 85 formed in the insulating layer 51 so as to be located around the high-potential coil 23 in a plan view. The dummy pattern 85 shields the electric field formed between the low-potential coil 22 and the high-potential coil 23, and suppresses the electric field concentration on the high-potential coil 23. Thereby, the electric field concentration on the high-potential coil 23 can be suppressed, and the breakdown voltage (average instantaneous breakdown voltage) can be improved. Further, according to the semiconductor device 5, when voltages are applied to the low-potential terminal 11 and the high-potential terminal 12, an undesired conduction between the dummy pattern 85 and the seal conductor 61 can be suppressed. Therefore, the effect of improving the breakdown voltage by the dummy pattern 85 and the seal conductor 61 can be appropriately realized.

[0273] In this embodiment, the dummy pattern 85 is interposed in the region between a plurality of adjacent high-potential coils 23 in a plan view. Thereby, the electric field concentration on the plurality of high-potential coils 23 can be suppressed by using the region between the plurality of adjacent high-potential coils 23.

[0274] In this embodiment, the dummy pattern 85 is interposed in the region between the low-potential terminal 11 and the high-potential coil 23 in a plan view. Thereby, an undesired conduction between the low-potential terminal 11 and the high-potential coil 23 due to the electric field concentration of the high-potential coil 23 can be suppressed.

[0275] In this embodiment, the dummy pattern 85 is interposed in the region between the low-potential terminal 11 and the high-potential terminal 12 in a plan view. Thereby, an undesired conduction between the low-potential terminal 11 and the high-potential terminal 12 due to the electric field concentration of the high-potential coil 23 can be suppressed.

[0276] In this embodiment, the dummy pattern 85 is interposed in the region between the seal conductor 61 and the high-potential coil 23 in a plan view. Thereby, an undesired conduction between the seal conductor 61 and the high-potential coil 23 due to the electric field concentration of the high-potential coil 23 can be suppressed.

[0277] In this form, the dummy pattern 85 is interposed in the region between the seal conductor 61 and the high-potential terminal 12 in a plan view. Thereby, an undesired conduction between the seal conductor 61 and the high-potential terminal 12 due to the electric field concentration of the high-potential coil 23 can be suppressed.

[0278] In this form, the dummy pattern 85 includes a high-potential dummy pattern 86 formed around the high-potential coil 23 in a plan view. The high-potential dummy pattern 86 suppresses the electric field leaking to the upper side of the high-potential coil 23 in the region around the high-potential coil 23. Thereby, the electric field concentration on the high-potential coil 23 can be appropriately suppressed in the region around the high-potential coil 23.

[0279] The dummy pattern 85 includes a first high-potential dummy pattern 87 interposed in the region between a plurality of adjacent high-potential coils 23 in a plan view. The first high-potential dummy pattern 87 suppresses the electric field leaking to the upper side of the plurality of high-potential coils 23 in the region between the plurality of adjacent high-potential coils 23. Thereby, the electric field concentration on the plurality of high-potential coils 23 can be appropriately suppressed in the region between the plurality of adjacent high-potential coils 23.

[0280] Further, the dummy pattern 85 includes a second high-potential dummy pattern 88 located in a region outside the region between a plurality of adjacent high-potential coils 23 in a plan view. The second high-potential dummy pattern 88 suppresses the electric field leaking to the upper side of the plurality of high-potential coils 23 in the region outside the region between the plurality of adjacent high-potential coils 23. Thereby, the electric field concentration on the plurality of high-potential coils 23 can be appropriately suppressed in the region outside the region between the plurality of adjacent high-potential coils 23.

[0281] Further, the dummy pattern 85 includes a floating dummy pattern 121 formed in an electrically floating state around the high-potential coil 23 in a plan view. The floating dummy pattern 121 shields the electric field between the low-potential coil 22 and the high-potential coil 23 so as to disperse the electric field leaking to the upper side of the high-potential coil 23. Thereby, the electric field concentration on the high-potential coil 23 can be suppressed.

[0282] Also, the floating dummy pattern 121 disperses the electric field leaking above the high-potential dummy pattern 86 around the high-potential dummy pattern 86. Thereby, the electric field concentration on the high-potential dummy pattern 86 can be suppressed, and at the same time, the electric field concentration on the high-potential coil 23 can be appropriately suppressed. In this structure, it is preferable that the sealing conductor 61 in an electrically floating state is formed. In this case, the sealing conductor 61 does not cause a voltage drop with the floating dummy pattern 121. Therefore, the undesired conduction between the dummy pattern 85 and the sealing conductor 61 can be appropriately suppressed.

[0283] As understood from FIG. 16, the dummy pattern 85 preferably includes all of the first high-potential dummy pattern 87, the floating dummy pattern 121, and the second high-potential dummy pattern 88. However, the dummy pattern 85 including any one or two of the first high-potential dummy pattern 87, the floating dummy pattern 121, and the second high-potential dummy pattern 88 can also improve the average instantaneous breakdown voltage.

[0284] That is, the dummy pattern 85 having only the first high-potential dummy pattern 87 may be adopted. Also, the dummy pattern 85 having only the second high-potential dummy pattern 88 may be adopted. Also, the dummy pattern 85 having only the floating dummy pattern 121 may be adopted.

[0285] Also, the dummy pattern 85 having only the first high-potential dummy pattern 87 and the second high-potential dummy pattern 88 may be adopted. Also, the dummy pattern 85 having only the first high-potential dummy pattern 87 and the floating dummy pattern 121 may be adopted. Also, the dummy pattern 85 having only the second high-potential dummy pattern 88 and the floating dummy pattern 121 may be adopted.

[0286] Further, the first high-potential dummy pattern 87 may be changed to the floating dummy pattern 121. Also, the first high-potential dummy pattern 87 and the second high-potential dummy pattern 88 may be changed to the floating dummy pattern 121.

[0287] Such a floating dummy pattern 121 is formed by disconnecting the first high-potential dummy pattern 87 and the second high-potential dummy pattern 88 from the high-potential connection wiring 81 (high-potential terminals 12A to 12F). According to the floating dummy pattern 121, since it is electrically formed in a floating state, no voltage drop is formed with the high-potential coil 23. Therefore, according to the floating dummy pattern 121, it is possible to suppress the electric field concentration on the high-potential coil 23 while suppressing the increase in the electric field strength between the high-potential coil 23. However, in the case of the floating dummy pattern 121, it should be noted that there is an electric field leaking above the high-potential coil 23.

[0288] Also, the floating dummy pattern 121 may be changed to the second high-potential dummy pattern 88. However, in this case, as a result of the distance between the low-potential terminal 11 (sealing conductor 61) and the second high-potential dummy pattern 88 becoming close, the electric field strength between the low-potential terminal 11 (sealing conductor 61) and the second high-potential dummy pattern 88 becomes high. It should be noted that when the electric field strength becomes high, there is a possibility that undesired electric field concentration may occur in the high-potential coil 23 and the second high-potential dummy pattern 88.

[0289] FIG. 19 is a plan view corresponding to FIG. 7, and is a plan view showing the semiconductor device 161 according to the second embodiment of the present invention. FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. 19. Hereinafter For the structure corresponding to the structure described for the semiconductor device 5, the same reference numerals are given and the description is omitted. FIG. 20 shows an example in which the isolation structure 130 (field insulating film 131) according to the first exemplary form is formed (see also FIG. 13). However, in the semiconductor device 161 according to the second embodiment, any one of the isolation structures 130 according to the second to fifth exemplary forms may be formed instead of the isolation structure 130 according to the first exemplary form (see also FIGS. 14A to 14D).

[0290] Referring to FIGS. 19 and 20, the dummy pattern 85 related to the semiconductor device 161 further includes a low-potential dummy pattern 162. In FIG. 19, the low-potential dummy pattern 162 is indicated by a thick line. The low-potential dummy pattern 162 is preferably formed of the same conductive material as the low-potential coil 22 or the like. That is, the low-potential dummy pattern 162 preferably includes a barrier layer and a main body layer, similar to the low-potential coil 22 or the like.

[0291] The low-potential dummy pattern 162 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22 and is independent of the transformers 21A to 21D. That is, the low-potential dummy pattern 162 does not function as the transformers 21A to 21D. A voltage lower than the voltage applied to the high-potential terminal 12 is applied to the low-potential dummy pattern 162. Preferably, the voltage applied to the low-potential terminal 11 (that is, the reference voltage) is applied to the low-potential dummy pattern 162. That is, the low-potential dummy pattern 162 is preferably fixed at the same potential as the low-potential terminal 11. The low-potential dummy pattern 162 includes a connection portion 163 connected to an arbitrary second electrode layer 79.

[0292] The low-potential dummy pattern 162 is formed around the low-potential terminal 11 in a plan view. Specifically, the low-potential dummy pattern 162 is formed in a region closer to the low-potential terminal 11 than the high-potential coil 23 (high-potential terminal 12) in a plan view. That the low-potential dummy pattern 162 is close to the low-potential terminal 11 in a plan view means that the distance between the low-potential dummy pattern 162 and the low-potential terminal 11 is less than the distance between the low-potential dummy pattern 162 and the high-potential coil 23 (high-potential terminal 12) in a plan view.

[0293] The depth position of the low-potential dummy pattern 162 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be relaxed. The low-potential dummy pattern 162 is preferably formed in a region within the insulating layer 51 that is close to the low-potential terminal 11 with respect to the low-potential coil 22 in the normal direction Z. That the low-potential dummy pattern 162 is close to the low-potential terminal 11 with respect to the normal direction Z means that the distance between the low-potential dummy pattern 162 and the low-potential terminal 11 is less than the distance between the low-potential dummy pattern 162 and the low-potential coil 22 with respect to the normal direction Z. The low-potential dummy pattern 162 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23.

[0294] The low-potential dummy pattern 162 preferably intervenes in the region between the low-potential terminal 11 and the high-potential coil 23 in plan view. The low-potential dummy pattern 162 preferably intervenes in the region between the low-potential terminal 11 and the high-potential terminal 12 in plan view.

[0295] In this form, the low-potential dummy pattern 162 is routed with a line density equal to that of the high-potential coil 23 per unit area. That the line density of the low-potential dummy pattern 162 is equal to that of the high-potential coil 23 means that the line density of the low-potential dummy pattern 162 falls within the range of ±20% of the line density of the high-potential coil 23.

[0296] The low-potential dummy pattern 162 is preferably formed in an open-ended shape. According to this structure, it is possible to appropriately suppress the formation of a current loop circuit in the low-potential dummy pattern 162. Thereby, noise caused by the current flowing through the low-potential dummy pattern 162 can be suppressed, so that undesired electric field concentration caused by the noise can be suppressed, and at the same time, fluctuations in the electrical characteristics of the transformers 21A to 21D can be appropriately suppressed.

[0297] In this embodiment, the low-potential dummy pattern 162 is formed in a strip shape extending in the first direction X. The low-potential dummy pattern 162 crosses a plurality of low-potential terminals 11A to 11F in a plan view. Thereby, the low-potential dummy pattern 162 is interposed in the region between the low-potential terminals 11A to 11F and the high-potential coil 23 in a plan view. Also, the low-potential dummy pattern 162 is interposed in the region between the low-potential terminals 11A to 11F and the high-potential terminals 12A to 12F in a plan view.

[0298] In this embodiment, the low-potential dummy pattern 162 includes a plurality (three in this embodiment) of low-potential lines 164A, 164B, and 164C. The plurality of low-potential lines 164A to 164C are formed at intervals in this order from the low-potential terminal 11A to 11F side toward the high-potential terminal 12A to 12F side. The plurality of low-potential lines 164A to 164C are electrically connected to an arbitrary low-potential connection wiring 72.

[0299] The plurality of low-potential lines 164A to 164C are each formed in a strip shape extending in the first direction X in a plan view. That is, the plurality of low-potential lines 164A to 164C are formed in a stripe shape extending in the first direction X as a whole in a plan view.

[0300] The width of the low-potential lines 164A to 164C may be 0.1 μm or more and 5 μm or less. The width of the low-potential lines 164A to 164C is preferably 1 μm or more and 3 μm or less. The width of the low-potential lines 164A to 164C is defined by the width in the direction orthogonal to the direction in which the low-potential lines 164A to 164C extend. The width of the low-potential lines 164A to 164C is preferably equal to the width of the high-potential coil 23. That the width of the low-potential lines 164A to 164C is equal to the width of the high-potential coil 23 means that the width of the low-potential lines 164A to 164C falls within the range of ±20% of the width of the high-potential coil 23.

[0301] The 13th pitch between two adjacent low-potential lines 164A to 164C may be 0.1 μm or more and 5 μm or less. The 13th pitch is preferably 1 μm or more and 3 μm or less. The 13th pitches are preferably equal to each other. That the 13th pitches are equal to each other means that the 13th pitch falls within the range of ±20% of the 13th pitch. According to these structures, since the bias of the electric field can be suppressed in the insulating layer 51, undesired electric field concentration can be suppressed. The number, width, and pitch of the low-potential lines 164A to 164C are adjusted according to the electric field to be relaxed and are not limited to specific values.

[0302] The semiconductor device 161 further includes a main surface insulating layer 165 that covers the main insulating surface 52 of the insulating layer 51. The main surface insulating layer 165 covers the low-potential terminals 11A to 11F, the high-potential terminals 12A to 12F, the organic insulating layer 145, the inorganic insulating layer 140 (the second inorganic insulating layer 142), etc. together on the main insulating surface 52.

[0303] The main surface insulating layer 165 has a second dielectric breakdown strength BS2 (BS2 ≤ BS1) that is equal to or less than the first dielectric breakdown strength BS1 of the insulating layer 51. Specifically, the second dielectric breakdown strength BS2 is less than the first dielectric breakdown strength BS1 (BS2 < BS1).

[0304] Specifically, the insulating layer 51 contains silicon oxide and / or silicon nitride and has a first dielectric breakdown strength BS1 of 1 MV / cm or more and 15 MV / cm or less. The first dielectric breakdown strength BS1 is preferably 5 MV / cm or more and 15 MV / cm or less. As long as the insulating layer 51 has a first dielectric breakdown strength BS1 of 1 MV / cm or more, it may contain an insulating material other than silicon oxide and silicon nitride. On the other hand, the second dielectric breakdown strength BS2 may be 0.1 MV / cm or more and 1 MV / cm or less. The second dielectric breakdown strength BS2 may be 0.1 MV / cm or more and 0.5 MV / cm or less.

[0305] In this form, the main surface insulating layer 165 is made of a resin layer. The main surface insulating layer 165 may include at least one of an epoxy resin layer, a polyimide resin layer, and a polybenzoxazole resin layer. The main surface insulating layer 165 may be formed by a part of the molding resin. When the main surface insulating layer 165 is formed by a part of the molding resin, the main surface insulating layer 165 may be formed by a part of the package body 2. That is, the main surface insulating layer 165 may include a portion that covers the insulating main surface 52 of the insulating layer 51 in the package body 2 in a state of being sealed by the package body 2.

[0306] The electric field strength between the low-potential terminals 11A to 11F and the high-potential dummy pattern 86 is governed by the distance between the low-potential dummy pattern 162 and the high-potential dummy pattern 86. Therefore, the electric field strength between the low-potential terminals 11A to 11F and the high-potential dummy pattern 86 in the insulating layer 51 is increased by the low-potential dummy pattern 162.

[0307] On the other hand, due to the increase in the electric field strength in the insulating layer 51, the electric field strength in the main surface insulating layer 165 decreases. That is, the low-potential dummy pattern 162 deliberately increases the electric field strength of the insulating layer 51 having a relatively high first dielectric breakdown strength BS1, and at the same time decreases the electric field strength of the main surface insulating layer 165 having a relatively low second dielectric breakdown strength BS2. Thereby, the dielectric withstand voltage of the main surface insulating layer 165 can be relatively improved.

[0308] As described above, according to the semiconductor device 161, the same effects as those described for the semiconductor device 5 can be achieved. Further, according to the semiconductor device 161, it includes a low-potential dummy pattern 162. Thereby, the breakdown voltage of the main surface insulating layer 165 can be improved. Also, according to the semiconductor device 161, the seal conductor 61 demarcates the region including the low-potential dummy pattern 162 from other regions in plan view and is electrically separated from the low-potential dummy pattern 162. According to this structure, when voltages are applied to the low-potential terminal 11 and the high-potential terminal 12, undesired conduction between the low-potential dummy pattern 162 and the seal conductor 61 can be suppressed. Therefore, the breakdown voltage can be increased.

[0309] FIG. 21 is a cross-sectional view of a region corresponding to FIG. 8 and shows a semiconductor device 191 according to the third embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 5, the same reference numerals are given and the description is omitted. In FIG. 21, an example in which the isolation structure 130 (field insulating film 131) according to the first exemplary form is formed is shown (see also FIG. 13). However, in the semiconductor device 191 according to the third embodiment, any one of the isolation structures 130 according to the second to fifth exemplary forms may be formed instead of the isolation structure 130 according to the first exemplary form (see also FIGS. 14A to 14D).

[0310] The semiconductor device 5 according to the first embodiment has a plurality of transformers 21A to 21D each having a low-potential coil 22 and a high-potential coil 23. In contrast, the semiconductor device 191 according to the third embodiment includes a plurality of capacitors 192 instead of the plurality of transformers 21A to 21D. The arrangement of the plurality of capacitors 192 is the same as the arrangement of the plurality of transformers 21A to 21D. In FIG. 21, only one capacitor 192 is shown.

[0311] The capacitor 192 includes a flat low-potential electrode 193 (low-potential pattern) and a flat high-potential electrode 194 (high-potential pattern) instead of the low-potential coil 22 and the high-potential coil 23, respectively. The low-potential electrode 193 is electrically connected to the low-potential terminal 11 via the first low-potential wiring 31. The low-potential electrode 193 is electrically connected to the lead-out wiring 73 via the second connection plug electrode 75.

[0312] The planar shape of the low-potential electrode 193 is arbitrary. The low-potential electrode 193 may be formed in a polygonal shape such as a triangular shape or a rectangular shape, a circular shape, or an elliptical shape in a plan view. The low-potential electrode 193 is electrically connected to the corresponding low-potential terminal 11 via the corresponding first low-potential wiring 31.

[0313] The high-potential electrode 194 faces the low-potential electrode 193 in the normal direction Z and accumulates charges with the low-potential electrode 193. The high-potential electrode 194 is electrically connected to the high-potential terminal 12 via the first high-potential wiring 33. The high-potential electrode 194 is electrically connected to the high-potential terminal 12 via the pad plug electrode 82.

[0314] The planar shape of the high-potential electrode 194 is arbitrary. The high-potential electrode 194 may be formed in a polygonal shape such as a triangular shape or a rectangular shape, a circular shape, or an elliptical shape in a plan view. The high-potential electrode 194 is electrically connected to the corresponding high-potential terminal 12 via the corresponding first high-potential wiring 33.

[0315] As described above, according to the semiconductor device 191, the same effects as those described for the semiconductor device 5 can be achieved. The semiconductor device 191 may include the low-potential dummy pattern 162 according to the second embodiment.

[0316] The embodiments of the present invention can be implemented in still other forms.

[0317] In each of the foregoing embodiments, the semiconductor devices 5, 161, and 191 may include a separation structure 130 having a structure in which at least two of the separation structures 130 according to the first to fifth exemplary forms are combined in an arbitrary manner.

[0318] In each of the foregoing embodiments, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form having only the second functional device 60 without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0319] That is, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, undesired conduction between the high-potential terminal 12 and the seal conductor 61 can be suppressed. Also, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, undesired conduction between the low-potential terminal 11 and the seal conductor 61 can be suppressed.

[0320] Also, in each of the foregoing embodiments, an example in which the second functional device 60 is formed has been described. However, the second functional device 60 is not necessarily required and may be removed.

[0321] Also, in each of the foregoing embodiments, an example in which the dummy pattern 85 is formed has been described. However, the dummy pattern 85 is not necessarily required and may be removed.

[0322] Also, in each of the foregoing embodiments, an example in which the first functional device 45 has a multi-channel type including a plurality of transformers 21 has been described. However, a first functional device 45 having a single-channel type including a single transformer 21 may be adopted.

[0323] Examples of features extracted from this specification and the drawings are shown below. The following [A1] to [A19] and the following [B1] to [B17] provide a semiconductor device having a pressure-resistant structure with a sealing conductor.

[0324] [A1] A semiconductor device including: a semiconductor chip having a main surface; an insulating layer formed on the main surface; a functional device formed on at least one of the semiconductor chip and the insulating layer; a low-potential terminal formed on the insulating layer and electrically connected to the functional device; a high-potential terminal formed on the insulating layer at a distance from the low-potential terminal and electrically connected to the functional device; a sealing conductor embedded in a wall shape in the insulating layer so as to partition a region including the functional device, the low-potential terminal, and the high-potential terminal from other regions in a plan view, and electrically isolated from the semiconductor chip, the functional device, the low-potential terminal, and the high-potential terminal.

[0325] According to this semiconductor device, when a voltage is applied to the low-potential terminal and the high-potential terminal, undesired conduction between the high-potential terminal and the sealing conductor can be suppressed. Also, undesired conduction between the low-potential terminal and the sealing conductor can be suppressed. Further, undesired conduction between the functional device and the sealing conductor can be suppressed. Therefore, the withstand voltage can be improved.

[0326] [A2] The semiconductor device according to A1, wherein the sealing conductor is electrically fixed in a floating state.

[0327] [A3] The semiconductor device according to A1 or A2, wherein the sealing conductor is embedded in the insulating layer at a distance from the semiconductor chip in the normal direction of the main surface.

[0328] [A4] The semiconductor device according to any one of A1 to A3, further including a separation structure interposed between the semiconductor chip and the sealing conductor to electrically isolate the sealing conductor from the semiconductor chip.

[0329] [A5] The semiconductor device according to A4, wherein the isolation structure includes an insulating film formed on the main surface of the semiconductor chip.

[0330] [A6] The semiconductor device according to A4, wherein the isolation structure includes a trench formed on the main surface and an embedded body embedded in the trench so as to be electrically separated from the semiconductor chip.

[0331] [A7] The semiconductor device according to A4, wherein the isolation structure is composed of a part of the insulating layer.

[0332] [A8] The semiconductor device according to any one of A4 to A7, wherein the isolation structure is exposed from the side wall of the semiconductor chip.

[0333] [A9] The semiconductor device according to any one of A1 to A8, wherein the insulating layer has an insulating side wall continuous with the side wall of the semiconductor chip.

[0334] [A10] The semiconductor device according to any one of A1 to A9, wherein the seal conductor is formed in an annular shape surrounding the functional device, the low potential terminal, and the high potential terminal in a plan view.

[0335] [A11] The semiconductor device according to any one of A1 to A10, further including an inorganic insulating layer covering the seal conductor on the insulating layer and having a plurality of pad openings exposing the low potential terminal and the high potential terminal respectively.

[0336] [A12] The semiconductor device according to A11, further including an organic insulating layer formed on the inorganic insulating layer so as to cover the seal conductor with the inorganic insulating layer interposed therebetween.

[0337] [A13] The functional device includes a low-potential pattern formed in the insulating layer and a high-potential pattern formed in the insulating layer so as to face the low-potential pattern in the normal direction of the main surface. The low-potential terminal is connected to the low-potential pattern, and the high-potential terminal is electrically connected to the high-potential pattern. The semiconductor device according to any one of A1 to A12.

[0338] [A14] The high-potential pattern faces the semiconductor chip with the low-potential pattern interposed therebetween. The semiconductor device according to A13.

[0339] [A15] The functional device is a transformer including a low-potential coil as the low-potential pattern and a high-potential coil as the high-potential pattern. The semiconductor device according to A13 or A14.

[0340] [A16] The functional device is a capacitor including a low-potential electrode as the low-potential pattern and a high-potential electrode as the high-potential pattern. The semiconductor device according to A13 or A14.

[0341] [A17] The functional device includes at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device, and is formed on the main surface of the semiconductor chip. The semiconductor device according to any one of A1 to A12.

[0342] [A18] The functional device includes a first functional device formed in the insulating layer and a second functional device formed in the semiconductor chip. The semiconductor device according to any one of A1 to A12.

[0343] A semiconductor device including: a semiconductor chip having a main surface; an insulating layer formed on the main surface; a low potential pattern formed in the insulating layer; a high potential pattern formed in the insulating layer so as to face the low potential pattern in a direction normal to the main surface; a dummy pattern formed in the insulating layer around the high potential pattern, including a conductor and shielding an electric field between the low potential pattern and the high potential pattern; a low potential terminal formed on the insulating layer and electrically connected to the low potential pattern; a high potential terminal formed on the insulating layer at a distance from the low potential terminal and electrically connected to the high potential pattern; and a seal conductor embedded in the insulating layer in a wall shape so as to partition a region including the low potential pattern, the high potential pattern, the dummy pattern, the low potential terminal, and the high potential terminal from other regions, and electrically separated from the semiconductor chip, the low potential pattern, the high potential pattern, the dummy pattern, the low potential terminal, and the high potential terminal.

[0344] According to this semiconductor device, when voltages are applied to the low potential terminal and the high potential terminal, electric field concentration on the high potential pattern can be suppressed by the dummy pattern. Further, according to this semiconductor device, when voltages are applied to the low potential terminal and the high potential terminal, undesired conduction between the high potential pattern (high potential terminal) and the seal conductor can be suppressed. Also, undesired conduction between the low potential pattern (low potential terminal) and the seal conductor can be suppressed. Further, undesired conduction between the dummy pattern and the seal conductor can be suppressed. Therefore, the breakdown voltage can be improved.

[0345] [B1] A semiconductor chip having a main surface; an insulating layer formed on the main surface; a functional device formed on at least one of the semiconductor chip and the insulating layer; a low potential terminal formed on the insulating layer and electrically connected to the functional device; a high potential terminal formed on the insulating layer at a distance from the low potential terminal and electrically connected to the functional device; A seal conductor embedded in the insulating layer in a wall shape so as to partition a region including the functional device, the low potential terminal, and the high potential terminal from other regions in a plan view; A separation structure interposed along the seal conductor between the semiconductor chip and the seal conductor, electrically isolating the seal conductor from the semiconductor chip, and including an insulating film formed on the main surface of the semiconductor chip; A semiconductor device including the above.

[0346] [B2] The semiconductor device according to B1, wherein the seal conductor is electrically floating and fixed.

[0347] [B3] The semiconductor device according to B1 or B2, wherein the seal conductor is embedded in the insulating layer at a distance from the semiconductor chip in the normal direction of the main surface.

[0348] [B4] The semiconductor device according to B1, wherein the separation structure is a part of the insulating layer.

[0349] [B5] The semiconductor device according to any one of B1 to B4, wherein the separation structure is exposed from a side wall of the semiconductor chip.

[0350] [B6] The semiconductor device according to any one of B1 to B5, wherein the insulating layer has an insulating side wall continuous with a side wall of the semiconductor chip.

[0351] [B7] The semiconductor device according to any one of B1 to B6, wherein the seal conductor is formed in an annular shape surrounding the functional device, the low potential terminal, and the high potential terminal in a plan view.

[0352] [B8] A semiconductor device according to any one of B1 to B7, further comprising an inorganic insulating layer having a plurality of pad openings that cover the seal conductor and expose the low potential terminal and the high potential terminal, respectively, on the insulating layer.

[0353] [B9] A semiconductor device according to B8, further comprising an organic insulating layer formed on the inorganic insulating layer so as to cover the seal conductor with the inorganic insulating layer interposed therebetween.

[0354] [B10] The functional device includes a low potential pattern formed in the insulating layer and a high potential pattern formed in the insulating layer so as to face the low potential pattern in the normal direction of the main surface. The low potential terminal is connected to the low potential pattern. A semiconductor device according to any one of B1 to B9, wherein the high potential terminal is electrically connected to the high potential pattern.

[0355] [B11] A semiconductor device according to B10, wherein the high potential pattern faces the semiconductor chip with the low potential pattern interposed therebetween.

[0356] [B12] A semiconductor device according to B10 or B11, wherein the functional device is a transformer including a low potential coil as the low potential pattern and a high potential coil as the high potential pattern.

[0357] [B13] A semiconductor device according to B10 or B11, wherein the functional device is a capacitor including a low potential electrode as the low potential pattern and a high potential electrode as the high potential pattern.

[0358] [B14] The functional device includes at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device, and is formed on the main surface of the semiconductor chip. The semiconductor device according to any one of B1 to B9.

[0359] [B15] The functional device includes a first functional device formed in the insulating layer and a second functional device formed in the semiconductor chip. The semiconductor device according to any one of B1 to B9.

[0360] [B16] A semiconductor chip having a main surface, An insulating layer formed on the main surface, A low potential pattern formed in the insulating layer, A high potential pattern formed in the insulating layer so as to face the low potential pattern in the normal direction of the main surface, A dummy pattern formed in the insulating layer around the high potential pattern, including a conductor, and shielding an electric field between the low potential pattern and the high potential pattern, A low potential terminal formed on the insulating layer and electrically connected to the low potential pattern, A high potential terminal formed on the insulating layer at a distance from the low potential terminal and electrically connected to the high potential pattern, A seal conductor embedded in the insulating layer in a wall shape so as to partition a region including the low potential pattern, the high potential pattern, the dummy pattern, the low potential terminal, and the high potential terminal in a plan view from other regions, A separation structure interposed between the semiconductor chip and the seal conductor along the seal conductor, electrically isolating the seal conductor from the semiconductor chip, and including an insulating film formed on the main surface of the semiconductor chip, A semiconductor device including.

[0361] [B17] A semiconductor chip having a main surface, An insulating layer formed on the main surface, At least one of the semiconductor chip and the insulating layer, and a functional device formed thereon A low-potential terminal formed on the insulating layer and electrically connected to the functional device A high-potential terminal formed on the insulating layer with a space from the low-potential terminal and electrically connected to the functional device A seal conductor embedded in a wall shape in the insulating layer so as to partition a region including the functional device, the low-potential terminal, and the high-potential terminal from other regions in a plan view A separation structure interposed between the semiconductor chip and the seal conductor, electrically disconnecting the seal conductor from the semiconductor chip, including a trench formed on the main surface, and an embedded body embedded in the trench so as to be electrically disconnected from the semiconductor chip A semiconductor device including the above

[0362] This application corresponds to Japanese Patent Application No. 2019-217565 filed with the Japan Patent Office on November 29, 2019, and the entire disclosure of this application is incorporated herein by reference. Although the embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these specific examples. The scope of the present invention is limited by the appended claims.

Explanation of Reference Numerals

[0363] 5 Semiconductor device 11 Low-potential terminal 12 High-potential terminal 21 Transformer 22 Low-potential coil 23 High-potential coil 41 Semiconductor chip 42 First main surface 44A First chip side wall 44B Second chip side wall 44C Third chip side wall 44D Fourth chip side wall 45 First functional device 51 Insulating layer 53A First Insulating Sidewall 53B Second Insulating Sidewall 53C Third Insulating Sidewall 53D Fourth Insulating Sidewall 60 Second Functional Device 61 Seal Conductor 85 Dummy Pattern 130 Isolation Structure 131 Field Insulating Film 135 Trench 136 Embedded Body 140 Inorganic Insulating Layer 145 Organic Insulating Layer 161 Semiconductor Device 191 Semiconductor Device 192 Capacitor 193 Low-Potential Electrode 194 High-Potential Electrode

Claims

1. A semiconductor chip having a main surface, an insulating layer formed on the main surface, a functional device formed on at least one of the semiconductor chip and the insulating layer, at least one terminal formed on the insulating layer and electrically connected to the functional device, a sealing conductor that partitions, in a plan view, a region including the functional device and at least one of the terminals from other regions, and includes a first portion, and a plurality of second portions that are located between the semiconductor chip and the first portion, are arranged adjacent to each other in a plan view, and each have a width smaller than that of the first portion in the plan view, A semiconductor device comprising the above.

2. The semiconductor device according to claim 1, wherein the second portion of the sealing conductor is composed of a plurality of via-shaped conductors.

3. The semiconductor device according to claim 2, wherein the first portion and the second portion of the sealing conductor are respectively arranged in a direction normal to the main surface from the semiconductor chip.

4. The semiconductor device according to any one of claims 1 to 3, wherein the second portion in the sealing conductor is in contact with the first portion.

5. The semiconductor device according to any one of claims 1 to 4, further comprising a conductor film that is located between the semiconductor chip and the second portion of the sealing conductor and is in contact with the second portion.

6. The semiconductor device according to any one of claims 1 to 5, wherein the sealing conductor is embedded in the insulating layer in a wall shape.

7. The semiconductor device according to any one of claims 1 to 6, wherein at least one of the terminals includes a low-potential terminal formed on the insulating layer and electrically connected to the functional device, and a high-potential terminal formed on the insulating layer at an interval from the low-potential terminal and electrically connected to the functional device.

8. The functional device includes a low-potential pattern formed in the insulating layer, and a high-potential pattern formed in the insulating layer so as to face the low-potential pattern in a direction normal to the main surface, the low-potential terminal is connected to the low-potential pattern, The semiconductor device according to claim 7, wherein the high-potential terminal is electrically connected to the high-potential pattern.

9. The semiconductor device according to claim 8, wherein the high-potential pattern faces the semiconductor chip with the low-potential pattern interposed therebetween.

10. The semiconductor device according to any one of claims 1 to 9, wherein the seal conductor is electrically isolated from the semiconductor chip, the functional device, and at least one of the terminals.

11. The semiconductor device according to any one of claims 1 to 10, wherein the seal conductor is formed in an annular shape surrounding the functional device and at least one of the terminals in a plan view.

12. The semiconductor device according to any one of claims 1 to 11, further comprising an inorganic insulating layer covering the seal conductor on the insulating layer and having a pad opening exposing at least one of the terminals.

13. The semiconductor device according to claim 12, further comprising an organic insulating layer formed on the inorganic insulating layer so as to cover the seal conductor with the inorganic insulating layer interposed therebetween.

14. The semiconductor device further includes an interlayer insulating layer in which the first portion and the second portion of the seal conductor are formed, wherein the interlayer insulating layer includes a first interlayer insulating layer and a second interlayer insulating layer having different widths and materials in a normal direction of the main surface with respect to the first interlayer insulating layer. The semiconductor device according to any one of claims 1 to 13.

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